4 * Copyright (C) 2014 Renesas Electronics Corporation
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
11 #include <linux/delay.h>
12 #include <linux/dma-mapping.h>
13 #include <linux/err.h>
14 #include <linux/export.h>
15 #include <linux/interrupt.h>
17 #include <linux/iommu.h>
18 #include <linux/module.h>
20 #include <linux/platform_device.h>
21 #include <linux/sizes.h>
22 #include <linux/slab.h>
24 #include <asm/dma-iommu.h>
25 #include <asm/pgalloc.h>
27 #include "io-pgtable.h"
29 struct ipmmu_vmsa_device {
32 struct list_head list;
34 unsigned int num_utlbs;
36 struct dma_iommu_mapping *mapping;
39 struct ipmmu_vmsa_domain {
40 struct ipmmu_vmsa_device *mmu;
41 struct iommu_domain io_domain;
43 struct io_pgtable_cfg cfg;
44 struct io_pgtable_ops *iop;
46 unsigned int context_id;
47 spinlock_t lock; /* Protects mappings */
50 struct ipmmu_vmsa_archdata {
51 struct ipmmu_vmsa_device *mmu;
53 unsigned int num_utlbs;
56 static DEFINE_SPINLOCK(ipmmu_devices_lock);
57 static LIST_HEAD(ipmmu_devices);
59 static struct ipmmu_vmsa_domain *to_vmsa_domain(struct iommu_domain *dom)
61 return container_of(dom, struct ipmmu_vmsa_domain, io_domain);
64 #define TLB_LOOP_TIMEOUT 100 /* 100us */
66 /* -----------------------------------------------------------------------------
67 * Registers Definition
70 #define IM_NS_ALIAS_OFFSET 0x800
72 #define IM_CTX_SIZE 0x40
75 #define IMCTR_TRE (1 << 17)
76 #define IMCTR_AFE (1 << 16)
77 #define IMCTR_RTSEL_MASK (3 << 4)
78 #define IMCTR_RTSEL_SHIFT 4
79 #define IMCTR_TREN (1 << 3)
80 #define IMCTR_INTEN (1 << 2)
81 #define IMCTR_FLUSH (1 << 1)
82 #define IMCTR_MMUEN (1 << 0)
86 #define IMTTBCR 0x0008
87 #define IMTTBCR_EAE (1 << 31)
88 #define IMTTBCR_PMB (1 << 30)
89 #define IMTTBCR_SH1_NON_SHAREABLE (0 << 28)
90 #define IMTTBCR_SH1_OUTER_SHAREABLE (2 << 28)
91 #define IMTTBCR_SH1_INNER_SHAREABLE (3 << 28)
92 #define IMTTBCR_SH1_MASK (3 << 28)
93 #define IMTTBCR_ORGN1_NC (0 << 26)
94 #define IMTTBCR_ORGN1_WB_WA (1 << 26)
95 #define IMTTBCR_ORGN1_WT (2 << 26)
96 #define IMTTBCR_ORGN1_WB (3 << 26)
97 #define IMTTBCR_ORGN1_MASK (3 << 26)
98 #define IMTTBCR_IRGN1_NC (0 << 24)
99 #define IMTTBCR_IRGN1_WB_WA (1 << 24)
100 #define IMTTBCR_IRGN1_WT (2 << 24)
101 #define IMTTBCR_IRGN1_WB (3 << 24)
102 #define IMTTBCR_IRGN1_MASK (3 << 24)
103 #define IMTTBCR_TSZ1_MASK (7 << 16)
104 #define IMTTBCR_TSZ1_SHIFT 16
105 #define IMTTBCR_SH0_NON_SHAREABLE (0 << 12)
106 #define IMTTBCR_SH0_OUTER_SHAREABLE (2 << 12)
107 #define IMTTBCR_SH0_INNER_SHAREABLE (3 << 12)
108 #define IMTTBCR_SH0_MASK (3 << 12)
109 #define IMTTBCR_ORGN0_NC (0 << 10)
110 #define IMTTBCR_ORGN0_WB_WA (1 << 10)
111 #define IMTTBCR_ORGN0_WT (2 << 10)
112 #define IMTTBCR_ORGN0_WB (3 << 10)
113 #define IMTTBCR_ORGN0_MASK (3 << 10)
114 #define IMTTBCR_IRGN0_NC (0 << 8)
115 #define IMTTBCR_IRGN0_WB_WA (1 << 8)
116 #define IMTTBCR_IRGN0_WT (2 << 8)
117 #define IMTTBCR_IRGN0_WB (3 << 8)
118 #define IMTTBCR_IRGN0_MASK (3 << 8)
119 #define IMTTBCR_SL0_LVL_2 (0 << 4)
120 #define IMTTBCR_SL0_LVL_1 (1 << 4)
121 #define IMTTBCR_TSZ0_MASK (7 << 0)
122 #define IMTTBCR_TSZ0_SHIFT O
124 #define IMBUSCR 0x000c
125 #define IMBUSCR_DVM (1 << 2)
126 #define IMBUSCR_BUSSEL_SYS (0 << 0)
127 #define IMBUSCR_BUSSEL_CCI (1 << 0)
128 #define IMBUSCR_BUSSEL_IMCAAR (2 << 0)
129 #define IMBUSCR_BUSSEL_CCI_IMCAAR (3 << 0)
130 #define IMBUSCR_BUSSEL_MASK (3 << 0)
132 #define IMTTLBR0 0x0010
133 #define IMTTUBR0 0x0014
134 #define IMTTLBR1 0x0018
135 #define IMTTUBR1 0x001c
138 #define IMSTR_ERRLVL_MASK (3 << 12)
139 #define IMSTR_ERRLVL_SHIFT 12
140 #define IMSTR_ERRCODE_TLB_FORMAT (1 << 8)
141 #define IMSTR_ERRCODE_ACCESS_PERM (4 << 8)
142 #define IMSTR_ERRCODE_SECURE_ACCESS (5 << 8)
143 #define IMSTR_ERRCODE_MASK (7 << 8)
144 #define IMSTR_MHIT (1 << 4)
145 #define IMSTR_ABORT (1 << 2)
146 #define IMSTR_PF (1 << 1)
147 #define IMSTR_TF (1 << 0)
149 #define IMMAIR0 0x0028
150 #define IMMAIR1 0x002c
151 #define IMMAIR_ATTR_MASK 0xff
152 #define IMMAIR_ATTR_DEVICE 0x04
153 #define IMMAIR_ATTR_NC 0x44
154 #define IMMAIR_ATTR_WBRWA 0xff
155 #define IMMAIR_ATTR_SHIFT(n) ((n) << 3)
156 #define IMMAIR_ATTR_IDX_NC 0
157 #define IMMAIR_ATTR_IDX_WBRWA 1
158 #define IMMAIR_ATTR_IDX_DEV 2
162 #define IMPCTR 0x0200
163 #define IMPSTR 0x0208
164 #define IMPEAR 0x020c
165 #define IMPMBA(n) (0x0280 + ((n) * 4))
166 #define IMPMBD(n) (0x02c0 + ((n) * 4))
168 #define IMUCTR(n) (0x0300 + ((n) * 16))
169 #define IMUCTR_FIXADDEN (1 << 31)
170 #define IMUCTR_FIXADD_MASK (0xff << 16)
171 #define IMUCTR_FIXADD_SHIFT 16
172 #define IMUCTR_TTSEL_MMU(n) ((n) << 4)
173 #define IMUCTR_TTSEL_PMB (8 << 4)
174 #define IMUCTR_TTSEL_MASK (15 << 4)
175 #define IMUCTR_FLUSH (1 << 1)
176 #define IMUCTR_MMUEN (1 << 0)
178 #define IMUASID(n) (0x0308 + ((n) * 16))
179 #define IMUASID_ASID8_MASK (0xff << 8)
180 #define IMUASID_ASID8_SHIFT 8
181 #define IMUASID_ASID0_MASK (0xff << 0)
182 #define IMUASID_ASID0_SHIFT 0
184 /* -----------------------------------------------------------------------------
188 static u32 ipmmu_read(struct ipmmu_vmsa_device *mmu, unsigned int offset)
190 return ioread32(mmu->base + offset);
193 static void ipmmu_write(struct ipmmu_vmsa_device *mmu, unsigned int offset,
196 iowrite32(data, mmu->base + offset);
199 static u32 ipmmu_ctx_read(struct ipmmu_vmsa_domain *domain, unsigned int reg)
201 return ipmmu_read(domain->mmu, domain->context_id * IM_CTX_SIZE + reg);
204 static void ipmmu_ctx_write(struct ipmmu_vmsa_domain *domain, unsigned int reg,
207 ipmmu_write(domain->mmu, domain->context_id * IM_CTX_SIZE + reg, data);
210 /* -----------------------------------------------------------------------------
211 * TLB and microTLB Management
214 /* Wait for any pending TLB invalidations to complete */
215 static void ipmmu_tlb_sync(struct ipmmu_vmsa_domain *domain)
217 unsigned int count = 0;
219 while (ipmmu_ctx_read(domain, IMCTR) & IMCTR_FLUSH) {
221 if (++count == TLB_LOOP_TIMEOUT) {
222 dev_err_ratelimited(domain->mmu->dev,
223 "TLB sync timed out -- MMU may be deadlocked\n");
230 static void ipmmu_tlb_invalidate(struct ipmmu_vmsa_domain *domain)
234 reg = ipmmu_ctx_read(domain, IMCTR);
236 ipmmu_ctx_write(domain, IMCTR, reg);
238 ipmmu_tlb_sync(domain);
242 * Enable MMU translation for the microTLB.
244 static void ipmmu_utlb_enable(struct ipmmu_vmsa_domain *domain,
247 struct ipmmu_vmsa_device *mmu = domain->mmu;
250 * TODO: Reference-count the microTLB as several bus masters can be
251 * connected to the same microTLB.
254 /* TODO: What should we set the ASID to ? */
255 ipmmu_write(mmu, IMUASID(utlb), 0);
256 /* TODO: Do we need to flush the microTLB ? */
257 ipmmu_write(mmu, IMUCTR(utlb),
258 IMUCTR_TTSEL_MMU(domain->context_id) | IMUCTR_FLUSH |
263 * Disable MMU translation for the microTLB.
265 static void ipmmu_utlb_disable(struct ipmmu_vmsa_domain *domain,
268 struct ipmmu_vmsa_device *mmu = domain->mmu;
270 ipmmu_write(mmu, IMUCTR(utlb), 0);
273 static void ipmmu_tlb_flush_all(void *cookie)
275 struct ipmmu_vmsa_domain *domain = cookie;
277 ipmmu_tlb_invalidate(domain);
280 static void ipmmu_tlb_add_flush(unsigned long iova, size_t size, bool leaf,
283 /* The hardware doesn't support selective TLB flush. */
286 static void ipmmu_flush_pgtable(void *ptr, size_t size, void *cookie)
288 unsigned long offset = (unsigned long)ptr & ~PAGE_MASK;
289 struct ipmmu_vmsa_domain *domain = cookie;
292 * TODO: Add support for coherent walk through CCI with DVM and remove
295 dma_map_page(domain->mmu->dev, virt_to_page(ptr), offset, size,
299 static struct iommu_gather_ops ipmmu_gather_ops = {
300 .tlb_flush_all = ipmmu_tlb_flush_all,
301 .tlb_add_flush = ipmmu_tlb_add_flush,
302 .tlb_sync = ipmmu_tlb_flush_all,
303 .flush_pgtable = ipmmu_flush_pgtable,
306 /* -----------------------------------------------------------------------------
307 * Domain/Context Management
310 static int ipmmu_domain_init_context(struct ipmmu_vmsa_domain *domain)
315 * Allocate the page table operations.
317 * VMSA states in section B3.6.3 "Control of Secure or Non-secure memory
318 * access, Long-descriptor format" that the NStable bit being set in a
319 * table descriptor will result in the NStable and NS bits of all child
320 * entries being ignored and considered as being set. The IPMMU seems
321 * not to comply with this, as it generates a secure access page fault
322 * if any of the NStable and NS bits isn't set when running in
325 domain->cfg.quirks = IO_PGTABLE_QUIRK_ARM_NS;
326 domain->cfg.pgsize_bitmap = SZ_1G | SZ_2M | SZ_4K,
327 domain->cfg.ias = 32;
328 domain->cfg.oas = 40;
329 domain->cfg.tlb = &ipmmu_gather_ops;
331 domain->iop = alloc_io_pgtable_ops(ARM_32_LPAE_S1, &domain->cfg,
337 * TODO: When adding support for multiple contexts, find an unused
340 domain->context_id = 0;
343 ttbr = domain->cfg.arm_lpae_s1_cfg.ttbr[0];
344 ipmmu_ctx_write(domain, IMTTLBR0, ttbr);
345 ipmmu_ctx_write(domain, IMTTUBR0, ttbr >> 32);
349 * We use long descriptors with inner-shareable WBWA tables and allocate
350 * the whole 32-bit VA space to TTBR0.
352 ipmmu_ctx_write(domain, IMTTBCR, IMTTBCR_EAE |
353 IMTTBCR_SH0_INNER_SHAREABLE | IMTTBCR_ORGN0_WB_WA |
354 IMTTBCR_IRGN0_WB_WA | IMTTBCR_SL0_LVL_1);
357 ipmmu_ctx_write(domain, IMMAIR0, domain->cfg.arm_lpae_s1_cfg.mair[0]);
360 ipmmu_ctx_write(domain, IMBUSCR,
361 ipmmu_ctx_read(domain, IMBUSCR) &
362 ~(IMBUSCR_DVM | IMBUSCR_BUSSEL_MASK));
366 * Clear all interrupt flags.
368 ipmmu_ctx_write(domain, IMSTR, ipmmu_ctx_read(domain, IMSTR));
372 * Enable the MMU and interrupt generation. The long-descriptor
373 * translation table format doesn't use TEX remapping. Don't enable AF
374 * software management as we have no use for it. Flush the TLB as
375 * required when modifying the context registers.
377 ipmmu_ctx_write(domain, IMCTR, IMCTR_INTEN | IMCTR_FLUSH | IMCTR_MMUEN);
382 static void ipmmu_domain_destroy_context(struct ipmmu_vmsa_domain *domain)
385 * Disable the context. Flush the TLB as required when modifying the
388 * TODO: Is TLB flush really needed ?
390 ipmmu_ctx_write(domain, IMCTR, IMCTR_FLUSH);
391 ipmmu_tlb_sync(domain);
394 /* -----------------------------------------------------------------------------
398 static irqreturn_t ipmmu_domain_irq(struct ipmmu_vmsa_domain *domain)
400 const u32 err_mask = IMSTR_MHIT | IMSTR_ABORT | IMSTR_PF | IMSTR_TF;
401 struct ipmmu_vmsa_device *mmu = domain->mmu;
405 status = ipmmu_ctx_read(domain, IMSTR);
406 if (!(status & err_mask))
409 iova = ipmmu_ctx_read(domain, IMEAR);
412 * Clear the error status flags. Unlike traditional interrupt flag
413 * registers that must be cleared by writing 1, this status register
414 * seems to require 0. The error address register must be read before,
415 * otherwise its value will be 0.
417 ipmmu_ctx_write(domain, IMSTR, 0);
419 /* Log fatal errors. */
420 if (status & IMSTR_MHIT)
421 dev_err_ratelimited(mmu->dev, "Multiple TLB hits @0x%08x\n",
423 if (status & IMSTR_ABORT)
424 dev_err_ratelimited(mmu->dev, "Page Table Walk Abort @0x%08x\n",
427 if (!(status & (IMSTR_PF | IMSTR_TF)))
431 * Try to handle page faults and translation faults.
433 * TODO: We need to look up the faulty device based on the I/O VA. Use
434 * the IOMMU device for now.
436 if (!report_iommu_fault(&domain->io_domain, mmu->dev, iova, 0))
439 dev_err_ratelimited(mmu->dev,
440 "Unhandled fault: status 0x%08x iova 0x%08x\n",
446 static irqreturn_t ipmmu_irq(int irq, void *dev)
448 struct ipmmu_vmsa_device *mmu = dev;
449 struct iommu_domain *io_domain;
450 struct ipmmu_vmsa_domain *domain;
455 io_domain = mmu->mapping->domain;
456 domain = to_vmsa_domain(io_domain);
458 return ipmmu_domain_irq(domain);
461 /* -----------------------------------------------------------------------------
465 static struct iommu_domain *ipmmu_domain_alloc(unsigned type)
467 struct ipmmu_vmsa_domain *domain;
469 if (type != IOMMU_DOMAIN_UNMANAGED)
472 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
476 spin_lock_init(&domain->lock);
478 return &domain->io_domain;
481 static void ipmmu_domain_free(struct iommu_domain *io_domain)
483 struct ipmmu_vmsa_domain *domain = to_vmsa_domain(io_domain);
486 * Free the domain resources. We assume that all devices have already
489 ipmmu_domain_destroy_context(domain);
490 free_io_pgtable_ops(domain->iop);
494 static int ipmmu_attach_device(struct iommu_domain *io_domain,
497 struct ipmmu_vmsa_archdata *archdata = dev->archdata.iommu;
498 struct ipmmu_vmsa_device *mmu = archdata->mmu;
499 struct ipmmu_vmsa_domain *domain = to_vmsa_domain(io_domain);
505 dev_err(dev, "Cannot attach to IPMMU\n");
509 spin_lock_irqsave(&domain->lock, flags);
512 /* The domain hasn't been used yet, initialize it. */
514 ret = ipmmu_domain_init_context(domain);
515 } else if (domain->mmu != mmu) {
517 * Something is wrong, we can't attach two devices using
518 * different IOMMUs to the same domain.
520 dev_err(dev, "Can't attach IPMMU %s to domain on IPMMU %s\n",
521 dev_name(mmu->dev), dev_name(domain->mmu->dev));
525 spin_unlock_irqrestore(&domain->lock, flags);
530 for (i = 0; i < archdata->num_utlbs; ++i)
531 ipmmu_utlb_enable(domain, archdata->utlbs[i]);
536 static void ipmmu_detach_device(struct iommu_domain *io_domain,
539 struct ipmmu_vmsa_archdata *archdata = dev->archdata.iommu;
540 struct ipmmu_vmsa_domain *domain = to_vmsa_domain(io_domain);
543 for (i = 0; i < archdata->num_utlbs; ++i)
544 ipmmu_utlb_disable(domain, archdata->utlbs[i]);
547 * TODO: Optimize by disabling the context when no device is attached.
551 static int ipmmu_map(struct iommu_domain *io_domain, unsigned long iova,
552 phys_addr_t paddr, size_t size, int prot)
554 struct ipmmu_vmsa_domain *domain = to_vmsa_domain(io_domain);
559 return domain->iop->map(domain->iop, iova, paddr, size, prot);
562 static size_t ipmmu_unmap(struct iommu_domain *io_domain, unsigned long iova,
565 struct ipmmu_vmsa_domain *domain = to_vmsa_domain(io_domain);
567 return domain->iop->unmap(domain->iop, iova, size);
570 static phys_addr_t ipmmu_iova_to_phys(struct iommu_domain *io_domain,
573 struct ipmmu_vmsa_domain *domain = to_vmsa_domain(io_domain);
575 /* TODO: Is locking needed ? */
577 return domain->iop->iova_to_phys(domain->iop, iova);
580 static int ipmmu_find_utlbs(struct ipmmu_vmsa_device *mmu, struct device *dev,
581 unsigned int *utlbs, unsigned int num_utlbs)
585 for (i = 0; i < num_utlbs; ++i) {
586 struct of_phandle_args args;
589 ret = of_parse_phandle_with_args(dev->of_node, "iommus",
590 "#iommu-cells", i, &args);
594 of_node_put(args.np);
596 if (args.np != mmu->dev->of_node || args.args_count != 1)
599 utlbs[i] = args.args[0];
605 static int ipmmu_add_device(struct device *dev)
607 struct ipmmu_vmsa_archdata *archdata;
608 struct ipmmu_vmsa_device *mmu;
609 struct iommu_group *group = NULL;
615 if (dev->archdata.iommu) {
616 dev_warn(dev, "IOMMU driver already assigned to device %s\n",
621 /* Find the master corresponding to the device. */
623 num_utlbs = of_count_phandle_with_args(dev->of_node, "iommus",
628 utlbs = kcalloc(num_utlbs, sizeof(*utlbs), GFP_KERNEL);
632 spin_lock(&ipmmu_devices_lock);
634 list_for_each_entry(mmu, &ipmmu_devices, list) {
635 ret = ipmmu_find_utlbs(mmu, dev, utlbs, num_utlbs);
638 * TODO Take a reference to the MMU to protect
639 * against device removal.
645 spin_unlock(&ipmmu_devices_lock);
650 for (i = 0; i < num_utlbs; ++i) {
651 if (utlbs[i] >= mmu->num_utlbs) {
657 /* Create a device group and add the device to it. */
658 group = iommu_group_alloc();
660 dev_err(dev, "Failed to allocate IOMMU group\n");
661 ret = PTR_ERR(group);
665 ret = iommu_group_add_device(group, dev);
666 iommu_group_put(group);
669 dev_err(dev, "Failed to add device to IPMMU group\n");
674 archdata = kzalloc(sizeof(*archdata), GFP_KERNEL);
681 archdata->utlbs = utlbs;
682 archdata->num_utlbs = num_utlbs;
683 dev->archdata.iommu = archdata;
686 * Create the ARM mapping, used by the ARM DMA mapping core to allocate
687 * VAs. This will allocate a corresponding IOMMU domain.
690 * - Create one mapping per context (TLB).
691 * - Make the mapping size configurable ? We currently use a 2GB mapping
692 * at a 1GB offset to ensure that NULL VAs will fault.
695 struct dma_iommu_mapping *mapping;
697 mapping = arm_iommu_create_mapping(&platform_bus_type,
699 if (IS_ERR(mapping)) {
700 dev_err(mmu->dev, "failed to create ARM IOMMU mapping\n");
701 ret = PTR_ERR(mapping);
705 mmu->mapping = mapping;
708 /* Attach the ARM VA mapping to the device. */
709 ret = arm_iommu_attach_device(dev, mmu->mapping);
711 dev_err(dev, "Failed to attach device to VA mapping\n");
718 arm_iommu_release_mapping(mmu->mapping);
720 kfree(dev->archdata.iommu);
723 dev->archdata.iommu = NULL;
725 if (!IS_ERR_OR_NULL(group))
726 iommu_group_remove_device(dev);
731 static void ipmmu_remove_device(struct device *dev)
733 struct ipmmu_vmsa_archdata *archdata = dev->archdata.iommu;
735 arm_iommu_detach_device(dev);
736 iommu_group_remove_device(dev);
738 kfree(archdata->utlbs);
741 dev->archdata.iommu = NULL;
744 static const struct iommu_ops ipmmu_ops = {
745 .domain_alloc = ipmmu_domain_alloc,
746 .domain_free = ipmmu_domain_free,
747 .attach_dev = ipmmu_attach_device,
748 .detach_dev = ipmmu_detach_device,
750 .unmap = ipmmu_unmap,
751 .map_sg = default_iommu_map_sg,
752 .iova_to_phys = ipmmu_iova_to_phys,
753 .add_device = ipmmu_add_device,
754 .remove_device = ipmmu_remove_device,
755 .pgsize_bitmap = SZ_1G | SZ_2M | SZ_4K,
758 /* -----------------------------------------------------------------------------
759 * Probe/remove and init
762 static void ipmmu_device_reset(struct ipmmu_vmsa_device *mmu)
766 /* Disable all contexts. */
767 for (i = 0; i < 4; ++i)
768 ipmmu_write(mmu, i * IM_CTX_SIZE + IMCTR, 0);
771 static int ipmmu_probe(struct platform_device *pdev)
773 struct ipmmu_vmsa_device *mmu;
774 struct resource *res;
778 if (!IS_ENABLED(CONFIG_OF) && !pdev->dev.platform_data) {
779 dev_err(&pdev->dev, "missing platform data\n");
783 mmu = devm_kzalloc(&pdev->dev, sizeof(*mmu), GFP_KERNEL);
785 dev_err(&pdev->dev, "cannot allocate device data\n");
789 mmu->dev = &pdev->dev;
792 /* Map I/O memory and request IRQ. */
793 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
794 mmu->base = devm_ioremap_resource(&pdev->dev, res);
795 if (IS_ERR(mmu->base))
796 return PTR_ERR(mmu->base);
799 * The IPMMU has two register banks, for secure and non-secure modes.
800 * The bank mapped at the beginning of the IPMMU address space
801 * corresponds to the running mode of the CPU. When running in secure
802 * mode the non-secure register bank is also available at an offset.
804 * Secure mode operation isn't clearly documented and is thus currently
805 * not implemented in the driver. Furthermore, preliminary tests of
806 * non-secure operation with the main register bank were not successful.
807 * Offset the registers base unconditionally to point to the non-secure
808 * alias space for now.
810 mmu->base += IM_NS_ALIAS_OFFSET;
812 irq = platform_get_irq(pdev, 0);
814 dev_err(&pdev->dev, "no IRQ found\n");
818 ret = devm_request_irq(&pdev->dev, irq, ipmmu_irq, 0,
819 dev_name(&pdev->dev), mmu);
821 dev_err(&pdev->dev, "failed to request IRQ %d\n", irq);
825 ipmmu_device_reset(mmu);
828 * We can't create the ARM mapping here as it requires the bus to have
829 * an IOMMU, which only happens when bus_set_iommu() is called in
830 * ipmmu_init() after the probe function returns.
833 spin_lock(&ipmmu_devices_lock);
834 list_add(&mmu->list, &ipmmu_devices);
835 spin_unlock(&ipmmu_devices_lock);
837 platform_set_drvdata(pdev, mmu);
842 static int ipmmu_remove(struct platform_device *pdev)
844 struct ipmmu_vmsa_device *mmu = platform_get_drvdata(pdev);
846 spin_lock(&ipmmu_devices_lock);
847 list_del(&mmu->list);
848 spin_unlock(&ipmmu_devices_lock);
850 arm_iommu_release_mapping(mmu->mapping);
852 ipmmu_device_reset(mmu);
857 static const struct of_device_id ipmmu_of_ids[] = {
858 { .compatible = "renesas,ipmmu-vmsa", },
862 static struct platform_driver ipmmu_driver = {
864 .name = "ipmmu-vmsa",
865 .of_match_table = of_match_ptr(ipmmu_of_ids),
867 .probe = ipmmu_probe,
868 .remove = ipmmu_remove,
871 static int __init ipmmu_init(void)
875 ret = platform_driver_register(&ipmmu_driver);
879 if (!iommu_present(&platform_bus_type))
880 bus_set_iommu(&platform_bus_type, &ipmmu_ops);
885 static void __exit ipmmu_exit(void)
887 return platform_driver_unregister(&ipmmu_driver);
890 subsys_initcall(ipmmu_init);
891 module_exit(ipmmu_exit);
893 MODULE_DESCRIPTION("IOMMU API for Renesas VMSA-compatible IPMMU");
894 MODULE_AUTHOR("Laurent Pinchart <laurent.pinchart@ideasonboard.com>");
895 MODULE_LICENSE("GPL v2");