2 * omap iommu: tlb and pagetable primitives
4 * Copyright (C) 2008-2010 Nokia Corporation
6 * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>,
7 * Paul Mundt and Toshihiro Kobayashi
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/err.h>
15 #include <linux/module.h>
16 #include <linux/slab.h>
17 #include <linux/interrupt.h>
18 #include <linux/ioport.h>
19 #include <linux/clk.h>
20 #include <linux/platform_device.h>
21 #include <linux/iommu.h>
22 #include <linux/omap-iommu.h>
23 #include <linux/mutex.h>
24 #include <linux/spinlock.h>
27 #include <asm/cacheflush.h>
29 #include <plat/iommu.h>
31 #include "omap-iopgtable.h"
32 #include "omap-iommu.h"
34 #define for_each_iotlb_cr(obj, n, __i, cr) \
36 (__i < (n)) && (cr = __iotlb_read_cr((obj), __i), true); \
39 /* bitmap of the page sizes currently supported */
40 #define OMAP_IOMMU_PGSIZES (SZ_4K | SZ_64K | SZ_1M | SZ_16M)
43 * struct omap_iommu_domain - omap iommu domain
44 * @pgtable: the page table
45 * @iommu_dev: an omap iommu device attached to this domain. only a single
46 * iommu device can be attached for now.
47 * @dev: Device using this domain.
48 * @lock: domain lock, should be taken when attaching/detaching
50 struct omap_iommu_domain {
52 struct omap_iommu *iommu_dev;
57 /* accommodate the difference between omap1 and omap2/3 */
58 static const struct iommu_functions *arch_iommu;
60 static struct platform_driver omap_iommu_driver;
61 static struct kmem_cache *iopte_cachep;
64 * omap_install_iommu_arch - Install archtecure specific iommu functions
65 * @ops: a pointer to architecture specific iommu functions
67 * There are several kind of iommu algorithm(tlb, pagetable) among
68 * omap series. This interface installs such an iommu algorighm.
70 int omap_install_iommu_arch(const struct iommu_functions *ops)
78 EXPORT_SYMBOL_GPL(omap_install_iommu_arch);
81 * omap_uninstall_iommu_arch - Uninstall archtecure specific iommu functions
82 * @ops: a pointer to architecture specific iommu functions
84 * This interface uninstalls the iommu algorighm installed previously.
86 void omap_uninstall_iommu_arch(const struct iommu_functions *ops)
88 if (arch_iommu != ops)
89 pr_err("%s: not your arch\n", __func__);
93 EXPORT_SYMBOL_GPL(omap_uninstall_iommu_arch);
96 * omap_iommu_save_ctx - Save registers for pm off-mode support
99 void omap_iommu_save_ctx(struct device *dev)
101 struct omap_iommu *obj = dev_to_omap_iommu(dev);
103 arch_iommu->save_ctx(obj);
105 EXPORT_SYMBOL_GPL(omap_iommu_save_ctx);
108 * omap_iommu_restore_ctx - Restore registers for pm off-mode support
109 * @dev: client device
111 void omap_iommu_restore_ctx(struct device *dev)
113 struct omap_iommu *obj = dev_to_omap_iommu(dev);
115 arch_iommu->restore_ctx(obj);
117 EXPORT_SYMBOL_GPL(omap_iommu_restore_ctx);
120 * omap_iommu_arch_version - Return running iommu arch version
122 u32 omap_iommu_arch_version(void)
124 return arch_iommu->version;
126 EXPORT_SYMBOL_GPL(omap_iommu_arch_version);
128 static int iommu_enable(struct omap_iommu *obj)
138 clk_enable(obj->clk);
140 err = arch_iommu->enable(obj);
142 clk_disable(obj->clk);
146 static void iommu_disable(struct omap_iommu *obj)
151 clk_enable(obj->clk);
153 arch_iommu->disable(obj);
155 clk_disable(obj->clk);
161 void omap_iotlb_cr_to_e(struct cr_regs *cr, struct iotlb_entry *e)
165 arch_iommu->cr_to_e(cr, e);
167 EXPORT_SYMBOL_GPL(omap_iotlb_cr_to_e);
169 static inline int iotlb_cr_valid(struct cr_regs *cr)
174 return arch_iommu->cr_valid(cr);
177 static inline struct cr_regs *iotlb_alloc_cr(struct omap_iommu *obj,
178 struct iotlb_entry *e)
183 return arch_iommu->alloc_cr(obj, e);
186 static u32 iotlb_cr_to_virt(struct cr_regs *cr)
188 return arch_iommu->cr_to_virt(cr);
191 static u32 get_iopte_attr(struct iotlb_entry *e)
193 return arch_iommu->get_pte_attr(e);
196 static u32 iommu_report_fault(struct omap_iommu *obj, u32 *da)
198 return arch_iommu->fault_isr(obj, da);
201 static void iotlb_lock_get(struct omap_iommu *obj, struct iotlb_lock *l)
205 val = iommu_read_reg(obj, MMU_LOCK);
207 l->base = MMU_LOCK_BASE(val);
208 l->vict = MMU_LOCK_VICT(val);
212 static void iotlb_lock_set(struct omap_iommu *obj, struct iotlb_lock *l)
216 val = (l->base << MMU_LOCK_BASE_SHIFT);
217 val |= (l->vict << MMU_LOCK_VICT_SHIFT);
219 iommu_write_reg(obj, val, MMU_LOCK);
222 static void iotlb_read_cr(struct omap_iommu *obj, struct cr_regs *cr)
224 arch_iommu->tlb_read_cr(obj, cr);
227 static void iotlb_load_cr(struct omap_iommu *obj, struct cr_regs *cr)
229 arch_iommu->tlb_load_cr(obj, cr);
231 iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY);
232 iommu_write_reg(obj, 1, MMU_LD_TLB);
236 * iotlb_dump_cr - Dump an iommu tlb entry into buf
238 * @cr: contents of cam and ram register
239 * @buf: output buffer
241 static inline ssize_t iotlb_dump_cr(struct omap_iommu *obj, struct cr_regs *cr,
246 return arch_iommu->dump_cr(obj, cr, buf);
249 /* only used in iotlb iteration for-loop */
250 static struct cr_regs __iotlb_read_cr(struct omap_iommu *obj, int n)
255 iotlb_lock_get(obj, &l);
257 iotlb_lock_set(obj, &l);
258 iotlb_read_cr(obj, &cr);
264 * load_iotlb_entry - Set an iommu tlb entry
266 * @e: an iommu tlb entry info
268 #ifdef PREFETCH_IOTLB
269 static int load_iotlb_entry(struct omap_iommu *obj, struct iotlb_entry *e)
275 if (!obj || !obj->nr_tlb_entries || !e)
278 clk_enable(obj->clk);
280 iotlb_lock_get(obj, &l);
281 if (l.base == obj->nr_tlb_entries) {
282 dev_warn(obj->dev, "%s: preserve entries full\n", __func__);
290 for_each_iotlb_cr(obj, obj->nr_tlb_entries, i, tmp)
291 if (!iotlb_cr_valid(&tmp))
294 if (i == obj->nr_tlb_entries) {
295 dev_dbg(obj->dev, "%s: full: no entry\n", __func__);
300 iotlb_lock_get(obj, &l);
303 iotlb_lock_set(obj, &l);
306 cr = iotlb_alloc_cr(obj, e);
308 clk_disable(obj->clk);
312 iotlb_load_cr(obj, cr);
317 /* increment victim for next tlb load */
318 if (++l.vict == obj->nr_tlb_entries)
320 iotlb_lock_set(obj, &l);
322 clk_disable(obj->clk);
326 #else /* !PREFETCH_IOTLB */
328 static int load_iotlb_entry(struct omap_iommu *obj, struct iotlb_entry *e)
333 #endif /* !PREFETCH_IOTLB */
335 static int prefetch_iotlb_entry(struct omap_iommu *obj, struct iotlb_entry *e)
337 return load_iotlb_entry(obj, e);
341 * flush_iotlb_page - Clear an iommu tlb entry
343 * @da: iommu device virtual address
345 * Clear an iommu tlb entry which includes 'da' address.
347 static void flush_iotlb_page(struct omap_iommu *obj, u32 da)
352 clk_enable(obj->clk);
354 for_each_iotlb_cr(obj, obj->nr_tlb_entries, i, cr) {
358 if (!iotlb_cr_valid(&cr))
361 start = iotlb_cr_to_virt(&cr);
362 bytes = iopgsz_to_bytes(cr.cam & 3);
364 if ((start <= da) && (da < start + bytes)) {
365 dev_dbg(obj->dev, "%s: %08x<=%08x(%x)\n",
366 __func__, start, da, bytes);
367 iotlb_load_cr(obj, &cr);
368 iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY);
371 clk_disable(obj->clk);
373 if (i == obj->nr_tlb_entries)
374 dev_dbg(obj->dev, "%s: no page for %08x\n", __func__, da);
378 * flush_iotlb_all - Clear all iommu tlb entries
381 static void flush_iotlb_all(struct omap_iommu *obj)
385 clk_enable(obj->clk);
389 iotlb_lock_set(obj, &l);
391 iommu_write_reg(obj, 1, MMU_GFLUSH);
393 clk_disable(obj->clk);
396 #if defined(CONFIG_OMAP_IOMMU_DEBUG) || defined(CONFIG_OMAP_IOMMU_DEBUG_MODULE)
398 ssize_t omap_iommu_dump_ctx(struct omap_iommu *obj, char *buf, ssize_t bytes)
403 clk_enable(obj->clk);
405 bytes = arch_iommu->dump_ctx(obj, buf, bytes);
407 clk_disable(obj->clk);
411 EXPORT_SYMBOL_GPL(omap_iommu_dump_ctx);
414 __dump_tlb_entries(struct omap_iommu *obj, struct cr_regs *crs, int num)
417 struct iotlb_lock saved;
419 struct cr_regs *p = crs;
421 clk_enable(obj->clk);
422 iotlb_lock_get(obj, &saved);
424 for_each_iotlb_cr(obj, num, i, tmp) {
425 if (!iotlb_cr_valid(&tmp))
430 iotlb_lock_set(obj, &saved);
431 clk_disable(obj->clk);
437 * omap_dump_tlb_entries - dump cr arrays to given buffer
439 * @buf: output buffer
441 size_t omap_dump_tlb_entries(struct omap_iommu *obj, char *buf, ssize_t bytes)
447 num = bytes / sizeof(*cr);
448 num = min(obj->nr_tlb_entries, num);
450 cr = kcalloc(num, sizeof(*cr), GFP_KERNEL);
454 num = __dump_tlb_entries(obj, cr, num);
455 for (i = 0; i < num; i++)
456 p += iotlb_dump_cr(obj, cr + i, p);
461 EXPORT_SYMBOL_GPL(omap_dump_tlb_entries);
463 int omap_foreach_iommu_device(void *data, int (*fn)(struct device *, void *))
465 return driver_for_each_device(&omap_iommu_driver.driver,
468 EXPORT_SYMBOL_GPL(omap_foreach_iommu_device);
470 #endif /* CONFIG_OMAP_IOMMU_DEBUG_MODULE */
473 * H/W pagetable operations
475 static void flush_iopgd_range(u32 *first, u32 *last)
477 /* FIXME: L2 cache should be taken care of if it exists */
479 asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pgd"
481 first += L1_CACHE_BYTES / sizeof(*first);
482 } while (first <= last);
485 static void flush_iopte_range(u32 *first, u32 *last)
487 /* FIXME: L2 cache should be taken care of if it exists */
489 asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pte"
491 first += L1_CACHE_BYTES / sizeof(*first);
492 } while (first <= last);
495 static void iopte_free(u32 *iopte)
497 /* Note: freed iopte's must be clean ready for re-use */
498 kmem_cache_free(iopte_cachep, iopte);
501 static u32 *iopte_alloc(struct omap_iommu *obj, u32 *iopgd, u32 da)
505 /* a table has already existed */
510 * do the allocation outside the page table lock
512 spin_unlock(&obj->page_table_lock);
513 iopte = kmem_cache_zalloc(iopte_cachep, GFP_KERNEL);
514 spin_lock(&obj->page_table_lock);
518 return ERR_PTR(-ENOMEM);
520 *iopgd = virt_to_phys(iopte) | IOPGD_TABLE;
521 flush_iopgd_range(iopgd, iopgd);
523 dev_vdbg(obj->dev, "%s: a new pte:%p\n", __func__, iopte);
525 /* We raced, free the reduniovant table */
530 iopte = iopte_offset(iopgd, da);
533 "%s: da:%08x pgd:%p *pgd:%08x pte:%p *pte:%08x\n",
534 __func__, da, iopgd, *iopgd, iopte, *iopte);
539 static int iopgd_alloc_section(struct omap_iommu *obj, u32 da, u32 pa, u32 prot)
541 u32 *iopgd = iopgd_offset(obj, da);
543 if ((da | pa) & ~IOSECTION_MASK) {
544 dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n",
545 __func__, da, pa, IOSECTION_SIZE);
549 *iopgd = (pa & IOSECTION_MASK) | prot | IOPGD_SECTION;
550 flush_iopgd_range(iopgd, iopgd);
554 static int iopgd_alloc_super(struct omap_iommu *obj, u32 da, u32 pa, u32 prot)
556 u32 *iopgd = iopgd_offset(obj, da);
559 if ((da | pa) & ~IOSUPER_MASK) {
560 dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n",
561 __func__, da, pa, IOSUPER_SIZE);
565 for (i = 0; i < 16; i++)
566 *(iopgd + i) = (pa & IOSUPER_MASK) | prot | IOPGD_SUPER;
567 flush_iopgd_range(iopgd, iopgd + 15);
571 static int iopte_alloc_page(struct omap_iommu *obj, u32 da, u32 pa, u32 prot)
573 u32 *iopgd = iopgd_offset(obj, da);
574 u32 *iopte = iopte_alloc(obj, iopgd, da);
577 return PTR_ERR(iopte);
579 *iopte = (pa & IOPAGE_MASK) | prot | IOPTE_SMALL;
580 flush_iopte_range(iopte, iopte);
582 dev_vdbg(obj->dev, "%s: da:%08x pa:%08x pte:%p *pte:%08x\n",
583 __func__, da, pa, iopte, *iopte);
588 static int iopte_alloc_large(struct omap_iommu *obj, u32 da, u32 pa, u32 prot)
590 u32 *iopgd = iopgd_offset(obj, da);
591 u32 *iopte = iopte_alloc(obj, iopgd, da);
594 if ((da | pa) & ~IOLARGE_MASK) {
595 dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n",
596 __func__, da, pa, IOLARGE_SIZE);
601 return PTR_ERR(iopte);
603 for (i = 0; i < 16; i++)
604 *(iopte + i) = (pa & IOLARGE_MASK) | prot | IOPTE_LARGE;
605 flush_iopte_range(iopte, iopte + 15);
610 iopgtable_store_entry_core(struct omap_iommu *obj, struct iotlb_entry *e)
612 int (*fn)(struct omap_iommu *, u32, u32, u32);
620 case MMU_CAM_PGSZ_16M:
621 fn = iopgd_alloc_super;
623 case MMU_CAM_PGSZ_1M:
624 fn = iopgd_alloc_section;
626 case MMU_CAM_PGSZ_64K:
627 fn = iopte_alloc_large;
629 case MMU_CAM_PGSZ_4K:
630 fn = iopte_alloc_page;
638 prot = get_iopte_attr(e);
640 spin_lock(&obj->page_table_lock);
641 err = fn(obj, e->da, e->pa, prot);
642 spin_unlock(&obj->page_table_lock);
648 * omap_iopgtable_store_entry - Make an iommu pte entry
650 * @e: an iommu tlb entry info
652 int omap_iopgtable_store_entry(struct omap_iommu *obj, struct iotlb_entry *e)
656 flush_iotlb_page(obj, e->da);
657 err = iopgtable_store_entry_core(obj, e);
659 prefetch_iotlb_entry(obj, e);
662 EXPORT_SYMBOL_GPL(omap_iopgtable_store_entry);
665 * iopgtable_lookup_entry - Lookup an iommu pte entry
667 * @da: iommu device virtual address
668 * @ppgd: iommu pgd entry pointer to be returned
669 * @ppte: iommu pte entry pointer to be returned
672 iopgtable_lookup_entry(struct omap_iommu *obj, u32 da, u32 **ppgd, u32 **ppte)
674 u32 *iopgd, *iopte = NULL;
676 iopgd = iopgd_offset(obj, da);
680 if (iopgd_is_table(*iopgd))
681 iopte = iopte_offset(iopgd, da);
687 static size_t iopgtable_clear_entry_core(struct omap_iommu *obj, u32 da)
690 u32 *iopgd = iopgd_offset(obj, da);
696 if (iopgd_is_table(*iopgd)) {
698 u32 *iopte = iopte_offset(iopgd, da);
701 if (*iopte & IOPTE_LARGE) {
703 /* rewind to the 1st entry */
704 iopte = iopte_offset(iopgd, (da & IOLARGE_MASK));
707 memset(iopte, 0, nent * sizeof(*iopte));
708 flush_iopte_range(iopte, iopte + (nent - 1) * sizeof(*iopte));
711 * do table walk to check if this table is necessary or not
713 iopte = iopte_offset(iopgd, 0);
714 for (i = 0; i < PTRS_PER_IOPTE; i++)
719 nent = 1; /* for the next L1 entry */
722 if ((*iopgd & IOPGD_SUPER) == IOPGD_SUPER) {
724 /* rewind to the 1st entry */
725 iopgd = iopgd_offset(obj, (da & IOSUPER_MASK));
729 memset(iopgd, 0, nent * sizeof(*iopgd));
730 flush_iopgd_range(iopgd, iopgd + (nent - 1) * sizeof(*iopgd));
736 * iopgtable_clear_entry - Remove an iommu pte entry
738 * @da: iommu device virtual address
740 static size_t iopgtable_clear_entry(struct omap_iommu *obj, u32 da)
744 spin_lock(&obj->page_table_lock);
746 bytes = iopgtable_clear_entry_core(obj, da);
747 flush_iotlb_page(obj, da);
749 spin_unlock(&obj->page_table_lock);
754 static void iopgtable_clear_entry_all(struct omap_iommu *obj)
758 spin_lock(&obj->page_table_lock);
760 for (i = 0; i < PTRS_PER_IOPGD; i++) {
764 da = i << IOPGD_SHIFT;
765 iopgd = iopgd_offset(obj, da);
770 if (iopgd_is_table(*iopgd))
771 iopte_free(iopte_offset(iopgd, 0));
774 flush_iopgd_range(iopgd, iopgd);
777 flush_iotlb_all(obj);
779 spin_unlock(&obj->page_table_lock);
783 * Device IOMMU generic operations
785 static irqreturn_t iommu_fault_handler(int irq, void *data)
789 struct omap_iommu *obj = data;
790 struct iommu_domain *domain = obj->domain;
795 clk_enable(obj->clk);
796 errs = iommu_report_fault(obj, &da);
797 clk_disable(obj->clk);
801 /* Fault callback or TLB/PTE Dynamic loading */
802 if (!report_iommu_fault(domain, obj->dev, da, 0))
807 iopgd = iopgd_offset(obj, da);
809 if (!iopgd_is_table(*iopgd)) {
810 dev_err(obj->dev, "%s: errs:0x%08x da:0x%08x pgd:0x%p "
811 "*pgd:px%08x\n", obj->name, errs, da, iopgd, *iopgd);
815 iopte = iopte_offset(iopgd, da);
817 dev_err(obj->dev, "%s: errs:0x%08x da:0x%08x pgd:0x%p *pgd:0x%08x "
818 "pte:0x%p *pte:0x%08x\n", obj->name, errs, da, iopgd, *iopgd,
824 static int device_match_by_alias(struct device *dev, void *data)
826 struct omap_iommu *obj = to_iommu(dev);
827 const char *name = data;
829 pr_debug("%s: %s %s\n", __func__, obj->name, name);
831 return strcmp(obj->name, name) == 0;
835 * omap_iommu_attach() - attach iommu device to an iommu domain
836 * @name: name of target omap iommu device
839 static struct omap_iommu *omap_iommu_attach(const char *name, u32 *iopgd)
843 struct omap_iommu *obj;
845 dev = driver_find_device(&omap_iommu_driver.driver, NULL,
847 device_match_by_alias);
853 spin_lock(&obj->iommu_lock);
855 /* an iommu device can only be attached once */
856 if (++obj->refcount > 1) {
857 dev_err(dev, "%s: already attached!\n", obj->name);
863 err = iommu_enable(obj);
866 flush_iotlb_all(obj);
868 if (!try_module_get(obj->owner))
871 spin_unlock(&obj->iommu_lock);
873 dev_dbg(obj->dev, "%s: %s\n", __func__, obj->name);
877 if (obj->refcount == 1)
881 spin_unlock(&obj->iommu_lock);
886 * omap_iommu_detach - release iommu device
889 static void omap_iommu_detach(struct omap_iommu *obj)
891 if (!obj || IS_ERR(obj))
894 spin_lock(&obj->iommu_lock);
896 if (--obj->refcount == 0)
899 module_put(obj->owner);
903 spin_unlock(&obj->iommu_lock);
905 dev_dbg(obj->dev, "%s: %s\n", __func__, obj->name);
909 * OMAP Device MMU(IOMMU) detection
911 static int __devinit omap_iommu_probe(struct platform_device *pdev)
915 struct omap_iommu *obj;
916 struct resource *res;
917 struct iommu_platform_data *pdata = pdev->dev.platform_data;
919 if (pdev->num_resources != 2)
922 obj = kzalloc(sizeof(*obj) + MMU_REG_SIZE, GFP_KERNEL);
926 obj->clk = clk_get(&pdev->dev, pdata->clk_name);
927 if (IS_ERR(obj->clk))
930 obj->nr_tlb_entries = pdata->nr_tlb_entries;
931 obj->name = pdata->name;
932 obj->dev = &pdev->dev;
933 obj->ctx = (void *)obj + sizeof(*obj);
934 obj->da_start = pdata->da_start;
935 obj->da_end = pdata->da_end;
937 spin_lock_init(&obj->iommu_lock);
938 mutex_init(&obj->mmap_lock);
939 spin_lock_init(&obj->page_table_lock);
940 INIT_LIST_HEAD(&obj->mmap);
942 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
948 res = request_mem_region(res->start, resource_size(res),
949 dev_name(&pdev->dev));
955 obj->regbase = ioremap(res->start, resource_size(res));
961 irq = platform_get_irq(pdev, 0);
966 err = request_irq(irq, iommu_fault_handler, IRQF_SHARED,
967 dev_name(&pdev->dev), obj);
970 platform_set_drvdata(pdev, obj);
972 dev_info(&pdev->dev, "%s registered\n", obj->name);
976 iounmap(obj->regbase);
978 release_mem_region(res->start, resource_size(res));
986 static int __devexit omap_iommu_remove(struct platform_device *pdev)
989 struct resource *res;
990 struct omap_iommu *obj = platform_get_drvdata(pdev);
992 platform_set_drvdata(pdev, NULL);
994 iopgtable_clear_entry_all(obj);
996 irq = platform_get_irq(pdev, 0);
998 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
999 release_mem_region(res->start, resource_size(res));
1000 iounmap(obj->regbase);
1003 dev_info(&pdev->dev, "%s removed\n", obj->name);
1008 static struct platform_driver omap_iommu_driver = {
1009 .probe = omap_iommu_probe,
1010 .remove = __devexit_p(omap_iommu_remove),
1012 .name = "omap-iommu",
1016 static void iopte_cachep_ctor(void *iopte)
1018 clean_dcache_area(iopte, IOPTE_TABLE_SIZE);
1021 static u32 iotlb_init_entry(struct iotlb_entry *e, u32 da, u32 pa,
1024 memset(e, 0, sizeof(*e));
1029 /* FIXME: add OMAP1 support */
1030 e->pgsz = flags & MMU_CAM_PGSZ_MASK;
1031 e->endian = flags & MMU_RAM_ENDIAN_MASK;
1032 e->elsz = flags & MMU_RAM_ELSZ_MASK;
1033 e->mixed = flags & MMU_RAM_MIXED_MASK;
1035 return iopgsz_to_bytes(e->pgsz);
1038 static int omap_iommu_map(struct iommu_domain *domain, unsigned long da,
1039 phys_addr_t pa, size_t bytes, int prot)
1041 struct omap_iommu_domain *omap_domain = domain->priv;
1042 struct omap_iommu *oiommu = omap_domain->iommu_dev;
1043 struct device *dev = oiommu->dev;
1044 struct iotlb_entry e;
1048 /* we only support mapping a single iommu page for now */
1049 omap_pgsz = bytes_to_iopgsz(bytes);
1050 if (omap_pgsz < 0) {
1051 dev_err(dev, "invalid size to map: %d\n", bytes);
1055 dev_dbg(dev, "mapping da 0x%lx to pa 0x%x size 0x%x\n", da, pa, bytes);
1057 flags = omap_pgsz | prot;
1059 iotlb_init_entry(&e, da, pa, flags);
1061 ret = omap_iopgtable_store_entry(oiommu, &e);
1063 dev_err(dev, "omap_iopgtable_store_entry failed: %d\n", ret);
1068 static size_t omap_iommu_unmap(struct iommu_domain *domain, unsigned long da,
1071 struct omap_iommu_domain *omap_domain = domain->priv;
1072 struct omap_iommu *oiommu = omap_domain->iommu_dev;
1073 struct device *dev = oiommu->dev;
1075 dev_dbg(dev, "unmapping da 0x%lx size %u\n", da, size);
1077 return iopgtable_clear_entry(oiommu, da);
1081 omap_iommu_attach_dev(struct iommu_domain *domain, struct device *dev)
1083 struct omap_iommu_domain *omap_domain = domain->priv;
1084 struct omap_iommu *oiommu;
1085 struct omap_iommu_arch_data *arch_data = dev->archdata.iommu;
1088 spin_lock(&omap_domain->lock);
1090 /* only a single device is supported per domain for now */
1091 if (omap_domain->iommu_dev) {
1092 dev_err(dev, "iommu domain is already attached\n");
1097 /* get a handle to and enable the omap iommu */
1098 oiommu = omap_iommu_attach(arch_data->name, omap_domain->pgtable);
1099 if (IS_ERR(oiommu)) {
1100 ret = PTR_ERR(oiommu);
1101 dev_err(dev, "can't get omap iommu: %d\n", ret);
1105 omap_domain->iommu_dev = arch_data->iommu_dev = oiommu;
1106 omap_domain->dev = dev;
1107 oiommu->domain = domain;
1110 spin_unlock(&omap_domain->lock);
1114 static void _omap_iommu_detach_dev(struct omap_iommu_domain *omap_domain,
1117 struct omap_iommu *oiommu = dev_to_omap_iommu(dev);
1118 struct omap_iommu_arch_data *arch_data = dev->archdata.iommu;
1120 /* only a single device is supported per domain for now */
1121 if (omap_domain->iommu_dev != oiommu) {
1122 dev_err(dev, "invalid iommu device\n");
1126 iopgtable_clear_entry_all(oiommu);
1128 omap_iommu_detach(oiommu);
1130 omap_domain->iommu_dev = arch_data->iommu_dev = NULL;
1131 omap_domain->dev = NULL;
1134 static void omap_iommu_detach_dev(struct iommu_domain *domain,
1137 struct omap_iommu_domain *omap_domain = domain->priv;
1139 spin_lock(&omap_domain->lock);
1140 _omap_iommu_detach_dev(omap_domain, dev);
1141 spin_unlock(&omap_domain->lock);
1144 static int omap_iommu_domain_init(struct iommu_domain *domain)
1146 struct omap_iommu_domain *omap_domain;
1148 omap_domain = kzalloc(sizeof(*omap_domain), GFP_KERNEL);
1150 pr_err("kzalloc failed\n");
1154 omap_domain->pgtable = kzalloc(IOPGD_TABLE_SIZE, GFP_KERNEL);
1155 if (!omap_domain->pgtable) {
1156 pr_err("kzalloc failed\n");
1161 * should never fail, but please keep this around to ensure
1162 * we keep the hardware happy
1164 BUG_ON(!IS_ALIGNED((long)omap_domain->pgtable, IOPGD_TABLE_SIZE));
1166 clean_dcache_area(omap_domain->pgtable, IOPGD_TABLE_SIZE);
1167 spin_lock_init(&omap_domain->lock);
1169 domain->priv = omap_domain;
1171 domain->geometry.aperture_start = 0;
1172 domain->geometry.aperture_end = (1ULL << 32) - 1;
1173 domain->geometry.force_aperture = true;
1183 static void omap_iommu_domain_destroy(struct iommu_domain *domain)
1185 struct omap_iommu_domain *omap_domain = domain->priv;
1187 domain->priv = NULL;
1190 * An iommu device is still attached
1191 * (currently, only one device can be attached) ?
1193 if (omap_domain->iommu_dev)
1194 _omap_iommu_detach_dev(omap_domain, omap_domain->dev);
1196 kfree(omap_domain->pgtable);
1200 static phys_addr_t omap_iommu_iova_to_phys(struct iommu_domain *domain,
1203 struct omap_iommu_domain *omap_domain = domain->priv;
1204 struct omap_iommu *oiommu = omap_domain->iommu_dev;
1205 struct device *dev = oiommu->dev;
1207 phys_addr_t ret = 0;
1209 iopgtable_lookup_entry(oiommu, da, &pgd, &pte);
1212 if (iopte_is_small(*pte))
1213 ret = omap_iommu_translate(*pte, da, IOPTE_MASK);
1214 else if (iopte_is_large(*pte))
1215 ret = omap_iommu_translate(*pte, da, IOLARGE_MASK);
1217 dev_err(dev, "bogus pte 0x%x, da 0x%lx", *pte, da);
1219 if (iopgd_is_section(*pgd))
1220 ret = omap_iommu_translate(*pgd, da, IOSECTION_MASK);
1221 else if (iopgd_is_super(*pgd))
1222 ret = omap_iommu_translate(*pgd, da, IOSUPER_MASK);
1224 dev_err(dev, "bogus pgd 0x%x, da 0x%lx", *pgd, da);
1230 static int omap_iommu_domain_has_cap(struct iommu_domain *domain,
1236 static struct iommu_ops omap_iommu_ops = {
1237 .domain_init = omap_iommu_domain_init,
1238 .domain_destroy = omap_iommu_domain_destroy,
1239 .attach_dev = omap_iommu_attach_dev,
1240 .detach_dev = omap_iommu_detach_dev,
1241 .map = omap_iommu_map,
1242 .unmap = omap_iommu_unmap,
1243 .iova_to_phys = omap_iommu_iova_to_phys,
1244 .domain_has_cap = omap_iommu_domain_has_cap,
1245 .pgsize_bitmap = OMAP_IOMMU_PGSIZES,
1248 static int __init omap_iommu_init(void)
1250 struct kmem_cache *p;
1251 const unsigned long flags = SLAB_HWCACHE_ALIGN;
1252 size_t align = 1 << 10; /* L2 pagetable alignement */
1254 p = kmem_cache_create("iopte_cache", IOPTE_TABLE_SIZE, align, flags,
1260 bus_set_iommu(&platform_bus_type, &omap_iommu_ops);
1262 return platform_driver_register(&omap_iommu_driver);
1264 /* must be ready before omap3isp is probed */
1265 subsys_initcall(omap_iommu_init);
1267 static void __exit omap_iommu_exit(void)
1269 kmem_cache_destroy(iopte_cachep);
1271 platform_driver_unregister(&omap_iommu_driver);
1273 module_exit(omap_iommu_exit);
1275 MODULE_DESCRIPTION("omap iommu: tlb and pagetable primitives");
1276 MODULE_ALIAS("platform:omap-iommu");
1277 MODULE_AUTHOR("Hiroshi DOYU, Paul Mundt and Toshihiro Kobayashi");
1278 MODULE_LICENSE("GPL v2");