2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License version 2 as
4 * published by the Free Software Foundation.
7 #ifdef CONFIG_ROCKCHIP_IOMMU_DEBUG
12 #include <linux/interrupt.h>
13 #include <linux/slab.h>
14 #include <linux/clk.h>
15 #include <linux/err.h>
17 #include <linux/errno.h>
18 #include <linux/memblock.h>
19 #include <linux/export.h>
20 #include <linux/module.h>
22 #include <asm/cacheflush.h>
23 #include <asm/pgtable.h>
25 #include <linux/rockchip-iovmm.h>
26 #include <linux/rockchip/grf.h>
27 #include <linux/rockchip/cpu.h>
28 #include <linux/rockchip/iomap.h>
29 #include <linux/device.h>
32 /* We does not consider super section mapping (16MB) */
33 #define SPAGE_ORDER 12
34 #define SPAGE_SIZE (1 << SPAGE_ORDER)
35 #define SPAGE_MASK (~(SPAGE_SIZE - 1))
37 static void __iomem *rk312x_vop_mmu_base;
39 enum iommu_entry_flags {
40 IOMMU_FLAGS_PRESENT = 0x01,
41 IOMMU_FLAGS_READ_PERMISSION = 0x02,
42 IOMMU_FLAGS_WRITE_PERMISSION = 0x04,
43 IOMMU_FLAGS_OVERRIDE_CACHE = 0x8,
44 IOMMU_FLAGS_WRITE_CACHEABLE = 0x10,
45 IOMMU_FLAGS_WRITE_ALLOCATE = 0x20,
46 IOMMU_FLAGS_WRITE_BUFFERABLE = 0x40,
47 IOMMU_FLAGS_READ_CACHEABLE = 0x80,
48 IOMMU_FLAGS_READ_ALLOCATE = 0x100,
49 IOMMU_FLAGS_MASK = 0x1FF,
52 #define rockchip_lv1ent_fault(sent) ((*(sent) & IOMMU_FLAGS_PRESENT) == 0)
53 #define rockchip_lv1ent_page(sent) ((*(sent) & IOMMU_FLAGS_PRESENT) == 1)
54 #define rockchip_lv2ent_fault(pent) ((*(pent) & IOMMU_FLAGS_PRESENT) == 0)
55 #define rockchip_spage_phys(pent) (*(pent) & SPAGE_MASK)
56 #define rockchip_spage_offs(iova) ((iova) & 0x0FFF)
58 #define rockchip_lv1ent_offset(iova) (((iova)>>22) & 0x03FF)
59 #define rockchip_lv2ent_offset(iova) (((iova)>>12) & 0x03FF)
61 #define NUM_LV1ENTRIES 1024
62 #define NUM_LV2ENTRIES 1024
64 #define LV2TABLE_SIZE (NUM_LV2ENTRIES * sizeof(long))
66 #define rockchip_lv2table_base(sent) (*(sent) & 0xFFFFFFFE)
68 #define rockchip_mk_lv1ent_page(pa) ((pa) | IOMMU_FLAGS_PRESENT)
69 /*write and read permission for level2 page default*/
70 #define rockchip_mk_lv2ent_spage(pa) ((pa) | IOMMU_FLAGS_PRESENT | \
71 IOMMU_FLAGS_READ_PERMISSION | \
72 IOMMU_FLAGS_WRITE_PERMISSION)
74 #define IOMMU_REG_POLL_COUNT_FAST 1000
77 * MMU register numbers
78 * Used in the register read/write routines.
79 * See the hardware documentation for more information about each register
82 /**< Current Page Directory Pointer */
83 IOMMU_REGISTER_DTE_ADDR = 0x0000,
84 /**< Status of the MMU */
85 IOMMU_REGISTER_STATUS = 0x0004,
86 /**< Command register, used to control the MMU */
87 IOMMU_REGISTER_COMMAND = 0x0008,
88 /**< Logical address of the last page fault */
89 IOMMU_REGISTER_PAGE_FAULT_ADDR = 0x000C,
90 /**< Used to invalidate the mapping of a single page from the MMU */
91 IOMMU_REGISTER_ZAP_ONE_LINE = 0x010,
92 /**< Raw interrupt status, all interrupts visible */
93 IOMMU_REGISTER_INT_RAWSTAT = 0x0014,
94 /**< Indicate to the MMU that the interrupt has been received */
95 IOMMU_REGISTER_INT_CLEAR = 0x0018,
96 /**< Enable/disable types of interrupts */
97 IOMMU_REGISTER_INT_MASK = 0x001C,
98 /**< Interrupt status based on the mask */
99 IOMMU_REGISTER_INT_STATUS = 0x0020,
100 IOMMU_REGISTER_AUTO_GATING = 0x0024
104 /**< Enable paging (memory translation) */
105 IOMMU_COMMAND_ENABLE_PAGING = 0x00,
106 /**< Disable paging (memory translation) */
107 IOMMU_COMMAND_DISABLE_PAGING = 0x01,
108 /**< Enable stall on page fault */
109 IOMMU_COMMAND_ENABLE_STALL = 0x02,
110 /**< Disable stall on page fault */
111 IOMMU_COMMAND_DISABLE_STALL = 0x03,
112 /**< Zap the entire page table cache */
113 IOMMU_COMMAND_ZAP_CACHE = 0x04,
114 /**< Page fault processed */
115 IOMMU_COMMAND_PAGE_FAULT_DONE = 0x05,
116 /**< Reset the MMU back to power-on settings */
117 IOMMU_COMMAND_HARD_RESET = 0x06
121 * MMU interrupt register bits
122 * Each cause of the interrupt is reported
123 * through the (raw) interrupt status registers.
124 * Multiple interrupts can be pending, so multiple bits
125 * can be set at once.
127 enum iommu_interrupt {
128 IOMMU_INTERRUPT_PAGE_FAULT = 0x01, /**< A page fault occured */
129 IOMMU_INTERRUPT_READ_BUS_ERROR = 0x02 /**< A bus read error occured */
132 enum iommu_status_bits {
133 IOMMU_STATUS_BIT_PAGING_ENABLED = 1 << 0,
134 IOMMU_STATUS_BIT_PAGE_FAULT_ACTIVE = 1 << 1,
135 IOMMU_STATUS_BIT_STALL_ACTIVE = 1 << 2,
136 IOMMU_STATUS_BIT_IDLE = 1 << 3,
137 IOMMU_STATUS_BIT_REPLAY_BUFFER_EMPTY = 1 << 4,
138 IOMMU_STATUS_BIT_PAGE_FAULT_IS_WRITE = 1 << 5,
139 IOMMU_STATUS_BIT_STALL_NOT_ACTIVE = 1 << 31,
143 * Size of an MMU page in bytes
145 #define IOMMU_PAGE_SIZE 0x1000
148 * Size of the address space referenced by a page table page
150 #define IOMMU_VIRTUAL_PAGE_SIZE 0x400000 /* 4 MiB */
153 * Page directory index from address
154 * Calculates the page directory index from the given address
156 #define IOMMU_PDE_ENTRY(address) (((address)>>22) & 0x03FF)
159 * Page table index from address
160 * Calculates the page table index from the given address
162 #define IOMMU_PTE_ENTRY(address) (((address)>>12) & 0x03FF)
165 * Extract the memory address from an PDE/PTE entry
167 #define IOMMU_ENTRY_ADDRESS(value) ((value) & 0xFFFFFC00)
169 #define INVALID_PAGE ((u32)(~0))
171 static struct kmem_cache *lv2table_kmem_cache;
173 static unsigned int *rockchip_section_entry(unsigned int *pgtable, unsigned long iova)
175 return pgtable + rockchip_lv1ent_offset(iova);
178 static unsigned int *rockchip_page_entry(unsigned int *sent, unsigned long iova)
180 return (unsigned int *)phys_to_virt(rockchip_lv2table_base(sent)) +
181 rockchip_lv2ent_offset(iova);
184 struct rk_iommu_domain {
185 struct list_head clients; /* list of iommu_drvdata.node */
186 unsigned int *pgtable; /* lv1 page table, 4KB */
187 short *lv2entcnt; /* free lv2 entry counter for each section */
188 spinlock_t lock; /* lock for this structure */
189 spinlock_t pgtablelock; /* lock for modifying page table @ pgtable */
190 struct iommu_domain domain;
193 static struct rk_iommu_domain *to_rk_domain(struct iommu_domain *dom)
195 return container_of(dom, struct rk_iommu_domain, domain);
198 static bool rockchip_set_iommu_active(struct iommu_drvdata *data)
200 /* return true if the IOMMU was not active previously
201 and it needs to be initialized */
202 return ++data->activations == 1;
205 static bool rockchip_set_iommu_inactive(struct iommu_drvdata *data)
207 /* return true if the IOMMU is needed to be disabled */
208 BUG_ON(data->activations < 1);
209 return --data->activations == 0;
212 static bool rockchip_is_iommu_active(struct iommu_drvdata *data)
214 return data->activations > 0;
217 static void rockchip_iommu_disable_stall(void __iomem *base)
222 if (base != rk312x_vop_mmu_base) {
223 mmu_status = __raw_readl(base + IOMMU_REGISTER_STATUS);
225 goto skip_vop_mmu_disable;
228 if (0 == (mmu_status & IOMMU_STATUS_BIT_PAGING_ENABLED)) {
232 if (mmu_status & IOMMU_STATUS_BIT_PAGE_FAULT_ACTIVE) {
233 pr_info("Aborting MMU disable stall request since it is in pagefault state.\n");
237 if (!(mmu_status & IOMMU_STATUS_BIT_STALL_ACTIVE)) {
241 __raw_writel(IOMMU_COMMAND_DISABLE_STALL, base + IOMMU_REGISTER_COMMAND);
243 skip_vop_mmu_disable:
245 for (i = 0; i < IOMMU_REG_POLL_COUNT_FAST; ++i) {
248 if (base != rk312x_vop_mmu_base) {
249 status = __raw_readl(base + IOMMU_REGISTER_STATUS);
257 if (0 == (status & IOMMU_STATUS_BIT_STALL_ACTIVE))
260 if (status & IOMMU_STATUS_BIT_PAGE_FAULT_ACTIVE)
263 if (0 == (mmu_status & IOMMU_STATUS_BIT_PAGING_ENABLED))
267 if (IOMMU_REG_POLL_COUNT_FAST == i) {
268 pr_info("Disable stall request failed, MMU status is 0x%08X\n",
269 __raw_readl(base + IOMMU_REGISTER_STATUS));
273 static bool rockchip_iommu_enable_stall(void __iomem *base)
279 if (base != rk312x_vop_mmu_base) {
280 mmu_status = __raw_readl(base + IOMMU_REGISTER_STATUS);
282 goto skip_vop_mmu_enable;
285 if (0 == (mmu_status & IOMMU_STATUS_BIT_PAGING_ENABLED)) {
289 if (mmu_status & IOMMU_STATUS_BIT_STALL_ACTIVE){
290 pr_info("MMU stall already enabled\n");
294 if (mmu_status & IOMMU_STATUS_BIT_PAGE_FAULT_ACTIVE) {
295 pr_info("Aborting MMU stall request since it is in pagefault state. mmu status is 0x%08x\n",
300 __raw_writel(IOMMU_COMMAND_ENABLE_STALL, base + IOMMU_REGISTER_COMMAND);
304 for (i = 0; i < IOMMU_REG_POLL_COUNT_FAST; ++i) {
305 if (base != rk312x_vop_mmu_base) {
306 mmu_status = __raw_readl(base + IOMMU_REGISTER_STATUS);
314 if (mmu_status & IOMMU_STATUS_BIT_PAGE_FAULT_ACTIVE)
317 if ((mmu_status & IOMMU_STATUS_BIT_STALL_ACTIVE) &&
318 (0 == (mmu_status & IOMMU_STATUS_BIT_STALL_NOT_ACTIVE)))
321 if (0 == (mmu_status & (IOMMU_STATUS_BIT_PAGING_ENABLED)))
325 if (IOMMU_REG_POLL_COUNT_FAST == i) {
326 pr_info("Enable stall request failed, MMU status is 0x%08X\n",
327 __raw_readl(base + IOMMU_REGISTER_STATUS));
331 if (mmu_status & IOMMU_STATUS_BIT_PAGE_FAULT_ACTIVE) {
332 pr_info("Aborting MMU stall request since it has a pagefault.\n");
339 static bool rockchip_iommu_enable_paging(void __iomem *base)
343 __raw_writel(IOMMU_COMMAND_ENABLE_PAGING,
344 base + IOMMU_REGISTER_COMMAND);
346 for (i = 0; i < IOMMU_REG_POLL_COUNT_FAST; ++i) {
347 if (base != rk312x_vop_mmu_base) {
348 if (__raw_readl(base + IOMMU_REGISTER_STATUS) &
349 IOMMU_STATUS_BIT_PAGING_ENABLED)
359 if (IOMMU_REG_POLL_COUNT_FAST == i) {
360 pr_info("Enable paging request failed, MMU status is 0x%08X\n",
361 __raw_readl(base + IOMMU_REGISTER_STATUS));
368 static bool rockchip_iommu_disable_paging(void __iomem *base)
372 __raw_writel(IOMMU_COMMAND_DISABLE_PAGING,
373 base + IOMMU_REGISTER_COMMAND);
375 for (i = 0; i < IOMMU_REG_POLL_COUNT_FAST; ++i) {
376 if (base != rk312x_vop_mmu_base) {
377 if (!(__raw_readl(base + IOMMU_REGISTER_STATUS) &
378 IOMMU_STATUS_BIT_PAGING_ENABLED))
388 if (IOMMU_REG_POLL_COUNT_FAST == i) {
389 pr_info("Disable paging request failed, MMU status is 0x%08X\n",
390 __raw_readl(base + IOMMU_REGISTER_STATUS));
397 static void rockchip_iommu_page_fault_done(void __iomem *base, const char *dbgname)
399 pr_info("MMU: %s: Leaving page fault mode\n",
401 __raw_writel(IOMMU_COMMAND_PAGE_FAULT_DONE,
402 base + IOMMU_REGISTER_COMMAND);
405 static int rockchip_iommu_zap_tlb_without_stall (void __iomem *base)
407 __raw_writel(IOMMU_COMMAND_ZAP_CACHE, base + IOMMU_REGISTER_COMMAND);
412 static int rockchip_iommu_zap_tlb(void __iomem *base)
414 if (!rockchip_iommu_enable_stall(base)) {
415 pr_err("%s failed\n", __func__);
419 __raw_writel(IOMMU_COMMAND_ZAP_CACHE, base + IOMMU_REGISTER_COMMAND);
421 rockchip_iommu_disable_stall(base);
426 static inline bool rockchip_iommu_raw_reset(void __iomem *base)
430 unsigned int grf_value;
432 __raw_writel(0xCAFEBABE, base + IOMMU_REGISTER_DTE_ADDR);
434 if (base != rk312x_vop_mmu_base) {
435 ret = __raw_readl(base + IOMMU_REGISTER_DTE_ADDR);
436 if (!(0xCAFEB000 == ret)) {
437 grf_value = readl_relaxed(RK_GRF_VIRT + RK3036_GRF_SOC_CON1);
438 pr_info("error when %s. grf = 0x%08x\n", __func__, grf_value);
442 __raw_writel(IOMMU_COMMAND_HARD_RESET,
443 base + IOMMU_REGISTER_COMMAND);
445 for (i = 0; i < IOMMU_REG_POLL_COUNT_FAST; ++i) {
446 if (base != rk312x_vop_mmu_base) {
447 if (__raw_readl(base + IOMMU_REGISTER_DTE_ADDR) == 0)
457 if (IOMMU_REG_POLL_COUNT_FAST == i) {
458 pr_info("%s,Reset request failed, MMU status is 0x%08X\n",
459 __func__, __raw_readl(base + IOMMU_REGISTER_DTE_ADDR));
465 static void rockchip_iommu_set_ptbase(void __iomem *base, unsigned int pgd)
467 __raw_writel(pgd, base + IOMMU_REGISTER_DTE_ADDR);
470 static bool rockchip_iommu_reset(void __iomem *base, const char *dbgname)
474 ret = rockchip_iommu_raw_reset(base);
476 pr_info("(%s), %s failed\n", dbgname, __func__);
480 if (base != rk312x_vop_mmu_base)
481 __raw_writel(IOMMU_INTERRUPT_PAGE_FAULT |
482 IOMMU_INTERRUPT_READ_BUS_ERROR,
483 base + IOMMU_REGISTER_INT_MASK);
485 __raw_writel(0x00, base + IOMMU_REGISTER_INT_MASK);
490 static inline void rockchip_pgtable_flush(void *vastart, void *vaend)
493 dmac_flush_range(vastart, vaend);
494 outer_flush_range(virt_to_phys(vastart), virt_to_phys(vaend));
495 #elif defined(CONFIG_ARM64)
496 __dma_flush_range(vastart, vaend);
501 static void dump_pagetbl(dma_addr_t fault_address, u32 addr_dte)
503 u32 dte_index, pte_index, page_offset;
505 phys_addr_t mmu_dte_addr_phys, dte_addr_phys;
508 phys_addr_t pte_addr_phys = 0;
509 u32 *pte_addr = NULL;
511 phys_addr_t page_addr_phys = 0;
514 dte_index = rockchip_lv1ent_offset(fault_address);
515 pte_index = rockchip_lv2ent_offset(fault_address);
516 page_offset = (u32)(fault_address & 0x00000fff);
518 mmu_dte_addr = addr_dte;
519 mmu_dte_addr_phys = (phys_addr_t)mmu_dte_addr;
521 dte_addr_phys = mmu_dte_addr_phys + (4 * dte_index);
522 dte_addr = phys_to_virt(dte_addr_phys);
525 if (!(IOMMU_FLAGS_PRESENT & dte))
528 pte_addr_phys = ((phys_addr_t)dte & 0xfffff000) + (pte_index * 4);
529 pte_addr = phys_to_virt(pte_addr_phys);
532 if (!(IOMMU_FLAGS_PRESENT & pte))
535 page_addr_phys = ((phys_addr_t)pte & 0xfffff000) + page_offset;
536 page_flags = pte & 0x000001fe;
539 pr_err("iova = %pad: dte_index: 0x%03x pte_index: 0x%03x page_offset: 0x%03x\n",
540 &fault_address, dte_index, pte_index, page_offset);
541 pr_err("mmu_dte_addr: %pa dte@%pa: %#08x valid: %u pte@%pa: %#08x valid: %u page@%pa flags: %#03x\n",
542 &mmu_dte_addr_phys, &dte_addr_phys, dte,
543 (dte & IOMMU_FLAGS_PRESENT), &pte_addr_phys, pte,
544 (pte & IOMMU_FLAGS_PRESENT), &page_addr_phys, page_flags);
547 static irqreturn_t rockchip_iommu_irq(int irq, void *dev_id)
549 /* SYSMMU is in blocked when interrupt occurred. */
550 struct iommu_drvdata *data = dev_id;
553 dma_addr_t fault_address;
559 spin_lock_irqsave(&data->data_lock, flags);
561 if (!rockchip_is_iommu_active(data)) {
562 spin_unlock_irqrestore(&data->data_lock, flags);
566 for (i = 0; i < data->num_res_mem; i++) {
567 status = __raw_readl(data->res_bases[i] +
568 IOMMU_REGISTER_INT_STATUS);
572 rawstat = __raw_readl(data->res_bases[i] +
573 IOMMU_REGISTER_INT_RAWSTAT);
575 reg_status = __raw_readl(data->res_bases[i] +
576 IOMMU_REGISTER_STATUS);
578 dev_info(data->iommu, "1.rawstat = 0x%08x,status = 0x%08x,reg_status = 0x%08x\n",
579 rawstat, status, reg_status);
581 if (rawstat & IOMMU_INTERRUPT_PAGE_FAULT) {
585 fault_address = __raw_readl(data->res_bases[i] +
586 IOMMU_REGISTER_PAGE_FAULT_ADDR);
588 dte = __raw_readl(data->res_bases[i] +
589 IOMMU_REGISTER_DTE_ADDR);
591 flags = (status & 32) ? 1 : 0;
593 dev_err(data->iommu, "Page fault detected at %pad from bus id %d of type %s on %s\n",
594 &fault_address, (status >> 6) & 0x1F,
595 (flags == 1) ? "write" : "read", data->dbgname);
597 dump_pagetbl(fault_address, dte);
600 report_iommu_fault(data->domain, data->iommu,
601 fault_address, flags);
602 if (data->fault_handler)
603 data->fault_handler(data->master, IOMMU_PAGEFAULT, dte, fault_address, 1);
605 rockchip_iommu_page_fault_done(data->res_bases[i],
609 if (rawstat & IOMMU_INTERRUPT_READ_BUS_ERROR) {
610 dev_err(data->iommu, "bus error occured at %pad\n",
614 if (rawstat & ~(IOMMU_INTERRUPT_READ_BUS_ERROR |
615 IOMMU_INTERRUPT_PAGE_FAULT)) {
616 dev_err(data->iommu, "unexpected int_status: %#08x\n\n",
620 __raw_writel(rawstat, data->res_bases[i] +
621 IOMMU_REGISTER_INT_CLEAR);
623 status = __raw_readl(data->res_bases[i] +
624 IOMMU_REGISTER_INT_STATUS);
626 rawstat = __raw_readl(data->res_bases[i] +
627 IOMMU_REGISTER_INT_RAWSTAT);
629 reg_status = __raw_readl(data->res_bases[i] +
630 IOMMU_REGISTER_STATUS);
632 dev_info(data->iommu, "2.rawstat = 0x%08x,status = 0x%08x,reg_status = 0x%08x\n",
633 rawstat, status, reg_status);
635 ret = rockchip_iommu_zap_tlb_without_stall(data->res_bases[i]);
637 dev_err(data->iommu, "(%s) %s failed\n", data->dbgname,
641 spin_unlock_irqrestore(&data->data_lock, flags);
645 static bool rockchip_iommu_disable(struct iommu_drvdata *data)
651 spin_lock_irqsave(&data->data_lock, flags);
653 if (!rockchip_set_iommu_inactive(data)) {
654 spin_unlock_irqrestore(&data->data_lock, flags);
655 dev_info(data->iommu,"(%s) %d times left to be disabled\n",
656 data->dbgname, data->activations);
660 for (i = 0; i < data->num_res_mem; i++) {
661 ret = rockchip_iommu_enable_stall(data->res_bases[i]);
663 dev_info(data->iommu, "(%s), %s failed\n",
664 data->dbgname, __func__);
665 spin_unlock_irqrestore(&data->data_lock, flags);
669 __raw_writel(0, data->res_bases[i] + IOMMU_REGISTER_INT_MASK);
671 ret = rockchip_iommu_disable_paging(data->res_bases[i]);
673 rockchip_iommu_disable_stall(data->res_bases[i]);
674 spin_unlock_irqrestore(&data->data_lock, flags);
675 dev_info(data->iommu, "%s error\n", __func__);
678 rockchip_iommu_disable_stall(data->res_bases[i]);
683 spin_unlock_irqrestore(&data->data_lock, flags);
685 dev_dbg(data->iommu,"(%s) Disabled\n", data->dbgname);
690 /* __rk_sysmmu_enable: Enables System MMU
692 * returns -error if an error occurred and System MMU is not enabled,
693 * 0 if the System MMU has been just enabled and 1 if System MMU was already
696 static int rockchip_iommu_enable(struct iommu_drvdata *data, unsigned int pgtable)
701 spin_lock_irqsave(&data->data_lock, flags);
703 if (!rockchip_set_iommu_active(data)) {
704 if (WARN_ON(pgtable != data->pgtable)) {
706 rockchip_set_iommu_inactive(data);
711 spin_unlock_irqrestore(&data->data_lock, flags);
712 dev_info(data->iommu, "(%s) Already enabled\n", data->dbgname);
717 for (i = 0; i < data->num_res_mem; i++) {
718 ret = rockchip_iommu_enable_stall(data->res_bases[i]);
720 dev_info(data->iommu, "(%s), %s failed\n",
721 data->dbgname, __func__);
722 spin_unlock_irqrestore(&data->data_lock, flags);
726 if (!strstr(data->dbgname, "isp")) {
727 if (!rockchip_iommu_reset(data->res_bases[i],
729 spin_unlock_irqrestore(&data->data_lock, flags);
734 rockchip_iommu_set_ptbase(data->res_bases[i], pgtable);
736 __raw_writel(IOMMU_COMMAND_ZAP_CACHE, data->res_bases[i] +
737 IOMMU_REGISTER_COMMAND);
739 if (strstr(data->dbgname, "isp")) {
740 __raw_writel(IOMMU_INTERRUPT_PAGE_FAULT |
741 IOMMU_INTERRUPT_READ_BUS_ERROR,
742 data->res_bases[i] + IOMMU_REGISTER_INT_MASK);
745 ret = rockchip_iommu_enable_paging(data->res_bases[i]);
747 spin_unlock_irqrestore(&data->data_lock, flags);
748 dev_info(data->iommu, "(%s), %s failed\n",
749 data->dbgname, __func__);
753 rockchip_iommu_disable_stall(data->res_bases[i]);
756 data->pgtable = pgtable;
758 dev_dbg(data->iommu,"(%s) Enabled\n", data->dbgname);
760 spin_unlock_irqrestore(&data->data_lock, flags);
765 int rockchip_iommu_tlb_invalidate_global(struct device *dev)
768 struct iommu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
771 spin_lock_irqsave(&data->data_lock, flags);
773 if (rockchip_is_iommu_active(data)) {
776 for (i = 0; i < data->num_res_mem; i++) {
777 ret = rockchip_iommu_zap_tlb(data->res_bases[i]);
779 dev_err(dev->archdata.iommu, "(%s) %s failed\n",
780 data->dbgname, __func__);
783 dev_dbg(dev->archdata.iommu, "(%s) Disabled. Skipping invalidating TLB.\n",
788 spin_unlock_irqrestore(&data->data_lock, flags);
793 int rockchip_iommu_tlb_invalidate(struct device *dev)
796 struct iommu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
798 if (strstr(data->dbgname, "vpu") || strstr(data->dbgname, "hevc"))
801 spin_lock_irqsave(&data->data_lock, flags);
803 if (rockchip_is_iommu_active(data)) {
807 for (i = 0; i < data->num_res_mem; i++) {
808 ret = rockchip_iommu_zap_tlb(data->res_bases[i]);
810 dev_err(dev->archdata.iommu, "(%s) %s failed\n",
811 data->dbgname, __func__);
812 spin_unlock_irqrestore(&data->data_lock, flags);
818 dev_dbg(dev->archdata.iommu, "(%s) Disabled. Skipping invalidating TLB.\n",
822 spin_unlock_irqrestore(&data->data_lock, flags);
827 static phys_addr_t rockchip_iommu_iova_to_phys(struct iommu_domain *domain,
830 struct rk_iommu_domain *priv = to_rk_domain(domain);
833 phys_addr_t phys = 0;
835 spin_lock_irqsave(&priv->pgtablelock, flags);
837 entry = rockchip_section_entry(priv->pgtable, iova);
838 entry = rockchip_page_entry(entry, iova);
839 phys = rockchip_spage_phys(entry) + rockchip_spage_offs(iova);
841 spin_unlock_irqrestore(&priv->pgtablelock, flags);
846 static int rockchip_lv2set_page(unsigned int *pent, phys_addr_t paddr,
847 size_t size, short *pgcnt)
849 if (!rockchip_lv2ent_fault(pent))
852 *pent = rockchip_mk_lv2ent_spage(paddr);
853 rockchip_pgtable_flush(pent, pent + 1);
858 static unsigned int *rockchip_alloc_lv2entry(unsigned int *sent,
859 unsigned long iova, short *pgcounter)
861 if (rockchip_lv1ent_fault(sent)) {
864 pent = kmem_cache_zalloc(lv2table_kmem_cache, GFP_ATOMIC);
865 BUG_ON((unsigned long)pent & (LV2TABLE_SIZE - 1));
869 *sent = rockchip_mk_lv1ent_page(virt_to_phys(pent));
870 kmemleak_ignore(pent);
871 *pgcounter = NUM_LV2ENTRIES;
872 rockchip_pgtable_flush(pent, pent + NUM_LV2ENTRIES);
873 rockchip_pgtable_flush(sent, sent + 1);
875 return rockchip_page_entry(sent, iova);
878 static size_t rockchip_iommu_unmap(struct iommu_domain *domain,
879 unsigned long iova, size_t size)
881 struct rk_iommu_domain *priv = to_rk_domain(domain);
885 BUG_ON(priv->pgtable == NULL);
887 spin_lock_irqsave(&priv->pgtablelock, flags);
889 ent = rockchip_section_entry(priv->pgtable, iova);
891 if (unlikely(rockchip_lv1ent_fault(ent))) {
892 if (size > SPAGE_SIZE)
897 /* lv1ent_page(sent) == true here */
899 ent = rockchip_page_entry(ent, iova);
901 if (unlikely(rockchip_lv2ent_fault(ent))) {
908 priv->lv2entcnt[rockchip_lv1ent_offset(iova)] += 1;
912 pr_debug("%s:unmap iova 0x%lx/%zx bytes\n",
913 __func__, iova,size);
914 spin_unlock_irqrestore(&priv->pgtablelock, flags);
919 static int rockchip_iommu_map(struct iommu_domain *domain, unsigned long iova,
920 phys_addr_t paddr, size_t size, int prot)
922 struct rk_iommu_domain *priv = to_rk_domain(domain);
928 BUG_ON(priv->pgtable == NULL);
930 spin_lock_irqsave(&priv->pgtablelock, flags);
932 entry = rockchip_section_entry(priv->pgtable, iova);
934 pent = rockchip_alloc_lv2entry(entry, iova,
935 &priv->lv2entcnt[rockchip_lv1ent_offset(iova)]);
939 ret = rockchip_lv2set_page(pent, paddr, size,
940 &priv->lv2entcnt[rockchip_lv1ent_offset(iova)]);
943 pr_info("%s: Failed to map iova 0x%lx/%zx bytes\n", __func__,
946 spin_unlock_irqrestore(&priv->pgtablelock, flags);
951 static void rockchip_iommu_detach_device(struct iommu_domain *domain, struct device *dev)
953 struct iommu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
954 struct rk_iommu_domain *priv = to_rk_domain(domain);
955 struct list_head *pos;
959 spin_lock_irqsave(&priv->lock, flags);
961 list_for_each(pos, &priv->clients) {
962 if (list_entry(pos, struct iommu_drvdata, node) == data) {
969 spin_unlock_irqrestore(&priv->lock, flags);
973 if (rockchip_iommu_disable(data)) {
974 if (!(strstr(data->dbgname, "vpu") || strstr(data->dbgname, "hevc")))
975 dev_dbg(dev->archdata.iommu,"%s: Detached IOMMU with pgtable %08lx\n",
976 __func__, (unsigned long)virt_to_phys(priv->pgtable));
978 list_del_init(&data->node);
981 dev_err(dev->archdata.iommu,"%s: Detaching IOMMU with pgtable %08lx delayed",
982 __func__, (unsigned long)virt_to_phys(priv->pgtable));
984 spin_unlock_irqrestore(&priv->lock, flags);
987 static int rockchip_iommu_attach_device(struct iommu_domain *domain, struct device *dev)
989 struct iommu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
990 struct rk_iommu_domain *priv = to_rk_domain(domain);
994 spin_lock_irqsave(&priv->lock, flags);
996 ret = rockchip_iommu_enable(data, virt_to_phys(priv->pgtable));
999 /* 'data->node' must not be appeared in priv->clients */
1000 BUG_ON(!list_empty(&data->node));
1001 list_add_tail(&data->node, &priv->clients);
1002 data->domain = domain;
1006 spin_unlock_irqrestore(&priv->lock, flags);
1009 dev_err(dev->archdata.iommu,"%s: Failed to attach IOMMU with pgtable %x\n",
1010 __func__, (unsigned int)virt_to_phys(priv->pgtable));
1011 } else if (ret > 0) {
1012 dev_dbg(dev->archdata.iommu,"%s: IOMMU with pgtable 0x%x already attached\n",
1013 __func__, (unsigned int)virt_to_phys(priv->pgtable));
1015 if (!(strstr(data->dbgname, "vpu") ||
1016 strstr(data->dbgname, "hevc") ||
1017 strstr(data->dbgname, "vdec")))
1018 dev_info(dev->archdata.iommu,"%s: Attached new IOMMU with pgtable 0x%x\n",
1019 __func__, (unsigned int)virt_to_phys(priv->pgtable));
1025 static void rockchip_iommu_domain_free(struct iommu_domain *domain)
1027 struct rk_iommu_domain *priv = to_rk_domain(domain);
1030 WARN_ON(!list_empty(&priv->clients));
1032 for (i = 0; i < NUM_LV1ENTRIES; i++)
1033 if (rockchip_lv1ent_page(priv->pgtable + i))
1034 kmem_cache_free(lv2table_kmem_cache,
1035 phys_to_virt(rockchip_lv2table_base(priv->pgtable + i)));
1037 free_pages((unsigned long)priv->pgtable, 0);
1038 free_pages((unsigned long)priv->lv2entcnt, 0);
1042 static struct iommu_domain *rockchip_iommu_domain_alloc(unsigned type)
1044 struct rk_iommu_domain *priv;
1046 if (type != IOMMU_DOMAIN_UNMANAGED)
1049 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
1053 /*rk32xx iommu use 2 level pagetable,
1054 level1 and leve2 both have 1024 entries,each entry occupy 4 bytes,
1055 so alloc a page size for each page table
1057 priv->pgtable = (unsigned int *)__get_free_pages(GFP_KERNEL |
1062 priv->lv2entcnt = (short *)__get_free_pages(GFP_KERNEL |
1064 if (!priv->lv2entcnt)
1067 rockchip_pgtable_flush(priv->pgtable, priv->pgtable + NUM_LV1ENTRIES);
1069 spin_lock_init(&priv->lock);
1070 spin_lock_init(&priv->pgtablelock);
1071 INIT_LIST_HEAD(&priv->clients);
1073 return &priv->domain;
1076 free_pages((unsigned long)priv->pgtable, 0);
1082 static struct iommu_ops rk_iommu_ops = {
1083 .domain_alloc = rockchip_iommu_domain_alloc,
1084 .domain_free = rockchip_iommu_domain_free,
1085 .attach_dev = rockchip_iommu_attach_device,
1086 .detach_dev = rockchip_iommu_detach_device,
1087 .map = rockchip_iommu_map,
1088 .unmap = rockchip_iommu_unmap,
1089 .iova_to_phys = rockchip_iommu_iova_to_phys,
1090 .pgsize_bitmap = SPAGE_SIZE,
1093 static int rockchip_get_iommu_resource_num(struct platform_device *pdev,
1099 for (i = 0; i < pdev->num_resources; i++) {
1100 struct resource *r = &pdev->resource[i];
1101 if (type == resource_type(r))
1108 static int rockchip_iommu_probe(struct platform_device *pdev)
1112 struct iommu_drvdata *data;
1116 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
1118 dev_dbg(dev, "Not enough memory\n");
1122 dev_set_drvdata(dev, data);
1124 if (pdev->dev.of_node)
1125 of_property_read_string(pdev->dev.of_node, "dbgname",
1128 dev_dbg(dev, "dbgname not assigned in device tree or device node not exist\r\n");
1130 dev_info(dev,"(%s) Enter\n", data->dbgname);
1132 data->num_res_mem = rockchip_get_iommu_resource_num(pdev,
1134 if (0 == data->num_res_mem) {
1135 dev_err(dev,"can't find iommu memory resource \r\n");
1138 dev_dbg(dev,"data->num_res_mem=%d\n", data->num_res_mem);
1140 data->num_res_irq = rockchip_get_iommu_resource_num(pdev,
1142 if (0 == data->num_res_irq) {
1143 dev_err(dev,"can't find iommu irq resource \r\n");
1146 dev_dbg(dev,"data->num_res_irq=%d\n", data->num_res_irq);
1148 data->res_bases = devm_kmalloc_array(dev, data->num_res_mem,
1149 sizeof(*data->res_bases), GFP_KERNEL);
1150 if (data->res_bases == NULL) {
1151 dev_err(dev, "Not enough memory\n");
1155 for (i = 0; i < data->num_res_mem; i++) {
1156 struct resource *res;
1158 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
1160 dev_err(dev,"Unable to find IOMEM region\n");
1164 data->res_bases[i] = devm_ioremap(dev,res->start,
1165 resource_size(res));
1166 if (!data->res_bases[i]) {
1167 dev_err(dev, "Unable to map IOMEM @ PA:%pa\n",
1172 dev_dbg(dev,"res->start = 0x%pa ioremap to data->res_bases[%d] = %p\n",
1173 &res->start, i, data->res_bases[i]);
1175 if (strstr(data->dbgname, "vop") &&
1176 (soc_is_rk3128() || soc_is_rk3126())) {
1177 rk312x_vop_mmu_base = data->res_bases[0];
1178 dev_dbg(dev, "rk312x_vop_mmu_base = %p\n",
1179 rk312x_vop_mmu_base);
1183 for (i = 0; i < data->num_res_irq; i++) {
1184 if ((soc_is_rk3128() || soc_is_rk3126()) &&
1185 strstr(data->dbgname, "vop")) {
1186 dev_info(dev, "skip request vop mmu irq\n");
1190 ret = platform_get_irq(pdev, i);
1192 dev_err(dev,"Unable to find IRQ resource\n");
1196 ret = devm_request_irq(dev, ret, rockchip_iommu_irq,
1197 IRQF_SHARED, dev_name(dev), data);
1199 dev_err(dev, "Unabled to register interrupt handler\n");
1204 ret = rockchip_init_iovmm(dev, &data->vmm);
1209 spin_lock_init(&data->data_lock);
1210 INIT_LIST_HEAD(&data->node);
1212 dev_info(dev,"(%s) Initialized\n", data->dbgname);
1218 static const struct of_device_id iommu_dt_ids[] = {
1219 { .compatible = IEP_IOMMU_COMPATIBLE_NAME},
1220 { .compatible = VIP_IOMMU_COMPATIBLE_NAME},
1221 { .compatible = VOPB_IOMMU_COMPATIBLE_NAME},
1222 { .compatible = VOPL_IOMMU_COMPATIBLE_NAME},
1223 { .compatible = HEVC_IOMMU_COMPATIBLE_NAME},
1224 { .compatible = VPU_IOMMU_COMPATIBLE_NAME},
1225 { .compatible = ISP_IOMMU_COMPATIBLE_NAME},
1226 { .compatible = VOP_IOMMU_COMPATIBLE_NAME},
1227 { .compatible = VDEC_IOMMU_COMPATIBLE_NAME},
1231 MODULE_DEVICE_TABLE(of, iommu_dt_ids);
1234 static struct platform_driver rk_iommu_driver = {
1235 .probe = rockchip_iommu_probe,
1239 .owner = THIS_MODULE,
1240 .of_match_table = of_match_ptr(iommu_dt_ids),
1244 static int __init rockchip_iommu_init_driver(void)
1248 lv2table_kmem_cache = kmem_cache_create("rk-iommu-lv2table",
1249 LV2TABLE_SIZE, LV2TABLE_SIZE,
1251 if (!lv2table_kmem_cache) {
1252 pr_info("%s: failed to create kmem cache\n", __func__);
1256 ret = bus_set_iommu(&platform_bus_type, &rk_iommu_ops);
1260 return platform_driver_register(&rk_iommu_driver);
1263 core_initcall(rockchip_iommu_init_driver);