drivers/iommu/rockchip-iommu.c

   1 /*
   2  * This program is free software; you can redistribute it and/or modify
   3  * it under the terms of the GNU General Public License version 2 as
   4  * published by the Free Software Foundation.
   5  */
   6
   7 #ifdef CONFIG_ROCKCHIP_IOMMU_DEBUG
   8 #define DEBUG
   9 #endif
  10
  11 #include <linux/io.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/slab.h>
  14 #include <linux/clk.h>
  15 #include <linux/err.h>
  16 #include <linux/mm.h>
  17 #include <linux/errno.h>
  18 #include <linux/memblock.h>
  19 #include <linux/export.h>
  20
  21 #include <asm/cacheflush.h>
  22 #include <asm/pgtable.h>
  23 #include <linux/of.h>
  24 #include <linux/rockchip/sysmmu.h>
  25
  26 #include "rockchip-iommu.h"
  27
  28 /* We does not consider super section mapping (16MB) */
  29 #define SPAGE_ORDER 12
  30 #define SPAGE_SIZE (1 << SPAGE_ORDER)
  31 #define SPAGE_MASK (~(SPAGE_SIZE - 1))
  32
  33 typedef enum sysmmu_entry_flags
  34 {
  35         SYSMMU_FLAGS_PRESENT = 0x01,
  36         SYSMMU_FLAGS_READ_PERMISSION = 0x02,
  37         SYSMMU_FLAGS_WRITE_PERMISSION = 0x04,
  38         SYSMMU_FLAGS_OVERRIDE_CACHE  = 0x8,
  39         SYSMMU_FLAGS_WRITE_CACHEABLE  = 0x10,
  40         SYSMMU_FLAGS_WRITE_ALLOCATE  = 0x20,
  41         SYSMMU_FLAGS_WRITE_BUFFERABLE  = 0x40,
  42         SYSMMU_FLAGS_READ_CACHEABLE  = 0x80,
  43         SYSMMU_FLAGS_READ_ALLOCATE  = 0x100,
  44         SYSMMU_FLAGS_MASK = 0x1FF,
  45 } sysmmu_entry_flags;
  46
  47 #define lv1ent_fault(sent) ((*(sent) & SYSMMU_FLAGS_PRESENT) == 0)
  48 #define lv1ent_page(sent) ((*(sent) & SYSMMU_FLAGS_PRESENT) == 1)
  49 #define lv2ent_fault(pent) ((*(pent) & SYSMMU_FLAGS_PRESENT) == 0)
  50 #define spage_phys(pent) (*(pent) & SPAGE_MASK)
  51 #define spage_offs(iova) ((iova) & 0x0FFF)
  52
  53 #define lv1ent_offset(iova) (((iova)>>22) & 0x03FF)
  54 #define lv2ent_offset(iova) (((iova)>>12) & 0x03FF)
  55
  56 #define NUM_LV1ENTRIES 1024
  57 #define NUM_LV2ENTRIES 1024
  58
  59 #define LV2TABLE_SIZE (NUM_LV2ENTRIES * sizeof(long))
  60
  61 #define lv2table_base(sent) (*(sent) & 0xFFFFFFFE)
  62
  63 #define mk_lv1ent_page(pa) ((pa) | SYSMMU_FLAGS_PRESENT)
  64 /*write and read permission for level2 page default*/
  65 #define mk_lv2ent_spage(pa) ((pa) | SYSMMU_FLAGS_PRESENT |SYSMMU_FLAGS_READ_PERMISSION |SYSMMU_FLAGS_WRITE_PERMISSION)
  66
  67 #define SYSMMU_REG_POLL_COUNT_FAST 1000
  68
  69 /**
  70  * MMU register numbers
  71  * Used in the register read/write routines.
  72  * See the hardware documentation for more information about each register
  73  */
  74 typedef enum sysmmu_register
  75 {
  76         SYSMMU_REGISTER_DTE_ADDR = 0x0000, /**< Current Page Directory Pointer */
  77         SYSMMU_REGISTER_STATUS = 0x0004, /**< Status of the MMU */
  78         SYSMMU_REGISTER_COMMAND = 0x0008, /**< Command register, used to control the MMU */
  79         SYSMMU_REGISTER_PAGE_FAULT_ADDR = 0x000C, /**< Logical address of the last page fault */
  80         SYSMMU_REGISTER_ZAP_ONE_LINE = 0x010, /**< Used to invalidate the mapping of a single page from the MMU */
  81         SYSMMU_REGISTER_INT_RAWSTAT = 0x0014, /**< Raw interrupt status, all interrupts visible */
  82         SYSMMU_REGISTER_INT_CLEAR = 0x0018, /**< Indicate to the MMU that the interrupt has been received */
  83         SYSMMU_REGISTER_INT_MASK = 0x001C, /**< Enable/disable types of interrupts */
  84         SYSMMU_REGISTER_INT_STATUS = 0x0020, /**< Interrupt status based on the mask */
  85         SYSMMU_REGISTER_AUTO_GATING     = 0x0024
  86 } sysmmu_register;
  87
  88 typedef enum sysmmu_command
  89 {
  90         SYSMMU_COMMAND_ENABLE_PAGING = 0x00, /**< Enable paging (memory translation) */
  91         SYSMMU_COMMAND_DISABLE_PAGING = 0x01, /**< Disable paging (memory translation) */
  92         SYSMMU_COMMAND_ENABLE_STALL = 0x02, /**<  Enable stall on page fault */
  93         SYSMMU_COMMAND_DISABLE_STALL = 0x03, /**< Disable stall on page fault */
  94         SYSMMU_COMMAND_ZAP_CACHE = 0x04, /**< Zap the entire page table cache */
  95         SYSMMU_COMMAND_PAGE_FAULT_DONE = 0x05, /**< Page fault processed */
  96         SYSMMU_COMMAND_HARD_RESET = 0x06 /**< Reset the MMU back to power-on settings */
  97 } sysmmu_command;
  98
  99 /**
 100  * MMU interrupt register bits
 101  * Each cause of the interrupt is reported
 102  * through the (raw) interrupt status registers.
 103  * Multiple interrupts can be pending, so multiple bits
 104  * can be set at once.
 105  */
 106 typedef enum sysmmu_interrupt
 107 {
 108         SYSMMU_INTERRUPT_PAGE_FAULT = 0x01, /**< A page fault occured */
 109         SYSMMU_INTERRUPT_READ_BUS_ERROR = 0x02 /**< A bus read error occured */
 110 } sysmmu_interrupt;
 111
 112 typedef enum sysmmu_status_bits
 113 {
 114         SYSMMU_STATUS_BIT_PAGING_ENABLED      = 1 << 0,
 115         SYSMMU_STATUS_BIT_PAGE_FAULT_ACTIVE   = 1 << 1,
 116         SYSMMU_STATUS_BIT_STALL_ACTIVE        = 1 << 2,
 117         SYSMMU_STATUS_BIT_IDLE                = 1 << 3,
 118         SYSMMU_STATUS_BIT_REPLAY_BUFFER_EMPTY = 1 << 4,
 119         SYSMMU_STATUS_BIT_PAGE_FAULT_IS_WRITE = 1 << 5,
 120         SYSMMU_STATUS_BIT_STALL_NOT_ACTIVE    = 1 << 31,
 121 } sys_mmu_status_bits;
 122
 123 /**
 124  * Size of an MMU page in bytes
 125  */
 126 #define SYSMMU_PAGE_SIZE 0x1000
 127
 128 /*
 129  * Size of the address space referenced by a page table page
 130  */
 131 #define SYSMMU_VIRTUAL_PAGE_SIZE 0x400000 /* 4 MiB */
 132
 133 /**
 134  * Page directory index from address
 135  * Calculates the page directory index from the given address
 136  */
 137 #define SYSMMU_PDE_ENTRY(address) (((address)>>22) & 0x03FF)
 138
 139 /**
 140  * Page table index from address
 141  * Calculates the page table index from the given address
 142  */
 143 #define SYSMMU_PTE_ENTRY(address) (((address)>>12) & 0x03FF)
 144
 145 /**
 146  * Extract the memory address from an PDE/PTE entry
 147  */
 148 #define SYSMMU_ENTRY_ADDRESS(value) ((value) & 0xFFFFFC00)
 149
 150 #define INVALID_PAGE ((u32)(~0))
 151
 152 static struct kmem_cache *lv2table_kmem_cache;
 153
 154 static unsigned long *section_entry(unsigned long *pgtable, unsigned long iova)
 155 {
 156         return pgtable + lv1ent_offset(iova);
 157 }
 158
 159 static unsigned long *page_entry(unsigned long *sent, unsigned long iova)
 160 {
 161         return (unsigned long *)__va(lv2table_base(sent)) + lv2ent_offset(iova);
 162 }
 163
 164 static char *sysmmu_fault_name[SYSMMU_FAULTS_NUM] = {
 165         "PAGE FAULT",
 166         "BUS ERROR",
 167         "UNKNOWN FAULT"
 168 };
 169
 170 struct rk_iommu_domain {
 171         struct list_head clients; /* list of sysmmu_drvdata.node */
 172         unsigned long *pgtable; /* lv1 page table, 4KB */
 173         short *lv2entcnt; /* free lv2 entry counter for each section */
 174         spinlock_t lock; /* lock for this structure */
 175         spinlock_t pgtablelock; /* lock for modifying page table @ pgtable */
 176 };
 177
 178 static bool set_sysmmu_active(struct sysmmu_drvdata *data)
 179 {
 180         /* return true if the System MMU was not active previously
 181            and it needs to be initialized */
 182         return ++data->activations == 1;
 183 }
 184
 185 static bool set_sysmmu_inactive(struct sysmmu_drvdata *data)
 186 {
 187         /* return true if the System MMU is needed to be disabled */
 188         BUG_ON(data->activations < 1);
 189         return --data->activations == 0;
 190 }
 191
 192 static bool is_sysmmu_active(struct sysmmu_drvdata *data)
 193 {
 194         return data->activations > 0;
 195 }
 196 static void sysmmu_disable_stall(void __iomem *sfrbase)
 197 {
 198         int i;
 199         u32 mmu_status = __raw_readl(sfrbase+SYSMMU_REGISTER_STATUS);
 200         if ( 0 == (mmu_status & SYSMMU_STATUS_BIT_PAGING_ENABLED ))
 201         {
 202                 pr_err("MMU disable skipped since it was not enabled.\n");
 203                 return;
 204         }
 205         if (mmu_status & SYSMMU_STATUS_BIT_PAGE_FAULT_ACTIVE)
 206         {
 207                 pr_err("Aborting MMU disable stall request since it is in pagefault state.\n");
 208                 return;
 209         }
 210
 211         __raw_writel(SYSMMU_COMMAND_DISABLE_STALL, sfrbase + SYSMMU_REGISTER_COMMAND);
 212
 213         for (i = 0; i < SYSMMU_REG_POLL_COUNT_FAST; ++i)
 214         {
 215                 u32 status = __raw_readl(sfrbase + SYSMMU_REGISTER_STATUS);
 216                 if ( 0 == (status & SYSMMU_STATUS_BIT_STALL_ACTIVE) )
 217                 {
 218                         break;
 219                 }
 220                 if ( status &  SYSMMU_STATUS_BIT_PAGE_FAULT_ACTIVE )
 221                 {
 222                         break;
 223                 }
 224                 if ( 0 == (mmu_status & SYSMMU_STATUS_BIT_PAGING_ENABLED ))
 225                 {
 226                         break;
 227                 }
 228         }
 229         if (SYSMMU_REG_POLL_COUNT_FAST == i)
 230                 pr_err("Disable stall request failed, MMU status is 0x%08X\n", __raw_readl(sfrbase + SYSMMU_REGISTER_STATUS));
 231 }
 232 static bool sysmmu_enable_stall(void __iomem *sfrbase)
 233 {
 234         int i;
 235         u32 mmu_status = __raw_readl(sfrbase + SYSMMU_REGISTER_STATUS);
 236
 237         if ( 0 == (mmu_status & SYSMMU_STATUS_BIT_PAGING_ENABLED) )
 238         {
 239                 pr_info("MMU stall is implicit when Paging is not enabled.\n");
 240                 return true;
 241         }
 242         if ( mmu_status & SYSMMU_STATUS_BIT_PAGE_FAULT_ACTIVE )
 243         {
 244                 pr_err("Aborting MMU stall request since it is in pagefault state.\n");
 245                 return false;
 246         }
 247
 248         __raw_writel(SYSMMU_COMMAND_ENABLE_STALL, sfrbase + SYSMMU_REGISTER_COMMAND);
 249
 250         for (i = 0; i < SYSMMU_REG_POLL_COUNT_FAST; ++i)
 251         {
 252                 mmu_status = __raw_readl(sfrbase + SYSMMU_REGISTER_STATUS);
 253                 if (mmu_status & SYSMMU_STATUS_BIT_PAGE_FAULT_ACTIVE)
 254                 {
 255                         break;
 256                 }
 257                 if ((mmu_status & SYSMMU_STATUS_BIT_STALL_ACTIVE)&&(0==(mmu_status & SYSMMU_STATUS_BIT_STALL_NOT_ACTIVE)))
 258                 {
 259                         break;
 260                 }
 261                 if (0 == (mmu_status & ( SYSMMU_STATUS_BIT_PAGING_ENABLED )))
 262                 {
 263                         break;
 264                 }
 265         }
 266         if (SYSMMU_REG_POLL_COUNT_FAST == i)
 267         {
 268                 pr_info("Enable stall request failed, MMU status is 0x%08X\n", __raw_readl(sfrbase + SYSMMU_REGISTER_STATUS));
 269                 return false;
 270         }
 271         if ( mmu_status & SYSMMU_STATUS_BIT_PAGE_FAULT_ACTIVE )
 272         {
 273                 pr_info("Aborting MMU stall request since it has a pagefault.\n");
 274                 return false;
 275         }
 276         return true;
 277 }
 278
 279 static bool sysmmu_enable_paging(void __iomem *sfrbase)
 280 {
 281         int i;
 282         __raw_writel(SYSMMU_COMMAND_ENABLE_PAGING, sfrbase + SYSMMU_REGISTER_COMMAND);
 283
 284         for (i = 0; i < SYSMMU_REG_POLL_COUNT_FAST; ++i)
 285         {
 286                 if (__raw_readl(sfrbase + SYSMMU_REGISTER_STATUS) & SYSMMU_STATUS_BIT_PAGING_ENABLED)
 287                 {
 288                         pr_info("Enable paging request success.\n");
 289                         break;
 290                 }
 291         }
 292         if (SYSMMU_REG_POLL_COUNT_FAST == i)
 293         {
 294                 pr_err("Enable paging request failed, MMU status is 0x%08X\n", __raw_readl(sfrbase + SYSMMU_REGISTER_STATUS));
 295                 return false;
 296         }
 297         return true;
 298 }
 299 void sysmmu_page_fault_done(void __iomem *sfrbase,const char *dbgname)
 300 {
 301         pr_info("MMU: %s: Leaving page fault mode\n", dbgname);
 302         __raw_writel(SYSMMU_COMMAND_PAGE_FAULT_DONE, sfrbase + SYSMMU_REGISTER_COMMAND);
 303 }
 304 bool sysmmu_zap_tlb(void __iomem *sfrbase)
 305 {
 306         bool stall_success = sysmmu_enable_stall(sfrbase);
 307
 308         __raw_writel(SYSMMU_COMMAND_ZAP_CACHE, sfrbase + SYSMMU_REGISTER_COMMAND);
 309         if (false == stall_success)
 310         {
 311                 /* False means that it is in Pagefault state. Not possible to disable_stall then */
 312                 return false;
 313         }
 314         sysmmu_disable_stall(sfrbase);
 315         return true;
 316 }
 317 static inline int sysmmu_raw_reset(void __iomem *sfrbase)
 318 {
 319         int i;
 320         __raw_writel(0xCAFEBABE, sfrbase + SYSMMU_REGISTER_DTE_ADDR);
 321
 322         if(!(0xCAFEB000 == __raw_readl(sfrbase+SYSMMU_REGISTER_DTE_ADDR)))
 323         {
 324                 pr_err("error when %s.\n",__func__);
 325                 return -1;
 326         }
 327         __raw_writel(SYSMMU_COMMAND_HARD_RESET, sfrbase + SYSMMU_REGISTER_COMMAND);
 328
 329         for (i = 0; i < SYSMMU_REG_POLL_COUNT_FAST; ++i)
 330         {
 331                 if(__raw_readl(sfrbase + SYSMMU_REGISTER_DTE_ADDR) == 0)
 332                 {
 333                         break;
 334                 }
 335         }
 336         if (SYSMMU_REG_POLL_COUNT_FAST == i) {
 337                 pr_err("Reset request failed, MMU status is 0x%08X\n", __raw_readl(sfrbase + SYSMMU_REGISTER_DTE_ADDR));
 338                 return -1;
 339         }
 340         return 0;
 341 }
 342
 343 static bool sysmmu_reset(void __iomem *sfrbase,const char *dbgname)
 344 {
 345         bool err = false;
 346         bool stall_success;
 347
 348         stall_success = sysmmu_enable_stall(sfrbase);
 349         if(!stall_success)
 350         {
 351                 pr_info("sysmmu reset:stall failed: %s\n",dbgname);
 352                 return err ;
 353         }
 354         if(0 == sysmmu_raw_reset(sfrbase))
 355         {
 356                 __raw_writel(SYSMMU_INTERRUPT_PAGE_FAULT|SYSMMU_INTERRUPT_READ_BUS_ERROR, sfrbase+SYSMMU_REGISTER_INT_MASK);
 357                 err = sysmmu_enable_paging(sfrbase);
 358         }
 359         sysmmu_disable_stall(sfrbase);
 360         if(err)
 361                 pr_info("SYSMMU: reset successed: %s\n",dbgname);
 362         else
 363                 pr_info("SYSMMU: reset failed: %s\n", dbgname);
 364         return err;
 365 }
 366
 367 static void __sysmmu_set_ptbase(void __iomem *sfrbase,unsigned long pgd)
 368 {
 369         __raw_writel(pgd, sfrbase + SYSMMU_REGISTER_DTE_ADDR);
 370
 371 }
 372 static inline void pgtable_flush(void *vastart, void *vaend)
 373 {
 374         dmac_flush_range(vastart, vaend);
 375         outer_flush_range(virt_to_phys(vastart),virt_to_phys(vaend));
 376 }
 377 static void __set_fault_handler(struct sysmmu_drvdata *data,
 378                                         sysmmu_fault_handler_t handler)
 379 {
 380         unsigned long flags;
 381
 382         write_lock_irqsave(&data->lock, flags);
 383         data->fault_handler = handler;
 384         write_unlock_irqrestore(&data->lock, flags);
 385 }
 386
 387 void rockchip_sysmmu_set_fault_handler(struct device *dev,sysmmu_fault_handler_t handler)
 388 {
 389         struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
 390
 391         __set_fault_handler(data, handler);
 392 }
 393
 394 static int default_fault_handler(struct device *dev,
 395                                         enum rk_sysmmu_inttype itype,
 396                                         unsigned long pgtable_base,
 397                                         unsigned long fault_addr,
 398                                         unsigned int status
 399                                         )
 400 {
 401         struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
 402
 403         if ((itype >= SYSMMU_FAULTS_NUM) || (itype < SYSMMU_PAGEFAULT))
 404                 itype = SYSMMU_FAULT_UNKNOWN;
 405
 406         if(itype == SYSMMU_BUSERROR)
 407                 pr_err("%s occured at 0x%lx(Page table base: 0x%lx)\n",sysmmu_fault_name[itype], fault_addr, pgtable_base);
 408
 409         if(itype == SYSMMU_PAGEFAULT)
 410                 pr_err("SYSMMU:Page fault detected at 0x%lx from bus id %d of type %s on %s\n",
 411                                 fault_addr,
 412                                 (status >> 6) & 0x1F,
 413                                 (status & 32) ? "write" : "read",
 414                                 data->dbgname
 415                                 );
 416
 417         pr_err("Generating Kernel OOPS... because it is unrecoverable.\n");
 418
 419         BUG();
 420
 421         return 0;
 422 }
 423
 424 static irqreturn_t rockchip_sysmmu_irq(int irq, void *dev_id)
 425 {
 426         /* SYSMMU is in blocked when interrupt occurred. */
 427         struct sysmmu_drvdata *data = dev_id;
 428         struct resource *irqres;
 429         struct platform_device *pdev;
 430         enum rk_sysmmu_inttype itype = SYSMMU_FAULT_UNKNOWN;
 431         u32 status;
 432         u32 rawstat;
 433         u32 int_status;
 434         u32 fault_address;
 435         int i, ret = -ENOSYS;
 436
 437         read_lock(&data->lock);
 438
 439         WARN_ON(!is_sysmmu_active(data));
 440
 441         pdev = to_platform_device(data->sysmmu);
 442         for (i = 0; i < data->num_res_irq; i++)
 443         {
 444                 irqres = platform_get_resource(pdev, IORESOURCE_IRQ, i);
 445                 if (irqres && ((int)irqres->start == irq))
 446                         break;
 447         }
 448
 449         if (i == data->num_res_irq)
 450         {
 451                 itype = SYSMMU_FAULT_UNKNOWN;
 452         }
 453         else
 454         {
 455                 int_status = __raw_readl(data->res_bases[i] + SYSMMU_REGISTER_INT_STATUS);
 456                 if(int_status != 0)
 457                 {
 458                         /*mask status*/
 459                         __raw_writel(0x00,data->res_bases[i] + SYSMMU_REGISTER_INT_MASK);
 460
 461                         rawstat = __raw_readl(data->res_bases[i] + SYSMMU_REGISTER_INT_RAWSTAT);
 462                         if(rawstat & SYSMMU_INTERRUPT_PAGE_FAULT)
 463                         {
 464                                 fault_address = __raw_readl(data->res_bases[i] + SYSMMU_REGISTER_PAGE_FAULT_ADDR);
 465                                 itype = SYSMMU_PAGEFAULT;
 466                         }
 467                         else if(rawstat & SYSMMU_INTERRUPT_READ_BUS_ERROR)
 468                         {
 469                                 itype = SYSMMU_BUSERROR;
 470                         }
 471                         else
 472                         {
 473                                 goto out;
 474                         }
 475                 }
 476                 else
 477                         goto out;
 478         }
 479
 480         if (data->domain)
 481                 ret = report_iommu_fault(data->domain, data->dev,fault_address, itype);
 482
 483         if ((ret == -ENOSYS) && data->fault_handler)
 484         {
 485                 unsigned long base = data->pgtable;
 486                 if (itype != SYSMMU_FAULT_UNKNOWN)
 487                         base = __raw_readl(data->res_bases[i] + SYSMMU_REGISTER_DTE_ADDR);
 488                 status = __raw_readl(data->res_bases[i] + SYSMMU_REGISTER_STATUS);
 489                 ret = data->fault_handler(data->dev, itype, base, fault_address,status);
 490         }
 491
 492         if (!ret && (itype != SYSMMU_FAULT_UNKNOWN))
 493         {
 494                 if(SYSMMU_PAGEFAULT == itype)
 495                 {
 496                         sysmmu_zap_tlb(data->res_bases[i]);
 497                         sysmmu_page_fault_done(data->res_bases[i],data->dbgname);
 498                 }
 499                 sysmmu_reset(data->res_bases[i],data->dbgname);
 500         }
 501         else
 502                 pr_err("(%s) %s is not handled.\n",data->dbgname, sysmmu_fault_name[itype]);
 503
 504 out :
 505         read_unlock(&data->lock);
 506
 507         return IRQ_HANDLED;
 508 }
 509
 510 static bool __rockchip_sysmmu_disable(struct sysmmu_drvdata *data)
 511 {
 512         unsigned long flags;
 513         bool disabled = false;
 514         int i;
 515         write_lock_irqsave(&data->lock, flags);
 516
 517         if (!set_sysmmu_inactive(data))
 518                 goto finish;
 519
 520         for(i=0;i<data->num_res_mem;i++)
 521         {
 522                 if(!sysmmu_reset(data->res_bases[i],data->dbgname))
 523                 goto finish;
 524         }
 525         disabled = true;
 526         data->pgtable = 0;
 527         data->domain = NULL;
 528 finish:
 529         write_unlock_irqrestore(&data->lock, flags);
 530
 531         if (disabled)
 532                 pr_info("(%s) Disabled\n", data->dbgname);
 533         else
 534                 pr_info("(%s) %d times left to be disabled\n",data->dbgname, data->activations);
 535
 536         return disabled;
 537 }
 538
 539 /* __rk_sysmmu_enable: Enables System MMU
 540  *
 541  * returns -error if an error occurred and System MMU is not enabled,
 542  * 0 if the System MMU has been just enabled and 1 if System MMU was already
 543  * enabled before.
 544  */
 545 static int __rockchip_sysmmu_enable(struct sysmmu_drvdata *data,unsigned long pgtable, struct iommu_domain *domain)
 546 {
 547         int i, ret = 0;
 548         unsigned long flags;
 549
 550         write_lock_irqsave(&data->lock, flags);
 551
 552         if (!set_sysmmu_active(data))
 553         {
 554                 if (WARN_ON(pgtable != data->pgtable))
 555                 {
 556                         ret = -EBUSY;
 557                         set_sysmmu_inactive(data);
 558                 }
 559                 else
 560                         ret = 1;
 561
 562                 pr_info("(%s) Already enabled\n", data->dbgname);
 563                 goto finish;
 564         }
 565
 566         data->pgtable = pgtable;
 567
 568         for (i = 0; i < data->num_res_mem; i++)
 569         {
 570                 bool status;
 571                 status = sysmmu_enable_stall(data->res_bases[i]);
 572                 if(status)
 573                 {
 574                         __sysmmu_set_ptbase(data->res_bases[i], pgtable);
 575                         __raw_writel(SYSMMU_COMMAND_ZAP_CACHE, data->res_bases[i] + SYSMMU_REGISTER_COMMAND);
 576                 }
 577                 sysmmu_disable_stall(data->res_bases[i]);
 578         }
 579
 580         data->domain = domain;
 581
 582         pr_info("(%s) Enabled\n", data->dbgname);
 583 finish:
 584         write_unlock_irqrestore(&data->lock, flags);
 585
 586         return ret;
 587 }
 588 bool rockchip_sysmmu_disable(struct device *dev)
 589 {
 590         struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
 591         bool disabled;
 592
 593         disabled = __rockchip_sysmmu_disable(data);
 594
 595         return disabled;
 596 }
 597 void rockchip_sysmmu_tlb_invalidate(struct device *dev)
 598 {
 599         unsigned long flags;
 600         struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
 601
 602         read_lock_irqsave(&data->lock, flags);
 603
 604         if (is_sysmmu_active(data))
 605         {
 606                 int i;
 607                 for (i = 0; i < data->num_res_mem; i++)
 608                 {
 609                         if(!sysmmu_zap_tlb(data->res_bases[i]))
 610                                 pr_err("%s,invalidating TLB failed\n",data->dbgname);
 611                 }
 612         }
 613         else
 614                 pr_info("(%s) Disabled. Skipping invalidating TLB.\n",data->dbgname);
 615
 616         read_unlock_irqrestore(&data->lock, flags);
 617 }
 618 static phys_addr_t rockchip_iommu_iova_to_phys(struct iommu_domain *domain,dma_addr_t iova)
 619 {
 620         struct rk_iommu_domain *priv = domain->priv;
 621         unsigned long *entry;
 622         unsigned long flags;
 623         phys_addr_t phys = 0;
 624
 625         spin_lock_irqsave(&priv->pgtablelock, flags);
 626
 627         entry = section_entry(priv->pgtable, iova);
 628         entry = page_entry(entry, iova);
 629         phys = spage_phys(entry) + spage_offs(iova);
 630
 631         spin_unlock_irqrestore(&priv->pgtablelock, flags);
 632
 633         return phys;
 634 }
 635 static int lv2set_page(unsigned long *pent, phys_addr_t paddr, size_t size,
 636                                                                 short *pgcnt)
 637 {
 638         if (!lv2ent_fault(pent))
 639                 return -EADDRINUSE;
 640
 641         *pent = mk_lv2ent_spage(paddr);
 642         pgtable_flush(pent, pent + 1);
 643         *pgcnt -= 1;
 644         return 0;
 645 }
 646
 647 static unsigned long *alloc_lv2entry(unsigned long *sent, unsigned long iova,short *pgcounter)
 648 {
 649         if (lv1ent_fault(sent))
 650         {
 651                 unsigned long *pent;
 652
 653                 pent = kmem_cache_zalloc(lv2table_kmem_cache, GFP_ATOMIC);
 654                 BUG_ON((unsigned long)pent & (LV2TABLE_SIZE - 1));
 655                 if (!pent)
 656                         return NULL;
 657
 658                 *sent = mk_lv1ent_page(__pa(pent));
 659                 kmemleak_ignore(pent);
 660                 *pgcounter = NUM_LV2ENTRIES;
 661                 pgtable_flush(pent, pent + NUM_LV2ENTRIES);
 662                 pgtable_flush(sent, sent + 1);
 663         }
 664         return page_entry(sent, iova);
 665 }
 666
 667 static size_t rockchip_iommu_unmap(struct iommu_domain *domain,unsigned long iova, size_t size)
 668 {
 669         struct rk_iommu_domain *priv = domain->priv;
 670         unsigned long flags;
 671         unsigned long *ent;
 672
 673         BUG_ON(priv->pgtable == NULL);
 674
 675         spin_lock_irqsave(&priv->pgtablelock, flags);
 676
 677         ent = section_entry(priv->pgtable, iova);
 678
 679         if (unlikely(lv1ent_fault(ent)))
 680         {
 681                 if (size > SPAGE_SIZE)
 682                         size = SPAGE_SIZE;
 683                 goto done;
 684         }
 685
 686         /* lv1ent_page(sent) == true here */
 687
 688         ent = page_entry(ent, iova);
 689
 690         if (unlikely(lv2ent_fault(ent)))
 691         {
 692                 size = SPAGE_SIZE;
 693                 goto done;
 694         }
 695
 696         *ent = 0;
 697         size = SPAGE_SIZE;
 698         priv->lv2entcnt[lv1ent_offset(iova)] += 1;
 699         goto done;
 700
 701 done:
 702         pr_info("%s:unmap iova 0x%lx/0x%x bytes\n",__func__, iova,size);
 703         spin_unlock_irqrestore(&priv->pgtablelock, flags);
 704
 705         return size;
 706 }
 707 static int rockchip_iommu_map(struct iommu_domain *domain, unsigned long iova,
 708                          phys_addr_t paddr, size_t size, int prot)
 709 {
 710         struct rk_iommu_domain *priv = domain->priv;
 711         unsigned long *entry;
 712         unsigned long flags;
 713         int ret = -ENOMEM;
 714         unsigned long *pent;
 715
 716         BUG_ON(priv->pgtable == NULL);
 717
 718         spin_lock_irqsave(&priv->pgtablelock, flags);
 719
 720         entry = section_entry(priv->pgtable, iova);
 721
 722         pent = alloc_lv2entry(entry, iova,&priv->lv2entcnt[lv1ent_offset(iova)]);
 723         if (!pent)
 724                 ret = -ENOMEM;
 725         else
 726                 ret = lv2set_page(pent, paddr, size,&priv->lv2entcnt[lv1ent_offset(iova)]);
 727
 728         if (ret)
 729         {
 730                 pr_debug("%s: Failed to map iova 0x%lx/0x%x bytes\n",__func__, iova, size);
 731         }
 732         spin_unlock_irqrestore(&priv->pgtablelock, flags);
 733
 734         return ret;
 735 }
 736
 737 static void rockchip_iommu_detach_device(struct iommu_domain *domain,
 738                                     struct device *dev)
 739 {
 740         struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
 741         struct rk_iommu_domain *priv = domain->priv;
 742         struct list_head *pos;
 743         unsigned long flags;
 744         bool found = false;
 745
 746         spin_lock_irqsave(&priv->lock, flags);
 747
 748         list_for_each(pos, &priv->clients)
 749         {
 750                 if (list_entry(pos, struct sysmmu_drvdata, node) == data)
 751                 {
 752                         found = true;
 753                         break;
 754                 }
 755         }
 756         if (!found)
 757                 goto finish;
 758
 759         if (__rockchip_sysmmu_disable(data))
 760         {
 761                 pr_info("%s: Detached IOMMU with pgtable %#lx\n",__func__, __pa(priv->pgtable));
 762                 list_del(&data->node);
 763                 INIT_LIST_HEAD(&data->node);
 764
 765         }
 766         else
 767                 pr_info("%s: Detaching IOMMU with pgtable %#lx delayed",__func__, __pa(priv->pgtable));
 768
 769 finish:
 770         spin_unlock_irqrestore(&priv->lock, flags);
 771 }
 772 static int rockchip_iommu_attach_device(struct iommu_domain *domain,struct device *dev)
 773 {
 774         struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
 775         struct rk_iommu_domain *priv = domain->priv;
 776         unsigned long flags;
 777         int ret;
 778
 779         spin_lock_irqsave(&priv->lock, flags);
 780
 781         ret = __rockchip_sysmmu_enable(data, __pa(priv->pgtable), domain);
 782
 783         if (ret == 0)
 784         {
 785                 /* 'data->node' must not be appeared in priv->clients */
 786                 BUG_ON(!list_empty(&data->node));
 787                 data->dev = dev;
 788                 list_add_tail(&data->node, &priv->clients);
 789         }
 790
 791         spin_unlock_irqrestore(&priv->lock, flags);
 792
 793         if (ret < 0)
 794         {
 795                 pr_err("%s: Failed to attach IOMMU with pgtable %#lx\n",__func__, __pa(priv->pgtable));
 796         }
 797         else if (ret > 0)
 798         {
 799                 pr_info("%s: IOMMU with pgtable 0x%lx already attached\n",__func__, __pa(priv->pgtable));
 800         }
 801         else
 802         {
 803                 pr_info("%s: Attached new IOMMU with pgtable 0x%lx\n",__func__, __pa(priv->pgtable));
 804         }
 805
 806         return ret;
 807 }
 808 static void rockchip_iommu_domain_destroy(struct iommu_domain *domain)
 809 {
 810         struct rk_iommu_domain *priv = domain->priv;
 811         struct sysmmu_drvdata *data;
 812         unsigned long flags;
 813         int i;
 814
 815         WARN_ON(!list_empty(&priv->clients));
 816
 817         spin_lock_irqsave(&priv->lock, flags);
 818
 819         list_for_each_entry(data, &priv->clients, node)
 820         {
 821                 while (!rockchip_sysmmu_disable(data->dev))
 822                         ; /* until System MMU is actually disabled */
 823         }
 824         spin_unlock_irqrestore(&priv->lock, flags);
 825
 826         for (i = 0; i < NUM_LV1ENTRIES; i++)
 827                 if (lv1ent_page(priv->pgtable + i))
 828                         kmem_cache_free(lv2table_kmem_cache,__va(lv2table_base(priv->pgtable + i)));
 829
 830         free_pages((unsigned long)priv->pgtable, 0);
 831         free_pages((unsigned long)priv->lv2entcnt, 0);
 832         kfree(domain->priv);
 833         domain->priv = NULL;
 834 }
 835
 836 static int rockchip_iommu_domain_init(struct iommu_domain *domain)
 837 {
 838         struct rk_iommu_domain *priv;
 839
 840         priv = kzalloc(sizeof(*priv), GFP_KERNEL);
 841         if (!priv)
 842                 return -ENOMEM;
 843
 844 /*rk32xx sysmmu use 2 level pagetable,
 845    level1 and leve2 both have 1024 entries,each entry  occupy 4 bytes,
 846    so alloc a page size for each page table
 847 */
 848         priv->pgtable = (unsigned long *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, 0);
 849         if (!priv->pgtable)
 850                 goto err_pgtable;
 851
 852         priv->lv2entcnt = (short *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, 0);
 853         if (!priv->lv2entcnt)
 854                 goto err_counter;
 855
 856         pgtable_flush(priv->pgtable, priv->pgtable + NUM_LV1ENTRIES);
 857
 858         spin_lock_init(&priv->lock);
 859         spin_lock_init(&priv->pgtablelock);
 860         INIT_LIST_HEAD(&priv->clients);
 861
 862         domain->priv = priv;
 863         return 0;
 864
 865 err_counter:
 866         free_pages((unsigned long)priv->pgtable, 2);
 867 err_pgtable:
 868         kfree(priv);
 869         return -ENOMEM;
 870 }
 871
 872 static struct iommu_ops rk_iommu_ops =
 873 {
 874         .domain_init = &rockchip_iommu_domain_init,
 875         .domain_destroy = &rockchip_iommu_domain_destroy,
 876         .attach_dev = &rockchip_iommu_attach_device,
 877         .detach_dev = &rockchip_iommu_detach_device,
 878         .map = &rockchip_iommu_map,
 879         .unmap = &rockchip_iommu_unmap,
 880         .iova_to_phys = &rockchip_iommu_iova_to_phys,
 881         .pgsize_bitmap = SPAGE_SIZE,
 882 };
 883
 884 static int rockchip_sysmmu_prepare(void)
 885 {
 886         int ret = 0;
 887         static int registed = 0;
 888
 889         if(registed)
 890                 return 0;
 891
 892         lv2table_kmem_cache = kmem_cache_create("rk-iommu-lv2table",LV2TABLE_SIZE, LV2TABLE_SIZE, 0, NULL);
 893         if (!lv2table_kmem_cache)
 894         {
 895                 pr_err("%s: failed to create kmem cache\n", __func__);
 896                 return -ENOMEM;
 897         }
 898         ret = bus_set_iommu(&platform_bus_type, &rk_iommu_ops);
 899         if(!ret)
 900                 registed = 1;
 901         else
 902                 pr_err("%s:failed to set iommu to bus\r\n",__func__);
 903         return ret;
 904 }
 905 static int  rockchip_get_sysmmu_resource_num(struct platform_device *pdev,unsigned int type)
 906 {
 907         struct resource *info = NULL;
 908         int num_resources = 0;
 909
 910         /*get resouce info*/
 911 again:
 912         info = platform_get_resource(pdev, type, num_resources);
 913         while(info)
 914         {
 915                 num_resources++;
 916                 goto again;
 917         }
 918
 919         if(IORESOURCE_MEM == type)
 920                 pr_info("have memory resource %d\r\n",num_resources);
 921         if(IORESOURCE_IRQ == type)
 922                 pr_info("have IRQ resource %d\r\n",num_resources);
 923         return num_resources;
 924 }
 925
 926 static int rockchip_sysmmu_probe(struct platform_device *pdev)
 927 {
 928         int i, ret;
 929         struct device *dev;
 930         struct sysmmu_drvdata *data;
 931
 932         dev = &pdev->dev;
 933
 934         ret = rockchip_sysmmu_prepare();
 935         if(ret)
 936         {
 937                 pr_err("%s,failed\r\n",__func__);
 938                 goto err_alloc;
 939         }
 940
 941         data = devm_kzalloc(dev,sizeof(*data), GFP_KERNEL);
 942         if (!data)
 943         {
 944                 dev_dbg(dev, "Not enough memory\n");
 945                 ret = -ENOMEM;
 946                 goto err_alloc;
 947         }
 948
 949         ret = dev_set_drvdata(dev, data);
 950         if (ret)
 951         {
 952                 dev_dbg(dev, "Unabled to initialize driver data\n");
 953                 goto err_init;
 954         }
 955
 956         /*rk32xx sysmmu need both irq and memory */
 957         data->num_res_mem = rockchip_get_sysmmu_resource_num(pdev,IORESOURCE_MEM);
 958         if(0 == data->num_res_mem)
 959         {
 960                 pr_err("can't find sysmmu memory resource \r\n");
 961                 goto err_init;
 962         }
 963         data->num_res_irq = rockchip_get_sysmmu_resource_num(pdev,IORESOURCE_IRQ);
 964         if(0 == data->num_res_irq)
 965         {
 966                 pr_err("can't find sysmmu irq resource \r\n");
 967                 goto err_init;
 968         }
 969
 970         data->res_bases = kmalloc(sizeof(*data->res_bases) * data->num_res_mem,GFP_KERNEL);
 971         if (data->res_bases == NULL)
 972         {
 973                 dev_dbg(dev, "Not enough memory\n");
 974                 ret = -ENOMEM;
 975                 goto err_init;
 976         }
 977
 978         for (i = 0; i < data->num_res_mem; i++)
 979         {
 980                 struct resource *res;
 981                 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
 982                 if (!res)
 983                 {
 984                         pr_err("Unable to find IOMEM region\n");
 985                         ret = -ENOENT;
 986                         goto err_res;
 987                 }
 988                 data->res_bases[i] = ioremap(res->start, resource_size(res));
 989                 if (!data->res_bases[i])
 990                 {
 991                         pr_err("Unable to map IOMEM @ PA:%#x\n",res->start);
 992                         ret = -ENOENT;
 993                         goto err_res;
 994                 }
 995                 /*reset sysmmu*/
 996                 if(!sysmmu_reset(data->res_bases[i],data->dbgname))
 997                 {
 998                         ret = -ENOENT;
 999                         goto err_res;
1000                 }
1001         }
1002
1003         for (i = 0; i < data->num_res_irq; i++)
1004         {
1005                 ret = platform_get_irq(pdev, i);
1006                 if (ret <= 0)
1007                 {
1008                         pr_err("Unable to find IRQ resource\n");
1009                         goto err_irq;
1010                 }
1011                 ret = request_irq(ret, rockchip_sysmmu_irq, IRQF_SHARED ,dev_name(dev), data);
1012                 if (ret)
1013                 {
1014                         pr_err("Unabled to register interrupt handler\n");
1015                         goto err_irq;
1016                 }
1017         }
1018
1019         if(pdev->dev.of_node)
1020         {
1021                 of_property_read_string(pdev->dev.of_node,"dbgname",&(data->dbgname));
1022                 pr_info("dbgname : %s\n",data->dbgname);
1023         }
1024         else
1025         {
1026                 pr_info("dbgname not assigned in device tree or device node not exist\r\n");
1027         }
1028         ret = rockchip_init_iovmm(dev, &data->vmm);
1029         if (ret)
1030                 goto err_irq;
1031
1032         data->sysmmu = dev;
1033         rwlock_init(&data->lock);
1034         INIT_LIST_HEAD(&data->node);
1035
1036         __set_fault_handler(data, &default_fault_handler);
1037
1038         pr_info("(%s) Initialized\n", data->dbgname);
1039         return 0;
1040
1041 err_irq:
1042         while (i-- > 0)
1043         {
1044                 int irq;
1045
1046                 irq = platform_get_irq(pdev, i);
1047                 free_irq(irq, data);
1048         }
1049 err_res:
1050         while (data->num_res_mem-- > 0)
1051                 iounmap(data->res_bases[data->num_res_mem]);
1052         kfree(data->res_bases);
1053 err_init:
1054         kfree(data);
1055 err_alloc:
1056         dev_err(dev, "Failed to initialize\n");
1057         return ret;
1058 }
1059
1060 #ifdef CONFIG_OF
1061 static const struct of_device_id sysmmu_dt_ids[] =
1062 {
1063         { .compatible = IEP_SYSMMU_COMPATIBLE_NAME},
1064         { .compatible = VIP_SYSMMU_COMPATIBLE_NAME},
1065         { .compatible = ISP_SYSMMU0_COMPATIBLE_NAME},
1066         { .compatible = ISP_SYSMMU1_COMPATIBLE_NAME},
1067         { .compatible = VOPB_SYSMMU_COMPATIBLE_NAME},
1068         { .compatible = VOPL_SYSMMU_COMPATIBLE_NAME},
1069         { .compatible = HEVC_SYSMMU_COMPATIBLE_NAME},
1070         { .compatible = VPU_SYSMMU_COMPATIBLE_NAME},
1071         { /* end */ }
1072 };
1073 MODULE_DEVICE_TABLE(of, sysmmu_dt_ids);
1074 #endif
1075
1076 static struct platform_driver rk_sysmmu_driver =
1077 {
1078         .probe = rockchip_sysmmu_probe,
1079         .remove = NULL,
1080         .driver =
1081         {
1082                    .name = "rk_sysmmu",
1083                    .owner = THIS_MODULE,
1084                    .of_match_table = of_match_ptr(sysmmu_dt_ids),
1085         },
1086 };
1087
1088 #if 0
1089 /*I don't know why this can't work*/
1090 #ifdef CONFIG_OF
1091 module_platform_driver(rk_sysmmu_driver);
1092 #endif
1093 #endif
1094 static int __init rockchip_sysmmu_init_driver(void)
1095 {
1096         return platform_driver_register(&rk_sysmmu_driver);
1097 }
1098
1099 core_initcall(rockchip_sysmmu_init_driver);
1100