drivers/iommu/rockchip-iommu.c

   1 /*
   2  * This program is free software; you can redistribute it and/or modify
   3  * it under the terms of the GNU General Public License version 2 as
   4  * published by the Free Software Foundation.
   5  */
   6
   7 #ifdef CONFIG_ROCKCHIP_IOMMU_DEBUG
   8 #define DEBUG
   9 #endif
  10
  11 #include <linux/io.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/slab.h>
  14 #include <linux/clk.h>
  15 #include <linux/err.h>
  16 #include <linux/mm.h>
  17 #include <linux/errno.h>
  18 #include <linux/memblock.h>
  19 #include <linux/export.h>
  20
  21 #include <asm/cacheflush.h>
  22 #include <asm/pgtable.h>
  23 #include <linux/of.h>
  24 #include <linux/rockchip/sysmmu.h>
  25
  26 #include "rockchip-iommu.h"
  27
  28 /* We does not consider super section mapping (16MB) */
  29 #define SPAGE_ORDER 12
  30 #define SPAGE_SIZE (1 << SPAGE_ORDER)
  31 #define SPAGE_MASK (~(SPAGE_SIZE - 1))
  32
  33 typedef enum sysmmu_entry_flags
  34 {
  35         SYSMMU_FLAGS_PRESENT = 0x01,
  36         SYSMMU_FLAGS_READ_PERMISSION = 0x02,
  37         SYSMMU_FLAGS_WRITE_PERMISSION = 0x04,
  38         SYSMMU_FLAGS_OVERRIDE_CACHE  = 0x8,
  39         SYSMMU_FLAGS_WRITE_CACHEABLE  = 0x10,
  40         SYSMMU_FLAGS_WRITE_ALLOCATE  = 0x20,
  41         SYSMMU_FLAGS_WRITE_BUFFERABLE  = 0x40,
  42         SYSMMU_FLAGS_READ_CACHEABLE  = 0x80,
  43         SYSMMU_FLAGS_READ_ALLOCATE  = 0x100,
  44         SYSMMU_FLAGS_MASK = 0x1FF,
  45 } sysmmu_entry_flags;
  46
  47 #define lv1ent_fault(sent) ((*(sent) & SYSMMU_FLAGS_PRESENT) == 0)
  48 #define lv1ent_page(sent) ((*(sent) & SYSMMU_FLAGS_PRESENT) == 1)
  49 #define lv2ent_fault(pent) ((*(pent) & SYSMMU_FLAGS_PRESENT) == 0)
  50 #define spage_phys(pent) (*(pent) & SPAGE_MASK)
  51 #define spage_offs(iova) ((iova) & 0x0FFF)
  52
  53 #define lv1ent_offset(iova) (((iova)>>22) & 0x03FF)
  54 #define lv2ent_offset(iova) (((iova)>>12) & 0x03FF)
  55
  56 #define NUM_LV1ENTRIES 1024
  57 #define NUM_LV2ENTRIES 1024
  58
  59 #define LV2TABLE_SIZE (NUM_LV2ENTRIES * sizeof(long))
  60
  61 #define lv2table_base(sent) (*(sent) & 0xFFFFFFFE)
  62
  63 #define mk_lv1ent_page(pa) ((pa) | SYSMMU_FLAGS_PRESENT)
  64 /*write and read permission for level2 page default*/
  65 #define mk_lv2ent_spage(pa) ((pa) | SYSMMU_FLAGS_PRESENT |SYSMMU_FLAGS_READ_PERMISSION |SYSMMU_FLAGS_WRITE_PERMISSION)
  66
  67 #define SYSMMU_REG_POLL_COUNT_FAST 1000
  68
  69 /**
  70  * MMU register numbers
  71  * Used in the register read/write routines.
  72  * See the hardware documentation for more information about each register
  73  */
  74 typedef enum sysmmu_register
  75 {
  76         SYSMMU_REGISTER_DTE_ADDR = 0x0000, /**< Current Page Directory Pointer */
  77         SYSMMU_REGISTER_STATUS = 0x0004, /**< Status of the MMU */
  78         SYSMMU_REGISTER_COMMAND = 0x0008, /**< Command register, used to control the MMU */
  79         SYSMMU_REGISTER_PAGE_FAULT_ADDR = 0x000C, /**< Logical address of the last page fault */
  80         SYSMMU_REGISTER_ZAP_ONE_LINE = 0x010, /**< Used to invalidate the mapping of a single page from the MMU */
  81         SYSMMU_REGISTER_INT_RAWSTAT = 0x0014, /**< Raw interrupt status, all interrupts visible */
  82         SYSMMU_REGISTER_INT_CLEAR = 0x0018, /**< Indicate to the MMU that the interrupt has been received */
  83         SYSMMU_REGISTER_INT_MASK = 0x001C, /**< Enable/disable types of interrupts */
  84         SYSMMU_REGISTER_INT_STATUS = 0x0020, /**< Interrupt status based on the mask */
  85         SYSMMU_REGISTER_AUTO_GATING     = 0x0024
  86 } sysmmu_register;
  87
  88 typedef enum sysmmu_command
  89 {
  90         SYSMMU_COMMAND_ENABLE_PAGING = 0x00, /**< Enable paging (memory translation) */
  91         SYSMMU_COMMAND_DISABLE_PAGING = 0x01, /**< Disable paging (memory translation) */
  92         SYSMMU_COMMAND_ENABLE_STALL = 0x02, /**<  Enable stall on page fault */
  93         SYSMMU_COMMAND_DISABLE_STALL = 0x03, /**< Disable stall on page fault */
  94         SYSMMU_COMMAND_ZAP_CACHE = 0x04, /**< Zap the entire page table cache */
  95         SYSMMU_COMMAND_PAGE_FAULT_DONE = 0x05, /**< Page fault processed */
  96         SYSMMU_COMMAND_HARD_RESET = 0x06 /**< Reset the MMU back to power-on settings */
  97 } sysmmu_command;
  98
  99 /**
 100  * MMU interrupt register bits
 101  * Each cause of the interrupt is reported
 102  * through the (raw) interrupt status registers.
 103  * Multiple interrupts can be pending, so multiple bits
 104  * can be set at once.
 105  */
 106 typedef enum sysmmu_interrupt
 107 {
 108         SYSMMU_INTERRUPT_PAGE_FAULT = 0x01, /**< A page fault occured */
 109         SYSMMU_INTERRUPT_READ_BUS_ERROR = 0x02 /**< A bus read error occured */
 110 } sysmmu_interrupt;
 111
 112 typedef enum sysmmu_status_bits
 113 {
 114         SYSMMU_STATUS_BIT_PAGING_ENABLED      = 1 << 0,
 115         SYSMMU_STATUS_BIT_PAGE_FAULT_ACTIVE   = 1 << 1,
 116         SYSMMU_STATUS_BIT_STALL_ACTIVE        = 1 << 2,
 117         SYSMMU_STATUS_BIT_IDLE                = 1 << 3,
 118         SYSMMU_STATUS_BIT_REPLAY_BUFFER_EMPTY = 1 << 4,
 119         SYSMMU_STATUS_BIT_PAGE_FAULT_IS_WRITE = 1 << 5,
 120         SYSMMU_STATUS_BIT_STALL_NOT_ACTIVE    = 1 << 31,
 121 } sys_mmu_status_bits;
 122
 123 /**
 124  * Size of an MMU page in bytes
 125  */
 126 #define SYSMMU_PAGE_SIZE 0x1000
 127
 128 /*
 129  * Size of the address space referenced by a page table page
 130  */
 131 #define SYSMMU_VIRTUAL_PAGE_SIZE 0x400000 /* 4 MiB */
 132
 133 /**
 134  * Page directory index from address
 135  * Calculates the page directory index from the given address
 136  */
 137 #define SYSMMU_PDE_ENTRY(address) (((address)>>22) & 0x03FF)
 138
 139 /**
 140  * Page table index from address
 141  * Calculates the page table index from the given address
 142  */
 143 #define SYSMMU_PTE_ENTRY(address) (((address)>>12) & 0x03FF)
 144
 145 /**
 146  * Extract the memory address from an PDE/PTE entry
 147  */
 148 #define SYSMMU_ENTRY_ADDRESS(value) ((value) & 0xFFFFFC00)
 149
 150 #define INVALID_PAGE ((u32)(~0))
 151
 152 static struct kmem_cache *lv2table_kmem_cache;
 153
 154 static unsigned long *section_entry(unsigned long *pgtable, unsigned long iova)
 155 {
 156         return pgtable + lv1ent_offset(iova);
 157 }
 158
 159 static unsigned long *page_entry(unsigned long *sent, unsigned long iova)
 160 {
 161         return (unsigned long *)__va(lv2table_base(sent)) + lv2ent_offset(iova);
 162 }
 163
 164 static char *sysmmu_fault_name[SYSMMU_FAULTS_NUM] = {
 165         "PAGE FAULT",
 166         "BUS ERROR",
 167         "UNKNOWN FAULT"
 168 };
 169
 170 struct rk_iommu_domain {
 171         struct list_head clients; /* list of sysmmu_drvdata.node */
 172         unsigned long *pgtable; /* lv1 page table, 4KB */
 173         short *lv2entcnt; /* free lv2 entry counter for each section */
 174         spinlock_t lock; /* lock for this structure */
 175         spinlock_t pgtablelock; /* lock for modifying page table @ pgtable */
 176 };
 177
 178 static bool set_sysmmu_active(struct sysmmu_drvdata *data)
 179 {
 180         /* return true if the System MMU was not active previously
 181            and it needs to be initialized */
 182         return ++data->activations == 1;
 183 }
 184
 185 static bool set_sysmmu_inactive(struct sysmmu_drvdata *data)
 186 {
 187         /* return true if the System MMU is needed to be disabled */
 188         BUG_ON(data->activations < 1);
 189         return --data->activations == 0;
 190 }
 191
 192 static bool is_sysmmu_active(struct sysmmu_drvdata *data)
 193 {
 194         return data->activations > 0;
 195 }
 196 static void sysmmu_disable_stall(void __iomem *sfrbase)
 197 {
 198         int i;
 199         u32 mmu_status = __raw_readl(sfrbase+SYSMMU_REGISTER_STATUS);
 200         if ( 0 == (mmu_status & SYSMMU_STATUS_BIT_PAGING_ENABLED ))
 201         {
 202                 pr_err("MMU disable skipped since it was not enabled.\n");
 203                 return;
 204         }
 205         if (mmu_status & SYSMMU_STATUS_BIT_PAGE_FAULT_ACTIVE)
 206         {
 207                 pr_err("Aborting MMU disable stall request since it is in pagefault state.\n");
 208                 return;
 209         }
 210
 211         __raw_writel(SYSMMU_COMMAND_DISABLE_STALL, sfrbase + SYSMMU_REGISTER_COMMAND);
 212
 213         for (i = 0; i < SYSMMU_REG_POLL_COUNT_FAST; ++i)
 214         {
 215                 u32 status = __raw_readl(sfrbase + SYSMMU_REGISTER_STATUS);
 216                 if ( 0 == (status & SYSMMU_STATUS_BIT_STALL_ACTIVE) )
 217                 {
 218                         break;
 219                 }
 220                 if ( status &  SYSMMU_STATUS_BIT_PAGE_FAULT_ACTIVE )
 221                 {
 222                         break;
 223                 }
 224                 if ( 0 == (mmu_status & SYSMMU_STATUS_BIT_PAGING_ENABLED ))
 225                 {
 226                         break;
 227                 }
 228         }
 229         if (SYSMMU_REG_POLL_COUNT_FAST == i)
 230                 pr_err("Disable stall request failed, MMU status is 0x%08X\n", __raw_readl(sfrbase + SYSMMU_REGISTER_STATUS));
 231 }
 232 static bool sysmmu_enable_stall(void __iomem *sfrbase)
 233 {
 234         int i;
 235         u32 mmu_status = __raw_readl(sfrbase + SYSMMU_REGISTER_STATUS);
 236
 237         if ( 0 == (mmu_status & SYSMMU_STATUS_BIT_PAGING_ENABLED) )
 238         {
 239                 pr_info("MMU stall is implicit when Paging is not enabled.\n");
 240                 return true;
 241         }
 242         if ( mmu_status & SYSMMU_STATUS_BIT_PAGE_FAULT_ACTIVE )
 243         {
 244                 pr_err("Aborting MMU stall request since it is in pagefault state.\n");
 245                 return false;
 246         }
 247
 248         __raw_writel(SYSMMU_COMMAND_ENABLE_STALL, sfrbase + SYSMMU_REGISTER_COMMAND);
 249
 250         for (i = 0; i < SYSMMU_REG_POLL_COUNT_FAST; ++i)
 251         {
 252                 mmu_status = __raw_readl(sfrbase + SYSMMU_REGISTER_STATUS);
 253                 if (mmu_status & SYSMMU_STATUS_BIT_PAGE_FAULT_ACTIVE)
 254                 {
 255                         break;
 256                 }
 257                 if ((mmu_status & SYSMMU_STATUS_BIT_STALL_ACTIVE)&&(0==(mmu_status & SYSMMU_STATUS_BIT_STALL_NOT_ACTIVE)))
 258                 {
 259                         break;
 260                 }
 261                 if (0 == (mmu_status & ( SYSMMU_STATUS_BIT_PAGING_ENABLED )))
 262                 {
 263                         break;
 264                 }
 265         }
 266         if (SYSMMU_REG_POLL_COUNT_FAST == i)
 267         {
 268                 pr_info("Enable stall request failed, MMU status is 0x%08X\n", __raw_readl(sfrbase + SYSMMU_REGISTER_STATUS));
 269                 return false;
 270         }
 271         if ( mmu_status & SYSMMU_STATUS_BIT_PAGE_FAULT_ACTIVE )
 272         {
 273                 pr_info("Aborting MMU stall request since it has a pagefault.\n");
 274                 return false;
 275         }
 276         return true;
 277 }
 278
 279 static bool sysmmu_enable_paging(void __iomem *sfrbase)
 280 {
 281         int i;
 282         __raw_writel(SYSMMU_COMMAND_ENABLE_PAGING, sfrbase + SYSMMU_REGISTER_COMMAND);
 283
 284         for (i = 0; i < SYSMMU_REG_POLL_COUNT_FAST; ++i)
 285         {
 286                 if (__raw_readl(sfrbase + SYSMMU_REGISTER_STATUS) & SYSMMU_STATUS_BIT_PAGING_ENABLED)
 287                 {
 288                         pr_info("Enable paging request success.\n");
 289                         break;
 290                 }
 291         }
 292         if (SYSMMU_REG_POLL_COUNT_FAST == i)
 293         {
 294                 pr_err("Enable paging request failed, MMU status is 0x%08X\n", __raw_readl(sfrbase + SYSMMU_REGISTER_STATUS));
 295                 return false;
 296         }
 297         return true;
 298 }
 299 void sysmmu_page_fault_done(void __iomem *sfrbase,const char *dbgname)
 300 {
 301         pr_info("MMU: %s: Leaving page fault mode\n", dbgname);
 302         __raw_writel(SYSMMU_COMMAND_PAGE_FAULT_DONE, sfrbase + SYSMMU_REGISTER_COMMAND);
 303 }
 304 bool sysmmu_zap_tlb(void __iomem *sfrbase)
 305 {
 306         bool stall_success = sysmmu_enable_stall(sfrbase);
 307
 308         __raw_writel(SYSMMU_COMMAND_ZAP_CACHE, sfrbase + SYSMMU_REGISTER_COMMAND);
 309         if (false == stall_success)
 310         {
 311                 /* False means that it is in Pagefault state. Not possible to disable_stall then */
 312                 return false;
 313         }
 314         sysmmu_disable_stall(sfrbase);
 315         return true;
 316 }
 317 static inline int sysmmu_raw_reset(void __iomem *sfrbase)
 318 {
 319         int i;
 320         __raw_writel(0xCAFEBABE, sfrbase + SYSMMU_REGISTER_DTE_ADDR);
 321
 322         if(!(0xCAFEB000 == __raw_readl(sfrbase+SYSMMU_REGISTER_DTE_ADDR)))
 323         {
 324                 pr_err("error when %s.\n",__func__);
 325                 return -1;
 326         }
 327         __raw_writel(SYSMMU_COMMAND_HARD_RESET, sfrbase + SYSMMU_REGISTER_COMMAND);
 328
 329         for (i = 0; i < SYSMMU_REG_POLL_COUNT_FAST; ++i)
 330         {
 331                 if(__raw_readl(sfrbase + SYSMMU_REGISTER_DTE_ADDR) == 0)
 332                 {
 333                         break;
 334                 }
 335         }
 336         if (SYSMMU_REG_POLL_COUNT_FAST == i) {
 337                 pr_err("Reset request failed, MMU status is 0x%08X\n", __raw_readl(sfrbase + SYSMMU_REGISTER_DTE_ADDR));
 338                 return -1;
 339         }
 340         return 0;
 341 }
 342
 343 static bool sysmmu_reset(void __iomem *sfrbase,const char *dbgname)
 344 {
 345         bool err = false;
 346         bool stall_success;
 347
 348         stall_success = sysmmu_enable_stall(sfrbase);
 349         if(!stall_success)
 350         {
 351                 pr_info("sysmmu reset:stall failed: %s\n",dbgname);
 352                 return err ;
 353         }
 354         if(0 == sysmmu_raw_reset(sfrbase))
 355         {
 356                 __raw_writel(SYSMMU_INTERRUPT_PAGE_FAULT|SYSMMU_INTERRUPT_READ_BUS_ERROR, sfrbase+SYSMMU_REGISTER_INT_MASK);
 357                 err = sysmmu_enable_paging(sfrbase);
 358         }
 359         sysmmu_disable_stall(sfrbase);
 360         if(err)
 361                 pr_info("SYSMMU: reset successed: %s\n",dbgname);
 362         else
 363                 pr_info("SYSMMU: reset failed: %s\n", dbgname);
 364         return err;
 365 }
 366
 367 static void __sysmmu_set_ptbase(void __iomem *sfrbase,unsigned long pgd)
 368 {
 369         __raw_writel(pgd, sfrbase + SYSMMU_REGISTER_DTE_ADDR);
 370
 371 }
 372 static inline void pgtable_flush(void *vastart, void *vaend)
 373 {
 374         dmac_flush_range(vastart, vaend);
 375         outer_flush_range(virt_to_phys(vastart),virt_to_phys(vaend));
 376 }
 377 static void __set_fault_handler(struct sysmmu_drvdata *data,
 378                                         sysmmu_fault_handler_t handler)
 379 {
 380         unsigned long flags;
 381
 382         write_lock_irqsave(&data->lock, flags);
 383         data->fault_handler = handler;
 384         write_unlock_irqrestore(&data->lock, flags);
 385 }
 386
 387 void rockchip_sysmmu_set_fault_handler(struct device *dev,sysmmu_fault_handler_t handler)
 388 {
 389         struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
 390
 391         __set_fault_handler(data, handler);
 392 }
 393
 394 static int default_fault_handler(struct device *dev,
 395                                         enum rk_sysmmu_inttype itype,
 396                                         unsigned long pgtable_base,
 397                                         unsigned long fault_addr,
 398                                         unsigned int status
 399                                         )
 400 {
 401         struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
 402
 403         if ((itype >= SYSMMU_FAULTS_NUM) || (itype < SYSMMU_PAGEFAULT))
 404                 itype = SYSMMU_FAULT_UNKNOWN;
 405
 406         if(itype == SYSMMU_BUSERROR)
 407                 pr_err("%s occured at 0x%lx(Page table base: 0x%lx)\n",sysmmu_fault_name[itype], fault_addr, pgtable_base);
 408
 409         if(itype == SYSMMU_PAGEFAULT)
 410                 pr_err("SYSMMU:Page fault detected at 0x%lx from bus id %d of type %s on %s\n",
 411                                 fault_addr,
 412                                 (status >> 6) & 0x1F,
 413                                 (status & 32) ? "write" : "read",
 414                                 data->dbgname
 415                                 );
 416
 417         pr_err("Generating Kernel OOPS... because it is unrecoverable.\n");
 418
 419         BUG();
 420
 421         return 0;
 422 }
 423
 424 static irqreturn_t rockchip_sysmmu_irq(int irq, void *dev_id)
 425 {
 426         /* SYSMMU is in blocked when interrupt occurred. */
 427         struct sysmmu_drvdata *data = dev_id;
 428         struct resource *irqres;
 429         struct platform_device *pdev;
 430         enum rk_sysmmu_inttype itype = SYSMMU_FAULT_UNKNOWN;
 431         u32 status;
 432         u32 rawstat;
 433         u32 fault_address;
 434         int i, ret = -ENOSYS;
 435
 436         read_lock(&data->lock);
 437
 438         WARN_ON(!is_sysmmu_active(data));
 439
 440         pdev = to_platform_device(data->sysmmu);
 441         for (i = 0; i < data->num_res_irq; i++)
 442         {
 443                 irqres = platform_get_resource(pdev, IORESOURCE_IRQ, i);
 444                 if (irqres && ((int)irqres->start == irq))
 445                         break;
 446         }
 447
 448         if (i == data->num_res_irq)
 449         {
 450                 itype = SYSMMU_FAULT_UNKNOWN;
 451         }
 452         else
 453         {
 454                 status = __raw_readl(data->res_bases[i] + SYSMMU_REGISTER_STATUS);
 455                 if(status != 0)
 456                 {
 457                         rawstat = __raw_readl(data->res_bases[i] + SYSMMU_REGISTER_INT_RAWSTAT);
 458                         if(rawstat & SYSMMU_INTERRUPT_PAGE_FAULT)
 459                         {
 460                                 fault_address = __raw_readl(data->res_bases[i] + SYSMMU_REGISTER_PAGE_FAULT_ADDR);
 461                                 itype = SYSMMU_PAGEFAULT;
 462                         }
 463                         else if(rawstat & SYSMMU_INTERRUPT_READ_BUS_ERROR)
 464                         {
 465                                 itype = SYSMMU_BUSERROR;
 466                         }
 467                         else
 468                         {
 469                                 goto out;
 470                         }
 471                 }
 472         }
 473
 474         if (data->domain)
 475                 ret = report_iommu_fault(data->domain, data->dev,fault_address, itype);
 476
 477         if ((ret == -ENOSYS) && data->fault_handler)
 478         {
 479                 unsigned long base = data->pgtable;
 480                 if (itype != SYSMMU_FAULT_UNKNOWN)
 481                         base = __raw_readl(data->res_bases[i] + SYSMMU_REGISTER_DTE_ADDR);
 482                 ret = data->fault_handler(data->dev, itype, base, fault_address,status);
 483         }
 484
 485         if (!ret && (itype != SYSMMU_FAULT_UNKNOWN))
 486         {
 487                 if(SYSMMU_PAGEFAULT == itype)
 488                         sysmmu_page_fault_done(data->res_bases[i],data->dbgname);
 489                 sysmmu_reset(data->res_bases[i],data->dbgname);
 490         }
 491         else
 492                 pr_err("(%s) %s is not handled.\n",data->dbgname, sysmmu_fault_name[itype]);
 493
 494 out :
 495         read_unlock(&data->lock);
 496
 497         return IRQ_HANDLED;
 498 }
 499
 500 static bool __rockchip_sysmmu_disable(struct sysmmu_drvdata *data)
 501 {
 502         unsigned long flags;
 503         bool disabled = false;
 504         int i;
 505         write_lock_irqsave(&data->lock, flags);
 506
 507         if (!set_sysmmu_inactive(data))
 508                 goto finish;
 509
 510         for(i=0;i<data->num_res_mem;i++)
 511         {
 512                 if(!sysmmu_reset(data->res_bases[i],data->dbgname))
 513                 goto finish;
 514         }
 515         disabled = true;
 516         data->pgtable = 0;
 517         data->domain = NULL;
 518 finish:
 519         write_unlock_irqrestore(&data->lock, flags);
 520
 521         if (disabled)
 522                 pr_info("(%s) Disabled\n", data->dbgname);
 523         else
 524                 pr_info("(%s) %d times left to be disabled\n",data->dbgname, data->activations);
 525
 526         return disabled;
 527 }
 528
 529 /* __rk_sysmmu_enable: Enables System MMU
 530  *
 531  * returns -error if an error occurred and System MMU is not enabled,
 532  * 0 if the System MMU has been just enabled and 1 if System MMU was already
 533  * enabled before.
 534  */
 535 static int __rockchip_sysmmu_enable(struct sysmmu_drvdata *data,unsigned long pgtable, struct iommu_domain *domain)
 536 {
 537         int i, ret = 0;
 538         unsigned long flags;
 539
 540         write_lock_irqsave(&data->lock, flags);
 541
 542         if (!set_sysmmu_active(data))
 543         {
 544                 if (WARN_ON(pgtable != data->pgtable))
 545                 {
 546                         ret = -EBUSY;
 547                         set_sysmmu_inactive(data);
 548                 }
 549                 else
 550                         ret = 1;
 551
 552                 pr_info("(%s) Already enabled\n", data->dbgname);
 553                 goto finish;
 554         }
 555
 556         data->pgtable = pgtable;
 557
 558         for (i = 0; i < data->num_res_mem; i++)
 559         {
 560                 bool status;
 561                 status = sysmmu_enable_stall(data->res_bases[i]);
 562                 if(status)
 563                 {
 564                         __sysmmu_set_ptbase(data->res_bases[i], pgtable);
 565                         __raw_writel(SYSMMU_COMMAND_ZAP_CACHE, data->res_bases[i] + SYSMMU_REGISTER_COMMAND);
 566                 }
 567                 sysmmu_disable_stall(data->res_bases[i]);
 568         }
 569
 570         data->domain = domain;
 571
 572         pr_info("(%s) Enabled\n", data->dbgname);
 573 finish:
 574         write_unlock_irqrestore(&data->lock, flags);
 575
 576         return ret;
 577 }
 578 bool rockchip_sysmmu_disable(struct device *dev)
 579 {
 580         struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
 581         bool disabled;
 582
 583         disabled = __rockchip_sysmmu_disable(data);
 584
 585         return disabled;
 586 }
 587 void rockchip_sysmmu_tlb_invalidate(struct device *dev)
 588 {
 589         unsigned long flags;
 590         struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
 591
 592         read_lock_irqsave(&data->lock, flags);
 593
 594         if (is_sysmmu_active(data))
 595         {
 596                 int i;
 597                 for (i = 0; i < data->num_res_mem; i++)
 598                 {
 599                         if(!sysmmu_zap_tlb(data->res_bases[i]))
 600                                 pr_err("%s,invalidating TLB failed\n",data->dbgname);
 601                 }
 602         }
 603         else
 604                 pr_info("(%s) Disabled. Skipping invalidating TLB.\n",data->dbgname);
 605
 606         read_unlock_irqrestore(&data->lock, flags);
 607 }
 608 static phys_addr_t rockchip_iommu_iova_to_phys(struct iommu_domain *domain,dma_addr_t iova)
 609 {
 610         struct rk_iommu_domain *priv = domain->priv;
 611         unsigned long *entry;
 612         unsigned long flags;
 613         phys_addr_t phys = 0;
 614
 615         spin_lock_irqsave(&priv->pgtablelock, flags);
 616
 617         entry = section_entry(priv->pgtable, iova);
 618         entry = page_entry(entry, iova);
 619         phys = spage_phys(entry) + spage_offs(iova);
 620
 621         spin_unlock_irqrestore(&priv->pgtablelock, flags);
 622
 623         return phys;
 624 }
 625 static int lv2set_page(unsigned long *pent, phys_addr_t paddr, size_t size,
 626                                                                 short *pgcnt)
 627 {
 628         if (!lv2ent_fault(pent))
 629                 return -EADDRINUSE;
 630
 631         *pent = mk_lv2ent_spage(paddr);
 632         pgtable_flush(pent, pent + 1);
 633         *pgcnt -= 1;
 634         return 0;
 635 }
 636
 637 static unsigned long *alloc_lv2entry(unsigned long *sent, unsigned long iova,short *pgcounter)
 638 {
 639         if (lv1ent_fault(sent))
 640         {
 641                 unsigned long *pent;
 642
 643                 pent = kmem_cache_zalloc(lv2table_kmem_cache, GFP_ATOMIC);
 644                 BUG_ON((unsigned long)pent & (LV2TABLE_SIZE - 1));
 645                 if (!pent)
 646                         return NULL;
 647
 648                 *sent = mk_lv1ent_page(__pa(pent));
 649                 kmemleak_ignore(pent);
 650                 *pgcounter = NUM_LV2ENTRIES;
 651                 pgtable_flush(pent, pent + NUM_LV2ENTRIES);
 652                 pgtable_flush(sent, sent + 1);
 653         }
 654         return page_entry(sent, iova);
 655 }
 656
 657 static size_t rockchip_iommu_unmap(struct iommu_domain *domain,unsigned long iova, size_t size)
 658 {
 659         struct rk_iommu_domain *priv = domain->priv;
 660         unsigned long flags;
 661         unsigned long *ent;
 662
 663         BUG_ON(priv->pgtable == NULL);
 664
 665         spin_lock_irqsave(&priv->pgtablelock, flags);
 666
 667         ent = section_entry(priv->pgtable, iova);
 668
 669         if (unlikely(lv1ent_fault(ent)))
 670         {
 671                 if (size > SPAGE_SIZE)
 672                         size = SPAGE_SIZE;
 673                 goto done;
 674         }
 675
 676         /* lv1ent_page(sent) == true here */
 677
 678         ent = page_entry(ent, iova);
 679
 680         if (unlikely(lv2ent_fault(ent)))
 681         {
 682                 size = SPAGE_SIZE;
 683                 goto done;
 684         }
 685
 686         *ent = 0;
 687         size = SPAGE_SIZE;
 688         priv->lv2entcnt[lv1ent_offset(iova)] += 1;
 689         goto done;
 690
 691 done:
 692         pr_info("%s:unmap iova 0x%lx/0x%x bytes\n",__func__, iova,size);
 693         spin_unlock_irqrestore(&priv->pgtablelock, flags);
 694
 695         return size;
 696 }
 697 static int rockchip_iommu_map(struct iommu_domain *domain, unsigned long iova,
 698                          phys_addr_t paddr, size_t size, int prot)
 699 {
 700         struct rk_iommu_domain *priv = domain->priv;
 701         unsigned long *entry;
 702         unsigned long flags;
 703         int ret = -ENOMEM;
 704         unsigned long *pent;
 705
 706         BUG_ON(priv->pgtable == NULL);
 707
 708         spin_lock_irqsave(&priv->pgtablelock, flags);
 709
 710         entry = section_entry(priv->pgtable, iova);
 711
 712         pent = alloc_lv2entry(entry, iova,&priv->lv2entcnt[lv1ent_offset(iova)]);
 713         if (!pent)
 714                 ret = -ENOMEM;
 715         else
 716                 ret = lv2set_page(pent, paddr, size,&priv->lv2entcnt[lv1ent_offset(iova)]);
 717
 718         if (ret)
 719         {
 720                 pr_debug("%s: Failed to map iova 0x%lx/0x%x bytes\n",__func__, iova, size);
 721         }
 722         spin_unlock_irqrestore(&priv->pgtablelock, flags);
 723
 724         return ret;
 725 }
 726
 727 static void rockchip_iommu_detach_device(struct iommu_domain *domain,
 728                                     struct device *dev)
 729 {
 730         struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
 731         struct rk_iommu_domain *priv = domain->priv;
 732         struct list_head *pos;
 733         unsigned long flags;
 734         bool found = false;
 735
 736         spin_lock_irqsave(&priv->lock, flags);
 737
 738         list_for_each(pos, &priv->clients)
 739         {
 740                 if (list_entry(pos, struct sysmmu_drvdata, node) == data)
 741                 {
 742                         found = true;
 743                         break;
 744                 }
 745         }
 746         if (!found)
 747                 goto finish;
 748
 749         if (__rockchip_sysmmu_disable(data))
 750         {
 751                 pr_info("%s: Detached IOMMU with pgtable %#lx\n",__func__, __pa(priv->pgtable));
 752                 list_del(&data->node);
 753                 INIT_LIST_HEAD(&data->node);
 754
 755         }
 756         else
 757                 pr_info("%s: Detaching IOMMU with pgtable %#lx delayed",__func__, __pa(priv->pgtable));
 758
 759 finish:
 760         spin_unlock_irqrestore(&priv->lock, flags);
 761 }
 762 static int rockchip_iommu_attach_device(struct iommu_domain *domain,struct device *dev)
 763 {
 764         struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
 765         struct rk_iommu_domain *priv = domain->priv;
 766         unsigned long flags;
 767         int ret;
 768
 769         spin_lock_irqsave(&priv->lock, flags);
 770
 771         ret = __rockchip_sysmmu_enable(data, __pa(priv->pgtable), domain);
 772
 773         if (ret == 0)
 774         {
 775                 /* 'data->node' must not be appeared in priv->clients */
 776                 BUG_ON(!list_empty(&data->node));
 777                 data->dev = dev;
 778                 list_add_tail(&data->node, &priv->clients);
 779         }
 780
 781         spin_unlock_irqrestore(&priv->lock, flags);
 782
 783         if (ret < 0)
 784         {
 785                 pr_err("%s: Failed to attach IOMMU with pgtable %#lx\n",__func__, __pa(priv->pgtable));
 786         }
 787         else if (ret > 0)
 788         {
 789                 pr_info("%s: IOMMU with pgtable 0x%lx already attached\n",__func__, __pa(priv->pgtable));
 790         }
 791         else
 792         {
 793                 pr_info("%s: Attached new IOMMU with pgtable 0x%lx\n",__func__, __pa(priv->pgtable));
 794         }
 795
 796         return ret;
 797 }
 798 static void rockchip_iommu_domain_destroy(struct iommu_domain *domain)
 799 {
 800         struct rk_iommu_domain *priv = domain->priv;
 801         struct sysmmu_drvdata *data;
 802         unsigned long flags;
 803         int i;
 804
 805         WARN_ON(!list_empty(&priv->clients));
 806
 807         spin_lock_irqsave(&priv->lock, flags);
 808
 809         list_for_each_entry(data, &priv->clients, node)
 810         {
 811                 while (!rockchip_sysmmu_disable(data->dev))
 812                         ; /* until System MMU is actually disabled */
 813         }
 814         spin_unlock_irqrestore(&priv->lock, flags);
 815
 816         for (i = 0; i < NUM_LV1ENTRIES; i++)
 817                 if (lv1ent_page(priv->pgtable + i))
 818                         kmem_cache_free(lv2table_kmem_cache,__va(lv2table_base(priv->pgtable + i)));
 819
 820         free_pages((unsigned long)priv->pgtable, 0);
 821         free_pages((unsigned long)priv->lv2entcnt, 0);
 822         kfree(domain->priv);
 823         domain->priv = NULL;
 824 }
 825
 826 static int rockchip_iommu_domain_init(struct iommu_domain *domain)
 827 {
 828         struct rk_iommu_domain *priv;
 829
 830         priv = kzalloc(sizeof(*priv), GFP_KERNEL);
 831         if (!priv)
 832                 return -ENOMEM;
 833
 834 /*rk32xx sysmmu use 2 level pagetable,
 835    level1 and leve2 both have 1024 entries,each entry  occupy 4 bytes,
 836    so alloc a page size for each page table
 837 */
 838         priv->pgtable = (unsigned long *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, 0);
 839         if (!priv->pgtable)
 840                 goto err_pgtable;
 841
 842         priv->lv2entcnt = (short *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, 0);
 843         if (!priv->lv2entcnt)
 844                 goto err_counter;
 845
 846         pgtable_flush(priv->pgtable, priv->pgtable + NUM_LV1ENTRIES);
 847
 848         spin_lock_init(&priv->lock);
 849         spin_lock_init(&priv->pgtablelock);
 850         INIT_LIST_HEAD(&priv->clients);
 851
 852         domain->priv = priv;
 853         return 0;
 854
 855 err_counter:
 856         free_pages((unsigned long)priv->pgtable, 2);
 857 err_pgtable:
 858         kfree(priv);
 859         return -ENOMEM;
 860 }
 861
 862 static struct iommu_ops rk_iommu_ops =
 863 {
 864         .domain_init = &rockchip_iommu_domain_init,
 865         .domain_destroy = &rockchip_iommu_domain_destroy,
 866         .attach_dev = &rockchip_iommu_attach_device,
 867         .detach_dev = &rockchip_iommu_detach_device,
 868         .map = &rockchip_iommu_map,
 869         .unmap = &rockchip_iommu_unmap,
 870         .iova_to_phys = &rockchip_iommu_iova_to_phys,
 871         .pgsize_bitmap = SPAGE_SIZE,
 872 };
 873
 874 static int rockchip_sysmmu_prepare(void)
 875 {
 876         int ret = 0;
 877         static int registed = 0;
 878
 879         if(registed)
 880                 return 0;
 881
 882         lv2table_kmem_cache = kmem_cache_create("rk-iommu-lv2table",LV2TABLE_SIZE, LV2TABLE_SIZE, 0, NULL);
 883         if (!lv2table_kmem_cache)
 884         {
 885                 pr_err("%s: failed to create kmem cache\n", __func__);
 886                 return -ENOMEM;
 887         }
 888         ret = bus_set_iommu(&platform_bus_type, &rk_iommu_ops);
 889         if(!ret)
 890                 registed = 1;
 891         else
 892                 pr_err("%s:failed to set iommu to bus\r\n",__func__);
 893         return ret;
 894 }
 895 static int  rockchip_get_sysmmu_resource_num(struct platform_device *pdev,unsigned int type)
 896 {
 897         struct resource *info = NULL;
 898         int num_resources = 0;
 899
 900         /*get resouce info*/
 901 again:
 902         info = platform_get_resource(pdev, type, num_resources);
 903         while(info)
 904         {
 905                 num_resources++;
 906                 goto again;
 907         }
 908
 909         if(IORESOURCE_MEM == type)
 910                 pr_info("have memory resource %d\r\n",num_resources);
 911         if(IORESOURCE_IRQ == type)
 912                 pr_info("have IRQ resource %d\r\n",num_resources);
 913         return num_resources;
 914 }
 915
 916 static int rockchip_sysmmu_probe(struct platform_device *pdev)
 917 {
 918         int i, ret;
 919         struct device *dev;
 920         struct sysmmu_drvdata *data;
 921
 922         dev = &pdev->dev;
 923
 924         ret = rockchip_sysmmu_prepare();
 925         if(ret)
 926         {
 927                 pr_err("%s,failed\r\n",__func__);
 928                 goto err_alloc;
 929         }
 930
 931         data = devm_kzalloc(dev,sizeof(*data), GFP_KERNEL);
 932         if (!data)
 933         {
 934                 dev_dbg(dev, "Not enough memory\n");
 935                 ret = -ENOMEM;
 936                 goto err_alloc;
 937         }
 938
 939         ret = dev_set_drvdata(dev, data);
 940         if (ret)
 941         {
 942                 dev_dbg(dev, "Unabled to initialize driver data\n");
 943                 goto err_init;
 944         }
 945
 946         /*rk32xx sysmmu need both irq and memory */
 947         data->num_res_mem = rockchip_get_sysmmu_resource_num(pdev,IORESOURCE_MEM);
 948         if(0 == data->num_res_mem)
 949         {
 950                 pr_err("can't find sysmmu memory resource \r\n");
 951                 goto err_init;
 952         }
 953         data->num_res_irq = rockchip_get_sysmmu_resource_num(pdev,IORESOURCE_IRQ);
 954         if(0 == data->num_res_irq)
 955         {
 956                 pr_err("can't find sysmmu irq resource \r\n");
 957                 goto err_init;
 958         }
 959
 960         data->res_bases = kmalloc(sizeof(*data->res_bases) * data->num_res_mem,GFP_KERNEL);
 961         if (data->res_bases == NULL)
 962         {
 963                 dev_dbg(dev, "Not enough memory\n");
 964                 ret = -ENOMEM;
 965                 goto err_init;
 966         }
 967
 968         for (i = 0; i < data->num_res_mem; i++)
 969         {
 970                 struct resource *res;
 971                 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
 972                 if (!res)
 973                 {
 974                         pr_err("Unable to find IOMEM region\n");
 975                         ret = -ENOENT;
 976                         goto err_res;
 977                 }
 978                 data->res_bases[i] = ioremap(res->start, resource_size(res));
 979                 if (!data->res_bases[i])
 980                 {
 981                         pr_err("Unable to map IOMEM @ PA:%#x\n",res->start);
 982                         ret = -ENOENT;
 983                         goto err_res;
 984                 }
 985                 /*reset sysmmu*/
 986                 if(!sysmmu_reset(data->res_bases[i],data->dbgname))
 987                 {
 988                         ret = -ENOENT;
 989                         goto err_res;
 990                 }
 991         }
 992
 993         for (i = 0; i < data->num_res_irq; i++)
 994         {
 995                 ret = platform_get_irq(pdev, i);
 996                 if (ret <= 0)
 997                 {
 998                         pr_err("Unable to find IRQ resource\n");
 999                         goto err_irq;
1000                 }
1001                 ret = request_irq(ret, rockchip_sysmmu_irq, IRQF_SHARED ,dev_name(dev), data);
1002                 if (ret)
1003                 {
1004                         pr_err("Unabled to register interrupt handler\n");
1005                         goto err_irq;
1006                 }
1007         }
1008
1009         if(pdev->dev.of_node)
1010         {
1011                 of_property_read_string(pdev->dev.of_node,"dbgname",&(data->dbgname));
1012                 pr_info("dbgname : %s\n",data->dbgname);
1013         }
1014         else
1015         {
1016                 pr_info("dbgname not assigned in device tree or device node not exist\r\n");
1017         }
1018         ret = rockchip_init_iovmm(dev, &data->vmm);
1019         if (ret)
1020                 goto err_irq;
1021
1022         data->sysmmu = dev;
1023         rwlock_init(&data->lock);
1024         INIT_LIST_HEAD(&data->node);
1025
1026         __set_fault_handler(data, &default_fault_handler);
1027
1028         pr_info("(%s) Initialized\n", data->dbgname);
1029         return 0;
1030
1031 err_irq:
1032         while (i-- > 0)
1033         {
1034                 int irq;
1035
1036                 irq = platform_get_irq(pdev, i);
1037                 free_irq(irq, data);
1038         }
1039 err_res:
1040         while (data->num_res_mem-- > 0)
1041                 iounmap(data->res_bases[data->num_res_mem]);
1042         kfree(data->res_bases);
1043 err_init:
1044         kfree(data);
1045 err_alloc:
1046         dev_err(dev, "Failed to initialize\n");
1047         return ret;
1048 }
1049
1050 #ifdef CONFIG_OF
1051 static const struct of_device_id sysmmu_dt_ids[] =
1052 {
1053         { .compatible = IEP_SYSMMU_COMPATIBLE_NAME},
1054         { .compatible = VIP_SYSMMU_COMPATIBLE_NAME},
1055         { .compatible = ISP0_SYSMMU_COMPATIBLE_NAME},
1056         { .compatible = ISP1_SYSMMU_COMPATIBLE_NAME},
1057         { .compatible = VOPB_SYSMMU_COMPATIBLE_NAME},
1058         { .compatible = VOPL_SYSMMU_COMPATIBLE_NAME},
1059         { /* end */ }
1060 };
1061 MODULE_DEVICE_TABLE(of, sysmmu_dt_ids);
1062 #endif
1063
1064 static struct platform_driver rk_sysmmu_driver =
1065 {
1066         .probe = rockchip_sysmmu_probe,
1067         .remove = NULL,
1068         .driver =
1069         {
1070                    .name = "rk_sysmmu",
1071                    .owner = THIS_MODULE,
1072                    .of_match_table = of_match_ptr(sysmmu_dt_ids),
1073         },
1074 };
1075
1076 #if 0
1077 /*I don't know why this can't work*/
1078 #ifdef CONFIG_OF
1079 module_platform_driver(rk_sysmmu_driver);
1080 #endif
1081 #endif
1082 static int __init rockchip_sysmmu_init_driver(void)
1083 {
1084         return platform_driver_register(&rk_sysmmu_driver);
1085 }
1086
1087 core_initcall(rockchip_sysmmu_init_driver);
1088