2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License version 2 as
4 * published by the Free Software Foundation.
7 #ifdef CONFIG_ROCKCHIP_IOMMU_DEBUG
12 #include <linux/interrupt.h>
13 #include <linux/slab.h>
14 #include <linux/clk.h>
15 #include <linux/err.h>
17 #include <linux/errno.h>
18 #include <linux/memblock.h>
19 #include <linux/export.h>
20 #include <linux/module.h>
22 #include <asm/cacheflush.h>
23 #include <asm/pgtable.h>
25 #include <linux/rockchip/sysmmu.h>
26 #include <linux/rockchip/iomap.h>
27 #include <linux/rockchip/grf.h>
29 #include "rockchip-iommu.h"
31 /* We does not consider super section mapping (16MB) */
32 #define SPAGE_ORDER 12
33 #define SPAGE_SIZE (1 << SPAGE_ORDER)
34 #define SPAGE_MASK (~(SPAGE_SIZE - 1))
35 typedef enum sysmmu_entry_flags
37 SYSMMU_FLAGS_PRESENT = 0x01,
38 SYSMMU_FLAGS_READ_PERMISSION = 0x02,
39 SYSMMU_FLAGS_WRITE_PERMISSION = 0x04,
40 SYSMMU_FLAGS_OVERRIDE_CACHE = 0x8,
41 SYSMMU_FLAGS_WRITE_CACHEABLE = 0x10,
42 SYSMMU_FLAGS_WRITE_ALLOCATE = 0x20,
43 SYSMMU_FLAGS_WRITE_BUFFERABLE = 0x40,
44 SYSMMU_FLAGS_READ_CACHEABLE = 0x80,
45 SYSMMU_FLAGS_READ_ALLOCATE = 0x100,
46 SYSMMU_FLAGS_MASK = 0x1FF,
49 #define lv1ent_fault(sent) ((*(sent) & SYSMMU_FLAGS_PRESENT) == 0)
50 #define lv1ent_page(sent) ((*(sent) & SYSMMU_FLAGS_PRESENT) == 1)
51 #define lv2ent_fault(pent) ((*(pent) & SYSMMU_FLAGS_PRESENT) == 0)
52 #define spage_phys(pent) (*(pent) & SPAGE_MASK)
53 #define spage_offs(iova) ((iova) & 0x0FFF)
55 #define lv1ent_offset(iova) (((iova)>>22) & 0x03FF)
56 #define lv2ent_offset(iova) (((iova)>>12) & 0x03FF)
58 #define NUM_LV1ENTRIES 1024
59 #define NUM_LV2ENTRIES 1024
61 #define LV2TABLE_SIZE (NUM_LV2ENTRIES * sizeof(long))
63 #define lv2table_base(sent) (*(sent) & 0xFFFFFFFE)
65 #define mk_lv1ent_page(pa) ((pa) | SYSMMU_FLAGS_PRESENT)
66 /*write and read permission for level2 page default*/
67 #define mk_lv2ent_spage(pa) ((pa) | SYSMMU_FLAGS_PRESENT |SYSMMU_FLAGS_READ_PERMISSION |SYSMMU_FLAGS_WRITE_PERMISSION)
69 #define SYSMMU_REG_POLL_COUNT_FAST 1000
71 /*rk3036:vpu and hevc share ahb interface*/
72 #define BIT_VCODEC_SEL (1<<3)
76 * MMU register numbers
77 * Used in the register read/write routines.
78 * See the hardware documentation for more information about each register
80 typedef enum sysmmu_register
82 SYSMMU_REGISTER_DTE_ADDR = 0x0000, /**< Current Page Directory Pointer */
83 SYSMMU_REGISTER_STATUS = 0x0004, /**< Status of the MMU */
84 SYSMMU_REGISTER_COMMAND = 0x0008, /**< Command register, used to control the MMU */
85 SYSMMU_REGISTER_PAGE_FAULT_ADDR = 0x000C, /**< Logical address of the last page fault */
86 SYSMMU_REGISTER_ZAP_ONE_LINE = 0x010, /**< Used to invalidate the mapping of a single page from the MMU */
87 SYSMMU_REGISTER_INT_RAWSTAT = 0x0014, /**< Raw interrupt status, all interrupts visible */
88 SYSMMU_REGISTER_INT_CLEAR = 0x0018, /**< Indicate to the MMU that the interrupt has been received */
89 SYSMMU_REGISTER_INT_MASK = 0x001C, /**< Enable/disable types of interrupts */
90 SYSMMU_REGISTER_INT_STATUS = 0x0020, /**< Interrupt status based on the mask */
91 SYSMMU_REGISTER_AUTO_GATING = 0x0024
94 typedef enum sysmmu_command
96 SYSMMU_COMMAND_ENABLE_PAGING = 0x00, /**< Enable paging (memory translation) */
97 SYSMMU_COMMAND_DISABLE_PAGING = 0x01, /**< Disable paging (memory translation) */
98 SYSMMU_COMMAND_ENABLE_STALL = 0x02, /**< Enable stall on page fault */
99 SYSMMU_COMMAND_DISABLE_STALL = 0x03, /**< Disable stall on page fault */
100 SYSMMU_COMMAND_ZAP_CACHE = 0x04, /**< Zap the entire page table cache */
101 SYSMMU_COMMAND_PAGE_FAULT_DONE = 0x05, /**< Page fault processed */
102 SYSMMU_COMMAND_HARD_RESET = 0x06 /**< Reset the MMU back to power-on settings */
106 * MMU interrupt register bits
107 * Each cause of the interrupt is reported
108 * through the (raw) interrupt status registers.
109 * Multiple interrupts can be pending, so multiple bits
110 * can be set at once.
112 typedef enum sysmmu_interrupt
114 SYSMMU_INTERRUPT_PAGE_FAULT = 0x01, /**< A page fault occured */
115 SYSMMU_INTERRUPT_READ_BUS_ERROR = 0x02 /**< A bus read error occured */
118 typedef enum sysmmu_status_bits
120 SYSMMU_STATUS_BIT_PAGING_ENABLED = 1 << 0,
121 SYSMMU_STATUS_BIT_PAGE_FAULT_ACTIVE = 1 << 1,
122 SYSMMU_STATUS_BIT_STALL_ACTIVE = 1 << 2,
123 SYSMMU_STATUS_BIT_IDLE = 1 << 3,
124 SYSMMU_STATUS_BIT_REPLAY_BUFFER_EMPTY = 1 << 4,
125 SYSMMU_STATUS_BIT_PAGE_FAULT_IS_WRITE = 1 << 5,
126 SYSMMU_STATUS_BIT_STALL_NOT_ACTIVE = 1 << 31,
127 } sys_mmu_status_bits;
130 * Size of an MMU page in bytes
132 #define SYSMMU_PAGE_SIZE 0x1000
135 * Size of the address space referenced by a page table page
137 #define SYSMMU_VIRTUAL_PAGE_SIZE 0x400000 /* 4 MiB */
140 * Page directory index from address
141 * Calculates the page directory index from the given address
143 #define SYSMMU_PDE_ENTRY(address) (((address)>>22) & 0x03FF)
146 * Page table index from address
147 * Calculates the page table index from the given address
149 #define SYSMMU_PTE_ENTRY(address) (((address)>>12) & 0x03FF)
152 * Extract the memory address from an PDE/PTE entry
154 #define SYSMMU_ENTRY_ADDRESS(value) ((value) & 0xFFFFFC00)
156 #define INVALID_PAGE ((u32)(~0))
158 static struct kmem_cache *lv2table_kmem_cache;
160 static void rockchip_vcodec_select(const char *string)
162 if(strstr(string,"hevc"))
164 writel_relaxed(readl_relaxed(RK_GRF_VIRT + RK3036_GRF_SOC_CON1) |
165 (BIT_VCODEC_SEL) | (BIT_VCODEC_SEL << 16),
166 RK_GRF_VIRT + RK3036_GRF_SOC_CON1);
168 else if(strstr(string,"vpu"))
170 writel_relaxed((readl_relaxed(RK_GRF_VIRT + RK3036_GRF_SOC_CON1) &
171 (~BIT_VCODEC_SEL)) | (BIT_VCODEC_SEL << 16),
172 RK_GRF_VIRT + RK3036_GRF_SOC_CON1);
175 static unsigned long *section_entry(unsigned long *pgtable, unsigned long iova)
177 return pgtable + lv1ent_offset(iova);
180 static unsigned long *page_entry(unsigned long *sent, unsigned long iova)
182 return (unsigned long *)__va(lv2table_base(sent)) + lv2ent_offset(iova);
185 static char *sysmmu_fault_name[SYSMMU_FAULTS_NUM] = {
191 struct rk_iommu_domain {
192 struct list_head clients; /* list of sysmmu_drvdata.node */
193 unsigned long *pgtable; /* lv1 page table, 4KB */
194 short *lv2entcnt; /* free lv2 entry counter for each section */
195 spinlock_t lock; /* lock for this structure */
196 spinlock_t pgtablelock; /* lock for modifying page table @ pgtable */
199 static bool set_sysmmu_active(struct sysmmu_drvdata *data)
201 /* return true if the System MMU was not active previously
202 and it needs to be initialized */
203 return ++data->activations == 1;
206 static bool set_sysmmu_inactive(struct sysmmu_drvdata *data)
208 /* return true if the System MMU is needed to be disabled */
209 BUG_ON(data->activations < 1);
210 return --data->activations == 0;
213 static bool is_sysmmu_active(struct sysmmu_drvdata *data)
215 return data->activations > 0;
217 static void sysmmu_disable_stall(void __iomem *base)
220 u32 mmu_status = __raw_readl(base+SYSMMU_REGISTER_STATUS);
221 if ( 0 == (mmu_status & SYSMMU_STATUS_BIT_PAGING_ENABLED ))
225 if (mmu_status & SYSMMU_STATUS_BIT_PAGE_FAULT_ACTIVE)
227 pr_err("Aborting MMU disable stall request since it is in pagefault state.\n");
231 __raw_writel(SYSMMU_COMMAND_DISABLE_STALL, base + SYSMMU_REGISTER_COMMAND);
233 for (i = 0; i < SYSMMU_REG_POLL_COUNT_FAST; ++i)
235 u32 status = __raw_readl(base + SYSMMU_REGISTER_STATUS);
236 if ( 0 == (status & SYSMMU_STATUS_BIT_STALL_ACTIVE) )
240 if ( status & SYSMMU_STATUS_BIT_PAGE_FAULT_ACTIVE )
244 if ( 0 == (mmu_status & SYSMMU_STATUS_BIT_PAGING_ENABLED ))
249 if (SYSMMU_REG_POLL_COUNT_FAST == i)
250 pr_err("Disable stall request failed, MMU status is 0x%08X\n", __raw_readl(base + SYSMMU_REGISTER_STATUS));
252 static bool sysmmu_enable_stall(void __iomem *base)
255 u32 mmu_status = __raw_readl(base + SYSMMU_REGISTER_STATUS);
257 if ( 0 == (mmu_status & SYSMMU_STATUS_BIT_PAGING_ENABLED) )
259 /*pr_info("MMU stall is implicit when Paging is not enabled.\n");*/
262 if ( mmu_status & SYSMMU_STATUS_BIT_PAGE_FAULT_ACTIVE )
264 pr_err("Aborting MMU stall request since it is in pagefault state.\n");
268 __raw_writel(SYSMMU_COMMAND_ENABLE_STALL, base + SYSMMU_REGISTER_COMMAND);
270 for (i = 0; i < SYSMMU_REG_POLL_COUNT_FAST; ++i)
272 mmu_status = __raw_readl(base + SYSMMU_REGISTER_STATUS);
273 if (mmu_status & SYSMMU_STATUS_BIT_PAGE_FAULT_ACTIVE)
277 if ((mmu_status & SYSMMU_STATUS_BIT_STALL_ACTIVE)&&(0==(mmu_status & SYSMMU_STATUS_BIT_STALL_NOT_ACTIVE)))
281 if (0 == (mmu_status & ( SYSMMU_STATUS_BIT_PAGING_ENABLED )))
286 if (SYSMMU_REG_POLL_COUNT_FAST == i)
288 pr_err("Enable stall request failed, MMU status is 0x%08X\n", __raw_readl(base + SYSMMU_REGISTER_STATUS));
291 if ( mmu_status & SYSMMU_STATUS_BIT_PAGE_FAULT_ACTIVE )
293 pr_err("Aborting MMU stall request since it has a pagefault.\n");
299 static bool sysmmu_enable_paging(void __iomem *base)
302 __raw_writel(SYSMMU_COMMAND_ENABLE_PAGING, base + SYSMMU_REGISTER_COMMAND);
304 for (i = 0; i < SYSMMU_REG_POLL_COUNT_FAST; ++i)
306 if (__raw_readl(base + SYSMMU_REGISTER_STATUS) & SYSMMU_STATUS_BIT_PAGING_ENABLED)
308 /*pr_info("Enable paging request success.\n");*/
312 if (SYSMMU_REG_POLL_COUNT_FAST == i)
314 pr_err("Enable paging request failed, MMU status is 0x%08X\n", __raw_readl(base + SYSMMU_REGISTER_STATUS));
319 static bool sysmmu_disable_paging(void __iomem *base)
322 __raw_writel(SYSMMU_COMMAND_DISABLE_PAGING, base + SYSMMU_REGISTER_COMMAND);
324 for (i = 0; i < SYSMMU_REG_POLL_COUNT_FAST; ++i)
326 if (!(__raw_readl(base + SYSMMU_REGISTER_STATUS) & SYSMMU_STATUS_BIT_PAGING_ENABLED))
328 /*pr_info("Disable paging request success.\n");*/
332 if (SYSMMU_REG_POLL_COUNT_FAST == i)
334 pr_err("Disable paging request failed, MMU status is 0x%08X\n", __raw_readl(base + SYSMMU_REGISTER_STATUS));
340 static void sysmmu_page_fault_done(void __iomem *base,const char *dbgname)
342 pr_info("MMU: %s: Leaving page fault mode\n", dbgname);
343 __raw_writel(SYSMMU_COMMAND_PAGE_FAULT_DONE, base + SYSMMU_REGISTER_COMMAND);
345 static bool sysmmu_zap_tlb(void __iomem *base)
347 bool stall_success = sysmmu_enable_stall(base);
349 __raw_writel(SYSMMU_COMMAND_ZAP_CACHE, base + SYSMMU_REGISTER_COMMAND);
350 if (false == stall_success)
352 /* False means that it is in Pagefault state. Not possible to disable_stall then */
355 sysmmu_disable_stall(base);
358 static inline bool sysmmu_raw_reset(void __iomem *base)
361 __raw_writel(0xCAFEBABE, base + SYSMMU_REGISTER_DTE_ADDR);
363 if(!(0xCAFEB000 == __raw_readl(base+SYSMMU_REGISTER_DTE_ADDR)))
365 pr_err("error when %s.\n",__func__);
368 __raw_writel(SYSMMU_COMMAND_HARD_RESET, base + SYSMMU_REGISTER_COMMAND);
370 for (i = 0; i < SYSMMU_REG_POLL_COUNT_FAST; ++i)
372 if(__raw_readl(base + SYSMMU_REGISTER_DTE_ADDR) == 0)
377 if (SYSMMU_REG_POLL_COUNT_FAST == i) {
378 pr_err("%s,Reset request failed, MMU status is 0x%08X\n", __func__,__raw_readl(base + SYSMMU_REGISTER_DTE_ADDR));
384 static void __sysmmu_set_ptbase(void __iomem *base,unsigned long pgd)
386 __raw_writel(pgd, base + SYSMMU_REGISTER_DTE_ADDR);
390 static bool sysmmu_reset(void __iomem *base,const char *dbgname)
394 err = sysmmu_enable_stall(base);
397 pr_err("%s:stall failed: %s\n",__func__,dbgname);
400 err = sysmmu_raw_reset(base);
403 __raw_writel(SYSMMU_INTERRUPT_PAGE_FAULT|SYSMMU_INTERRUPT_READ_BUS_ERROR, base+SYSMMU_REGISTER_INT_MASK);
405 sysmmu_disable_stall(base);
407 pr_err("%s: failed: %s\n", __func__,dbgname);
411 static inline void pgtable_flush(void *vastart, void *vaend)
413 dmac_flush_range(vastart, vaend);
414 outer_flush_range(virt_to_phys(vastart),virt_to_phys(vaend));
416 static void __set_fault_handler(struct sysmmu_drvdata *data,
417 sysmmu_fault_handler_t handler)
421 write_lock_irqsave(&data->lock, flags);
422 data->fault_handler = handler;
423 write_unlock_irqrestore(&data->lock, flags);
426 void rockchip_sysmmu_set_fault_handler(struct device *dev,sysmmu_fault_handler_t handler)
428 struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
430 __set_fault_handler(data, handler);
433 static int default_fault_handler(struct device *dev,
434 enum rk_sysmmu_inttype itype,
435 unsigned long pgtable_base,
436 unsigned long fault_addr,
440 struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
444 pr_err("%s,iommu device not assigned yet\n",__func__);
447 if ((itype >= SYSMMU_FAULTS_NUM) || (itype < SYSMMU_PAGEFAULT))
448 itype = SYSMMU_FAULT_UNKNOWN;
450 if(itype == SYSMMU_BUSERROR)
451 pr_err("%s occured at 0x%lx(Page table base: 0x%lx)\n",sysmmu_fault_name[itype], fault_addr, pgtable_base);
453 if(itype == SYSMMU_PAGEFAULT)
454 pr_err("SYSMMU:Page fault detected at 0x%lx from bus id %d of type %s on %s\n",
456 (status >> 6) & 0x1F,
457 (status & 32) ? "write" : "read",
461 pr_err("Generating Kernel OOPS... because it is unrecoverable.\n");
467 static void dump_pagetbl(u32 fault_address,u32 addr_dte)
474 u32 *lv1_entry_value;
479 u32 *lv2_entry_value;
482 lv1_offset = lv1ent_offset(fault_address);
483 lv2_offset = lv2ent_offset(fault_address);
485 lv1_entry_pa = (u32 *)addr_dte + lv1_offset;
486 lv1_entry_va = (u32 *)(__va(addr_dte)) + lv1_offset;
487 lv1_entry_value = (u32 *)(*lv1_entry_va);
489 lv2_base = (u32 *)((*lv1_entry_va) & 0xfffffffe);
490 lv2_entry_pa = (u32 * )lv2_base + lv2_offset;
491 lv2_entry_va = (u32 * )(__va(lv2_base)) + lv2_offset;
492 lv2_entry_value = (u32 *)(*lv2_entry_va);
494 pr_info("fault address = 0x%08x,dte addr pa = 0x%08x,va = 0x%08x\n",fault_address,addr_dte,(u32)__va(addr_dte));
495 pr_info("lv1_offset = 0x%x,lv1_entry_pa = 0x%08x,lv1_entry_va = 0x%08x\n",lv1_offset,(u32)lv1_entry_pa,(u32)lv1_entry_va);
496 pr_info("lv1_entry_value(*lv1_entry_va) = 0x%08x,lv2_base = 0x%08x\n",(u32)lv1_entry_value,(u32)lv2_base);
497 pr_info("lv2_offset = 0x%x,lv2_entry_pa = 0x%08x,lv2_entry_va = 0x%08x\n",lv2_offset,(u32)lv2_entry_pa,(u32)lv2_entry_va);
498 pr_info("lv2_entry value(*lv2_entry_va) = 0x%08x\n",(u32)lv2_entry_value);
500 static irqreturn_t rockchip_sysmmu_irq(int irq, void *dev_id)
502 /* SYSMMU is in blocked when interrupt occurred. */
503 struct sysmmu_drvdata *data = dev_id;
504 struct resource *irqres;
505 struct platform_device *pdev;
506 enum rk_sysmmu_inttype itype = SYSMMU_FAULT_UNKNOWN;
513 read_lock(&data->lock);
516 WARN_ON(!is_sysmmu_active(data));
518 if(!is_sysmmu_active(data))
520 read_unlock(&data->lock);
524 rockchip_vcodec_select(data->dbgname);
526 pdev = to_platform_device(data->sysmmu);
528 for (i = 0; i < data->num_res_irq; i++)
530 irqres = platform_get_resource(pdev, IORESOURCE_IRQ, i);
531 if (irqres && ((int)irqres->start == irq))
535 if (i == data->num_res_irq)
537 itype = SYSMMU_FAULT_UNKNOWN;
541 int_status = __raw_readl(data->res_bases[i] + SYSMMU_REGISTER_INT_STATUS);
546 __raw_writel(0x00,data->res_bases[i] + SYSMMU_REGISTER_INT_MASK);
548 rawstat = __raw_readl(data->res_bases[i] + SYSMMU_REGISTER_INT_RAWSTAT);
550 if(rawstat & SYSMMU_INTERRUPT_PAGE_FAULT)
552 fault_address = __raw_readl(data->res_bases[i] + SYSMMU_REGISTER_PAGE_FAULT_ADDR);
553 itype = SYSMMU_PAGEFAULT;
555 else if(rawstat & SYSMMU_INTERRUPT_READ_BUS_ERROR)
557 itype = SYSMMU_BUSERROR;
563 dump_pagetbl(fault_address,__raw_readl(data->res_bases[i] + SYSMMU_REGISTER_DTE_ADDR));
569 if (data->fault_handler)
571 unsigned long base = __raw_readl(data->res_bases[i] + SYSMMU_REGISTER_DTE_ADDR);
572 status = __raw_readl(data->res_bases[i] + SYSMMU_REGISTER_STATUS);
573 ret = data->fault_handler(data->dev, itype, base, fault_address,status);
576 if (!ret && (itype != SYSMMU_FAULT_UNKNOWN))
578 if(SYSMMU_PAGEFAULT == itype)
580 sysmmu_zap_tlb(data->res_bases[i]);
581 sysmmu_page_fault_done(data->res_bases[i],data->dbgname);
582 __raw_writel(SYSMMU_INTERRUPT_PAGE_FAULT|SYSMMU_INTERRUPT_READ_BUS_ERROR, data->res_bases[i]+SYSMMU_REGISTER_INT_MASK);
586 pr_err("(%s) %s is not handled.\n",data->dbgname, sysmmu_fault_name[itype]);
589 read_unlock(&data->lock);
594 static bool __rockchip_sysmmu_disable(struct sysmmu_drvdata *data)
597 bool disabled = false;
599 write_lock_irqsave(&data->lock, flags);
601 if (!set_sysmmu_inactive(data))
604 for(i=0;i<data->num_res_mem;i++)
606 sysmmu_disable_paging(data->res_bases[i]);
613 write_unlock_irqrestore(&data->lock, flags);
616 pr_info("(%s) Disabled\n", data->dbgname);
618 pr_info("(%s) %d times left to be disabled\n",data->dbgname, data->activations);
623 /* __rk_sysmmu_enable: Enables System MMU
625 * returns -error if an error occurred and System MMU is not enabled,
626 * 0 if the System MMU has been just enabled and 1 if System MMU was already
629 static int __rockchip_sysmmu_enable(struct sysmmu_drvdata *data,unsigned long pgtable, struct iommu_domain *domain)
634 write_lock_irqsave(&data->lock, flags);
636 if (!set_sysmmu_active(data))
638 if (WARN_ON(pgtable != data->pgtable))
641 set_sysmmu_inactive(data);
646 pr_info("(%s) Already enabled\n", data->dbgname);
650 data->pgtable = pgtable;
652 for (i = 0; i < data->num_res_mem; i++)
655 status = sysmmu_enable_stall(data->res_bases[i]);
658 __sysmmu_set_ptbase(data->res_bases[i], pgtable);
659 __raw_writel(SYSMMU_COMMAND_ZAP_CACHE, data->res_bases[i] + SYSMMU_REGISTER_COMMAND);
661 __raw_writel(SYSMMU_INTERRUPT_PAGE_FAULT|SYSMMU_INTERRUPT_READ_BUS_ERROR, data->res_bases[i]+SYSMMU_REGISTER_INT_MASK);
662 sysmmu_enable_paging(data->res_bases[i]);
663 sysmmu_disable_stall(data->res_bases[i]);
666 data->domain = domain;
668 pr_info("(%s) Enabled\n", data->dbgname);
670 write_unlock_irqrestore(&data->lock, flags);
674 bool rockchip_sysmmu_disable(struct device *dev)
676 struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
679 disabled = __rockchip_sysmmu_disable(data);
683 void rockchip_sysmmu_tlb_invalidate(struct device *dev)
686 struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
688 read_lock_irqsave(&data->lock, flags);
690 rockchip_vcodec_select(data->dbgname);
692 if (is_sysmmu_active(data))
695 for (i = 0; i < data->num_res_mem; i++)
697 if(!sysmmu_zap_tlb(data->res_bases[i]))
698 pr_err("%s,invalidating TLB failed\n",data->dbgname);
702 pr_info("(%s) Disabled. Skipping invalidating TLB.\n",data->dbgname);
704 read_unlock_irqrestore(&data->lock, flags);
706 static phys_addr_t rockchip_iommu_iova_to_phys(struct iommu_domain *domain,dma_addr_t iova)
708 struct rk_iommu_domain *priv = domain->priv;
709 unsigned long *entry;
711 phys_addr_t phys = 0;
713 spin_lock_irqsave(&priv->pgtablelock, flags);
715 entry = section_entry(priv->pgtable, iova);
716 entry = page_entry(entry, iova);
717 phys = spage_phys(entry) + spage_offs(iova);
719 spin_unlock_irqrestore(&priv->pgtablelock, flags);
723 static int lv2set_page(unsigned long *pent, phys_addr_t paddr, size_t size,
726 if (!lv2ent_fault(pent))
729 *pent = mk_lv2ent_spage(paddr);
730 pgtable_flush(pent, pent + 1);
735 static unsigned long *alloc_lv2entry(unsigned long *sent, unsigned long iova,short *pgcounter)
737 if (lv1ent_fault(sent))
741 pent = kmem_cache_zalloc(lv2table_kmem_cache, GFP_ATOMIC);
742 BUG_ON((unsigned long)pent & (LV2TABLE_SIZE - 1));
746 *sent = mk_lv1ent_page(__pa(pent));
747 kmemleak_ignore(pent);
748 *pgcounter = NUM_LV2ENTRIES;
749 pgtable_flush(pent, pent + NUM_LV2ENTRIES);
750 pgtable_flush(sent, sent + 1);
752 return page_entry(sent, iova);
755 static size_t rockchip_iommu_unmap(struct iommu_domain *domain,unsigned long iova, size_t size)
757 struct rk_iommu_domain *priv = domain->priv;
761 BUG_ON(priv->pgtable == NULL);
763 spin_lock_irqsave(&priv->pgtablelock, flags);
765 ent = section_entry(priv->pgtable, iova);
767 if (unlikely(lv1ent_fault(ent)))
769 if (size > SPAGE_SIZE)
774 /* lv1ent_page(sent) == true here */
776 ent = page_entry(ent, iova);
778 if (unlikely(lv2ent_fault(ent)))
786 priv->lv2entcnt[lv1ent_offset(iova)] += 1;
790 //pr_info("%s:unmap iova 0x%lx/0x%x bytes\n",__func__, iova,size);
791 spin_unlock_irqrestore(&priv->pgtablelock, flags);
795 static int rockchip_iommu_map(struct iommu_domain *domain, unsigned long iova,
796 phys_addr_t paddr, size_t size, int prot)
798 struct rk_iommu_domain *priv = domain->priv;
799 unsigned long *entry;
804 BUG_ON(priv->pgtable == NULL);
806 spin_lock_irqsave(&priv->pgtablelock, flags);
808 entry = section_entry(priv->pgtable, iova);
810 pent = alloc_lv2entry(entry, iova,&priv->lv2entcnt[lv1ent_offset(iova)]);
814 ret = lv2set_page(pent, paddr, size,&priv->lv2entcnt[lv1ent_offset(iova)]);
818 pr_err("%s: Failed to map iova 0x%lx/0x%x bytes\n",__func__, iova, size);
820 spin_unlock_irqrestore(&priv->pgtablelock, flags);
825 static void rockchip_iommu_detach_device(struct iommu_domain *domain,
828 struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
829 struct rk_iommu_domain *priv = domain->priv;
830 struct list_head *pos;
834 spin_lock_irqsave(&priv->lock, flags);
836 list_for_each(pos, &priv->clients)
838 if (list_entry(pos, struct sysmmu_drvdata, node) == data)
847 rockchip_vcodec_select(data->dbgname);
849 if (__rockchip_sysmmu_disable(data))
851 pr_info("%s: Detached IOMMU with pgtable %#lx\n",__func__, __pa(priv->pgtable));
852 list_del(&data->node);
853 INIT_LIST_HEAD(&data->node);
857 pr_info("%s: Detaching IOMMU with pgtable %#lx delayed",__func__, __pa(priv->pgtable));
860 spin_unlock_irqrestore(&priv->lock, flags);
862 static int rockchip_iommu_attach_device(struct iommu_domain *domain,struct device *dev)
864 struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
865 struct rk_iommu_domain *priv = domain->priv;
869 spin_lock_irqsave(&priv->lock, flags);
871 rockchip_vcodec_select(data->dbgname);
873 ret = __rockchip_sysmmu_enable(data, __pa(priv->pgtable), domain);
877 /* 'data->node' must not be appeared in priv->clients */
878 BUG_ON(!list_empty(&data->node));
880 list_add_tail(&data->node, &priv->clients);
883 spin_unlock_irqrestore(&priv->lock, flags);
887 pr_err("%s: Failed to attach IOMMU with pgtable %#lx\n",__func__, __pa(priv->pgtable));
891 pr_info("%s: IOMMU with pgtable 0x%lx already attached\n",__func__, __pa(priv->pgtable));
895 pr_info("%s: Attached new IOMMU with pgtable 0x%lx\n",__func__, __pa(priv->pgtable));
900 static void rockchip_iommu_domain_destroy(struct iommu_domain *domain)
902 struct rk_iommu_domain *priv = domain->priv;
903 struct sysmmu_drvdata *data;
907 WARN_ON(!list_empty(&priv->clients));
909 spin_lock_irqsave(&priv->lock, flags);
911 list_for_each_entry(data, &priv->clients, node)
913 rockchip_vcodec_select(data->dbgname);
914 while (!rockchip_sysmmu_disable(data->dev))
915 ; /* until System MMU is actually disabled */
917 spin_unlock_irqrestore(&priv->lock, flags);
919 for (i = 0; i < NUM_LV1ENTRIES; i++)
920 if (lv1ent_page(priv->pgtable + i))
921 kmem_cache_free(lv2table_kmem_cache,__va(lv2table_base(priv->pgtable + i)));
923 free_pages((unsigned long)priv->pgtable, 0);
924 free_pages((unsigned long)priv->lv2entcnt, 0);
929 static int rockchip_iommu_domain_init(struct iommu_domain *domain)
931 struct rk_iommu_domain *priv;
933 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
937 /*rk32xx sysmmu use 2 level pagetable,
938 level1 and leve2 both have 1024 entries,each entry occupy 4 bytes,
939 so alloc a page size for each page table
941 priv->pgtable = (unsigned long *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, 0);
945 priv->lv2entcnt = (short *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, 0);
946 if (!priv->lv2entcnt)
949 pgtable_flush(priv->pgtable, priv->pgtable + NUM_LV1ENTRIES);
951 spin_lock_init(&priv->lock);
952 spin_lock_init(&priv->pgtablelock);
953 INIT_LIST_HEAD(&priv->clients);
959 free_pages((unsigned long)priv->pgtable, 0);
965 static struct iommu_ops rk_iommu_ops =
967 .domain_init = &rockchip_iommu_domain_init,
968 .domain_destroy = &rockchip_iommu_domain_destroy,
969 .attach_dev = &rockchip_iommu_attach_device,
970 .detach_dev = &rockchip_iommu_detach_device,
971 .map = &rockchip_iommu_map,
972 .unmap = &rockchip_iommu_unmap,
973 .iova_to_phys = &rockchip_iommu_iova_to_phys,
974 .pgsize_bitmap = SPAGE_SIZE,
977 static int rockchip_sysmmu_prepare(void)
980 static int registed = 0;
985 lv2table_kmem_cache = kmem_cache_create("rk-iommu-lv2table",LV2TABLE_SIZE, LV2TABLE_SIZE, 0, NULL);
986 if (!lv2table_kmem_cache)
988 pr_err("%s: failed to create kmem cache\n", __func__);
991 ret = bus_set_iommu(&platform_bus_type, &rk_iommu_ops);
995 pr_err("%s:failed to set iommu to bus\r\n",__func__);
998 static int rockchip_get_sysmmu_resource_num(struct platform_device *pdev,unsigned int type)
1000 struct resource *info = NULL;
1001 int num_resources = 0;
1003 /*get resouce info*/
1005 info = platform_get_resource(pdev, type, num_resources);
1011 return num_resources;
1014 static struct kobject *dump_mmu_object;
1016 static int dump_mmu_pagetbl(struct device *dev,struct device_attribute *attr, const char *buf,u32 count)
1023 ret = kstrtouint(buf,0,&mmu_base);
1025 printk("%s is not in hexdecimal form.\n", buf);
1026 base = ioremap(mmu_base, 0x100);
1027 iommu_dte = __raw_readl(base + SYSMMU_REGISTER_DTE_ADDR);
1028 fault_address = __raw_readl(base + SYSMMU_REGISTER_PAGE_FAULT_ADDR);
1029 dump_pagetbl(fault_address,iommu_dte);
1032 static DEVICE_ATTR(dump_mmu_pgtable, 0644, NULL, dump_mmu_pagetbl);
1034 void dump_iommu_sysfs_init(void )
1037 dump_mmu_object = kobject_create_and_add("rk_iommu", NULL);
1038 if (dump_mmu_object == NULL)
1040 ret = sysfs_create_file(dump_mmu_object, &dev_attr_dump_mmu_pgtable.attr);
1046 static int rockchip_sysmmu_probe(struct platform_device *pdev)
1050 struct sysmmu_drvdata *data;
1054 ret = rockchip_sysmmu_prepare();
1057 pr_err("%s,failed\r\n",__func__);
1061 data = devm_kzalloc(dev,sizeof(*data), GFP_KERNEL);
1064 dev_dbg(dev, "Not enough memory\n");
1069 ret = dev_set_drvdata(dev, data);
1072 dev_dbg(dev, "Unabled to initialize driver data\n");
1076 if(pdev->dev.of_node)
1078 of_property_read_string(pdev->dev.of_node,"dbgname",&(data->dbgname));
1082 pr_info("dbgname not assigned in device tree or device node not exist\r\n");
1085 pr_info("(%s) Enter\n", data->dbgname);
1087 /*rk32xx sysmmu need both irq and memory */
1088 data->num_res_mem = rockchip_get_sysmmu_resource_num(pdev,IORESOURCE_MEM);
1089 if(0 == data->num_res_mem)
1091 pr_err("can't find sysmmu memory resource \r\n");
1094 pr_info("data->num_res_mem=%d\n",data->num_res_mem);
1095 data->num_res_irq = rockchip_get_sysmmu_resource_num(pdev,IORESOURCE_IRQ);
1096 if(0 == data->num_res_irq)
1098 pr_err("can't find sysmmu irq resource \r\n");
1102 data->res_bases = kmalloc(sizeof(*data->res_bases) * data->num_res_mem,GFP_KERNEL);
1103 if (data->res_bases == NULL)
1105 dev_dbg(dev, "Not enough memory\n");
1110 for (i = 0; i < data->num_res_mem; i++)
1112 struct resource *res;
1113 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
1116 pr_err("Unable to find IOMEM region\n");
1120 data->res_bases[i] = ioremap(res->start, resource_size(res));
1121 pr_info("res->start = 0x%08x ioremap to data->res_bases[%d] = 0x%08x\n",res->start,i,(unsigned int)data->res_bases[i]);
1122 if (!data->res_bases[i])
1124 pr_err("Unable to map IOMEM @ PA:%#x\n",res->start);
1129 rockchip_vcodec_select(data->dbgname);
1131 if(!strstr(data->dbgname,"isp"))
1134 if(!sysmmu_reset(data->res_bases[i],data->dbgname))
1142 for (i = 0; i < data->num_res_irq; i++)
1144 ret = platform_get_irq(pdev, i);
1147 pr_err("Unable to find IRQ resource\n");
1150 ret = request_irq(ret, rockchip_sysmmu_irq, IRQF_SHARED ,dev_name(dev), data);
1153 pr_err("Unabled to register interrupt handler\n");
1157 ret = rockchip_init_iovmm(dev, &data->vmm);
1163 rwlock_init(&data->lock);
1164 INIT_LIST_HEAD(&data->node);
1166 __set_fault_handler(data, &default_fault_handler);
1168 pr_info("(%s) Initialized\n", data->dbgname);
1176 irq = platform_get_irq(pdev, i);
1177 free_irq(irq, data);
1180 while (data->num_res_mem-- > 0)
1181 iounmap(data->res_bases[data->num_res_mem]);
1182 kfree(data->res_bases);
1186 dev_err(dev, "Failed to initialize\n");
1191 static const struct of_device_id sysmmu_dt_ids[] =
1193 { .compatible = IEP_SYSMMU_COMPATIBLE_NAME},
1194 { .compatible = VIP_SYSMMU_COMPATIBLE_NAME},
1195 { .compatible = VOPB_SYSMMU_COMPATIBLE_NAME},
1196 { .compatible = VOPL_SYSMMU_COMPATIBLE_NAME},
1197 { .compatible = HEVC_SYSMMU_COMPATIBLE_NAME},
1198 { .compatible = VPU_SYSMMU_COMPATIBLE_NAME},
1199 { .compatible = ISP_SYSMMU_COMPATIBLE_NAME},
1200 { .compatible = VOP_SYSMMU_COMPATIBLE_NAME},
1203 MODULE_DEVICE_TABLE(of, sysmmu_dt_ids);
1206 static struct platform_driver rk_sysmmu_driver =
1208 .probe = rockchip_sysmmu_probe,
1212 .name = "rk_sysmmu",
1213 .owner = THIS_MODULE,
1214 .of_match_table = of_match_ptr(sysmmu_dt_ids),
1218 static int __init rockchip_sysmmu_init_driver(void)
1220 dump_iommu_sysfs_init();
1222 return platform_driver_register(&rk_sysmmu_driver);
1225 core_initcall(rockchip_sysmmu_init_driver);