2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License version 2 as
4 * published by the Free Software Foundation.
7 #ifdef CONFIG_ROCKCHIP_IOMMU_DEBUG
12 #include <linux/interrupt.h>
13 #include <linux/slab.h>
14 #include <linux/clk.h>
15 #include <linux/err.h>
17 #include <linux/errno.h>
18 #include <linux/memblock.h>
19 #include <linux/export.h>
20 #include <linux/module.h>
22 #include <asm/cacheflush.h>
23 #include <asm/pgtable.h>
25 #include <linux/rockchip-iovmm.h>
26 #include <linux/rockchip/grf.h>
27 #include <linux/rockchip/cpu.h>
28 #include <linux/rockchip/iomap.h>
29 #include <linux/device.h>
30 #include "rockchip-iommu.h"
32 /* We does not consider super section mapping (16MB) */
33 #define SPAGE_ORDER 12
34 #define SPAGE_SIZE (1 << SPAGE_ORDER)
35 #define SPAGE_MASK (~(SPAGE_SIZE - 1))
37 static void __iomem *rk312x_vop_mmu_base;
39 enum iommu_entry_flags {
40 IOMMU_FLAGS_PRESENT = 0x01,
41 IOMMU_FLAGS_READ_PERMISSION = 0x02,
42 IOMMU_FLAGS_WRITE_PERMISSION = 0x04,
43 IOMMU_FLAGS_OVERRIDE_CACHE = 0x8,
44 IOMMU_FLAGS_WRITE_CACHEABLE = 0x10,
45 IOMMU_FLAGS_WRITE_ALLOCATE = 0x20,
46 IOMMU_FLAGS_WRITE_BUFFERABLE = 0x40,
47 IOMMU_FLAGS_READ_CACHEABLE = 0x80,
48 IOMMU_FLAGS_READ_ALLOCATE = 0x100,
49 IOMMU_FLAGS_MASK = 0x1FF,
52 #define lv1ent_fault(sent) ((*(sent) & IOMMU_FLAGS_PRESENT) == 0)
53 #define lv1ent_page(sent) ((*(sent) & IOMMU_FLAGS_PRESENT) == 1)
54 #define lv2ent_fault(pent) ((*(pent) & IOMMU_FLAGS_PRESENT) == 0)
55 #define spage_phys(pent) (*(pent) & SPAGE_MASK)
56 #define spage_offs(iova) ((iova) & 0x0FFF)
58 #define lv1ent_offset(iova) (((iova)>>22) & 0x03FF)
59 #define lv2ent_offset(iova) (((iova)>>12) & 0x03FF)
61 #define NUM_LV1ENTRIES 1024
62 #define NUM_LV2ENTRIES 1024
64 #define LV2TABLE_SIZE (NUM_LV2ENTRIES * sizeof(long))
66 #define lv2table_base(sent) (*(sent) & 0xFFFFFFFE)
68 #define mk_lv1ent_page(pa) ((pa) | IOMMU_FLAGS_PRESENT)
69 /*write and read permission for level2 page default*/
70 #define mk_lv2ent_spage(pa) ((pa) | IOMMU_FLAGS_PRESENT | \
71 IOMMU_FLAGS_READ_PERMISSION | \
72 IOMMU_FLAGS_WRITE_PERMISSION)
74 #define IOMMU_REG_POLL_COUNT_FAST 1000
76 /*rk3036:vpu and hevc share ahb interface*/
77 #define BIT_VCODEC_SEL_3036 (1<<3)
78 #define BIT_VCODEC_SEL_312x (1<<15)
82 * MMU register numbers
83 * Used in the register read/write routines.
84 * See the hardware documentation for more information about each register
87 /**< Current Page Directory Pointer */
88 IOMMU_REGISTER_DTE_ADDR = 0x0000,
89 /**< Status of the MMU */
90 IOMMU_REGISTER_STATUS = 0x0004,
91 /**< Command register, used to control the MMU */
92 IOMMU_REGISTER_COMMAND = 0x0008,
93 /**< Logical address of the last page fault */
94 IOMMU_REGISTER_PAGE_FAULT_ADDR = 0x000C,
95 /**< Used to invalidate the mapping of a single page from the MMU */
96 IOMMU_REGISTER_ZAP_ONE_LINE = 0x010,
97 /**< Raw interrupt status, all interrupts visible */
98 IOMMU_REGISTER_INT_RAWSTAT = 0x0014,
99 /**< Indicate to the MMU that the interrupt has been received */
100 IOMMU_REGISTER_INT_CLEAR = 0x0018,
101 /**< Enable/disable types of interrupts */
102 IOMMU_REGISTER_INT_MASK = 0x001C,
103 /**< Interrupt status based on the mask */
104 IOMMU_REGISTER_INT_STATUS = 0x0020,
105 IOMMU_REGISTER_AUTO_GATING = 0x0024
109 /**< Enable paging (memory translation) */
110 IOMMU_COMMAND_ENABLE_PAGING = 0x00,
111 /**< Disable paging (memory translation) */
112 IOMMU_COMMAND_DISABLE_PAGING = 0x01,
113 /**< Enable stall on page fault */
114 IOMMU_COMMAND_ENABLE_STALL = 0x02,
115 /**< Disable stall on page fault */
116 IOMMU_COMMAND_DISABLE_STALL = 0x03,
117 /**< Zap the entire page table cache */
118 IOMMU_COMMAND_ZAP_CACHE = 0x04,
119 /**< Page fault processed */
120 IOMMU_COMMAND_PAGE_FAULT_DONE = 0x05,
121 /**< Reset the MMU back to power-on settings */
122 IOMMU_COMMAND_HARD_RESET = 0x06
126 * MMU interrupt register bits
127 * Each cause of the interrupt is reported
128 * through the (raw) interrupt status registers.
129 * Multiple interrupts can be pending, so multiple bits
130 * can be set at once.
132 enum iommu_interrupt {
133 IOMMU_INTERRUPT_PAGE_FAULT = 0x01, /**< A page fault occured */
134 IOMMU_INTERRUPT_READ_BUS_ERROR = 0x02 /**< A bus read error occured */
137 enum iommu_status_bits {
138 IOMMU_STATUS_BIT_PAGING_ENABLED = 1 << 0,
139 IOMMU_STATUS_BIT_PAGE_FAULT_ACTIVE = 1 << 1,
140 IOMMU_STATUS_BIT_STALL_ACTIVE = 1 << 2,
141 IOMMU_STATUS_BIT_IDLE = 1 << 3,
142 IOMMU_STATUS_BIT_REPLAY_BUFFER_EMPTY = 1 << 4,
143 IOMMU_STATUS_BIT_PAGE_FAULT_IS_WRITE = 1 << 5,
144 IOMMU_STATUS_BIT_STALL_NOT_ACTIVE = 1 << 31,
148 * Size of an MMU page in bytes
150 #define IOMMU_PAGE_SIZE 0x1000
153 * Size of the address space referenced by a page table page
155 #define IOMMU_VIRTUAL_PAGE_SIZE 0x400000 /* 4 MiB */
158 * Page directory index from address
159 * Calculates the page directory index from the given address
161 #define IOMMU_PDE_ENTRY(address) (((address)>>22) & 0x03FF)
164 * Page table index from address
165 * Calculates the page table index from the given address
167 #define IOMMU_PTE_ENTRY(address) (((address)>>12) & 0x03FF)
170 * Extract the memory address from an PDE/PTE entry
172 #define IOMMU_ENTRY_ADDRESS(value) ((value) & 0xFFFFFC00)
174 #define INVALID_PAGE ((u32)(~0))
176 static struct kmem_cache *lv2table_kmem_cache;
178 static void rockchip_vcodec_select(const char *string)
180 if (strstr(string,"hevc")) {
181 if (cpu_is_rk3036()) {
182 writel_relaxed(readl_relaxed(RK_GRF_VIRT + RK3036_GRF_SOC_CON1) |
183 (BIT_VCODEC_SEL_3036) | (BIT_VCODEC_SEL_3036 << 16),
184 RK_GRF_VIRT + RK3036_GRF_SOC_CON1);
186 writel_relaxed(readl_relaxed(RK_GRF_VIRT + RK312X_GRF_SOC_CON1) |
187 (BIT_VCODEC_SEL_312x) | (BIT_VCODEC_SEL_312x << 16),
188 RK_GRF_VIRT + RK312X_GRF_SOC_CON1);
190 } else if (strstr(string,"vpu")) {
191 if (cpu_is_rk3036()) {
192 writel_relaxed((readl_relaxed(RK_GRF_VIRT + RK3036_GRF_SOC_CON1) &
193 (~BIT_VCODEC_SEL_3036)) | (BIT_VCODEC_SEL_3036 << 16),
194 RK_GRF_VIRT + RK3036_GRF_SOC_CON1);
196 writel_relaxed((readl_relaxed(RK_GRF_VIRT + RK312X_GRF_SOC_CON1) &
197 (~BIT_VCODEC_SEL_312x)) | (BIT_VCODEC_SEL_312x << 16),
198 RK_GRF_VIRT + RK312X_GRF_SOC_CON1);
202 static unsigned long *section_entry(unsigned long *pgtable, unsigned long iova)
204 return pgtable + lv1ent_offset(iova);
207 static unsigned long *page_entry(unsigned long *sent, unsigned long iova)
209 return (unsigned long *)__va(lv2table_base(sent)) + lv2ent_offset(iova);
212 static char *iommu_fault_name[IOMMU_FAULTS_NUM] = {
218 struct rk_iommu_domain {
219 struct list_head clients; /* list of iommu_drvdata.node */
220 unsigned long *pgtable; /* lv1 page table, 4KB */
221 short *lv2entcnt; /* free lv2 entry counter for each section */
222 spinlock_t lock; /* lock for this structure */
223 spinlock_t pgtablelock; /* lock for modifying page table @ pgtable */
226 static bool set_iommu_active(struct iommu_drvdata *data)
228 /* return true if the IOMMU was not active previously
229 and it needs to be initialized */
230 return ++data->activations == 1;
233 static bool set_iommu_inactive(struct iommu_drvdata *data)
235 /* return true if the IOMMU is needed to be disabled */
236 BUG_ON(data->activations < 1);
237 return --data->activations == 0;
240 static bool is_iommu_active(struct iommu_drvdata *data)
242 return data->activations > 0;
245 static void iommu_disable_stall(void __iomem *base)
250 if (base != rk312x_vop_mmu_base) {
251 mmu_status = __raw_readl(base + IOMMU_REGISTER_STATUS);
253 goto skip_vop_mmu_disable;
255 if (0 == (mmu_status & IOMMU_STATUS_BIT_PAGING_ENABLED))
257 if (mmu_status & IOMMU_STATUS_BIT_PAGE_FAULT_ACTIVE) {
258 pr_info("Aborting MMU disable stall request since it is in pagefault state.\n");
261 skip_vop_mmu_disable:
262 __raw_writel(IOMMU_COMMAND_DISABLE_STALL,
263 base + IOMMU_REGISTER_COMMAND);
265 for (i = 0; i < IOMMU_REG_POLL_COUNT_FAST; ++i) {
268 if (base != rk312x_vop_mmu_base) {
269 status = __raw_readl(base + IOMMU_REGISTER_STATUS);
276 if (0 == (status & IOMMU_STATUS_BIT_STALL_ACTIVE))
278 if (status & IOMMU_STATUS_BIT_PAGE_FAULT_ACTIVE)
280 if (0 == (mmu_status & IOMMU_STATUS_BIT_PAGING_ENABLED))
283 if (IOMMU_REG_POLL_COUNT_FAST == i) {
284 pr_info("Disable stall request failed, MMU status is 0x%08X\n",
285 __raw_readl(base + IOMMU_REGISTER_STATUS));
289 static bool iommu_enable_stall(void __iomem *base)
295 if (base != rk312x_vop_mmu_base) {
296 mmu_status = __raw_readl(base + IOMMU_REGISTER_STATUS);
298 goto skip_vop_mmu_enable;
300 if (0 == (mmu_status & IOMMU_STATUS_BIT_PAGING_ENABLED))
302 if (mmu_status & IOMMU_STATUS_BIT_PAGE_FAULT_ACTIVE) {
303 pr_info("Aborting MMU stall request since it is in pagefault state.\n");
307 __raw_writel(IOMMU_COMMAND_ENABLE_STALL,
308 base + IOMMU_REGISTER_COMMAND);
310 for (i = 0; i < IOMMU_REG_POLL_COUNT_FAST; ++i) {
311 if (base != rk312x_vop_mmu_base) {
312 mmu_status = __raw_readl(base + IOMMU_REGISTER_STATUS);
319 if (mmu_status & IOMMU_STATUS_BIT_PAGE_FAULT_ACTIVE)
321 if ((mmu_status & IOMMU_STATUS_BIT_STALL_ACTIVE) &&
322 (0 == (mmu_status & IOMMU_STATUS_BIT_STALL_NOT_ACTIVE)))
324 if (0 == (mmu_status & (IOMMU_STATUS_BIT_PAGING_ENABLED)))
327 if (IOMMU_REG_POLL_COUNT_FAST == i) {
328 pr_info("Enable stall request failed, MMU status is 0x%08X\n",
329 __raw_readl(base + IOMMU_REGISTER_STATUS));
332 if (mmu_status & IOMMU_STATUS_BIT_PAGE_FAULT_ACTIVE) {
333 pr_info("Aborting MMU stall request since it has a pagefault.\n");
339 static bool iommu_enable_paging(void __iomem *base)
343 __raw_writel(IOMMU_COMMAND_ENABLE_PAGING,
344 base + IOMMU_REGISTER_COMMAND);
346 for (i = 0; i < IOMMU_REG_POLL_COUNT_FAST; ++i) {
347 if (base != rk312x_vop_mmu_base) {
348 if (__raw_readl(base + IOMMU_REGISTER_STATUS) &
349 IOMMU_STATUS_BIT_PAGING_ENABLED)
358 if (IOMMU_REG_POLL_COUNT_FAST == i) {
359 pr_info("Enable paging request failed, MMU status is 0x%08X\n",
360 __raw_readl(base + IOMMU_REGISTER_STATUS));
366 static bool iommu_disable_paging(void __iomem *base)
370 __raw_writel(IOMMU_COMMAND_DISABLE_PAGING,
371 base + IOMMU_REGISTER_COMMAND);
373 for (i = 0; i < IOMMU_REG_POLL_COUNT_FAST; ++i) {
374 if (base != rk312x_vop_mmu_base) {
375 if (!(__raw_readl(base + IOMMU_REGISTER_STATUS) &
376 IOMMU_STATUS_BIT_PAGING_ENABLED))
385 if (IOMMU_REG_POLL_COUNT_FAST == i) {
386 pr_info("Disable paging request failed, MMU status is 0x%08X\n",
387 __raw_readl(base + IOMMU_REGISTER_STATUS));
393 static void iommu_page_fault_done(void __iomem *base, const char *dbgname)
395 pr_info("MMU: %s: Leaving page fault mode\n",
397 __raw_writel(IOMMU_COMMAND_PAGE_FAULT_DONE,
398 base + IOMMU_REGISTER_COMMAND);
401 static bool iommu_zap_tlb(void __iomem *base)
403 bool stall_success = iommu_enable_stall(base);
405 __raw_writel(IOMMU_COMMAND_ZAP_CACHE,
406 base + IOMMU_REGISTER_COMMAND);
409 iommu_disable_stall(base);
412 extern bool __clk_is_enabled(struct clk *clk);
413 static inline bool iommu_raw_reset(void __iomem *base)
418 __raw_writel(0xCAFEBABE, base + IOMMU_REGISTER_DTE_ADDR);
420 if (base != rk312x_vop_mmu_base) {
421 ret = __raw_readl(base + IOMMU_REGISTER_DTE_ADDR);
422 if (!(0xCAFEB000 == ret)) {
423 pr_info("error when %s.\n", __func__);
427 __raw_writel(IOMMU_COMMAND_HARD_RESET,
428 base + IOMMU_REGISTER_COMMAND);
430 for (i = 0; i < IOMMU_REG_POLL_COUNT_FAST; ++i) {
431 if (base != rk312x_vop_mmu_base) {
432 if (__raw_readl(base + IOMMU_REGISTER_DTE_ADDR) == 0)
441 if (IOMMU_REG_POLL_COUNT_FAST == i) {
442 pr_info("%s,Reset request failed, MMU status is 0x%08X\n",
443 __func__, __raw_readl(base + IOMMU_REGISTER_DTE_ADDR));
449 static void __iommu_set_ptbase(void __iomem *base, unsigned long pgd)
451 __raw_writel(pgd, base + IOMMU_REGISTER_DTE_ADDR);
454 static bool iommu_reset(void __iomem *base, const char *dbgname)
458 err = iommu_enable_stall(base);
460 pr_info("%s:stall failed: %s\n", __func__, dbgname);
463 err = iommu_raw_reset(base);
465 __raw_writel(IOMMU_INTERRUPT_PAGE_FAULT |
466 IOMMU_INTERRUPT_READ_BUS_ERROR,
467 base+IOMMU_REGISTER_INT_MASK);
468 iommu_disable_stall(base);
470 pr_info("%s: failed: %s\n", __func__, dbgname);
474 static inline void pgtable_flush(void *vastart, void *vaend)
476 dmac_flush_range(vastart, vaend);
477 outer_flush_range(virt_to_phys(vastart), virt_to_phys(vaend));
480 static void set_fault_handler(struct iommu_drvdata *data,
481 rockchip_iommu_fault_handler_t handler)
485 write_lock_irqsave(&data->lock, flags);
486 data->fault_handler = handler;
487 write_unlock_irqrestore(&data->lock, flags);
490 static int default_fault_handler(struct device *dev,
491 enum rk_iommu_inttype itype,
492 unsigned long pgtable_base,
493 unsigned long fault_addr,
496 struct iommu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
499 dev_err(dev->archdata.iommu,"%s,iommu device not assigned yet\n", __func__);
502 if ((itype >= IOMMU_FAULTS_NUM) || (itype < IOMMU_PAGEFAULT))
503 itype = IOMMU_FAULT_UNKNOWN;
505 if (itype == IOMMU_BUSERROR)
506 dev_err(dev->archdata.iommu,"%s occured at 0x%lx(Page table base: 0x%lx)\n",
507 iommu_fault_name[itype], fault_addr, pgtable_base);
509 if (itype == IOMMU_PAGEFAULT)
510 dev_err(dev->archdata.iommu,"IOMMU:Page fault detected at 0x%lx from bus id %d of type %s on %s\n",
512 (status >> 6) & 0x1F,
513 (status & 32) ? "write" : "read",
516 dev_err(dev->archdata.iommu,"Generating Kernel OOPS... because it is unrecoverable.\n");
523 static void dump_pagetbl(u32 fault_address, u32 addr_dte)
530 u32 *lv1_entry_value;
535 u32 *lv2_entry_value;
538 lv1_offset = lv1ent_offset(fault_address);
539 lv2_offset = lv2ent_offset(fault_address);
541 lv1_entry_pa = (u32 *)addr_dte + lv1_offset;
542 lv1_entry_va = (u32 *)(__va(addr_dte)) + lv1_offset;
543 lv1_entry_value = (u32 *)(*lv1_entry_va);
545 lv2_base = (u32 *)((*lv1_entry_va) & 0xfffffffe);
546 lv2_entry_pa = (u32 *)lv2_base + lv2_offset;
547 lv2_entry_va = (u32 *)(__va(lv2_base)) + lv2_offset;
548 lv2_entry_value = (u32 *)(*lv2_entry_va);
550 dev_info(NULL,"fault address = 0x%08x,dte addr pa = 0x%08x,va = 0x%08x\n",
551 fault_address, addr_dte, (u32)__va(addr_dte));
552 dev_info(NULL,"lv1_offset = 0x%x,lv1_entry_pa = 0x%08x,lv1_entry_va = 0x%08x\n",
553 lv1_offset, (u32)lv1_entry_pa, (u32)lv1_entry_va);
554 dev_info(NULL,"lv1_entry_value(*lv1_entry_va) = 0x%08x,lv2_base = 0x%08x\n",
555 (u32)lv1_entry_value, (u32)lv2_base);
556 dev_info(NULL,"lv2_offset = 0x%x,lv2_entry_pa = 0x%08x,lv2_entry_va = 0x%08x\n",
557 lv2_offset, (u32)lv2_entry_pa, (u32)lv2_entry_va);
558 dev_info(NULL,"lv2_entry value(*lv2_entry_va) = 0x%08x\n",
559 (u32)lv2_entry_value);
562 static irqreturn_t rockchip_iommu_irq(int irq, void *dev_id)
564 /* SYSMMU is in blocked when interrupt occurred. */
565 struct iommu_drvdata *data = dev_id;
566 struct resource *irqres;
567 struct platform_device *pdev;
568 enum rk_iommu_inttype itype = IOMMU_FAULT_UNKNOWN;
575 read_lock(&data->lock);
577 if (!is_iommu_active(data)) {
578 read_unlock(&data->lock);
582 if(cpu_is_rk312x() || cpu_is_rk3036())
583 rockchip_vcodec_select(data->dbgname);
585 pdev = to_platform_device(data->iommu);
587 for (i = 0; i < data->num_res_irq; i++) {
588 irqres = platform_get_resource(pdev, IORESOURCE_IRQ, i);
589 if (irqres && ((int)irqres->start == irq)) {
590 if (data->res_bases[i] == rk312x_vop_mmu_base) {
591 read_unlock(&data->lock);
598 if (i == data->num_res_irq) {
599 itype = IOMMU_FAULT_UNKNOWN;
601 int_status = __raw_readl(data->res_bases[i] +
602 IOMMU_REGISTER_INT_STATUS);
604 if (int_status != 0) {
606 __raw_writel(0x00, data->res_bases[i] +
607 IOMMU_REGISTER_INT_MASK);
609 rawstat = __raw_readl(data->res_bases[i] +
610 IOMMU_REGISTER_INT_RAWSTAT);
612 if (rawstat & IOMMU_INTERRUPT_PAGE_FAULT) {
613 fault_address = __raw_readl(data->res_bases[i] +
614 IOMMU_REGISTER_PAGE_FAULT_ADDR);
615 itype = IOMMU_PAGEFAULT;
616 } else if (rawstat & IOMMU_INTERRUPT_READ_BUS_ERROR) {
617 itype = IOMMU_BUSERROR;
621 dump_pagetbl(fault_address,
622 __raw_readl(data->res_bases[i] +
623 IOMMU_REGISTER_DTE_ADDR));
629 if (data->fault_handler) {
630 unsigned long base = __raw_readl(data->res_bases[i] +
631 IOMMU_REGISTER_DTE_ADDR);
632 status = __raw_readl(data->res_bases[i] +
633 IOMMU_REGISTER_STATUS);
634 ret = data->fault_handler(data->dev, itype, base,
635 fault_address, status);
638 if (!ret && (itype != IOMMU_FAULT_UNKNOWN)) {
639 if (IOMMU_PAGEFAULT == itype) {
640 iommu_zap_tlb(data->res_bases[i]);
641 iommu_page_fault_done(data->res_bases[i],
643 __raw_writel(IOMMU_INTERRUPT_PAGE_FAULT |
644 IOMMU_INTERRUPT_READ_BUS_ERROR,
646 IOMMU_REGISTER_INT_MASK);
649 dev_err(data->iommu,"(%s) %s is not handled.\n",
650 data->dbgname, iommu_fault_name[itype]);
654 read_unlock(&data->lock);
659 static bool __rockchip_iommu_disable(struct iommu_drvdata *data)
663 bool disabled = false;
665 write_lock_irqsave(&data->lock, flags);
667 if (!set_iommu_inactive(data))
670 for (i = 0; i < data->num_res_mem; i++)
671 iommu_disable_paging(data->res_bases[i]);
677 write_unlock_irqrestore(&data->lock, flags);
680 dev_info(data->iommu,"(%s) Disabled\n", data->dbgname);
682 dev_info(data->iommu,"(%s) %d times left to be disabled\n",
683 data->dbgname, data->activations);
688 /* __rk_sysmmu_enable: Enables System MMU
690 * returns -error if an error occurred and System MMU is not enabled,
691 * 0 if the System MMU has been just enabled and 1 if System MMU was already
694 static int __rockchip_iommu_enable(struct iommu_drvdata *data,
695 unsigned long pgtable,
696 struct iommu_domain *domain)
701 write_lock_irqsave(&data->lock, flags);
703 if (!set_iommu_active(data)) {
704 if (WARN_ON(pgtable != data->pgtable)) {
706 set_iommu_inactive(data);
711 dev_info(data->iommu,"(%s) Already enabled\n", data->dbgname);
715 data->pgtable = pgtable;
717 for (i = 0; i < data->num_res_mem; i++) {
720 status = iommu_enable_stall(data->res_bases[i]);
722 __iommu_set_ptbase(data->res_bases[i], pgtable);
723 __raw_writel(IOMMU_COMMAND_ZAP_CACHE,
725 IOMMU_REGISTER_COMMAND);
727 __raw_writel(IOMMU_INTERRUPT_PAGE_FAULT |
728 IOMMU_INTERRUPT_READ_BUS_ERROR,
729 data->res_bases[i]+IOMMU_REGISTER_INT_MASK);
730 iommu_enable_paging(data->res_bases[i]);
731 iommu_disable_stall(data->res_bases[i]);
734 data->domain = domain;
736 dev_info(data->iommu,"(%s) Enabled\n", data->dbgname);
738 write_unlock_irqrestore(&data->lock, flags);
743 bool rockchip_iommu_disable(struct device *dev)
745 struct iommu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
748 disabled = __rockchip_iommu_disable(data);
753 void rockchip_iommu_tlb_invalidate(struct device *dev)
756 struct iommu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
758 read_lock_irqsave(&data->lock, flags);
760 if(cpu_is_rk312x() || cpu_is_rk3036())
761 rockchip_vcodec_select(data->dbgname);
763 if (is_iommu_active(data)) {
766 for (i = 0; i < data->num_res_mem; i++) {
767 if (!iommu_zap_tlb(data->res_bases[i]))
768 dev_err(dev->archdata.iommu,"%s,invalidating TLB failed\n",
772 dev_dbg(dev->archdata.iommu,"(%s) Disabled. Skipping invalidating TLB.\n",
776 read_unlock_irqrestore(&data->lock, flags);
779 static phys_addr_t rockchip_iommu_iova_to_phys(struct iommu_domain *domain,
782 struct rk_iommu_domain *priv = domain->priv;
783 unsigned long *entry;
785 phys_addr_t phys = 0;
787 spin_lock_irqsave(&priv->pgtablelock, flags);
789 entry = section_entry(priv->pgtable, iova);
790 entry = page_entry(entry, iova);
791 phys = spage_phys(entry) + spage_offs(iova);
793 spin_unlock_irqrestore(&priv->pgtablelock, flags);
798 static int lv2set_page(unsigned long *pent, phys_addr_t paddr,
799 size_t size, short *pgcnt)
801 if (!lv2ent_fault(pent))
804 *pent = mk_lv2ent_spage(paddr);
805 pgtable_flush(pent, pent + 1);
810 static unsigned long *alloc_lv2entry(unsigned long *sent,
811 unsigned long iova, short *pgcounter)
813 if (lv1ent_fault(sent)) {
816 pent = kmem_cache_zalloc(lv2table_kmem_cache, GFP_ATOMIC);
817 BUG_ON((unsigned long)pent & (LV2TABLE_SIZE - 1));
821 *sent = mk_lv1ent_page(__pa(pent));
822 kmemleak_ignore(pent);
823 *pgcounter = NUM_LV2ENTRIES;
824 pgtable_flush(pent, pent + NUM_LV2ENTRIES);
825 pgtable_flush(sent, sent + 1);
827 return page_entry(sent, iova);
830 static size_t rockchip_iommu_unmap(struct iommu_domain *domain,
831 unsigned long iova, size_t size)
833 struct rk_iommu_domain *priv = domain->priv;
837 BUG_ON(priv->pgtable == NULL);
839 spin_lock_irqsave(&priv->pgtablelock, flags);
841 ent = section_entry(priv->pgtable, iova);
843 if (unlikely(lv1ent_fault(ent))) {
844 if (size > SPAGE_SIZE)
849 /* lv1ent_page(sent) == true here */
851 ent = page_entry(ent, iova);
853 if (unlikely(lv2ent_fault(ent))) {
860 priv->lv2entcnt[lv1ent_offset(iova)] += 1;
865 pr_info("%s:unmap iova 0x%lx/0x%x bytes\n",
866 __func__, iova,size);
868 spin_unlock_irqrestore(&priv->pgtablelock, flags);
873 static int rockchip_iommu_map(struct iommu_domain *domain, unsigned long iova,
874 phys_addr_t paddr, size_t size, int prot)
876 struct rk_iommu_domain *priv = domain->priv;
877 unsigned long *entry;
882 BUG_ON(priv->pgtable == NULL);
884 spin_lock_irqsave(&priv->pgtablelock, flags);
886 entry = section_entry(priv->pgtable, iova);
888 pent = alloc_lv2entry(entry, iova,
889 &priv->lv2entcnt[lv1ent_offset(iova)]);
893 ret = lv2set_page(pent, paddr, size,
894 &priv->lv2entcnt[lv1ent_offset(iova)]);
897 pr_info("%s: Failed to map iova 0x%lx/0x%x bytes\n", __func__,
900 spin_unlock_irqrestore(&priv->pgtablelock, flags);
905 static void rockchip_iommu_detach_device(struct iommu_domain *domain,
908 struct iommu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
909 struct rk_iommu_domain *priv = domain->priv;
910 struct list_head *pos;
914 spin_lock_irqsave(&priv->lock, flags);
916 list_for_each(pos, &priv->clients)
918 if (list_entry(pos, struct iommu_drvdata, node) == data) {
926 if(cpu_is_rk312x() || cpu_is_rk3036())
927 rockchip_vcodec_select(data->dbgname);
929 if (__rockchip_iommu_disable(data)) {
930 dev_info(dev->archdata.iommu,"%s: Detached IOMMU with pgtable %#lx\n",
931 __func__, __pa(priv->pgtable));
932 list_del(&data->node);
933 INIT_LIST_HEAD(&data->node);
936 dev_info(dev->archdata.iommu,"%s: Detaching IOMMU with pgtable %#lx delayed",
937 __func__, __pa(priv->pgtable));
940 spin_unlock_irqrestore(&priv->lock, flags);
943 static int rockchip_iommu_attach_device(struct iommu_domain *domain,
946 struct iommu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
947 struct rk_iommu_domain *priv = domain->priv;
951 spin_lock_irqsave(&priv->lock, flags);
953 if(cpu_is_rk312x() || cpu_is_rk3036())
954 rockchip_vcodec_select(data->dbgname);
956 ret = __rockchip_iommu_enable(data, __pa(priv->pgtable), domain);
959 /* 'data->node' must not be appeared in priv->clients */
960 BUG_ON(!list_empty(&data->node));
962 list_add_tail(&data->node, &priv->clients);
965 spin_unlock_irqrestore(&priv->lock, flags);
968 dev_err(dev->archdata.iommu,"%s: Failed to attach IOMMU with pgtable %#lx\n",
969 __func__, __pa(priv->pgtable));
970 } else if (ret > 0) {
971 dev_dbg(dev->archdata.iommu,"%s: IOMMU with pgtable 0x%lx already attached\n",
972 __func__, __pa(priv->pgtable));
974 dev_dbg(dev->archdata.iommu,"%s: Attached new IOMMU with pgtable 0x%lx\n",
975 __func__, __pa(priv->pgtable));
981 static void rockchip_iommu_domain_destroy(struct iommu_domain *domain)
983 struct rk_iommu_domain *priv = domain->priv;
984 struct iommu_drvdata *data;
988 WARN_ON(!list_empty(&priv->clients));
990 spin_lock_irqsave(&priv->lock, flags);
992 list_for_each_entry(data, &priv->clients, node) {
993 if(cpu_is_rk312x() || cpu_is_rk3036())
994 rockchip_vcodec_select(data->dbgname);
995 while (!rockchip_iommu_disable(data->dev))
996 ; /* until System MMU is actually disabled */
998 spin_unlock_irqrestore(&priv->lock, flags);
1000 for (i = 0; i < NUM_LV1ENTRIES; i++)
1001 if (lv1ent_page(priv->pgtable + i))
1002 kmem_cache_free(lv2table_kmem_cache,
1003 __va(lv2table_base(priv->pgtable + i)));
1005 free_pages((unsigned long)priv->pgtable, 0);
1006 free_pages((unsigned long)priv->lv2entcnt, 0);
1007 kfree(domain->priv);
1008 domain->priv = NULL;
1011 static int rockchip_iommu_domain_init(struct iommu_domain *domain)
1013 struct rk_iommu_domain *priv;
1015 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
1019 /*rk32xx iommu use 2 level pagetable,
1020 level1 and leve2 both have 1024 entries,each entry occupy 4 bytes,
1021 so alloc a page size for each page table
1023 priv->pgtable = (unsigned long *)__get_free_pages(GFP_KERNEL |
1028 priv->lv2entcnt = (short *)__get_free_pages(GFP_KERNEL |
1030 if (!priv->lv2entcnt)
1033 pgtable_flush(priv->pgtable, priv->pgtable + NUM_LV1ENTRIES);
1035 spin_lock_init(&priv->lock);
1036 spin_lock_init(&priv->pgtablelock);
1037 INIT_LIST_HEAD(&priv->clients);
1039 domain->priv = priv;
1043 free_pages((unsigned long)priv->pgtable, 0);
1049 static struct iommu_ops rk_iommu_ops = {
1050 .domain_init = &rockchip_iommu_domain_init,
1051 .domain_destroy = &rockchip_iommu_domain_destroy,
1052 .attach_dev = &rockchip_iommu_attach_device,
1053 .detach_dev = &rockchip_iommu_detach_device,
1054 .map = &rockchip_iommu_map,
1055 .unmap = &rockchip_iommu_unmap,
1056 .iova_to_phys = &rockchip_iommu_iova_to_phys,
1057 .pgsize_bitmap = SPAGE_SIZE,
1060 static int rockchip_iommu_prepare(void)
1063 static int registed;
1068 lv2table_kmem_cache = kmem_cache_create("rk-iommu-lv2table",
1072 if (!lv2table_kmem_cache) {
1073 pr_info("%s: failed to create kmem cache\n", __func__);
1076 ret = bus_set_iommu(&platform_bus_type, &rk_iommu_ops);
1080 pr_info("%s:failed to set iommu to bus\r\n", __func__);
1084 static int rockchip_get_iommu_resource_num(struct platform_device *pdev,
1090 pr_info("dev num_resources %d type = 0x%08x\n",pdev->num_resources, type);
1092 for (i = 0; i < pdev->num_resources; i++) {
1093 struct resource *r = &pdev->resource[i];
1095 dev_info(&pdev->dev, "r[%d] start %08x end %08x flags %08lx name (%s) resource_type %08lx\n", i, r->start, r->end, r->flags, r->name, resource_type(r));
1097 if (type == resource_type(r))
1104 static struct kobject *dump_mmu_object;
1106 static int dump_mmu_pagetbl(struct device *dev, struct device_attribute *attr,
1107 const char *buf, u32 count)
1115 ret = kstrtouint(buf, 0, &mmu_base);
1117 dev_dbg(dev,"%s is not in hexdecimal form.\n", buf);
1118 base = ioremap(mmu_base, 0x100);
1119 if (base != rk312x_vop_mmu_base) {
1120 iommu_dte = __raw_readl(base + IOMMU_REGISTER_DTE_ADDR);
1121 fault_address = __raw_readl(base + IOMMU_REGISTER_PAGE_FAULT_ADDR);
1122 dump_pagetbl(fault_address, iommu_dte);
1124 dev_dbg(dev,"vop mmu not support\n");
1129 static DEVICE_ATTR(dump_mmu_pgtable, 0644, NULL, dump_mmu_pagetbl);
1131 void dump_iommu_sysfs_init(void)
1135 dump_mmu_object = kobject_create_and_add("rk_iommu", NULL);
1136 if (dump_mmu_object == NULL)
1138 ret = sysfs_create_file(dump_mmu_object,
1139 &dev_attr_dump_mmu_pgtable.attr);
1142 static int rockchip_iommu_probe(struct platform_device *pdev)
1146 struct iommu_drvdata *data;
1151 struct resource *res = pdev->resource;
1153 for (i = 0; i < pdev->num_resources; i++, res++) {
1154 pr_info("r[%d] start %08x end %08x flags %08lx name (%s) resource_type %08lx\n", i, res->start, res->end, res->flags, res->name, resource_type(res));
1157 ret = rockchip_iommu_prepare();
1159 dev_err(dev,"%s,failed\r\n", __func__);
1163 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
1165 dev_dbg(dev, "Not enough memory\n");
1169 dev_set_drvdata(dev, data);
1171 ret = dev_set_drvdata(dev, data);
1174 dev_dbg(dev, "Unabled to initialize driver data\n");
1178 if (pdev->dev.of_node) {
1179 of_property_read_string(pdev->dev.of_node,
1180 "dbgname", &(data->dbgname));
1183 "dbgname not assigned in device tree or device node not exist\r\n");
1186 dev_info(dev,"(%s) Enter\n", data->dbgname);
1189 data->num_res_mem = rockchip_get_iommu_resource_num(pdev,
1191 if (0 == data->num_res_mem) {
1192 dev_err(dev,"can't find iommu memory resource \r\n");
1195 dev_dbg(dev,"data->num_res_mem=%d\n", data->num_res_mem);
1196 data->num_res_irq = rockchip_get_iommu_resource_num(pdev,
1198 if (0 == data->num_res_irq) {
1199 dev_err(dev,"can't find iommu irq resource \r\n");
1202 dev_dbg(dev,"data->num_res_irq=%d\n", data->num_res_irq);
1204 data->res_bases = devm_kmalloc_array(dev, data->num_res_mem,
1205 sizeof(*data->res_bases), GFP_KERNEL);
1206 if (data->res_bases == NULL) {
1207 dev_err(dev, "Not enough memory\n");
1212 for (i = 0; i < data->num_res_mem; i++) {
1213 struct resource *res;
1215 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
1217 dev_err(dev,"Unable to find IOMEM region\n");
1221 data->res_bases[i] = ioremap(res->start, resource_size(res));
1222 dev_dbg(dev,"res->start = 0x%08x ioremap to data->res_bases[%d] = 0x%08x\n",
1223 res->start, i, (unsigned int)data->res_bases[i]);
1224 if (!data->res_bases[i]) {
1225 pr_err("Unable to map IOMEM @ PA:%#x\n", res->start);
1230 if (cpu_is_rk312x() || cpu_is_rk3036()) {
1231 rockchip_vcodec_select(data->dbgname);
1232 if (strstr(data->dbgname, "vop") && cpu_is_rk312x()) {
1233 rk312x_vop_mmu_base = data->res_bases[0];
1234 dev_dbg(dev,"rk312x_vop_mmu_base = 0x%08x\n",(unsigned int)rk312x_vop_mmu_base);
1237 if (!strstr(data->dbgname, "isp")) {
1238 if (!iommu_reset(data->res_bases[i], data->dbgname)) {
1245 for (i = 0; i < data->num_res_irq; i++) {
1246 ret = platform_get_irq(pdev, i);
1248 dev_err(dev,"Unable to find IRQ resource\n");
1251 ret = devm_request_irq(dev, ret, rockchip_iommu_irq,
1252 IRQF_SHARED, dev_name(dev), data);
1254 dev_err(dev,"Unabled to register interrupt handler\n");
1258 ret = rockchip_init_iovmm(dev, &data->vmm);
1263 rwlock_init(&data->lock);
1264 INIT_LIST_HEAD(&data->node);
1266 set_fault_handler(data, &default_fault_handler);
1268 dev_info(dev,"(%s) Initialized\n", data->dbgname);
1273 while (data->num_res_mem-- > 0)
1274 devm_iounmap(dev,data->res_bases[data->num_res_mem]);
1277 dev_err(dev, "Failed to initialize\n");
1282 static const struct of_device_id iommu_dt_ids[] = {
1283 { .compatible = IEP_IOMMU_COMPATIBLE_NAME},
1284 { .compatible = VIP_IOMMU_COMPATIBLE_NAME},
1285 { .compatible = VOPB_IOMMU_COMPATIBLE_NAME},
1286 { .compatible = VOPL_IOMMU_COMPATIBLE_NAME},
1287 { .compatible = HEVC_IOMMU_COMPATIBLE_NAME},
1288 { .compatible = VPU_IOMMU_COMPATIBLE_NAME},
1289 { .compatible = ISP_IOMMU_COMPATIBLE_NAME},
1290 { .compatible = VOP_IOMMU_COMPATIBLE_NAME},
1294 MODULE_DEVICE_TABLE(of, iommu_dt_ids);
1297 static struct platform_driver rk_iommu_driver = {
1298 .probe = rockchip_iommu_probe,
1302 .owner = THIS_MODULE,
1303 .of_match_table = of_match_ptr(iommu_dt_ids),
1307 static int __init rockchip_iommu_init_driver(void)
1309 dump_iommu_sysfs_init();
1311 return platform_driver_register(&rk_iommu_driver);
1314 core_initcall(rockchip_iommu_init_driver);