rockchip: iommu: fix some issue on iommu
[firefly-linux-kernel-4.4.55.git] / drivers / iommu / rockchip-iommu.c
1 /*
2  * This program is free software; you can redistribute it and/or modify
3  * it under the terms of the GNU General Public License version 2 as
4  * published by the Free Software Foundation.
5  */
6
7 #ifdef CONFIG_ROCKCHIP_IOMMU_DEBUG
8 #define DEBUG
9 #endif
10
11 #include <linux/io.h>
12 #include <linux/interrupt.h>
13 #include <linux/slab.h>
14 #include <linux/clk.h>
15 #include <linux/err.h>
16 #include <linux/mm.h>
17 #include <linux/errno.h>
18 #include <linux/memblock.h>
19 #include <linux/export.h>
20 #include <linux/module.h>
21
22 #include <asm/cacheflush.h>
23 #include <asm/pgtable.h>
24 #include <linux/of.h>
25 #include <linux/rockchip-iovmm.h>
26 #include <linux/rockchip/grf.h>
27 #include <linux/rockchip/cpu.h>
28 #include <linux/rockchip/iomap.h>
29 #include <linux/device.h>
30 #include "rockchip-iommu.h"
31
32 /* We does not consider super section mapping (16MB) */
33 #define SPAGE_ORDER 12
34 #define SPAGE_SIZE (1 << SPAGE_ORDER)
35 #define SPAGE_MASK (~(SPAGE_SIZE - 1))
36
37 static void __iomem *rk312x_vop_mmu_base;
38
39 enum iommu_entry_flags {
40         IOMMU_FLAGS_PRESENT = 0x01,
41         IOMMU_FLAGS_READ_PERMISSION = 0x02,
42         IOMMU_FLAGS_WRITE_PERMISSION = 0x04,
43         IOMMU_FLAGS_OVERRIDE_CACHE = 0x8,
44         IOMMU_FLAGS_WRITE_CACHEABLE = 0x10,
45         IOMMU_FLAGS_WRITE_ALLOCATE = 0x20,
46         IOMMU_FLAGS_WRITE_BUFFERABLE = 0x40,
47         IOMMU_FLAGS_READ_CACHEABLE = 0x80,
48         IOMMU_FLAGS_READ_ALLOCATE = 0x100,
49         IOMMU_FLAGS_MASK = 0x1FF,
50 };
51
52 #define lv1ent_fault(sent) ((*(sent) & IOMMU_FLAGS_PRESENT) == 0)
53 #define lv1ent_page(sent) ((*(sent) & IOMMU_FLAGS_PRESENT) == 1)
54 #define lv2ent_fault(pent) ((*(pent) & IOMMU_FLAGS_PRESENT) == 0)
55 #define spage_phys(pent) (*(pent) & SPAGE_MASK)
56 #define spage_offs(iova) ((iova) & 0x0FFF)
57
58 #define lv1ent_offset(iova) (((iova)>>22) & 0x03FF)
59 #define lv2ent_offset(iova) (((iova)>>12) & 0x03FF)
60
61 #define NUM_LV1ENTRIES 1024
62 #define NUM_LV2ENTRIES 1024
63
64 #define LV2TABLE_SIZE (NUM_LV2ENTRIES * sizeof(long))
65
66 #define lv2table_base(sent) (*(sent) & 0xFFFFFFFE)
67
68 #define mk_lv1ent_page(pa) ((pa) | IOMMU_FLAGS_PRESENT)
69 /*write and read permission for level2 page default*/
70 #define mk_lv2ent_spage(pa) ((pa) | IOMMU_FLAGS_PRESENT | \
71                              IOMMU_FLAGS_READ_PERMISSION | \
72                              IOMMU_FLAGS_WRITE_PERMISSION)
73
74 #define IOMMU_REG_POLL_COUNT_FAST 1000
75
76 /*rk3036:vpu and hevc share ahb interface*/
77 #define BIT_VCODEC_SEL_3036 (1<<3)
78 #define BIT_VCODEC_SEL_312x (1<<15)
79
80
81 /**
82  * MMU register numbers
83  * Used in the register read/write routines.
84  * See the hardware documentation for more information about each register
85  */
86 enum iommu_register {
87         /**< Current Page Directory Pointer */
88         IOMMU_REGISTER_DTE_ADDR = 0x0000,
89         /**< Status of the MMU */
90         IOMMU_REGISTER_STATUS = 0x0004,
91         /**< Command register, used to control the MMU */
92         IOMMU_REGISTER_COMMAND = 0x0008,
93         /**< Logical address of the last page fault */
94         IOMMU_REGISTER_PAGE_FAULT_ADDR = 0x000C,
95         /**< Used to invalidate the mapping of a single page from the MMU */
96         IOMMU_REGISTER_ZAP_ONE_LINE = 0x010,
97         /**< Raw interrupt status, all interrupts visible */
98         IOMMU_REGISTER_INT_RAWSTAT = 0x0014,
99         /**< Indicate to the MMU that the interrupt has been received */
100         IOMMU_REGISTER_INT_CLEAR = 0x0018,
101         /**< Enable/disable types of interrupts */
102         IOMMU_REGISTER_INT_MASK = 0x001C,
103         /**< Interrupt status based on the mask */
104         IOMMU_REGISTER_INT_STATUS = 0x0020,
105         IOMMU_REGISTER_AUTO_GATING = 0x0024
106 };
107
108 enum iommu_command {
109         /**< Enable paging (memory translation) */
110         IOMMU_COMMAND_ENABLE_PAGING = 0x00,
111         /**< Disable paging (memory translation) */
112         IOMMU_COMMAND_DISABLE_PAGING = 0x01,
113         /**<  Enable stall on page fault */
114         IOMMU_COMMAND_ENABLE_STALL = 0x02,
115         /**< Disable stall on page fault */
116         IOMMU_COMMAND_DISABLE_STALL = 0x03,
117         /**< Zap the entire page table cache */
118         IOMMU_COMMAND_ZAP_CACHE = 0x04,
119         /**< Page fault processed */
120         IOMMU_COMMAND_PAGE_FAULT_DONE = 0x05,
121         /**< Reset the MMU back to power-on settings */
122         IOMMU_COMMAND_HARD_RESET = 0x06
123 };
124
125 /**
126  * MMU interrupt register bits
127  * Each cause of the interrupt is reported
128  * through the (raw) interrupt status registers.
129  * Multiple interrupts can be pending, so multiple bits
130  * can be set at once.
131  */
132 enum iommu_interrupt {
133         IOMMU_INTERRUPT_PAGE_FAULT = 0x01, /**< A page fault occured */
134         IOMMU_INTERRUPT_READ_BUS_ERROR = 0x02 /**< A bus read error occured */
135 };
136
137 enum iommu_status_bits {
138         IOMMU_STATUS_BIT_PAGING_ENABLED      = 1 << 0,
139         IOMMU_STATUS_BIT_PAGE_FAULT_ACTIVE   = 1 << 1,
140         IOMMU_STATUS_BIT_STALL_ACTIVE        = 1 << 2,
141         IOMMU_STATUS_BIT_IDLE                = 1 << 3,
142         IOMMU_STATUS_BIT_REPLAY_BUFFER_EMPTY = 1 << 4,
143         IOMMU_STATUS_BIT_PAGE_FAULT_IS_WRITE = 1 << 5,
144         IOMMU_STATUS_BIT_STALL_NOT_ACTIVE    = 1 << 31,
145 };
146
147 /**
148  * Size of an MMU page in bytes
149  */
150 #define IOMMU_PAGE_SIZE 0x1000
151
152 /*
153  * Size of the address space referenced by a page table page
154  */
155 #define IOMMU_VIRTUAL_PAGE_SIZE 0x400000 /* 4 MiB */
156
157 /**
158  * Page directory index from address
159  * Calculates the page directory index from the given address
160  */
161 #define IOMMU_PDE_ENTRY(address) (((address)>>22) & 0x03FF)
162
163 /**
164  * Page table index from address
165  * Calculates the page table index from the given address
166  */
167 #define IOMMU_PTE_ENTRY(address) (((address)>>12) & 0x03FF)
168
169 /**
170  * Extract the memory address from an PDE/PTE entry
171  */
172 #define IOMMU_ENTRY_ADDRESS(value) ((value) & 0xFFFFFC00)
173
174 #define INVALID_PAGE ((u32)(~0))
175
176 static struct kmem_cache *lv2table_kmem_cache;
177
178 static void rockchip_vcodec_select(const char *string)
179 {
180         if (strstr(string,"hevc")) {
181                 if (cpu_is_rk3036()) {
182                         writel_relaxed(readl_relaxed(RK_GRF_VIRT + RK3036_GRF_SOC_CON1) |
183                               (BIT_VCODEC_SEL_3036) | (BIT_VCODEC_SEL_3036 << 16),
184                               RK_GRF_VIRT + RK3036_GRF_SOC_CON1);
185                 } else {
186                         writel_relaxed(readl_relaxed(RK_GRF_VIRT + RK312X_GRF_SOC_CON1) |
187                               (BIT_VCODEC_SEL_312x) | (BIT_VCODEC_SEL_312x << 16),
188                               RK_GRF_VIRT + RK312X_GRF_SOC_CON1);
189                 }
190         } else if (strstr(string,"vpu")) {
191                 if (cpu_is_rk3036()) {
192                         writel_relaxed((readl_relaxed(RK_GRF_VIRT + RK3036_GRF_SOC_CON1) &
193                                (~BIT_VCODEC_SEL_3036)) | (BIT_VCODEC_SEL_3036 << 16),
194                                RK_GRF_VIRT + RK3036_GRF_SOC_CON1);
195                 } else {
196                         writel_relaxed((readl_relaxed(RK_GRF_VIRT + RK312X_GRF_SOC_CON1) &
197                                (~BIT_VCODEC_SEL_312x)) | (BIT_VCODEC_SEL_312x << 16),
198                                RK_GRF_VIRT + RK312X_GRF_SOC_CON1);
199                 }
200         }
201 }
202 static unsigned long *section_entry(unsigned long *pgtable, unsigned long iova)
203 {
204         return pgtable + lv1ent_offset(iova);
205 }
206
207 static unsigned long *page_entry(unsigned long *sent, unsigned long iova)
208 {
209         return (unsigned long *)__va(lv2table_base(sent)) + lv2ent_offset(iova);
210 }
211
212 static char *iommu_fault_name[IOMMU_FAULTS_NUM] = {
213         "PAGE FAULT",
214         "BUS ERROR",
215         "UNKNOWN FAULT"
216 };
217
218 struct rk_iommu_domain {
219         struct list_head clients; /* list of iommu_drvdata.node */
220         unsigned long *pgtable; /* lv1 page table, 4KB */
221         short *lv2entcnt; /* free lv2 entry counter for each section */
222         spinlock_t lock; /* lock for this structure */
223         spinlock_t pgtablelock; /* lock for modifying page table @ pgtable */
224 };
225
226 static bool set_iommu_active(struct iommu_drvdata *data)
227 {
228         /* return true if the IOMMU was not active previously
229            and it needs to be initialized */
230         return ++data->activations == 1;
231 }
232
233 static bool set_iommu_inactive(struct iommu_drvdata *data)
234 {
235         /* return true if the IOMMU is needed to be disabled */
236         BUG_ON(data->activations < 1);
237         return --data->activations == 0;
238 }
239
240 static bool is_iommu_active(struct iommu_drvdata *data)
241 {
242         return data->activations > 0;
243 }
244
245 static void iommu_disable_stall(void __iomem *base)
246 {
247         int i;
248         u32 mmu_status;
249
250         if (base != rk312x_vop_mmu_base) {
251                 mmu_status = __raw_readl(base + IOMMU_REGISTER_STATUS);
252         } else {
253                 goto skip_vop_mmu_disable;
254         }
255         if (0 == (mmu_status & IOMMU_STATUS_BIT_PAGING_ENABLED))
256                 return;
257         if (mmu_status & IOMMU_STATUS_BIT_PAGE_FAULT_ACTIVE) {
258                 pr_info("Aborting MMU disable stall request since it is in pagefault state.\n");
259                 return;
260         }
261         skip_vop_mmu_disable:
262         __raw_writel(IOMMU_COMMAND_DISABLE_STALL,
263                      base + IOMMU_REGISTER_COMMAND);
264
265         for (i = 0; i < IOMMU_REG_POLL_COUNT_FAST; ++i) {
266                 u32 status;
267                 
268                 if (base != rk312x_vop_mmu_base) {
269                         status = __raw_readl(base + IOMMU_REGISTER_STATUS);
270                 } else {
271                         int j;
272                         while (j < 5)
273                                 j++;
274                         return; 
275                 }
276                 if (0 == (status & IOMMU_STATUS_BIT_STALL_ACTIVE))
277                         break;
278                 if (status & IOMMU_STATUS_BIT_PAGE_FAULT_ACTIVE)
279                         break;
280                 if (0 == (mmu_status & IOMMU_STATUS_BIT_PAGING_ENABLED))
281                         break;
282         }
283         if (IOMMU_REG_POLL_COUNT_FAST == i) {
284                 pr_info("Disable stall request failed, MMU status is 0x%08X\n",
285                       __raw_readl(base + IOMMU_REGISTER_STATUS));
286         }
287 }
288
289 static bool iommu_enable_stall(void __iomem *base)
290 {
291         int i;
292
293         u32 mmu_status;
294         
295         if (base != rk312x_vop_mmu_base) {
296                 mmu_status = __raw_readl(base + IOMMU_REGISTER_STATUS);
297         } else {
298                 goto skip_vop_mmu_enable;
299         }
300         if (0 == (mmu_status & IOMMU_STATUS_BIT_PAGING_ENABLED))
301                 return true;
302         if (mmu_status & IOMMU_STATUS_BIT_PAGE_FAULT_ACTIVE) {
303                 pr_info("Aborting MMU stall request since it is in pagefault state.\n");
304                 return false;
305         }
306         skip_vop_mmu_enable:
307         __raw_writel(IOMMU_COMMAND_ENABLE_STALL,
308                      base + IOMMU_REGISTER_COMMAND);
309
310         for (i = 0; i < IOMMU_REG_POLL_COUNT_FAST; ++i) {
311                 if (base != rk312x_vop_mmu_base) {
312                         mmu_status = __raw_readl(base + IOMMU_REGISTER_STATUS);
313                 } else {
314                         int j;
315                         while (j < 5)
316                                 j++;
317                         return true;
318                 }
319                 if (mmu_status & IOMMU_STATUS_BIT_PAGE_FAULT_ACTIVE)
320                         break;
321                 if ((mmu_status & IOMMU_STATUS_BIT_STALL_ACTIVE) &&
322                     (0 == (mmu_status & IOMMU_STATUS_BIT_STALL_NOT_ACTIVE)))
323                         break;
324                 if (0 == (mmu_status & (IOMMU_STATUS_BIT_PAGING_ENABLED)))
325                         break;
326         }
327         if (IOMMU_REG_POLL_COUNT_FAST == i) {
328                 pr_info("Enable stall request failed, MMU status is 0x%08X\n",
329                        __raw_readl(base + IOMMU_REGISTER_STATUS));
330                 return false;
331         }
332         if (mmu_status & IOMMU_STATUS_BIT_PAGE_FAULT_ACTIVE) {
333                 pr_info("Aborting MMU stall request since it has a pagefault.\n");
334                 return false;
335         }
336         return true;
337 }
338
339 static bool iommu_enable_paging(void __iomem *base)
340 {
341         int i;
342
343         __raw_writel(IOMMU_COMMAND_ENABLE_PAGING,
344                      base + IOMMU_REGISTER_COMMAND);
345
346         for (i = 0; i < IOMMU_REG_POLL_COUNT_FAST; ++i) {
347                 if (base != rk312x_vop_mmu_base) {
348                         if (__raw_readl(base + IOMMU_REGISTER_STATUS) &
349                                 IOMMU_STATUS_BIT_PAGING_ENABLED)
350                         break;
351                 } else {
352                         int j;
353                         while (j < 5)
354                                 j++;
355                         return true;
356                 }
357         }
358         if (IOMMU_REG_POLL_COUNT_FAST == i) {
359                 pr_info("Enable paging request failed, MMU status is 0x%08X\n",
360                        __raw_readl(base + IOMMU_REGISTER_STATUS));
361                 return false;
362         }
363         return true;
364 }
365
366 static bool iommu_disable_paging(void __iomem *base)
367 {
368         int i;
369
370         __raw_writel(IOMMU_COMMAND_DISABLE_PAGING,
371                      base + IOMMU_REGISTER_COMMAND);
372
373         for (i = 0; i < IOMMU_REG_POLL_COUNT_FAST; ++i) {
374                 if (base != rk312x_vop_mmu_base) {
375                         if (!(__raw_readl(base + IOMMU_REGISTER_STATUS) &
376                                   IOMMU_STATUS_BIT_PAGING_ENABLED))
377                                 break;
378                 } else {
379                         int j;
380                         while (j < 5)
381                                 j++;
382                         return true;
383                 }
384         }
385         if (IOMMU_REG_POLL_COUNT_FAST == i) {
386                 pr_info("Disable paging request failed, MMU status is 0x%08X\n",
387                        __raw_readl(base + IOMMU_REGISTER_STATUS));
388                 return false;
389         }
390         return true;
391 }
392
393 static void iommu_page_fault_done(void __iomem *base, const char *dbgname)
394 {
395         pr_info("MMU: %s: Leaving page fault mode\n",
396                 dbgname);
397         __raw_writel(IOMMU_COMMAND_PAGE_FAULT_DONE,
398                      base + IOMMU_REGISTER_COMMAND);
399 }
400
401 static bool iommu_zap_tlb(void __iomem *base)
402 {
403         bool stall_success = iommu_enable_stall(base);
404
405         __raw_writel(IOMMU_COMMAND_ZAP_CACHE,
406                      base + IOMMU_REGISTER_COMMAND);
407         if (!stall_success)
408                 return false;
409         iommu_disable_stall(base);
410         return true;
411 }
412 extern bool __clk_is_enabled(struct clk *clk);
413 static inline bool iommu_raw_reset(void __iomem *base)
414 {
415         int i;
416         unsigned int ret;
417
418         __raw_writel(0xCAFEBABE, base + IOMMU_REGISTER_DTE_ADDR);
419
420         if (base != rk312x_vop_mmu_base) {
421                 ret = __raw_readl(base + IOMMU_REGISTER_DTE_ADDR);
422                 if (!(0xCAFEB000 == ret)) {
423                         pr_info("error when %s.\n", __func__);
424                         return false;
425                 }
426         }
427         __raw_writel(IOMMU_COMMAND_HARD_RESET,
428                      base + IOMMU_REGISTER_COMMAND);
429
430         for (i = 0; i < IOMMU_REG_POLL_COUNT_FAST; ++i) {
431                 if (base != rk312x_vop_mmu_base) {
432                         if (__raw_readl(base + IOMMU_REGISTER_DTE_ADDR) == 0)
433                                 break;
434                 } else {
435                         int j;
436                         while (j < 5)
437                                 j++;
438                         return true;
439                 }
440         }
441         if (IOMMU_REG_POLL_COUNT_FAST == i) {
442                 pr_info("%s,Reset request failed, MMU status is 0x%08X\n",
443                        __func__, __raw_readl(base + IOMMU_REGISTER_DTE_ADDR));
444                 return false;
445         }
446         return true;
447 }
448
449 static void __iommu_set_ptbase(void __iomem *base, unsigned long pgd)
450 {
451         __raw_writel(pgd, base + IOMMU_REGISTER_DTE_ADDR);
452 }
453
454 static bool iommu_reset(void __iomem *base, const char *dbgname)
455 {
456         bool err = true;
457
458         err = iommu_enable_stall(base);
459         if (!err) {
460                 pr_info("%s:stall failed: %s\n", __func__, dbgname);
461                 return err;
462         }
463         err = iommu_raw_reset(base);
464         if (err)
465                 __raw_writel(IOMMU_INTERRUPT_PAGE_FAULT |
466                              IOMMU_INTERRUPT_READ_BUS_ERROR,
467                              base+IOMMU_REGISTER_INT_MASK);
468         iommu_disable_stall(base);
469         if (!err)
470                 pr_info("%s: failed: %s\n", __func__, dbgname);
471         return err;
472 }
473
474 static inline void pgtable_flush(void *vastart, void *vaend)
475 {
476         dmac_flush_range(vastart, vaend);
477         outer_flush_range(virt_to_phys(vastart), virt_to_phys(vaend));
478 }
479
480 static void set_fault_handler(struct iommu_drvdata *data,
481                                 rockchip_iommu_fault_handler_t handler)
482 {
483         unsigned long flags;
484
485         write_lock_irqsave(&data->lock, flags);
486         data->fault_handler = handler;
487         write_unlock_irqrestore(&data->lock, flags);
488 }
489
490 static int default_fault_handler(struct device *dev,
491                                  enum rk_iommu_inttype itype,
492                                  unsigned long pgtable_base,
493                                  unsigned long fault_addr,
494                                  unsigned int status)
495 {
496         struct iommu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
497
498         if (!data) {
499                 dev_err(dev->archdata.iommu,"%s,iommu device not assigned yet\n", __func__);
500                 return 0;
501         }
502         if ((itype >= IOMMU_FAULTS_NUM) || (itype < IOMMU_PAGEFAULT))
503                 itype = IOMMU_FAULT_UNKNOWN;
504
505         if (itype == IOMMU_BUSERROR)
506                 dev_err(dev->archdata.iommu,"%s occured at 0x%lx(Page table base: 0x%lx)\n",
507                        iommu_fault_name[itype], fault_addr, pgtable_base);
508
509         if (itype == IOMMU_PAGEFAULT)
510                 dev_err(dev->archdata.iommu,"IOMMU:Page fault detected at 0x%lx from bus id %d of type %s on %s\n",
511                        fault_addr,
512                        (status >> 6) & 0x1F,
513                        (status & 32) ? "write" : "read",
514                        data->dbgname);
515
516         dev_err(dev->archdata.iommu,"Generating Kernel OOPS... because it is unrecoverable.\n");
517
518         BUG();
519
520         return 0;
521 }
522
523 static void dump_pagetbl(u32 fault_address, u32 addr_dte)
524 {
525         u32 lv1_offset;
526         u32 lv2_offset;
527
528         u32 *lv1_entry_pa;
529         u32 *lv1_entry_va;
530         u32 *lv1_entry_value;
531
532         u32 *lv2_base;
533         u32 *lv2_entry_pa;
534         u32 *lv2_entry_va;
535         u32 *lv2_entry_value;
536
537
538         lv1_offset = lv1ent_offset(fault_address);
539         lv2_offset = lv2ent_offset(fault_address);
540
541         lv1_entry_pa = (u32 *)addr_dte + lv1_offset;
542         lv1_entry_va = (u32 *)(__va(addr_dte)) + lv1_offset;
543         lv1_entry_value = (u32 *)(*lv1_entry_va);
544
545         lv2_base = (u32 *)((*lv1_entry_va) & 0xfffffffe);
546         lv2_entry_pa = (u32 *)lv2_base + lv2_offset;
547         lv2_entry_va = (u32 *)(__va(lv2_base)) + lv2_offset;
548         lv2_entry_value = (u32 *)(*lv2_entry_va);
549
550         dev_info(NULL,"fault address = 0x%08x,dte addr pa = 0x%08x,va = 0x%08x\n",
551                 fault_address, addr_dte, (u32)__va(addr_dte));
552         dev_info(NULL,"lv1_offset = 0x%x,lv1_entry_pa = 0x%08x,lv1_entry_va = 0x%08x\n",
553                 lv1_offset, (u32)lv1_entry_pa, (u32)lv1_entry_va);
554         dev_info(NULL,"lv1_entry_value(*lv1_entry_va) = 0x%08x,lv2_base = 0x%08x\n",
555                 (u32)lv1_entry_value, (u32)lv2_base);
556         dev_info(NULL,"lv2_offset = 0x%x,lv2_entry_pa = 0x%08x,lv2_entry_va = 0x%08x\n",
557                 lv2_offset, (u32)lv2_entry_pa, (u32)lv2_entry_va);
558         dev_info(NULL,"lv2_entry value(*lv2_entry_va) = 0x%08x\n",
559                 (u32)lv2_entry_value);
560 }
561
562 static irqreturn_t rockchip_iommu_irq(int irq, void *dev_id)
563 {
564         /* SYSMMU is in blocked when interrupt occurred. */
565         struct iommu_drvdata *data = dev_id;
566         struct resource *irqres;
567         struct platform_device *pdev;
568         enum rk_iommu_inttype itype = IOMMU_FAULT_UNKNOWN;
569         u32 status;
570         u32 rawstat;
571         u32 int_status;
572         u32 fault_address;
573         int i, ret = 0;
574
575         read_lock(&data->lock);
576
577         if (!is_iommu_active(data)) {
578                 read_unlock(&data->lock);
579                 return IRQ_HANDLED;
580         }
581         
582         if(cpu_is_rk312x() || cpu_is_rk3036())
583                 rockchip_vcodec_select(data->dbgname);
584         
585         pdev = to_platform_device(data->iommu);
586
587         for (i = 0; i < data->num_res_irq; i++) {
588                 irqres = platform_get_resource(pdev, IORESOURCE_IRQ, i);
589                 if (irqres && ((int)irqres->start == irq)) {
590                         if (data->res_bases[i] == rk312x_vop_mmu_base) {
591                                 read_unlock(&data->lock);
592                                 return IRQ_HANDLED;
593                         }
594                         break;
595                 }
596         }
597
598         if (i == data->num_res_irq) {
599                 itype = IOMMU_FAULT_UNKNOWN;
600         } else {
601                 int_status = __raw_readl(data->res_bases[i] +
602                                          IOMMU_REGISTER_INT_STATUS);
603
604                 if (int_status != 0) {
605                         /*mask status*/
606                         __raw_writel(0x00, data->res_bases[i] +
607                                      IOMMU_REGISTER_INT_MASK);
608
609                         rawstat = __raw_readl(data->res_bases[i] +
610                                               IOMMU_REGISTER_INT_RAWSTAT);
611
612                         if (rawstat & IOMMU_INTERRUPT_PAGE_FAULT) {
613                                 fault_address = __raw_readl(data->res_bases[i] +
614                                 IOMMU_REGISTER_PAGE_FAULT_ADDR);
615                                 itype = IOMMU_PAGEFAULT;
616                         } else if (rawstat & IOMMU_INTERRUPT_READ_BUS_ERROR) {
617                                 itype = IOMMU_BUSERROR;
618                         } else {
619                                 goto out;
620                         }
621                         dump_pagetbl(fault_address,
622                                      __raw_readl(data->res_bases[i] +
623                                      IOMMU_REGISTER_DTE_ADDR));
624                 } else {
625                         goto out;
626                 }
627         }
628
629         if (data->fault_handler) {
630                 unsigned long base = __raw_readl(data->res_bases[i] +
631                                                  IOMMU_REGISTER_DTE_ADDR);
632                 status = __raw_readl(data->res_bases[i] +
633                                      IOMMU_REGISTER_STATUS);
634                 ret = data->fault_handler(data->dev, itype, base,
635                                           fault_address, status);
636         }
637
638         if (!ret && (itype != IOMMU_FAULT_UNKNOWN)) {
639                 if (IOMMU_PAGEFAULT == itype) {
640                         iommu_zap_tlb(data->res_bases[i]);
641                         iommu_page_fault_done(data->res_bases[i],
642                                                data->dbgname);
643                         __raw_writel(IOMMU_INTERRUPT_PAGE_FAULT |
644                                      IOMMU_INTERRUPT_READ_BUS_ERROR,
645                                      data->res_bases[i] +
646                                      IOMMU_REGISTER_INT_MASK);
647                 }
648         } else {
649                 dev_err(data->iommu,"(%s) %s is not handled.\n",
650                        data->dbgname, iommu_fault_name[itype]);
651         }
652
653 out:
654         read_unlock(&data->lock);
655
656         return IRQ_HANDLED;
657 }
658
659 static bool __rockchip_iommu_disable(struct iommu_drvdata *data)
660 {
661         unsigned long flags;
662         int i;
663         bool disabled = false;
664
665         write_lock_irqsave(&data->lock, flags);
666
667         if (!set_iommu_inactive(data))
668                 goto finish;
669
670         for (i = 0; i < data->num_res_mem; i++)
671                 iommu_disable_paging(data->res_bases[i]);
672
673         disabled = true;
674         data->pgtable = 0;
675         data->domain = NULL;
676 finish:
677         write_unlock_irqrestore(&data->lock, flags);
678
679         if (disabled)
680                 dev_info(data->iommu,"(%s) Disabled\n", data->dbgname);
681         else
682                 dev_info(data->iommu,"(%s) %d times left to be disabled\n",
683                         data->dbgname, data->activations);
684
685         return disabled;
686 }
687
688 /* __rk_sysmmu_enable: Enables System MMU
689  *
690  * returns -error if an error occurred and System MMU is not enabled,
691  * 0 if the System MMU has been just enabled and 1 if System MMU was already
692  * enabled before.
693  */
694 static int __rockchip_iommu_enable(struct iommu_drvdata *data,
695                                     unsigned long pgtable,
696                                     struct iommu_domain *domain)
697 {
698         int i, ret = 0;
699         unsigned long flags;
700
701         write_lock_irqsave(&data->lock, flags);
702
703         if (!set_iommu_active(data)) {
704                 if (WARN_ON(pgtable != data->pgtable)) {
705                         ret = -EBUSY;
706                         set_iommu_inactive(data);
707                 } else {
708                         ret = 1;
709                 }
710
711                 dev_info(data->iommu,"(%s) Already enabled\n", data->dbgname);
712                 goto finish;
713         }
714
715         data->pgtable = pgtable;
716
717         for (i = 0; i < data->num_res_mem; i++) {
718                 bool status;
719
720                 status = iommu_enable_stall(data->res_bases[i]);
721                 if (status) {
722                         __iommu_set_ptbase(data->res_bases[i], pgtable);
723                         __raw_writel(IOMMU_COMMAND_ZAP_CACHE,
724                                      data->res_bases[i] +
725                                      IOMMU_REGISTER_COMMAND);
726                 }
727                 __raw_writel(IOMMU_INTERRUPT_PAGE_FAULT |
728                              IOMMU_INTERRUPT_READ_BUS_ERROR,
729                              data->res_bases[i]+IOMMU_REGISTER_INT_MASK);
730                 iommu_enable_paging(data->res_bases[i]);
731                 iommu_disable_stall(data->res_bases[i]);
732         }
733
734         data->domain = domain;
735
736         dev_info(data->iommu,"(%s) Enabled\n", data->dbgname);
737 finish:
738         write_unlock_irqrestore(&data->lock, flags);
739
740         return ret;
741 }
742
743 bool rockchip_iommu_disable(struct device *dev)
744 {
745         struct iommu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
746         bool disabled;
747
748         disabled = __rockchip_iommu_disable(data);
749
750         return disabled;
751 }
752
753 void rockchip_iommu_tlb_invalidate(struct device *dev)
754 {
755         unsigned long flags;
756         struct iommu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
757
758         read_lock_irqsave(&data->lock, flags);
759         
760         if(cpu_is_rk312x() || cpu_is_rk3036())
761                 rockchip_vcodec_select(data->dbgname);
762         
763         if (is_iommu_active(data)) {
764                 int i;
765
766                 for (i = 0; i < data->num_res_mem; i++) {
767                         if (!iommu_zap_tlb(data->res_bases[i]))
768                                 dev_err(dev->archdata.iommu,"%s,invalidating TLB failed\n",
769                                        data->dbgname);
770                 }
771         } else {
772                 dev_dbg(dev->archdata.iommu,"(%s) Disabled. Skipping invalidating TLB.\n",
773                         data->dbgname);
774         }
775
776         read_unlock_irqrestore(&data->lock, flags);
777 }
778
779 static phys_addr_t rockchip_iommu_iova_to_phys(struct iommu_domain *domain,
780                                                dma_addr_t iova)
781 {
782         struct rk_iommu_domain *priv = domain->priv;
783         unsigned long *entry;
784         unsigned long flags;
785         phys_addr_t phys = 0;
786
787         spin_lock_irqsave(&priv->pgtablelock, flags);
788
789         entry = section_entry(priv->pgtable, iova);
790         entry = page_entry(entry, iova);
791         phys = spage_phys(entry) + spage_offs(iova);
792
793         spin_unlock_irqrestore(&priv->pgtablelock, flags);
794
795         return phys;
796 }
797
798 static int lv2set_page(unsigned long *pent, phys_addr_t paddr,
799                        size_t size, short *pgcnt)
800 {
801         if (!lv2ent_fault(pent))
802                 return -EADDRINUSE;
803
804         *pent = mk_lv2ent_spage(paddr);
805         pgtable_flush(pent, pent + 1);
806         *pgcnt -= 1;
807         return 0;
808 }
809
810 static unsigned long *alloc_lv2entry(unsigned long *sent,
811                                      unsigned long iova, short *pgcounter)
812 {
813         if (lv1ent_fault(sent)) {
814                 unsigned long *pent;
815
816                 pent = kmem_cache_zalloc(lv2table_kmem_cache, GFP_ATOMIC);
817                 BUG_ON((unsigned long)pent & (LV2TABLE_SIZE - 1));
818                 if (!pent)
819                         return NULL;
820
821                 *sent = mk_lv1ent_page(__pa(pent));
822                 kmemleak_ignore(pent);
823                 *pgcounter = NUM_LV2ENTRIES;
824                 pgtable_flush(pent, pent + NUM_LV2ENTRIES);
825                 pgtable_flush(sent, sent + 1);
826         }
827         return page_entry(sent, iova);
828 }
829
830 static size_t rockchip_iommu_unmap(struct iommu_domain *domain,
831                                    unsigned long iova, size_t size)
832 {
833         struct rk_iommu_domain *priv = domain->priv;
834         unsigned long flags;
835         unsigned long *ent;
836
837         BUG_ON(priv->pgtable == NULL);
838
839         spin_lock_irqsave(&priv->pgtablelock, flags);
840
841         ent = section_entry(priv->pgtable, iova);
842
843         if (unlikely(lv1ent_fault(ent))) {
844                 if (size > SPAGE_SIZE)
845                         size = SPAGE_SIZE;
846                 goto done;
847         }
848
849         /* lv1ent_page(sent) == true here */
850
851         ent = page_entry(ent, iova);
852
853         if (unlikely(lv2ent_fault(ent))) {
854                 size = SPAGE_SIZE;
855                 goto done;
856         }
857
858         *ent = 0;
859         size = SPAGE_SIZE;
860         priv->lv2entcnt[lv1ent_offset(iova)] += 1;
861         goto done;
862
863 done:
864         #if 0
865         pr_info("%s:unmap iova 0x%lx/0x%x bytes\n",
866                   __func__, iova,size);
867         #endif
868         spin_unlock_irqrestore(&priv->pgtablelock, flags);
869
870         return size;
871 }
872
873 static int rockchip_iommu_map(struct iommu_domain *domain, unsigned long iova,
874                               phys_addr_t paddr, size_t size, int prot)
875 {
876         struct rk_iommu_domain *priv = domain->priv;
877         unsigned long *entry;
878         unsigned long flags;
879         int ret = -ENOMEM;
880         unsigned long *pent;
881
882         BUG_ON(priv->pgtable == NULL);
883
884         spin_lock_irqsave(&priv->pgtablelock, flags);
885
886         entry = section_entry(priv->pgtable, iova);
887
888         pent = alloc_lv2entry(entry, iova,
889                               &priv->lv2entcnt[lv1ent_offset(iova)]);
890         if (!pent)
891                 ret = -ENOMEM;
892         else
893                 ret = lv2set_page(pent, paddr, size,
894                                   &priv->lv2entcnt[lv1ent_offset(iova)]);
895
896         if (ret) {
897                 pr_info("%s: Failed to map iova 0x%lx/0x%x bytes\n", __func__,
898                        iova, size);
899         }
900         spin_unlock_irqrestore(&priv->pgtablelock, flags);
901
902         return ret;
903 }
904
905 static void rockchip_iommu_detach_device(struct iommu_domain *domain,
906                                          struct device *dev)
907 {
908         struct iommu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
909         struct rk_iommu_domain *priv = domain->priv;
910         struct list_head *pos;
911         unsigned long flags;
912         bool found = false;
913
914         spin_lock_irqsave(&priv->lock, flags);
915
916         list_for_each(pos, &priv->clients)
917         {
918                 if (list_entry(pos, struct iommu_drvdata, node) == data) {
919                         found = true;
920                         break;
921                 }
922         }
923         if (!found)
924                 goto finish;
925         
926         if(cpu_is_rk312x() || cpu_is_rk3036())
927                 rockchip_vcodec_select(data->dbgname);
928         
929         if (__rockchip_iommu_disable(data)) {
930                 dev_info(dev->archdata.iommu,"%s: Detached IOMMU with pgtable %#lx\n",
931                         __func__, __pa(priv->pgtable));
932                 list_del(&data->node);
933                 INIT_LIST_HEAD(&data->node);
934
935         } else
936                 dev_info(dev->archdata.iommu,"%s: Detaching IOMMU with pgtable %#lx delayed",
937                         __func__, __pa(priv->pgtable));
938
939 finish:
940         spin_unlock_irqrestore(&priv->lock, flags);
941 }
942
943 static int rockchip_iommu_attach_device(struct iommu_domain *domain,
944                                         struct device *dev)
945 {
946         struct iommu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
947         struct rk_iommu_domain *priv = domain->priv;
948         unsigned long flags;
949         int ret;
950
951         spin_lock_irqsave(&priv->lock, flags);
952
953         if(cpu_is_rk312x() || cpu_is_rk3036())
954                 rockchip_vcodec_select(data->dbgname);
955         
956         ret = __rockchip_iommu_enable(data, __pa(priv->pgtable), domain);
957
958         if (ret == 0) {
959                 /* 'data->node' must not be appeared in priv->clients */
960                 BUG_ON(!list_empty(&data->node));
961                 data->dev = dev;
962                 list_add_tail(&data->node, &priv->clients);
963         }
964
965         spin_unlock_irqrestore(&priv->lock, flags);
966
967         if (ret < 0) {
968                 dev_err(dev->archdata.iommu,"%s: Failed to attach IOMMU with pgtable %#lx\n",
969                        __func__, __pa(priv->pgtable));
970         } else if (ret > 0) {
971                 dev_dbg(dev->archdata.iommu,"%s: IOMMU with pgtable 0x%lx already attached\n",
972                         __func__, __pa(priv->pgtable));
973         } else {
974                 dev_dbg(dev->archdata.iommu,"%s: Attached new IOMMU with pgtable 0x%lx\n",
975                         __func__, __pa(priv->pgtable));
976         }
977
978         return ret;
979 }
980
981 static void rockchip_iommu_domain_destroy(struct iommu_domain *domain)
982 {
983         struct rk_iommu_domain *priv = domain->priv;
984         struct iommu_drvdata *data;
985         unsigned long flags;
986         int i;
987
988         WARN_ON(!list_empty(&priv->clients));
989
990         spin_lock_irqsave(&priv->lock, flags);
991
992         list_for_each_entry(data, &priv->clients, node) {
993                 if(cpu_is_rk312x() || cpu_is_rk3036())
994                         rockchip_vcodec_select(data->dbgname);
995                 while (!rockchip_iommu_disable(data->dev))
996                         ; /* until System MMU is actually disabled */
997         }
998         spin_unlock_irqrestore(&priv->lock, flags);
999
1000         for (i = 0; i < NUM_LV1ENTRIES; i++)
1001                 if (lv1ent_page(priv->pgtable + i))
1002                         kmem_cache_free(lv2table_kmem_cache,
1003                                         __va(lv2table_base(priv->pgtable + i)));
1004
1005         free_pages((unsigned long)priv->pgtable, 0);
1006         free_pages((unsigned long)priv->lv2entcnt, 0);
1007         kfree(domain->priv);
1008         domain->priv = NULL;
1009 }
1010
1011 static int rockchip_iommu_domain_init(struct iommu_domain *domain)
1012 {
1013         struct rk_iommu_domain *priv;
1014
1015         priv = kzalloc(sizeof(*priv), GFP_KERNEL);
1016         if (!priv)
1017                 return -ENOMEM;
1018
1019 /*rk32xx iommu use 2 level pagetable,
1020    level1 and leve2 both have 1024 entries,each entry  occupy 4 bytes,
1021    so alloc a page size for each page table
1022 */
1023         priv->pgtable = (unsigned long *)__get_free_pages(GFP_KERNEL |
1024                                                           __GFP_ZERO, 0);
1025         if (!priv->pgtable)
1026                 goto err_pgtable;
1027
1028         priv->lv2entcnt = (short *)__get_free_pages(GFP_KERNEL |
1029                                                     __GFP_ZERO, 0);
1030         if (!priv->lv2entcnt)
1031                 goto err_counter;
1032
1033         pgtable_flush(priv->pgtable, priv->pgtable + NUM_LV1ENTRIES);
1034
1035         spin_lock_init(&priv->lock);
1036         spin_lock_init(&priv->pgtablelock);
1037         INIT_LIST_HEAD(&priv->clients);
1038
1039         domain->priv = priv;
1040         return 0;
1041
1042 err_counter:
1043         free_pages((unsigned long)priv->pgtable, 0);
1044 err_pgtable:
1045         kfree(priv);
1046         return -ENOMEM;
1047 }
1048
1049 static struct iommu_ops rk_iommu_ops = {
1050         .domain_init = &rockchip_iommu_domain_init,
1051         .domain_destroy = &rockchip_iommu_domain_destroy,
1052         .attach_dev = &rockchip_iommu_attach_device,
1053         .detach_dev = &rockchip_iommu_detach_device,
1054         .map = &rockchip_iommu_map,
1055         .unmap = &rockchip_iommu_unmap,
1056         .iova_to_phys = &rockchip_iommu_iova_to_phys,
1057         .pgsize_bitmap = SPAGE_SIZE,
1058 };
1059
1060 static int rockchip_iommu_prepare(void)
1061 {
1062         int ret = 0;
1063         static int registed;
1064
1065         if (registed)
1066                 return 0;
1067
1068         lv2table_kmem_cache = kmem_cache_create("rk-iommu-lv2table",
1069                                                 LV2TABLE_SIZE,
1070                                                 LV2TABLE_SIZE,
1071                                                 0, NULL);
1072         if (!lv2table_kmem_cache) {
1073                 pr_info("%s: failed to create kmem cache\n", __func__);
1074                 return -ENOMEM;
1075         }
1076         ret = bus_set_iommu(&platform_bus_type, &rk_iommu_ops);
1077         if (!ret)
1078                 registed = 1;
1079         else
1080                 pr_info("%s:failed to set iommu to bus\r\n", __func__);
1081         return ret;
1082 }
1083
1084 static int  rockchip_get_iommu_resource_num(struct platform_device *pdev,
1085                                              unsigned int type)
1086 {
1087         int num = 0;
1088         int i;
1089 #if 0
1090         pr_info("dev num_resources %d type = 0x%08x\n",pdev->num_resources, type);
1091 #endif
1092         for (i = 0; i < pdev->num_resources; i++) {
1093                 struct resource *r = &pdev->resource[i];
1094 #if 0
1095 dev_info(&pdev->dev, "r[%d] start %08x end %08x flags %08lx name (%s) resource_type %08lx\n", i, r->start, r->end, r->flags, r->name, resource_type(r));
1096 #endif
1097                 if (type == resource_type(r))
1098                         num++;
1099         }
1100
1101         return num;
1102 }
1103
1104 static struct kobject *dump_mmu_object;
1105
1106 static int dump_mmu_pagetbl(struct device *dev, struct device_attribute *attr,
1107                             const char *buf, u32 count)
1108 {
1109         u32 fault_address;
1110         u32 iommu_dte;
1111         u32 mmu_base;
1112         void __iomem *base;
1113         u32 ret;
1114
1115         ret = kstrtouint(buf, 0, &mmu_base);
1116         if (ret)
1117                 dev_dbg(dev,"%s is not in hexdecimal form.\n", buf);
1118         base = ioremap(mmu_base, 0x100);
1119         if (base != rk312x_vop_mmu_base) {
1120                 iommu_dte = __raw_readl(base + IOMMU_REGISTER_DTE_ADDR);
1121                 fault_address = __raw_readl(base + IOMMU_REGISTER_PAGE_FAULT_ADDR);
1122                 dump_pagetbl(fault_address, iommu_dte);
1123         } else {
1124                 dev_dbg(dev,"vop mmu not support\n");
1125         }
1126         return count;
1127 }
1128
1129 static DEVICE_ATTR(dump_mmu_pgtable, 0644, NULL, dump_mmu_pagetbl);
1130
1131 void dump_iommu_sysfs_init(void)
1132 {
1133         u32 ret;
1134
1135         dump_mmu_object = kobject_create_and_add("rk_iommu", NULL);
1136         if (dump_mmu_object == NULL)
1137                 return;
1138         ret = sysfs_create_file(dump_mmu_object,
1139                                 &dev_attr_dump_mmu_pgtable.attr);
1140 }
1141
1142 static int rockchip_iommu_probe(struct platform_device *pdev)
1143 {
1144         int i, ret;
1145         struct device *dev;
1146         struct iommu_drvdata *data;
1147         
1148         dev = &pdev->dev;
1149         
1150 #if 0
1151 struct resource *res = pdev->resource;
1152
1153 for (i = 0; i < pdev->num_resources; i++, res++) {
1154         pr_info("r[%d] start %08x end %08x flags %08lx name (%s) resource_type %08lx\n", i, res->start, res->end, res->flags, res->name,   resource_type(res));
1155 }
1156 #endif
1157         ret = rockchip_iommu_prepare();
1158         if (ret) {
1159                 dev_err(dev,"%s,failed\r\n", __func__);
1160                 goto err_alloc;
1161         }
1162
1163         data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
1164         if (!data) {
1165                 dev_dbg(dev, "Not enough memory\n");
1166                 ret = -ENOMEM;
1167                 goto err_alloc;
1168         }
1169         dev_set_drvdata(dev, data);
1170 /*
1171         ret = dev_set_drvdata(dev, data);
1172         if (ret)
1173         {
1174                 dev_dbg(dev, "Unabled to initialize driver data\n");
1175                 goto err_init;
1176         }
1177 */
1178         if (pdev->dev.of_node) {
1179                 of_property_read_string(pdev->dev.of_node,
1180                                         "dbgname", &(data->dbgname));
1181         } else {
1182                 dev_dbg(dev,
1183                                 "dbgname not assigned in device tree or device node not exist\r\n");
1184         }
1185
1186         dev_info(dev,"(%s) Enter\n", data->dbgname);
1187         
1188
1189         data->num_res_mem = rockchip_get_iommu_resource_num(pdev,
1190                                 IORESOURCE_MEM);
1191         if (0 == data->num_res_mem) {
1192                 dev_err(dev,"can't find iommu memory resource \r\n");
1193                 goto err_init;
1194         }
1195         dev_dbg(dev,"data->num_res_mem=%d\n", data->num_res_mem);
1196         data->num_res_irq = rockchip_get_iommu_resource_num(pdev,
1197                                 IORESOURCE_IRQ);
1198         if (0 == data->num_res_irq) {
1199                 dev_err(dev,"can't find iommu irq resource \r\n");
1200                 goto err_init;
1201         }
1202         dev_dbg(dev,"data->num_res_irq=%d\n", data->num_res_irq);
1203
1204         data->res_bases = devm_kmalloc_array(dev, data->num_res_mem,
1205                                 sizeof(*data->res_bases), GFP_KERNEL);
1206         if (data->res_bases == NULL) {
1207                 dev_err(dev, "Not enough memory\n");
1208                 ret = -ENOMEM;
1209                 goto err_init;
1210         }
1211
1212         for (i = 0; i < data->num_res_mem; i++) {
1213                 struct resource *res;
1214
1215                 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
1216                 if (!res) {
1217                         dev_err(dev,"Unable to find IOMEM region\n");
1218                         ret = -ENOENT;
1219                         goto err_res;
1220                 }
1221                 data->res_bases[i] = ioremap(res->start, resource_size(res));
1222                 dev_dbg(dev,"res->start = 0x%08x  ioremap to  data->res_bases[%d] = 0x%08x\n",
1223                         res->start, i, (unsigned int)data->res_bases[i]);
1224                 if (!data->res_bases[i]) {
1225                         pr_err("Unable to map IOMEM @ PA:%#x\n", res->start);
1226                         ret = -ENOENT;
1227                         goto err_res;
1228                 }
1229
1230                 if (cpu_is_rk312x() || cpu_is_rk3036()) {
1231                         rockchip_vcodec_select(data->dbgname);
1232                         if (strstr(data->dbgname, "vop") && cpu_is_rk312x()) {
1233                                 rk312x_vop_mmu_base = data->res_bases[0];
1234                                 dev_dbg(dev,"rk312x_vop_mmu_base = 0x%08x\n",(unsigned int)rk312x_vop_mmu_base);
1235                         }
1236                 }
1237                 if (!strstr(data->dbgname, "isp")) {
1238                         if (!iommu_reset(data->res_bases[i], data->dbgname)) {
1239                                 ret = -ENOENT;
1240                                 goto err_res;
1241                         }
1242                 }
1243         }
1244
1245         for (i = 0; i < data->num_res_irq; i++) {
1246                 ret = platform_get_irq(pdev, i);
1247                 if (ret <= 0) {
1248                         dev_err(dev,"Unable to find IRQ resource\n");
1249                         goto err_irq;
1250                 }
1251                 ret = devm_request_irq(dev, ret, rockchip_iommu_irq,
1252                                   IRQF_SHARED, dev_name(dev), data);
1253                 if (ret) {
1254                         dev_err(dev,"Unabled to register interrupt handler\n");
1255                         goto err_irq;
1256                 }
1257         }
1258         ret = rockchip_init_iovmm(dev, &data->vmm);
1259         if (ret)
1260                 goto err_irq;
1261
1262         data->iommu = dev;
1263         rwlock_init(&data->lock);
1264         INIT_LIST_HEAD(&data->node);
1265
1266         set_fault_handler(data, &default_fault_handler);
1267
1268         dev_info(dev,"(%s) Initialized\n", data->dbgname);
1269         return 0;
1270
1271 err_irq:
1272 err_res:
1273         while (data->num_res_mem-- > 0)
1274                 devm_iounmap(dev,data->res_bases[data->num_res_mem]);
1275 err_init:
1276 err_alloc:
1277         dev_err(dev, "Failed to initialize\n");
1278         return ret;
1279 }
1280
1281 #ifdef CONFIG_OF
1282 static const struct of_device_id iommu_dt_ids[] = {
1283         { .compatible = IEP_IOMMU_COMPATIBLE_NAME},
1284         { .compatible = VIP_IOMMU_COMPATIBLE_NAME},
1285         { .compatible = VOPB_IOMMU_COMPATIBLE_NAME},
1286         { .compatible = VOPL_IOMMU_COMPATIBLE_NAME},
1287         { .compatible = HEVC_IOMMU_COMPATIBLE_NAME},
1288         { .compatible = VPU_IOMMU_COMPATIBLE_NAME},
1289         { .compatible = ISP_IOMMU_COMPATIBLE_NAME},
1290         { .compatible = VOP_IOMMU_COMPATIBLE_NAME},
1291         { /* end */ }
1292 };
1293
1294 MODULE_DEVICE_TABLE(of, iommu_dt_ids);
1295 #endif
1296
1297 static struct platform_driver rk_iommu_driver = {
1298         .probe = rockchip_iommu_probe,
1299         .remove = NULL,
1300         .driver = {
1301                    .name = "rk_iommu",
1302                    .owner = THIS_MODULE,
1303                    .of_match_table = of_match_ptr(iommu_dt_ids),
1304         },
1305 };
1306
1307 static int __init rockchip_iommu_init_driver(void)
1308 {
1309         dump_iommu_sysfs_init();
1310
1311         return platform_driver_register(&rk_iommu_driver);
1312 }
1313
1314 core_initcall(rockchip_iommu_init_driver);