2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License version 2 as
4 * published by the Free Software Foundation.
7 #include <linux/compiler.h>
8 #include <linux/delay.h>
9 #include <linux/device.h>
10 #include <linux/dma-iommu.h>
11 #include <linux/errno.h>
12 #include <linux/interrupt.h>
14 #include <linux/iommu.h>
15 #include <linux/jiffies.h>
16 #include <linux/list.h>
18 #include <linux/module.h>
20 #include <linux/of_platform.h>
21 #include <linux/platform_device.h>
22 #include <linux/slab.h>
23 #include <linux/spinlock.h>
25 /** MMU register offsets */
26 #define RK_MMU_DTE_ADDR 0x00 /* Directory table address */
27 #define RK_MMU_STATUS 0x04
28 #define RK_MMU_COMMAND 0x08
29 #define RK_MMU_PAGE_FAULT_ADDR 0x0C /* IOVA of last page fault */
30 #define RK_MMU_ZAP_ONE_LINE 0x10 /* Shootdown one IOTLB entry */
31 #define RK_MMU_INT_RAWSTAT 0x14 /* IRQ status ignoring mask */
32 #define RK_MMU_INT_CLEAR 0x18 /* Acknowledge and re-arm irq */
33 #define RK_MMU_INT_MASK 0x1C /* IRQ enable */
34 #define RK_MMU_INT_STATUS 0x20 /* IRQ status after masking */
35 #define RK_MMU_AUTO_GATING 0x24
37 #define DTE_ADDR_DUMMY 0xCAFEBABE
38 #define FORCE_RESET_TIMEOUT 100 /* ms */
40 /* RK_MMU_STATUS fields */
41 #define RK_MMU_STATUS_PAGING_ENABLED BIT(0)
42 #define RK_MMU_STATUS_PAGE_FAULT_ACTIVE BIT(1)
43 #define RK_MMU_STATUS_STALL_ACTIVE BIT(2)
44 #define RK_MMU_STATUS_IDLE BIT(3)
45 #define RK_MMU_STATUS_REPLAY_BUFFER_EMPTY BIT(4)
46 #define RK_MMU_STATUS_PAGE_FAULT_IS_WRITE BIT(5)
47 #define RK_MMU_STATUS_STALL_NOT_ACTIVE BIT(31)
49 /* RK_MMU_COMMAND command values */
50 #define RK_MMU_CMD_ENABLE_PAGING 0 /* Enable memory translation */
51 #define RK_MMU_CMD_DISABLE_PAGING 1 /* Disable memory translation */
52 #define RK_MMU_CMD_ENABLE_STALL 2 /* Stall paging to allow other cmds */
53 #define RK_MMU_CMD_DISABLE_STALL 3 /* Stop stall re-enables paging */
54 #define RK_MMU_CMD_ZAP_CACHE 4 /* Shoot down entire IOTLB */
55 #define RK_MMU_CMD_PAGE_FAULT_DONE 5 /* Clear page fault */
56 #define RK_MMU_CMD_FORCE_RESET 6 /* Reset all registers */
58 /* RK_MMU_INT_* register fields */
59 #define RK_MMU_IRQ_PAGE_FAULT 0x01 /* page fault */
60 #define RK_MMU_IRQ_BUS_ERROR 0x02 /* bus read error */
61 #define RK_MMU_IRQ_MASK (RK_MMU_IRQ_PAGE_FAULT | RK_MMU_IRQ_BUS_ERROR)
63 #define NUM_DT_ENTRIES 1024
64 #define NUM_PT_ENTRIES 1024
66 #define SPAGE_ORDER 12
67 #define SPAGE_SIZE (1 << SPAGE_ORDER)
70 * Support mapping any size that fits in one page table:
73 #define RK_IOMMU_PGSIZE_BITMAP 0x007ff000
75 #define IOMMU_REG_POLL_COUNT_FAST 1000
77 struct rk_iommu_domain {
78 struct list_head iommus;
79 struct platform_device *pdev;
80 u32 *dt; /* page directory table */
82 spinlock_t iommus_lock; /* lock for iommus list */
83 spinlock_t dt_lock; /* lock for modifying page directory table */
85 struct iommu_domain domain;
93 struct list_head node; /* entry in rk_iommu_domain.iommus */
94 struct iommu_domain *domain; /* domain to which iommu is attached */
97 static inline void rk_table_flush(struct rk_iommu_domain *dom, dma_addr_t dma,
100 size_t size = count * sizeof(u32); /* count of u32 entry */
102 dma_sync_single_for_device(&dom->pdev->dev, dma, size, DMA_TO_DEVICE);
105 static struct rk_iommu_domain *to_rk_domain(struct iommu_domain *dom)
107 return container_of(dom, struct rk_iommu_domain, domain);
111 * Inspired by _wait_for in intel_drv.h
112 * This is NOT safe for use in interrupt context.
114 * Note that it's important that we check the condition again after having
115 * timed out, since the timeout could be due to preemption or similar and
116 * we've never had a chance to check the condition before the timeout.
118 #define rk_wait_for(COND, MS) ({ \
119 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \
122 if (time_after(jiffies, timeout__)) { \
123 ret__ = (COND) ? 0 : -ETIMEDOUT; \
126 usleep_range(50, 100); \
132 * The Rockchip rk3288 iommu uses a 2-level page table.
133 * The first level is the "Directory Table" (DT).
134 * The DT consists of 1024 4-byte Directory Table Entries (DTEs), each pointing
136 * The second level is the 1024 Page Tables (PT).
137 * Each PT consists of 1024 4-byte Page Table Entries (PTEs), each pointing to
138 * a 4 KB page of physical memory.
140 * The DT and each PT fits in a single 4 KB page (4-bytes * 1024 entries).
141 * Each iommu device has a MMU_DTE_ADDR register that contains the physical
142 * address of the start of the DT page.
144 * The structure of the page table is as follows:
147 * MMU_DTE_ADDR -> +-----+
153 * | | | PTE | -> +-----+
154 * +-----+ +-----+ | |
164 * Each DTE has a PT address and a valid bit:
165 * +---------------------+-----------+-+
166 * | PT address | Reserved |V|
167 * +---------------------+-----------+-+
168 * 31:12 - PT address (PTs always starts on a 4 KB boundary)
170 * 0 - 1 if PT @ PT address is valid
172 #define RK_DTE_PT_ADDRESS_MASK 0xfffff000
173 #define RK_DTE_PT_VALID BIT(0)
175 static inline phys_addr_t rk_dte_pt_address(u32 dte)
177 return (phys_addr_t)dte & RK_DTE_PT_ADDRESS_MASK;
180 static inline bool rk_dte_is_pt_valid(u32 dte)
182 return dte & RK_DTE_PT_VALID;
185 static inline u32 rk_mk_dte(dma_addr_t pt_dma)
187 return (pt_dma & RK_DTE_PT_ADDRESS_MASK) | RK_DTE_PT_VALID;
191 * Each PTE has a Page address, some flags and a valid bit:
192 * +---------------------+---+-------+-+
193 * | Page address |Rsv| Flags |V|
194 * +---------------------+---+-------+-+
195 * 31:12 - Page address (Pages always start on a 4 KB boundary)
198 * 8 - Read allocate - allocate cache space on read misses
199 * 7 - Read cache - enable cache & prefetch of data
200 * 6 - Write buffer - enable delaying writes on their way to memory
201 * 5 - Write allocate - allocate cache space on write misses
202 * 4 - Write cache - different writes can be merged together
203 * 3 - Override cache attributes
204 * if 1, bits 4-8 control cache attributes
205 * if 0, the system bus defaults are used
208 * 0 - 1 if Page @ Page address is valid
210 #define RK_PTE_PAGE_ADDRESS_MASK 0xfffff000
211 #define RK_PTE_PAGE_FLAGS_MASK 0x000001fe
212 #define RK_PTE_PAGE_WRITABLE BIT(2)
213 #define RK_PTE_PAGE_READABLE BIT(1)
214 #define RK_PTE_PAGE_VALID BIT(0)
216 static inline phys_addr_t rk_pte_page_address(u32 pte)
218 return (phys_addr_t)pte & RK_PTE_PAGE_ADDRESS_MASK;
221 static inline bool rk_pte_is_page_valid(u32 pte)
223 return pte & RK_PTE_PAGE_VALID;
226 /* TODO: set cache flags per prot IOMMU_CACHE */
227 static u32 rk_mk_pte(phys_addr_t page, int prot)
230 flags |= (prot & IOMMU_READ) ? RK_PTE_PAGE_READABLE : 0;
231 flags |= (prot & IOMMU_WRITE) ? RK_PTE_PAGE_WRITABLE : 0;
232 page &= RK_PTE_PAGE_ADDRESS_MASK;
233 return page | flags | RK_PTE_PAGE_VALID;
236 static u32 rk_mk_pte_invalid(u32 pte)
238 return pte & ~RK_PTE_PAGE_VALID;
242 * rk3288 iova (IOMMU Virtual Address) format
244 * +-----------+-----------+-------------+
245 * | DTE index | PTE index | Page offset |
246 * +-----------+-----------+-------------+
247 * 31:22 - DTE index - index of DTE in DT
248 * 21:12 - PTE index - index of PTE in PT @ DTE.pt_address
249 * 11: 0 - Page offset - offset into page @ PTE.page_address
251 #define RK_IOVA_DTE_MASK 0xffc00000
252 #define RK_IOVA_DTE_SHIFT 22
253 #define RK_IOVA_PTE_MASK 0x003ff000
254 #define RK_IOVA_PTE_SHIFT 12
255 #define RK_IOVA_PAGE_MASK 0x00000fff
256 #define RK_IOVA_PAGE_SHIFT 0
258 static u32 rk_iova_dte_index(dma_addr_t iova)
260 return (u32)(iova & RK_IOVA_DTE_MASK) >> RK_IOVA_DTE_SHIFT;
263 static u32 rk_iova_pte_index(dma_addr_t iova)
265 return (u32)(iova & RK_IOVA_PTE_MASK) >> RK_IOVA_PTE_SHIFT;
268 static u32 rk_iova_page_offset(dma_addr_t iova)
270 return (u32)(iova & RK_IOVA_PAGE_MASK) >> RK_IOVA_PAGE_SHIFT;
273 static u32 rk_iommu_read(void __iomem *base, u32 offset)
275 return readl(base + offset);
278 static void rk_iommu_write(void __iomem *base, u32 offset, u32 value)
280 writel(value, base + offset);
283 static void rk_iommu_command(struct rk_iommu *iommu, u32 command)
287 for (i = 0; i < iommu->num_mmu; i++)
288 writel(command, iommu->bases[i] + RK_MMU_COMMAND);
291 static void rk_iommu_base_command(void __iomem *base, u32 command)
293 writel(command, base + RK_MMU_COMMAND);
295 static void rk_iommu_zap_lines(struct rk_iommu *iommu, dma_addr_t iova_start,
299 dma_addr_t iova_end = iova_start + size;
301 * TODO(djkurtz): Figure out when it is more efficient to shootdown the
302 * entire iotlb rather than iterate over individual iovas.
304 for (i = 0; i < iommu->num_mmu; i++) {
307 for (iova = iova_start; iova < iova_end; iova += SPAGE_SIZE)
308 rk_iommu_write(iommu->bases[i], RK_MMU_ZAP_ONE_LINE, iova);
312 static bool rk_iommu_is_stall_active(struct rk_iommu *iommu)
317 for (i = 0; i < iommu->num_mmu; i++)
318 active &= !!(rk_iommu_read(iommu->bases[i], RK_MMU_STATUS) &
319 RK_MMU_STATUS_STALL_ACTIVE);
324 static bool rk_iommu_is_paging_enabled(struct rk_iommu *iommu)
329 for (i = 0; i < iommu->num_mmu; i++)
330 enable &= !!(rk_iommu_read(iommu->bases[i], RK_MMU_STATUS) &
331 RK_MMU_STATUS_PAGING_ENABLED);
336 static int rk_iommu_enable_stall(struct rk_iommu *iommu)
340 if (rk_iommu_is_stall_active(iommu))
343 /* Stall can only be enabled if paging is enabled */
344 if (!rk_iommu_is_paging_enabled(iommu))
347 rk_iommu_command(iommu, RK_MMU_CMD_ENABLE_STALL);
349 ret = rk_wait_for(rk_iommu_is_stall_active(iommu), 1);
351 for (i = 0; i < iommu->num_mmu; i++)
352 dev_err(iommu->dev, "Enable stall request timed out, status: %#08x\n",
353 rk_iommu_read(iommu->bases[i], RK_MMU_STATUS));
358 static int rk_iommu_disable_stall(struct rk_iommu *iommu)
362 if (!rk_iommu_is_stall_active(iommu))
365 rk_iommu_command(iommu, RK_MMU_CMD_DISABLE_STALL);
367 ret = rk_wait_for(!rk_iommu_is_stall_active(iommu), 1);
369 for (i = 0; i < iommu->num_mmu; i++)
370 dev_err(iommu->dev, "Disable stall request timed out, status: %#08x\n",
371 rk_iommu_read(iommu->bases[i], RK_MMU_STATUS));
376 static int rk_iommu_enable_paging(struct rk_iommu *iommu)
380 if (rk_iommu_is_paging_enabled(iommu))
383 rk_iommu_command(iommu, RK_MMU_CMD_ENABLE_PAGING);
385 ret = rk_wait_for(rk_iommu_is_paging_enabled(iommu), 1);
387 for (i = 0; i < iommu->num_mmu; i++)
388 dev_err(iommu->dev, "Enable paging request timed out, status: %#08x\n",
389 rk_iommu_read(iommu->bases[i], RK_MMU_STATUS));
394 static int rk_iommu_disable_paging(struct rk_iommu *iommu)
398 if (!rk_iommu_is_paging_enabled(iommu))
401 rk_iommu_command(iommu, RK_MMU_CMD_DISABLE_PAGING);
403 ret = rk_wait_for(!rk_iommu_is_paging_enabled(iommu), 1);
405 for (i = 0; i < iommu->num_mmu; i++)
406 dev_err(iommu->dev, "Disable paging request timed out, status: %#08x\n",
407 rk_iommu_read(iommu->bases[i], RK_MMU_STATUS));
412 static int rk_iommu_force_reset(struct rk_iommu *iommu)
418 * Check if register DTE_ADDR is working by writing DTE_ADDR_DUMMY
419 * and verifying that upper 5 nybbles are read back.
421 for (i = 0; i < iommu->num_mmu; i++) {
422 rk_iommu_write(iommu->bases[i], RK_MMU_DTE_ADDR, DTE_ADDR_DUMMY);
424 dte_addr = rk_iommu_read(iommu->bases[i], RK_MMU_DTE_ADDR);
425 if (dte_addr != (DTE_ADDR_DUMMY & RK_DTE_PT_ADDRESS_MASK)) {
426 dev_err(iommu->dev, "Error during raw reset. MMU_DTE_ADDR is not functioning\n");
431 rk_iommu_command(iommu, RK_MMU_CMD_FORCE_RESET);
433 for (i = 0; i < iommu->num_mmu; i++) {
434 ret = rk_wait_for(rk_iommu_read(iommu->bases[i], RK_MMU_DTE_ADDR) == 0x00000000,
435 FORCE_RESET_TIMEOUT);
437 dev_err(iommu->dev, "FORCE_RESET command timed out\n");
445 static void log_iova(struct rk_iommu *iommu, int index, dma_addr_t iova)
447 void __iomem *base = iommu->bases[index];
448 u32 dte_index, pte_index, page_offset;
450 phys_addr_t mmu_dte_addr_phys, dte_addr_phys;
453 phys_addr_t pte_addr_phys = 0;
454 u32 *pte_addr = NULL;
456 phys_addr_t page_addr_phys = 0;
459 dte_index = rk_iova_dte_index(iova);
460 pte_index = rk_iova_pte_index(iova);
461 page_offset = rk_iova_page_offset(iova);
463 mmu_dte_addr = rk_iommu_read(base, RK_MMU_DTE_ADDR);
464 mmu_dte_addr_phys = (phys_addr_t)mmu_dte_addr;
466 dte_addr_phys = mmu_dte_addr_phys + (4 * dte_index);
467 dte_addr = phys_to_virt(dte_addr_phys);
470 if (!rk_dte_is_pt_valid(dte))
473 pte_addr_phys = rk_dte_pt_address(dte) + (pte_index * 4);
474 pte_addr = phys_to_virt(pte_addr_phys);
477 if (!rk_pte_is_page_valid(pte))
480 page_addr_phys = rk_pte_page_address(pte) + page_offset;
481 page_flags = pte & RK_PTE_PAGE_FLAGS_MASK;
484 dev_err(iommu->dev, "iova = %pad: dte_index: %#03x pte_index: %#03x page_offset: %#03x\n",
485 &iova, dte_index, pte_index, page_offset);
486 dev_err(iommu->dev, "mmu_dte_addr: %pa dte@%pa: %#08x valid: %u pte@%pa: %#08x valid: %u page@%pa flags: %#03x\n",
487 &mmu_dte_addr_phys, &dte_addr_phys, dte,
488 rk_dte_is_pt_valid(dte), &pte_addr_phys, pte,
489 rk_pte_is_page_valid(pte), &page_addr_phys, page_flags);
492 static irqreturn_t rk_iommu_irq(int irq, void *dev_id)
494 struct rk_iommu *iommu = dev_id;
498 irqreturn_t ret = IRQ_NONE;
501 for (i = 0; i < iommu->num_mmu; i++) {
502 int_status = rk_iommu_read(iommu->bases[i], RK_MMU_INT_STATUS);
507 iova = rk_iommu_read(iommu->bases[i], RK_MMU_PAGE_FAULT_ADDR);
509 if (int_status & RK_MMU_IRQ_PAGE_FAULT) {
512 status = rk_iommu_read(iommu->bases[i], RK_MMU_STATUS);
513 flags = (status & RK_MMU_STATUS_PAGE_FAULT_IS_WRITE) ?
514 IOMMU_FAULT_WRITE : IOMMU_FAULT_READ;
516 dev_err(iommu->dev, "Page fault at %pad of type %s\n",
518 (flags == IOMMU_FAULT_WRITE) ? "write" : "read");
520 log_iova(iommu, i, iova);
523 * Report page fault to any installed handlers.
524 * Ignore the return code, though, since we always zap cache
525 * and clear the page fault anyway.
528 report_iommu_fault(iommu->domain, iommu->dev, iova,
531 dev_err(iommu->dev, "Page fault while iommu not attached to domain?\n");
533 rk_iommu_base_command(iommu->bases[i], RK_MMU_CMD_ZAP_CACHE);
534 rk_iommu_base_command(iommu->bases[i], RK_MMU_CMD_PAGE_FAULT_DONE);
537 if (int_status & RK_MMU_IRQ_BUS_ERROR)
538 dev_err(iommu->dev, "BUS_ERROR occurred at %pad\n", &iova);
540 if (int_status & ~RK_MMU_IRQ_MASK)
541 dev_err(iommu->dev, "unexpected int_status: %#08x\n",
544 rk_iommu_write(iommu->bases[i], RK_MMU_INT_CLEAR, int_status);
550 static phys_addr_t rk_iommu_iova_to_phys(struct iommu_domain *domain,
553 struct rk_iommu_domain *rk_domain = to_rk_domain(domain);
555 phys_addr_t pt_phys, phys = 0;
559 spin_lock_irqsave(&rk_domain->dt_lock, flags);
561 dte = rk_domain->dt[rk_iova_dte_index(iova)];
562 if (!rk_dte_is_pt_valid(dte))
565 pt_phys = rk_dte_pt_address(dte);
566 page_table = (u32 *)phys_to_virt(pt_phys);
567 pte = page_table[rk_iova_pte_index(iova)];
568 if (!rk_pte_is_page_valid(pte))
571 phys = rk_pte_page_address(pte) + rk_iova_page_offset(iova);
573 spin_unlock_irqrestore(&rk_domain->dt_lock, flags);
578 static void rk_iommu_zap_iova(struct rk_iommu_domain *rk_domain,
579 dma_addr_t iova, size_t size)
581 struct list_head *pos;
584 /* shootdown these iova from all iommus using this domain */
585 spin_lock_irqsave(&rk_domain->iommus_lock, flags);
586 list_for_each(pos, &rk_domain->iommus) {
587 struct rk_iommu *iommu;
588 iommu = list_entry(pos, struct rk_iommu, node);
589 rk_iommu_zap_lines(iommu, iova, size);
591 spin_unlock_irqrestore(&rk_domain->iommus_lock, flags);
594 static void rk_iommu_zap_iova_first_last(struct rk_iommu_domain *rk_domain,
595 dma_addr_t iova, size_t size)
597 rk_iommu_zap_iova(rk_domain, iova, SPAGE_SIZE);
598 if (size > SPAGE_SIZE)
599 rk_iommu_zap_iova(rk_domain, iova + size - SPAGE_SIZE,
603 static u32 *rk_dte_get_page_table(struct rk_iommu_domain *rk_domain,
606 struct device *dev = &rk_domain->pdev->dev;
607 u32 *page_table, *dte_addr;
612 assert_spin_locked(&rk_domain->dt_lock);
614 dte_index = rk_iova_dte_index(iova);
615 dte_addr = &rk_domain->dt[dte_index];
617 if (rk_dte_is_pt_valid(dte))
620 page_table = (u32 *)get_zeroed_page(GFP_ATOMIC | GFP_DMA32);
622 return ERR_PTR(-ENOMEM);
624 pt_dma = dma_map_single(dev, page_table, SPAGE_SIZE, DMA_TO_DEVICE);
625 if (dma_mapping_error(dev, pt_dma)) {
626 dev_err(dev, "DMA mapping error while allocating page table\n");
627 free_page((unsigned long)page_table);
628 return ERR_PTR(-ENOMEM);
631 dte = rk_mk_dte(pt_dma);
634 rk_table_flush(rk_domain, pt_dma, NUM_PT_ENTRIES);
635 rk_table_flush(rk_domain,
636 rk_domain->dt_dma + dte_index * sizeof(u32), 1);
638 pt_phys = rk_dte_pt_address(dte);
639 return (u32 *)phys_to_virt(pt_phys);
642 static size_t rk_iommu_unmap_iova(struct rk_iommu_domain *rk_domain,
643 u32 *pte_addr, dma_addr_t pte_dma,
646 unsigned int pte_count;
647 unsigned int pte_total = size / SPAGE_SIZE;
649 assert_spin_locked(&rk_domain->dt_lock);
651 for (pte_count = 0; pte_count < pte_total; pte_count++) {
652 u32 pte = pte_addr[pte_count];
653 if (!rk_pte_is_page_valid(pte))
656 pte_addr[pte_count] = rk_mk_pte_invalid(pte);
659 rk_table_flush(rk_domain, pte_dma, pte_count);
661 return pte_count * SPAGE_SIZE;
664 static int rk_iommu_map_iova(struct rk_iommu_domain *rk_domain, u32 *pte_addr,
665 dma_addr_t pte_dma, dma_addr_t iova,
666 phys_addr_t paddr, size_t size, int prot)
668 unsigned int pte_count;
669 unsigned int pte_total = size / SPAGE_SIZE;
670 phys_addr_t page_phys;
672 assert_spin_locked(&rk_domain->dt_lock);
674 for (pte_count = 0; pte_count < pte_total; pte_count++) {
675 u32 pte = pte_addr[pte_count];
677 if (rk_pte_is_page_valid(pte))
680 pte_addr[pte_count] = rk_mk_pte(paddr, prot);
685 rk_table_flush(rk_domain, pte_dma, pte_total);
688 * Zap the first and last iova to evict from iotlb any previously
689 * mapped cachelines holding stale values for its dte and pte.
690 * We only zap the first and last iova, since only they could have
691 * dte or pte shared with an existing mapping.
693 rk_iommu_zap_iova_first_last(rk_domain, iova, size);
697 /* Unmap the range of iovas that we just mapped */
698 rk_iommu_unmap_iova(rk_domain, pte_addr, pte_dma,
699 pte_count * SPAGE_SIZE);
701 iova += pte_count * SPAGE_SIZE;
702 page_phys = rk_pte_page_address(pte_addr[pte_count]);
703 pr_err("iova: %pad already mapped to %pa cannot remap to phys: %pa prot: %#x\n",
704 &iova, &page_phys, &paddr, prot);
709 static int rk_iommu_map(struct iommu_domain *domain, unsigned long _iova,
710 phys_addr_t paddr, size_t size, int prot)
712 struct rk_iommu_domain *rk_domain = to_rk_domain(domain);
714 dma_addr_t pte_dma, iova = (dma_addr_t)_iova;
715 u32 *page_table, *pte_addr;
716 u32 dte_index, pte_index;
719 spin_lock_irqsave(&rk_domain->dt_lock, flags);
722 * pgsize_bitmap specifies iova sizes that fit in one page table
723 * (1024 4-KiB pages = 4 MiB).
724 * So, size will always be 4096 <= size <= 4194304.
725 * Since iommu_map() guarantees that both iova and size will be
726 * aligned, we will always only be mapping from a single dte here.
728 page_table = rk_dte_get_page_table(rk_domain, iova);
729 if (IS_ERR(page_table)) {
730 spin_unlock_irqrestore(&rk_domain->dt_lock, flags);
731 return PTR_ERR(page_table);
734 dte_index = rk_domain->dt[rk_iova_dte_index(iova)];
735 pte_index = rk_iova_pte_index(iova);
736 pte_addr = &page_table[pte_index];
737 pte_dma = rk_dte_pt_address(dte_index) + pte_index * sizeof(u32);
738 ret = rk_iommu_map_iova(rk_domain, pte_addr, pte_dma, iova,
741 spin_unlock_irqrestore(&rk_domain->dt_lock, flags);
746 static size_t rk_iommu_unmap(struct iommu_domain *domain, unsigned long _iova,
749 struct rk_iommu_domain *rk_domain = to_rk_domain(domain);
751 dma_addr_t pte_dma, iova = (dma_addr_t)_iova;
757 spin_lock_irqsave(&rk_domain->dt_lock, flags);
760 * pgsize_bitmap specifies iova sizes that fit in one page table
761 * (1024 4-KiB pages = 4 MiB).
762 * So, size will always be 4096 <= size <= 4194304.
763 * Since iommu_unmap() guarantees that both iova and size will be
764 * aligned, we will always only be unmapping from a single dte here.
766 dte = rk_domain->dt[rk_iova_dte_index(iova)];
767 /* Just return 0 if iova is unmapped */
768 if (!rk_dte_is_pt_valid(dte)) {
769 spin_unlock_irqrestore(&rk_domain->dt_lock, flags);
773 pt_phys = rk_dte_pt_address(dte);
774 pte_addr = (u32 *)phys_to_virt(pt_phys) + rk_iova_pte_index(iova);
775 pte_dma = pt_phys + rk_iova_pte_index(iova) * sizeof(u32);
776 unmap_size = rk_iommu_unmap_iova(rk_domain, pte_addr, pte_dma, size);
778 spin_unlock_irqrestore(&rk_domain->dt_lock, flags);
780 /* Shootdown iotlb entries for iova range that was just unmapped */
781 rk_iommu_zap_iova(rk_domain, iova, unmap_size);
786 static struct rk_iommu *rk_iommu_from_dev(struct device *dev)
788 struct iommu_group *group;
789 struct device *iommu_dev;
790 struct rk_iommu *rk_iommu;
792 group = iommu_group_get(dev);
795 iommu_dev = iommu_group_get_iommudata(group);
797 dev_info(dev, "Possibly a virtual device\n");
801 rk_iommu = dev_get_drvdata(iommu_dev);
802 iommu_group_put(group);
807 static int rk_iommu_attach_device(struct iommu_domain *domain,
810 struct rk_iommu *iommu;
811 struct rk_iommu_domain *rk_domain = to_rk_domain(domain);
816 * Allow 'virtual devices' (e.g., drm) to attach to domain.
817 * Such a device does not belong to an iommu group.
819 iommu = rk_iommu_from_dev(dev);
823 ret = rk_iommu_enable_stall(iommu);
827 ret = rk_iommu_force_reset(iommu);
831 iommu->domain = domain;
833 ret = devm_request_irq(iommu->dev, iommu->irq, rk_iommu_irq,
834 IRQF_SHARED, dev_name(dev), iommu);
838 for (i = 0; i < iommu->num_mmu; i++) {
839 rk_iommu_write(iommu->bases[i], RK_MMU_DTE_ADDR,
841 rk_iommu_base_command(iommu->bases[i], RK_MMU_CMD_ZAP_CACHE);
842 rk_iommu_write(iommu->bases[i], RK_MMU_INT_MASK, RK_MMU_IRQ_MASK);
845 ret = rk_iommu_enable_paging(iommu);
849 spin_lock_irqsave(&rk_domain->iommus_lock, flags);
850 list_add_tail(&iommu->node, &rk_domain->iommus);
851 spin_unlock_irqrestore(&rk_domain->iommus_lock, flags);
853 dev_dbg(dev, "Attached to iommu domain\n");
855 rk_iommu_disable_stall(iommu);
860 static void rk_iommu_detach_device(struct iommu_domain *domain,
863 struct rk_iommu *iommu;
864 struct rk_iommu_domain *rk_domain = to_rk_domain(domain);
868 /* Allow 'virtual devices' (eg drm) to detach from domain */
869 iommu = rk_iommu_from_dev(dev);
873 spin_lock_irqsave(&rk_domain->iommus_lock, flags);
874 list_del_init(&iommu->node);
875 spin_unlock_irqrestore(&rk_domain->iommus_lock, flags);
877 /* Ignore error while disabling, just keep going */
878 rk_iommu_enable_stall(iommu);
879 rk_iommu_disable_paging(iommu);
880 for (i = 0; i < iommu->num_mmu; i++) {
881 rk_iommu_write(iommu->bases[i], RK_MMU_INT_MASK, 0);
882 rk_iommu_write(iommu->bases[i], RK_MMU_DTE_ADDR, 0);
884 rk_iommu_disable_stall(iommu);
886 devm_free_irq(iommu->dev, iommu->irq, iommu);
888 iommu->domain = NULL;
890 dev_dbg(dev, "Detached from iommu domain\n");
893 static struct iommu_domain *rk_iommu_domain_alloc(unsigned type)
895 struct rk_iommu_domain *rk_domain;
896 struct platform_device *pdev;
897 struct device *iommu_dev;
899 if (type != IOMMU_DOMAIN_UNMANAGED && type != IOMMU_DOMAIN_DMA)
902 /* Register a pdev per domain, so DMA API can base on this *dev
903 * even some virtual master doesn't have an iommu slave
905 pdev = platform_device_register_simple("rk_iommu_domain",
906 PLATFORM_DEVID_AUTO, NULL, 0);
910 rk_domain = devm_kzalloc(&pdev->dev, sizeof(*rk_domain), GFP_KERNEL);
914 rk_domain->pdev = pdev;
916 if (type == IOMMU_DOMAIN_DMA &&
917 iommu_get_dma_cookie(&rk_domain->domain))
921 * rk32xx iommus use a 2 level pagetable.
922 * Each level1 (dt) and level2 (pt) table has 1024 4-byte entries.
923 * Allocate one 4 KiB page for each table.
925 rk_domain->dt = (u32 *)get_zeroed_page(GFP_KERNEL | GFP_DMA32);
929 iommu_dev = &pdev->dev;
930 rk_domain->dt_dma = dma_map_single(iommu_dev, rk_domain->dt,
931 SPAGE_SIZE, DMA_TO_DEVICE);
932 if (dma_mapping_error(iommu_dev, rk_domain->dt_dma)) {
933 dev_err(iommu_dev, "DMA map error for DT\n");
937 rk_table_flush(rk_domain, rk_domain->dt_dma, NUM_DT_ENTRIES);
939 spin_lock_init(&rk_domain->iommus_lock);
940 spin_lock_init(&rk_domain->dt_lock);
941 INIT_LIST_HEAD(&rk_domain->iommus);
943 rk_domain->domain.geometry.aperture_start = 0;
944 rk_domain->domain.geometry.aperture_end = DMA_BIT_MASK(32);
945 rk_domain->domain.geometry.force_aperture = true;
947 return &rk_domain->domain;
950 free_page((unsigned long)rk_domain->dt);
952 if (type == IOMMU_DOMAIN_DMA)
953 iommu_put_dma_cookie(&rk_domain->domain);
955 platform_device_unregister(pdev);
960 static void rk_iommu_domain_free(struct iommu_domain *domain)
962 struct rk_iommu_domain *rk_domain = to_rk_domain(domain);
965 WARN_ON(!list_empty(&rk_domain->iommus));
967 for (i = 0; i < NUM_DT_ENTRIES; i++) {
968 u32 dte = rk_domain->dt[i];
969 if (rk_dte_is_pt_valid(dte)) {
970 phys_addr_t pt_phys = rk_dte_pt_address(dte);
971 u32 *page_table = phys_to_virt(pt_phys);
972 dma_unmap_single(&rk_domain->pdev->dev, pt_phys,
973 SPAGE_SIZE, DMA_TO_DEVICE);
974 free_page((unsigned long)page_table);
978 dma_unmap_single(&rk_domain->pdev->dev, rk_domain->dt_dma,
979 SPAGE_SIZE, DMA_TO_DEVICE);
980 free_page((unsigned long)rk_domain->dt);
982 if (domain->type == IOMMU_DOMAIN_DMA)
983 iommu_put_dma_cookie(&rk_domain->domain);
985 platform_device_unregister(rk_domain->pdev);
988 static bool rk_iommu_is_dev_iommu_master(struct device *dev)
990 struct device_node *np = dev->of_node;
994 * An iommu master has an iommus property containing a list of phandles
995 * to iommu nodes, each with an #iommu-cells property with value 0.
997 ret = of_count_phandle_with_args(np, "iommus", "#iommu-cells");
1001 static int rk_iommu_group_set_iommudata(struct iommu_group *group,
1004 struct device_node *np = dev->of_node;
1005 struct platform_device *pd;
1007 struct of_phandle_args args;
1010 * An iommu master has an iommus property containing a list of phandles
1011 * to iommu nodes, each with an #iommu-cells property with value 0.
1013 ret = of_parse_phandle_with_args(np, "iommus", "#iommu-cells", 0,
1016 dev_err(dev, "of_parse_phandle_with_args(%s) => %d\n",
1017 np->full_name, ret);
1020 if (args.args_count != 0) {
1021 dev_err(dev, "incorrect number of iommu params found for %s (found %d, expected 0)\n",
1022 args.np->full_name, args.args_count);
1026 pd = of_find_device_by_node(args.np);
1027 of_node_put(args.np);
1029 dev_err(dev, "iommu %s not found\n", args.np->full_name);
1030 return -EPROBE_DEFER;
1033 /* TODO(djkurtz): handle multiple slave iommus for a single master */
1034 iommu_group_set_iommudata(group, &pd->dev, NULL);
1039 static int rk_iommu_add_device(struct device *dev)
1041 struct iommu_group *group;
1044 if (!rk_iommu_is_dev_iommu_master(dev))
1047 group = iommu_group_get(dev);
1049 group = iommu_group_alloc();
1050 if (IS_ERR(group)) {
1051 dev_err(dev, "Failed to allocate IOMMU group\n");
1052 return PTR_ERR(group);
1056 ret = iommu_group_add_device(group, dev);
1060 ret = rk_iommu_group_set_iommudata(group, dev);
1062 goto err_remove_device;
1064 iommu_group_put(group);
1069 iommu_group_remove_device(dev);
1071 iommu_group_put(group);
1075 static void rk_iommu_remove_device(struct device *dev)
1077 if (!rk_iommu_is_dev_iommu_master(dev))
1080 iommu_group_remove_device(dev);
1083 static const struct iommu_ops rk_iommu_ops = {
1084 .domain_alloc = rk_iommu_domain_alloc,
1085 .domain_free = rk_iommu_domain_free,
1086 .attach_dev = rk_iommu_attach_device,
1087 .detach_dev = rk_iommu_detach_device,
1088 .map = rk_iommu_map,
1089 .unmap = rk_iommu_unmap,
1090 .map_sg = default_iommu_map_sg,
1091 .add_device = rk_iommu_add_device,
1092 .remove_device = rk_iommu_remove_device,
1093 .iova_to_phys = rk_iommu_iova_to_phys,
1094 .pgsize_bitmap = RK_IOMMU_PGSIZE_BITMAP,
1097 static int rk_iommu_domain_probe(struct platform_device *pdev)
1099 struct device *dev = &pdev->dev;
1101 dev->dma_parms = devm_kzalloc(dev, sizeof(*dev->dma_parms), GFP_KERNEL);
1102 if (!dev->dma_parms)
1105 /* Set dma_ops for dev, otherwise it would be dummy_dma_ops */
1106 arch_setup_dma_ops(dev, 0, DMA_BIT_MASK(32), NULL, false);
1108 dma_set_max_seg_size(dev, DMA_BIT_MASK(32));
1109 dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(32));
1114 static struct platform_driver rk_iommu_domain_driver = {
1115 .probe = rk_iommu_domain_probe,
1117 .name = "rk_iommu_domain",
1121 static int rk_iommu_probe(struct platform_device *pdev)
1123 struct device *dev = &pdev->dev;
1124 struct rk_iommu *iommu;
1125 struct resource *res;
1126 int num_res = pdev->num_resources;
1129 iommu = devm_kzalloc(dev, sizeof(*iommu), GFP_KERNEL);
1133 platform_set_drvdata(pdev, iommu);
1137 iommu->bases = devm_kzalloc(dev, sizeof(*iommu->bases) * num_res,
1142 for (i = 0; i < num_res; i++) {
1143 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
1146 iommu->bases[i] = devm_ioremap_resource(&pdev->dev, res);
1147 if (IS_ERR(iommu->bases[i]))
1151 if (iommu->num_mmu == 0)
1152 return PTR_ERR(iommu->bases[0]);
1154 iommu->irq = platform_get_irq(pdev, 0);
1155 if (iommu->irq < 0) {
1156 dev_err(dev, "Failed to get IRQ, %d\n", iommu->irq);
1163 static int rk_iommu_remove(struct platform_device *pdev)
1168 static const struct of_device_id rk_iommu_dt_ids[] = {
1169 { .compatible = "rockchip,iommu" },
1172 MODULE_DEVICE_TABLE(of, rk_iommu_dt_ids);
1174 static struct platform_driver rk_iommu_driver = {
1175 .probe = rk_iommu_probe,
1176 .remove = rk_iommu_remove,
1179 .of_match_table = rk_iommu_dt_ids,
1183 static int __init rk_iommu_init(void)
1185 struct device_node *np;
1188 np = of_find_matching_node(NULL, rk_iommu_dt_ids);
1194 ret = bus_set_iommu(&platform_bus_type, &rk_iommu_ops);
1198 ret = platform_driver_register(&rk_iommu_domain_driver);
1202 ret = platform_driver_register(&rk_iommu_driver);
1204 platform_driver_unregister(&rk_iommu_domain_driver);
1207 static void __exit rk_iommu_exit(void)
1209 platform_driver_unregister(&rk_iommu_driver);
1210 platform_driver_unregister(&rk_iommu_domain_driver);
1213 subsys_initcall(rk_iommu_init);
1214 module_exit(rk_iommu_exit);
1216 MODULE_DESCRIPTION("IOMMU API for Rockchip");
1217 MODULE_AUTHOR("Simon Xue <xxm@rock-chips.com> and Daniel Kurtz <djkurtz@chromium.org>");
1218 MODULE_ALIAS("platform:rockchip-iommu");
1219 MODULE_LICENSE("GPL v2");