drivers/iommu/tegra-smmu.c

   1 /*
   2  * IOMMU API for SMMU in Tegra30
   3  *
   4  * Copyright (c) 2011-2013, NVIDIA CORPORATION.  All rights reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along with
  16  * this program; if not, write to the Free Software Foundation, Inc.,
  17  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18  */
  19
  20 #define pr_fmt(fmt)     "%s(): " fmt, __func__
  21
  22 #include <linux/module.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/spinlock.h>
  25 #include <linux/slab.h>
  26 #include <linux/vmalloc.h>
  27 #include <linux/mm.h>
  28 #include <linux/pagemap.h>
  29 #include <linux/device.h>
  30 #include <linux/sched.h>
  31 #include <linux/iommu.h>
  32 #include <linux/io.h>
  33 #include <linux/of.h>
  34 #include <linux/of_iommu.h>
  35 #include <linux/debugfs.h>
  36 #include <linux/seq_file.h>
  37 #include <linux/tegra-ahb.h>
  38
  39 #include <asm/page.h>
  40 #include <asm/cacheflush.h>
  41
  42 enum smmu_hwgrp {
  43         HWGRP_AFI,
  44         HWGRP_AVPC,
  45         HWGRP_DC,
  46         HWGRP_DCB,
  47         HWGRP_EPP,
  48         HWGRP_G2,
  49         HWGRP_HC,
  50         HWGRP_HDA,
  51         HWGRP_ISP,
  52         HWGRP_MPE,
  53         HWGRP_NV,
  54         HWGRP_NV2,
  55         HWGRP_PPCS,
  56         HWGRP_SATA,
  57         HWGRP_VDE,
  58         HWGRP_VI,
  59
  60         HWGRP_COUNT,
  61
  62         HWGRP_END = ~0,
  63 };
  64
  65 #define HWG_AFI         (1 << HWGRP_AFI)
  66 #define HWG_AVPC        (1 << HWGRP_AVPC)
  67 #define HWG_DC          (1 << HWGRP_DC)
  68 #define HWG_DCB         (1 << HWGRP_DCB)
  69 #define HWG_EPP         (1 << HWGRP_EPP)
  70 #define HWG_G2          (1 << HWGRP_G2)
  71 #define HWG_HC          (1 << HWGRP_HC)
  72 #define HWG_HDA         (1 << HWGRP_HDA)
  73 #define HWG_ISP         (1 << HWGRP_ISP)
  74 #define HWG_MPE         (1 << HWGRP_MPE)
  75 #define HWG_NV          (1 << HWGRP_NV)
  76 #define HWG_NV2         (1 << HWGRP_NV2)
  77 #define HWG_PPCS        (1 << HWGRP_PPCS)
  78 #define HWG_SATA        (1 << HWGRP_SATA)
  79 #define HWG_VDE         (1 << HWGRP_VDE)
  80 #define HWG_VI          (1 << HWGRP_VI)
  81
  82 /* bitmap of the page sizes currently supported */
  83 #define SMMU_IOMMU_PGSIZES      (SZ_4K)
  84
  85 #define SMMU_CONFIG                             0x10
  86 #define SMMU_CONFIG_DISABLE                     0
  87 #define SMMU_CONFIG_ENABLE                      1
  88
  89 /* REVISIT: To support multiple MCs */
  90 enum {
  91         _MC = 0,
  92 };
  93
  94 enum {
  95         _TLB = 0,
  96         _PTC,
  97 };
  98
  99 #define SMMU_CACHE_CONFIG_BASE                  0x14
 100 #define __SMMU_CACHE_CONFIG(mc, cache)          (SMMU_CACHE_CONFIG_BASE + 4 * cache)
 101 #define SMMU_CACHE_CONFIG(cache)                __SMMU_CACHE_CONFIG(_MC, cache)
 102
 103 #define SMMU_CACHE_CONFIG_STATS_SHIFT           31
 104 #define SMMU_CACHE_CONFIG_STATS_ENABLE          (1 << SMMU_CACHE_CONFIG_STATS_SHIFT)
 105 #define SMMU_CACHE_CONFIG_STATS_TEST_SHIFT      30
 106 #define SMMU_CACHE_CONFIG_STATS_TEST            (1 << SMMU_CACHE_CONFIG_STATS_TEST_SHIFT)
 107
 108 #define SMMU_TLB_CONFIG_HIT_UNDER_MISS__ENABLE  (1 << 29)
 109 #define SMMU_TLB_CONFIG_ACTIVE_LINES__VALUE     0x10
 110 #define SMMU_TLB_CONFIG_RESET_VAL               0x20000010
 111
 112 #define SMMU_PTC_CONFIG_CACHE__ENABLE           (1 << 29)
 113 #define SMMU_PTC_CONFIG_INDEX_MAP__PATTERN      0x3f
 114 #define SMMU_PTC_CONFIG_RESET_VAL               0x2000003f
 115
 116 #define SMMU_PTB_ASID                           0x1c
 117 #define SMMU_PTB_ASID_CURRENT_SHIFT             0
 118
 119 #define SMMU_PTB_DATA                           0x20
 120 #define SMMU_PTB_DATA_RESET_VAL                 0
 121 #define SMMU_PTB_DATA_ASID_NONSECURE_SHIFT      29
 122 #define SMMU_PTB_DATA_ASID_WRITABLE_SHIFT       30
 123 #define SMMU_PTB_DATA_ASID_READABLE_SHIFT       31
 124
 125 #define SMMU_TLB_FLUSH                          0x30
 126 #define SMMU_TLB_FLUSH_VA_MATCH_ALL             0
 127 #define SMMU_TLB_FLUSH_VA_MATCH_SECTION         2
 128 #define SMMU_TLB_FLUSH_VA_MATCH_GROUP           3
 129 #define SMMU_TLB_FLUSH_ASID_SHIFT               29
 130 #define SMMU_TLB_FLUSH_ASID_MATCH_DISABLE       0
 131 #define SMMU_TLB_FLUSH_ASID_MATCH_ENABLE        1
 132 #define SMMU_TLB_FLUSH_ASID_MATCH_SHIFT         31
 133
 134 #define SMMU_PTC_FLUSH                          0x34
 135 #define SMMU_PTC_FLUSH_TYPE_ALL                 0
 136 #define SMMU_PTC_FLUSH_TYPE_ADR                 1
 137 #define SMMU_PTC_FLUSH_ADR_SHIFT                4
 138
 139 #define SMMU_ASID_SECURITY                      0x38
 140
 141 #define SMMU_STATS_CACHE_COUNT_BASE             0x1f0
 142
 143 #define SMMU_STATS_CACHE_COUNT(mc, cache, hitmiss)              \
 144         (SMMU_STATS_CACHE_COUNT_BASE + 8 * cache + 4 * hitmiss)
 145
 146 #define SMMU_TRANSLATION_ENABLE_0               0x228
 147 #define SMMU_TRANSLATION_ENABLE_1               0x22c
 148 #define SMMU_TRANSLATION_ENABLE_2               0x230
 149
 150 #define SMMU_AFI_ASID   0x238   /* PCIE */
 151 #define SMMU_AVPC_ASID  0x23c   /* AVP */
 152 #define SMMU_DC_ASID    0x240   /* Display controller */
 153 #define SMMU_DCB_ASID   0x244   /* Display controller B */
 154 #define SMMU_EPP_ASID   0x248   /* Encoder pre-processor */
 155 #define SMMU_G2_ASID    0x24c   /* 2D engine */
 156 #define SMMU_HC_ASID    0x250   /* Host1x */
 157 #define SMMU_HDA_ASID   0x254   /* High-def audio */
 158 #define SMMU_ISP_ASID   0x258   /* Image signal processor */
 159 #define SMMU_MPE_ASID   0x264   /* MPEG encoder */
 160 #define SMMU_NV_ASID    0x268   /* (3D) */
 161 #define SMMU_NV2_ASID   0x26c   /* (3D) */
 162 #define SMMU_PPCS_ASID  0x270   /* AHB */
 163 #define SMMU_SATA_ASID  0x278   /* SATA */
 164 #define SMMU_VDE_ASID   0x27c   /* Video decoder */
 165 #define SMMU_VI_ASID    0x280   /* Video input */
 166
 167 #define SMMU_PDE_NEXT_SHIFT             28
 168
 169 #define SMMU_TLB_FLUSH_VA_SECTION__MASK         0xffc00000
 170 #define SMMU_TLB_FLUSH_VA_SECTION__SHIFT        12 /* right shift */
 171 #define SMMU_TLB_FLUSH_VA_GROUP__MASK           0xffffc000
 172 #define SMMU_TLB_FLUSH_VA_GROUP__SHIFT          12 /* right shift */
 173 #define SMMU_TLB_FLUSH_VA(iova, which)  \
 174         ((((iova) & SMMU_TLB_FLUSH_VA_##which##__MASK) >> \
 175                 SMMU_TLB_FLUSH_VA_##which##__SHIFT) |   \
 176         SMMU_TLB_FLUSH_VA_MATCH_##which)
 177 #define SMMU_PTB_ASID_CUR(n)    \
 178                 ((n) << SMMU_PTB_ASID_CURRENT_SHIFT)
 179 #define SMMU_TLB_FLUSH_ASID_MATCH_disable               \
 180                 (SMMU_TLB_FLUSH_ASID_MATCH_DISABLE <<   \
 181                         SMMU_TLB_FLUSH_ASID_MATCH_SHIFT)
 182 #define SMMU_TLB_FLUSH_ASID_MATCH__ENABLE               \
 183                 (SMMU_TLB_FLUSH_ASID_MATCH_ENABLE <<    \
 184                         SMMU_TLB_FLUSH_ASID_MATCH_SHIFT)
 185
 186 #define SMMU_PAGE_SHIFT 12
 187 #define SMMU_PAGE_SIZE  (1 << SMMU_PAGE_SHIFT)
 188 #define SMMU_PAGE_MASK  ((1 << SMMU_PAGE_SHIFT) - 1)
 189
 190 #define SMMU_PDIR_COUNT 1024
 191 #define SMMU_PDIR_SIZE  (sizeof(unsigned long) * SMMU_PDIR_COUNT)
 192 #define SMMU_PTBL_COUNT 1024
 193 #define SMMU_PTBL_SIZE  (sizeof(unsigned long) * SMMU_PTBL_COUNT)
 194 #define SMMU_PDIR_SHIFT 12
 195 #define SMMU_PDE_SHIFT  12
 196 #define SMMU_PTE_SHIFT  12
 197 #define SMMU_PFN_MASK   0x000fffff
 198
 199 #define SMMU_ADDR_TO_PFN(addr)  ((addr) >> 12)
 200 #define SMMU_ADDR_TO_PDN(addr)  ((addr) >> 22)
 201 #define SMMU_PDN_TO_ADDR(pdn)   ((pdn) << 22)
 202
 203 #define _READABLE       (1 << SMMU_PTB_DATA_ASID_READABLE_SHIFT)
 204 #define _WRITABLE       (1 << SMMU_PTB_DATA_ASID_WRITABLE_SHIFT)
 205 #define _NONSECURE      (1 << SMMU_PTB_DATA_ASID_NONSECURE_SHIFT)
 206 #define _PDE_NEXT       (1 << SMMU_PDE_NEXT_SHIFT)
 207 #define _MASK_ATTR      (_READABLE | _WRITABLE | _NONSECURE)
 208
 209 #define _PDIR_ATTR      (_READABLE | _WRITABLE | _NONSECURE)
 210
 211 #define _PDE_ATTR       (_READABLE | _WRITABLE | _NONSECURE)
 212 #define _PDE_ATTR_N     (_PDE_ATTR | _PDE_NEXT)
 213 #define _PDE_VACANT(pdn)        (((pdn) << 10) | _PDE_ATTR)
 214
 215 #define _PTE_ATTR       (_READABLE | _WRITABLE | _NONSECURE)
 216 #define _PTE_VACANT(addr)       (((addr) >> SMMU_PAGE_SHIFT) | _PTE_ATTR)
 217
 218 #define SMMU_MK_PDIR(page, attr)        \
 219                 ((page_to_phys(page) >> SMMU_PDIR_SHIFT) | (attr))
 220 #define SMMU_MK_PDE(page, attr)         \
 221                 (unsigned long)((page_to_phys(page) >> SMMU_PDE_SHIFT) | (attr))
 222 #define SMMU_EX_PTBL_PAGE(pde)          \
 223                 pfn_to_page((unsigned long)(pde) & SMMU_PFN_MASK)
 224 #define SMMU_PFN_TO_PTE(pfn, attr)      (unsigned long)((pfn) | (attr))
 225
 226 #define SMMU_ASID_ENABLE(asid)  ((asid) | (1 << 31))
 227 #define SMMU_ASID_DISABLE       0
 228 #define SMMU_ASID_ASID(n)       ((n) & ~SMMU_ASID_ENABLE(0))
 229
 230 #define NUM_SMMU_REG_BANKS      3
 231
 232 #define smmu_client_enable_hwgrp(c, m)  smmu_client_set_hwgrp(c, m, 1)
 233 #define smmu_client_disable_hwgrp(c)    smmu_client_set_hwgrp(c, 0, 0)
 234 #define __smmu_client_enable_hwgrp(c, m) __smmu_client_set_hwgrp(c, m, 1)
 235 #define __smmu_client_disable_hwgrp(c)  __smmu_client_set_hwgrp(c, 0, 0)
 236
 237 #define HWGRP_INIT(client) [HWGRP_##client] = SMMU_##client##_ASID
 238
 239 static const u32 smmu_hwgrp_asid_reg[] = {
 240         HWGRP_INIT(AFI),
 241         HWGRP_INIT(AVPC),
 242         HWGRP_INIT(DC),
 243         HWGRP_INIT(DCB),
 244         HWGRP_INIT(EPP),
 245         HWGRP_INIT(G2),
 246         HWGRP_INIT(HC),
 247         HWGRP_INIT(HDA),
 248         HWGRP_INIT(ISP),
 249         HWGRP_INIT(MPE),
 250         HWGRP_INIT(NV),
 251         HWGRP_INIT(NV2),
 252         HWGRP_INIT(PPCS),
 253         HWGRP_INIT(SATA),
 254         HWGRP_INIT(VDE),
 255         HWGRP_INIT(VI),
 256 };
 257 #define HWGRP_ASID_REG(x) (smmu_hwgrp_asid_reg[x])
 258
 259 /*
 260  * Per client for address space
 261  */
 262 struct smmu_client {
 263         struct device           *dev;
 264         struct list_head        list;
 265         struct smmu_as          *as;
 266         u32                     hwgrp;
 267 };
 268
 269 /*
 270  * Per address space
 271  */
 272 struct smmu_as {
 273         struct smmu_device      *smmu;  /* back pointer to container */
 274         unsigned int            asid;
 275         spinlock_t              lock;   /* for pagetable */
 276         struct page             *pdir_page;
 277         unsigned long           pdir_attr;
 278         unsigned long           pde_attr;
 279         unsigned long           pte_attr;
 280         unsigned int            *pte_count;
 281
 282         struct list_head        client;
 283         spinlock_t              client_lock; /* for client list */
 284 };
 285
 286 struct smmu_debugfs_info {
 287         struct smmu_device *smmu;
 288         int mc;
 289         int cache;
 290 };
 291
 292 /*
 293  * Per SMMU device - IOMMU device
 294  */
 295 struct smmu_device {
 296         void __iomem    *regbase;       /* register offset base */
 297         void __iomem    **regs;         /* register block start address array */
 298         void __iomem    **rege;         /* register block end address array */
 299         int             nregs;          /* number of register blocks */
 300
 301         unsigned long   iovmm_base;     /* remappable base address */
 302         unsigned long   page_count;     /* total remappable size */
 303         spinlock_t      lock;
 304         char            *name;
 305         struct device   *dev;
 306         struct page *avp_vector_page;   /* dummy page shared by all AS's */
 307
 308         /*
 309          * Register image savers for suspend/resume
 310          */
 311         unsigned long translation_enable_0;
 312         unsigned long translation_enable_1;
 313         unsigned long translation_enable_2;
 314         unsigned long asid_security;
 315
 316         struct dentry *debugfs_root;
 317         struct smmu_debugfs_info *debugfs_info;
 318
 319         struct device_node *ahb;
 320
 321         int             num_as;
 322         struct smmu_as  as[0];          /* Run-time allocated array */
 323 };
 324
 325 static struct smmu_device *smmu_handle; /* unique for a system */
 326
 327 /*
 328  *      SMMU register accessors
 329  */
 330 static bool inline smmu_valid_reg(struct smmu_device *smmu,
 331                                   void __iomem *addr)
 332 {
 333         int i;
 334
 335         for (i = 0; i < smmu->nregs; i++) {
 336                 if (addr < smmu->regs[i])
 337                         break;
 338                 if (addr <= smmu->rege[i])
 339                         return true;
 340         }
 341
 342         return false;
 343 }
 344
 345 static inline u32 smmu_read(struct smmu_device *smmu, size_t offs)
 346 {
 347         void __iomem *addr = smmu->regbase + offs;
 348
 349         BUG_ON(!smmu_valid_reg(smmu, addr));
 350
 351         return readl(addr);
 352 }
 353
 354 static inline void smmu_write(struct smmu_device *smmu, u32 val, size_t offs)
 355 {
 356         void __iomem *addr = smmu->regbase + offs;
 357
 358         BUG_ON(!smmu_valid_reg(smmu, addr));
 359
 360         writel(val, addr);
 361 }
 362
 363 #define VA_PAGE_TO_PA(va, page) \
 364         (page_to_phys(page) + ((unsigned long)(va) & ~PAGE_MASK))
 365
 366 #define FLUSH_CPU_DCACHE(va, page, size)        \
 367         do {    \
 368                 unsigned long _pa_ = VA_PAGE_TO_PA(va, page);           \
 369                 __cpuc_flush_dcache_area((void *)(va), (size_t)(size)); \
 370                 outer_flush_range(_pa_, _pa_+(size_t)(size));           \
 371         } while (0)
 372
 373 /*
 374  * Any interaction between any block on PPSB and a block on APB or AHB
 375  * must have these read-back barriers to ensure the APB/AHB bus
 376  * transaction is complete before initiating activity on the PPSB
 377  * block.
 378  */
 379 #define FLUSH_SMMU_REGS(smmu)   smmu_read(smmu, SMMU_CONFIG)
 380
 381 #define smmu_client_hwgrp(c) (u32)((c)->dev->platform_data)
 382
 383 static int __smmu_client_set_hwgrp(struct smmu_client *c,
 384                                    unsigned long map, int on)
 385 {
 386         int i;
 387         struct smmu_as *as = c->as;
 388         u32 val, offs, mask = SMMU_ASID_ENABLE(as->asid);
 389         struct smmu_device *smmu = as->smmu;
 390
 391         WARN_ON(!on && map);
 392         if (on && !map)
 393                 return -EINVAL;
 394         if (!on)
 395                 map = smmu_client_hwgrp(c);
 396
 397         for_each_set_bit(i, &map, HWGRP_COUNT) {
 398                 offs = HWGRP_ASID_REG(i);
 399                 val = smmu_read(smmu, offs);
 400                 if (on) {
 401                         if (WARN_ON(val & mask))
 402                                 goto err_hw_busy;
 403                         val |= mask;
 404                 } else {
 405                         WARN_ON((val & mask) == mask);
 406                         val &= ~mask;
 407                 }
 408                 smmu_write(smmu, val, offs);
 409         }
 410         FLUSH_SMMU_REGS(smmu);
 411         c->hwgrp = map;
 412         return 0;
 413
 414 err_hw_busy:
 415         for_each_set_bit(i, &map, HWGRP_COUNT) {
 416                 offs = HWGRP_ASID_REG(i);
 417                 val = smmu_read(smmu, offs);
 418                 val &= ~mask;
 419                 smmu_write(smmu, val, offs);
 420         }
 421         return -EBUSY;
 422 }
 423
 424 static int smmu_client_set_hwgrp(struct smmu_client *c, u32 map, int on)
 425 {
 426         u32 val;
 427         unsigned long flags;
 428         struct smmu_as *as = c->as;
 429         struct smmu_device *smmu = as->smmu;
 430
 431         spin_lock_irqsave(&smmu->lock, flags);
 432         val = __smmu_client_set_hwgrp(c, map, on);
 433         spin_unlock_irqrestore(&smmu->lock, flags);
 434         return val;
 435 }
 436
 437 /*
 438  * Flush all TLB entries and all PTC entries
 439  * Caller must lock smmu
 440  */
 441 static void smmu_flush_regs(struct smmu_device *smmu, int enable)
 442 {
 443         u32 val;
 444
 445         smmu_write(smmu, SMMU_PTC_FLUSH_TYPE_ALL, SMMU_PTC_FLUSH);
 446         FLUSH_SMMU_REGS(smmu);
 447         val = SMMU_TLB_FLUSH_VA_MATCH_ALL |
 448                 SMMU_TLB_FLUSH_ASID_MATCH_disable;
 449         smmu_write(smmu, val, SMMU_TLB_FLUSH);
 450
 451         if (enable)
 452                 smmu_write(smmu, SMMU_CONFIG_ENABLE, SMMU_CONFIG);
 453         FLUSH_SMMU_REGS(smmu);
 454 }
 455
 456 static int smmu_setup_regs(struct smmu_device *smmu)
 457 {
 458         int i;
 459         u32 val;
 460
 461         for (i = 0; i < smmu->num_as; i++) {
 462                 struct smmu_as *as = &smmu->as[i];
 463                 struct smmu_client *c;
 464
 465                 smmu_write(smmu, SMMU_PTB_ASID_CUR(as->asid), SMMU_PTB_ASID);
 466                 val = as->pdir_page ?
 467                         SMMU_MK_PDIR(as->pdir_page, as->pdir_attr) :
 468                         SMMU_PTB_DATA_RESET_VAL;
 469                 smmu_write(smmu, val, SMMU_PTB_DATA);
 470
 471                 list_for_each_entry(c, &as->client, list)
 472                         __smmu_client_set_hwgrp(c, c->hwgrp, 1);
 473         }
 474
 475         smmu_write(smmu, smmu->translation_enable_0, SMMU_TRANSLATION_ENABLE_0);
 476         smmu_write(smmu, smmu->translation_enable_1, SMMU_TRANSLATION_ENABLE_1);
 477         smmu_write(smmu, smmu->translation_enable_2, SMMU_TRANSLATION_ENABLE_2);
 478         smmu_write(smmu, smmu->asid_security, SMMU_ASID_SECURITY);
 479         smmu_write(smmu, SMMU_TLB_CONFIG_RESET_VAL, SMMU_CACHE_CONFIG(_TLB));
 480         smmu_write(smmu, SMMU_PTC_CONFIG_RESET_VAL, SMMU_CACHE_CONFIG(_PTC));
 481
 482         smmu_flush_regs(smmu, 1);
 483
 484         return tegra_ahb_enable_smmu(smmu->ahb);
 485 }
 486
 487 static void flush_ptc_and_tlb(struct smmu_device *smmu,
 488                       struct smmu_as *as, dma_addr_t iova,
 489                       unsigned long *pte, struct page *page, int is_pde)
 490 {
 491         u32 val;
 492         unsigned long tlb_flush_va = is_pde
 493                 ?  SMMU_TLB_FLUSH_VA(iova, SECTION)
 494                 :  SMMU_TLB_FLUSH_VA(iova, GROUP);
 495
 496         val = SMMU_PTC_FLUSH_TYPE_ADR | VA_PAGE_TO_PA(pte, page);
 497         smmu_write(smmu, val, SMMU_PTC_FLUSH);
 498         FLUSH_SMMU_REGS(smmu);
 499         val = tlb_flush_va |
 500                 SMMU_TLB_FLUSH_ASID_MATCH__ENABLE |
 501                 (as->asid << SMMU_TLB_FLUSH_ASID_SHIFT);
 502         smmu_write(smmu, val, SMMU_TLB_FLUSH);
 503         FLUSH_SMMU_REGS(smmu);
 504 }
 505
 506 static void free_ptbl(struct smmu_as *as, dma_addr_t iova)
 507 {
 508         unsigned long pdn = SMMU_ADDR_TO_PDN(iova);
 509         unsigned long *pdir = (unsigned long *)page_address(as->pdir_page);
 510
 511         if (pdir[pdn] != _PDE_VACANT(pdn)) {
 512                 dev_dbg(as->smmu->dev, "pdn: %lx\n", pdn);
 513
 514                 ClearPageReserved(SMMU_EX_PTBL_PAGE(pdir[pdn]));
 515                 __free_page(SMMU_EX_PTBL_PAGE(pdir[pdn]));
 516                 pdir[pdn] = _PDE_VACANT(pdn);
 517                 FLUSH_CPU_DCACHE(&pdir[pdn], as->pdir_page, sizeof pdir[pdn]);
 518                 flush_ptc_and_tlb(as->smmu, as, iova, &pdir[pdn],
 519                                   as->pdir_page, 1);
 520         }
 521 }
 522
 523 static void free_pdir(struct smmu_as *as)
 524 {
 525         unsigned addr;
 526         int count;
 527         struct device *dev = as->smmu->dev;
 528
 529         if (!as->pdir_page)
 530                 return;
 531
 532         addr = as->smmu->iovmm_base;
 533         count = as->smmu->page_count;
 534         while (count-- > 0) {
 535                 free_ptbl(as, addr);
 536                 addr += SMMU_PAGE_SIZE * SMMU_PTBL_COUNT;
 537         }
 538         ClearPageReserved(as->pdir_page);
 539         __free_page(as->pdir_page);
 540         as->pdir_page = NULL;
 541         devm_kfree(dev, as->pte_count);
 542         as->pte_count = NULL;
 543 }
 544
 545 /*
 546  * Maps PTBL for given iova and returns the PTE address
 547  * Caller must unmap the mapped PTBL returned in *ptbl_page_p
 548  */
 549 static unsigned long *locate_pte(struct smmu_as *as,
 550                                  dma_addr_t iova, bool allocate,
 551                                  struct page **ptbl_page_p,
 552                                  unsigned int **count)
 553 {
 554         unsigned long ptn = SMMU_ADDR_TO_PFN(iova);
 555         unsigned long pdn = SMMU_ADDR_TO_PDN(iova);
 556         unsigned long *pdir = page_address(as->pdir_page);
 557         unsigned long *ptbl;
 558
 559         if (pdir[pdn] != _PDE_VACANT(pdn)) {
 560                 /* Mapped entry table already exists */
 561                 *ptbl_page_p = SMMU_EX_PTBL_PAGE(pdir[pdn]);
 562                 ptbl = page_address(*ptbl_page_p);
 563         } else if (!allocate) {
 564                 return NULL;
 565         } else {
 566                 int pn;
 567                 unsigned long addr = SMMU_PDN_TO_ADDR(pdn);
 568
 569                 /* Vacant - allocate a new page table */
 570                 dev_dbg(as->smmu->dev, "New PTBL pdn: %lx\n", pdn);
 571
 572                 *ptbl_page_p = alloc_page(GFP_ATOMIC);
 573                 if (!*ptbl_page_p) {
 574                         dev_err(as->smmu->dev,
 575                                 "failed to allocate smmu_device page table\n");
 576                         return NULL;
 577                 }
 578                 SetPageReserved(*ptbl_page_p);
 579                 ptbl = (unsigned long *)page_address(*ptbl_page_p);
 580                 for (pn = 0; pn < SMMU_PTBL_COUNT;
 581                      pn++, addr += SMMU_PAGE_SIZE) {
 582                         ptbl[pn] = _PTE_VACANT(addr);
 583                 }
 584                 FLUSH_CPU_DCACHE(ptbl, *ptbl_page_p, SMMU_PTBL_SIZE);
 585                 pdir[pdn] = SMMU_MK_PDE(*ptbl_page_p,
 586                                         as->pde_attr | _PDE_NEXT);
 587                 FLUSH_CPU_DCACHE(&pdir[pdn], as->pdir_page, sizeof pdir[pdn]);
 588                 flush_ptc_and_tlb(as->smmu, as, iova, &pdir[pdn],
 589                                   as->pdir_page, 1);
 590         }
 591         *count = &as->pte_count[pdn];
 592
 593         return &ptbl[ptn % SMMU_PTBL_COUNT];
 594 }
 595
 596 #ifdef CONFIG_SMMU_SIG_DEBUG
 597 static void put_signature(struct smmu_as *as,
 598                           dma_addr_t iova, unsigned long pfn)
 599 {
 600         struct page *page;
 601         unsigned long *vaddr;
 602
 603         page = pfn_to_page(pfn);
 604         vaddr = page_address(page);
 605         if (!vaddr)
 606                 return;
 607
 608         vaddr[0] = iova;
 609         vaddr[1] = pfn << PAGE_SHIFT;
 610         FLUSH_CPU_DCACHE(vaddr, page, sizeof(vaddr[0]) * 2);
 611 }
 612 #else
 613 static inline void put_signature(struct smmu_as *as,
 614                                  unsigned long addr, unsigned long pfn)
 615 {
 616 }
 617 #endif
 618
 619 /*
 620  * Caller must not hold as->lock
 621  */
 622 static int alloc_pdir(struct smmu_as *as)
 623 {
 624         unsigned long *pdir, flags;
 625         int pdn, err = 0;
 626         u32 val;
 627         struct smmu_device *smmu = as->smmu;
 628         struct page *page;
 629         unsigned int *cnt;
 630
 631         /*
 632          * do the allocation, then grab as->lock
 633          */
 634         cnt = devm_kzalloc(smmu->dev,
 635                            sizeof(cnt[0]) * SMMU_PDIR_COUNT,
 636                            GFP_KERNEL);
 637         page = alloc_page(GFP_KERNEL | __GFP_DMA);
 638
 639         spin_lock_irqsave(&as->lock, flags);
 640
 641         if (as->pdir_page) {
 642                 /* We raced, free the redundant */
 643                 err = -EAGAIN;
 644                 goto err_out;
 645         }
 646
 647         if (!page || !cnt) {
 648                 dev_err(smmu->dev, "failed to allocate at %s\n", __func__);
 649                 err = -ENOMEM;
 650                 goto err_out;
 651         }
 652
 653         as->pdir_page = page;
 654         as->pte_count = cnt;
 655
 656         SetPageReserved(as->pdir_page);
 657         pdir = page_address(as->pdir_page);
 658
 659         for (pdn = 0; pdn < SMMU_PDIR_COUNT; pdn++)
 660                 pdir[pdn] = _PDE_VACANT(pdn);
 661         FLUSH_CPU_DCACHE(pdir, as->pdir_page, SMMU_PDIR_SIZE);
 662         val = SMMU_PTC_FLUSH_TYPE_ADR | VA_PAGE_TO_PA(pdir, as->pdir_page);
 663         smmu_write(smmu, val, SMMU_PTC_FLUSH);
 664         FLUSH_SMMU_REGS(as->smmu);
 665         val = SMMU_TLB_FLUSH_VA_MATCH_ALL |
 666                 SMMU_TLB_FLUSH_ASID_MATCH__ENABLE |
 667                 (as->asid << SMMU_TLB_FLUSH_ASID_SHIFT);
 668         smmu_write(smmu, val, SMMU_TLB_FLUSH);
 669         FLUSH_SMMU_REGS(as->smmu);
 670
 671         spin_unlock_irqrestore(&as->lock, flags);
 672
 673         return 0;
 674
 675 err_out:
 676         spin_unlock_irqrestore(&as->lock, flags);
 677
 678         devm_kfree(smmu->dev, cnt);
 679         if (page)
 680                 __free_page(page);
 681         return err;
 682 }
 683
 684 static void __smmu_iommu_unmap(struct smmu_as *as, dma_addr_t iova)
 685 {
 686         unsigned long *pte;
 687         struct page *page;
 688         unsigned int *count;
 689
 690         pte = locate_pte(as, iova, false, &page, &count);
 691         if (WARN_ON(!pte))
 692                 return;
 693
 694         if (WARN_ON(*pte == _PTE_VACANT(iova)))
 695                 return;
 696
 697         *pte = _PTE_VACANT(iova);
 698         FLUSH_CPU_DCACHE(pte, page, sizeof(*pte));
 699         flush_ptc_and_tlb(as->smmu, as, iova, pte, page, 0);
 700         if (!--(*count))
 701                 free_ptbl(as, iova);
 702 }
 703
 704 static void __smmu_iommu_map_pfn(struct smmu_as *as, dma_addr_t iova,
 705                                  unsigned long pfn)
 706 {
 707         struct smmu_device *smmu = as->smmu;
 708         unsigned long *pte;
 709         unsigned int *count;
 710         struct page *page;
 711
 712         pte = locate_pte(as, iova, true, &page, &count);
 713         if (WARN_ON(!pte))
 714                 return;
 715
 716         if (*pte == _PTE_VACANT(iova))
 717                 (*count)++;
 718         *pte = SMMU_PFN_TO_PTE(pfn, as->pte_attr);
 719         if (unlikely((*pte == _PTE_VACANT(iova))))
 720                 (*count)--;
 721         FLUSH_CPU_DCACHE(pte, page, sizeof(*pte));
 722         flush_ptc_and_tlb(smmu, as, iova, pte, page, 0);
 723         put_signature(as, iova, pfn);
 724 }
 725
 726 static int smmu_iommu_map(struct iommu_domain *domain, unsigned long iova,
 727                           phys_addr_t pa, size_t bytes, int prot)
 728 {
 729         struct smmu_as *as = domain->priv;
 730         unsigned long pfn = __phys_to_pfn(pa);
 731         unsigned long flags;
 732
 733         dev_dbg(as->smmu->dev, "[%d] %08lx:%08x\n", as->asid, iova, pa);
 734
 735         if (!pfn_valid(pfn))
 736                 return -ENOMEM;
 737
 738         spin_lock_irqsave(&as->lock, flags);
 739         __smmu_iommu_map_pfn(as, iova, pfn);
 740         spin_unlock_irqrestore(&as->lock, flags);
 741         return 0;
 742 }
 743
 744 static size_t smmu_iommu_unmap(struct iommu_domain *domain, unsigned long iova,
 745                                size_t bytes)
 746 {
 747         struct smmu_as *as = domain->priv;
 748         unsigned long flags;
 749
 750         dev_dbg(as->smmu->dev, "[%d] %08lx\n", as->asid, iova);
 751
 752         spin_lock_irqsave(&as->lock, flags);
 753         __smmu_iommu_unmap(as, iova);
 754         spin_unlock_irqrestore(&as->lock, flags);
 755         return SMMU_PAGE_SIZE;
 756 }
 757
 758 static phys_addr_t smmu_iommu_iova_to_phys(struct iommu_domain *domain,
 759                                            unsigned long iova)
 760 {
 761         struct smmu_as *as = domain->priv;
 762         unsigned long *pte;
 763         unsigned int *count;
 764         struct page *page;
 765         unsigned long pfn;
 766         unsigned long flags;
 767
 768         spin_lock_irqsave(&as->lock, flags);
 769
 770         pte = locate_pte(as, iova, true, &page, &count);
 771         pfn = *pte & SMMU_PFN_MASK;
 772         WARN_ON(!pfn_valid(pfn));
 773         dev_dbg(as->smmu->dev,
 774                 "iova:%08lx pfn:%08lx asid:%d\n", iova, pfn, as->asid);
 775
 776         spin_unlock_irqrestore(&as->lock, flags);
 777         return PFN_PHYS(pfn);
 778 }
 779
 780 static int smmu_iommu_domain_has_cap(struct iommu_domain *domain,
 781                                      unsigned long cap)
 782 {
 783         return 0;
 784 }
 785
 786 static int smmu_iommu_attach_dev(struct iommu_domain *domain,
 787                                  struct device *dev)
 788 {
 789         struct smmu_as *as = domain->priv;
 790         struct smmu_device *smmu = as->smmu;
 791         struct smmu_client *client, *c;
 792         u32 map;
 793         int err;
 794
 795         client = devm_kzalloc(smmu->dev, sizeof(*c), GFP_KERNEL);
 796         if (!client)
 797                 return -ENOMEM;
 798         client->dev = dev;
 799         client->as = as;
 800         map = (unsigned long)dev->platform_data;
 801         if (!map)
 802                 return -EINVAL;
 803
 804         err = smmu_client_enable_hwgrp(client, map);
 805         if (err)
 806                 goto err_hwgrp;
 807
 808         spin_lock(&as->client_lock);
 809         list_for_each_entry(c, &as->client, list) {
 810                 if (c->dev == dev) {
 811                         dev_err(smmu->dev,
 812                                 "%s is already attached\n", dev_name(c->dev));
 813                         err = -EINVAL;
 814                         goto err_client;
 815                 }
 816         }
 817         list_add(&client->list, &as->client);
 818         spin_unlock(&as->client_lock);
 819
 820         /*
 821          * Reserve "page zero" for AVP vectors using a common dummy
 822          * page.
 823          */
 824         if (map & HWG_AVPC) {
 825                 struct page *page;
 826
 827                 page = as->smmu->avp_vector_page;
 828                 __smmu_iommu_map_pfn(as, 0, page_to_pfn(page));
 829
 830                 pr_info("Reserve \"page zero\" for AVP vectors using a common dummy\n");
 831         }
 832
 833         dev_dbg(smmu->dev, "%s is attached\n", dev_name(dev));
 834         return 0;
 835
 836 err_client:
 837         smmu_client_disable_hwgrp(client);
 838         spin_unlock(&as->client_lock);
 839 err_hwgrp:
 840         devm_kfree(smmu->dev, client);
 841         return err;
 842 }
 843
 844 static void smmu_iommu_detach_dev(struct iommu_domain *domain,
 845                                   struct device *dev)
 846 {
 847         struct smmu_as *as = domain->priv;
 848         struct smmu_device *smmu = as->smmu;
 849         struct smmu_client *c;
 850
 851         spin_lock(&as->client_lock);
 852
 853         list_for_each_entry(c, &as->client, list) {
 854                 if (c->dev == dev) {
 855                         smmu_client_disable_hwgrp(c);
 856                         list_del(&c->list);
 857                         devm_kfree(smmu->dev, c);
 858                         c->as = NULL;
 859                         dev_dbg(smmu->dev,
 860                                 "%s is detached\n", dev_name(c->dev));
 861                         goto out;
 862                 }
 863         }
 864         dev_err(smmu->dev, "Couldn't find %s\n", dev_name(dev));
 865 out:
 866         spin_unlock(&as->client_lock);
 867 }
 868
 869 static int smmu_iommu_domain_init(struct iommu_domain *domain)
 870 {
 871         int i, err = -EAGAIN;
 872         unsigned long flags;
 873         struct smmu_as *as;
 874         struct smmu_device *smmu = smmu_handle;
 875
 876         /* Look for a free AS with lock held */
 877         for  (i = 0; i < smmu->num_as; i++) {
 878                 as = &smmu->as[i];
 879
 880                 if (as->pdir_page)
 881                         continue;
 882
 883                 err = alloc_pdir(as);
 884                 if (!err)
 885                         goto found;
 886
 887                 if (err != -EAGAIN)
 888                         break;
 889         }
 890         if (i == smmu->num_as)
 891                 dev_err(smmu->dev,  "no free AS\n");
 892         return err;
 893
 894 found:
 895         spin_lock_irqsave(&smmu->lock, flags);
 896
 897         /* Update PDIR register */
 898         smmu_write(smmu, SMMU_PTB_ASID_CUR(as->asid), SMMU_PTB_ASID);
 899         smmu_write(smmu,
 900                    SMMU_MK_PDIR(as->pdir_page, as->pdir_attr), SMMU_PTB_DATA);
 901         FLUSH_SMMU_REGS(smmu);
 902
 903         spin_unlock_irqrestore(&smmu->lock, flags);
 904
 905         domain->priv = as;
 906
 907         domain->geometry.aperture_start = smmu->iovmm_base;
 908         domain->geometry.aperture_end   = smmu->iovmm_base +
 909                 smmu->page_count * SMMU_PAGE_SIZE - 1;
 910         domain->geometry.force_aperture = true;
 911
 912         dev_dbg(smmu->dev, "smmu_as@%p\n", as);
 913
 914         return 0;
 915 }
 916
 917 static void smmu_iommu_domain_destroy(struct iommu_domain *domain)
 918 {
 919         struct smmu_as *as = domain->priv;
 920         struct smmu_device *smmu = as->smmu;
 921         unsigned long flags;
 922
 923         spin_lock_irqsave(&as->lock, flags);
 924
 925         if (as->pdir_page) {
 926                 spin_lock(&smmu->lock);
 927                 smmu_write(smmu, SMMU_PTB_ASID_CUR(as->asid), SMMU_PTB_ASID);
 928                 smmu_write(smmu, SMMU_PTB_DATA_RESET_VAL, SMMU_PTB_DATA);
 929                 FLUSH_SMMU_REGS(smmu);
 930                 spin_unlock(&smmu->lock);
 931
 932                 free_pdir(as);
 933         }
 934
 935         if (!list_empty(&as->client)) {
 936                 struct smmu_client *c;
 937
 938                 list_for_each_entry(c, &as->client, list)
 939                         smmu_iommu_detach_dev(domain, c->dev);
 940         }
 941
 942         spin_unlock_irqrestore(&as->lock, flags);
 943
 944         domain->priv = NULL;
 945         dev_dbg(smmu->dev, "smmu_as@%p\n", as);
 946 }
 947
 948 static struct iommu_ops smmu_iommu_ops = {
 949         .domain_init    = smmu_iommu_domain_init,
 950         .domain_destroy = smmu_iommu_domain_destroy,
 951         .attach_dev     = smmu_iommu_attach_dev,
 952         .detach_dev     = smmu_iommu_detach_dev,
 953         .map            = smmu_iommu_map,
 954         .unmap          = smmu_iommu_unmap,
 955         .iova_to_phys   = smmu_iommu_iova_to_phys,
 956         .domain_has_cap = smmu_iommu_domain_has_cap,
 957         .pgsize_bitmap  = SMMU_IOMMU_PGSIZES,
 958 };
 959
 960 /* Should be in the order of enum */
 961 static const char * const smmu_debugfs_mc[] = { "mc", };
 962 static const char * const smmu_debugfs_cache[] = {  "tlb", "ptc", };
 963
 964 static ssize_t smmu_debugfs_stats_write(struct file *file,
 965                                         const char __user *buffer,
 966                                         size_t count, loff_t *pos)
 967 {
 968         struct smmu_debugfs_info *info;
 969         struct smmu_device *smmu;
 970         struct dentry *dent;
 971         int i;
 972         enum {
 973                 _OFF = 0,
 974                 _ON,
 975                 _RESET,
 976         };
 977         const char * const command[] = {
 978                 [_OFF]          = "off",
 979                 [_ON]           = "on",
 980                 [_RESET]        = "reset",
 981         };
 982         char str[] = "reset";
 983         u32 val;
 984         size_t offs;
 985
 986         count = min_t(size_t, count, sizeof(str));
 987         if (copy_from_user(str, buffer, count))
 988                 return -EINVAL;
 989
 990         for (i = 0; i < ARRAY_SIZE(command); i++)
 991                 if (strncmp(str, command[i],
 992                             strlen(command[i])) == 0)
 993                         break;
 994
 995         if (i == ARRAY_SIZE(command))
 996                 return -EINVAL;
 997
 998         dent = file->f_dentry;
 999         info = dent->d_inode->i_private;
1000         smmu = info->smmu;
1001
1002         offs = SMMU_CACHE_CONFIG(info->cache);
1003         val = smmu_read(smmu, offs);
1004         switch (i) {
1005         case _OFF:
1006                 val &= ~SMMU_CACHE_CONFIG_STATS_ENABLE;
1007                 val &= ~SMMU_CACHE_CONFIG_STATS_TEST;
1008                 smmu_write(smmu, val, offs);
1009                 break;
1010         case _ON:
1011                 val |= SMMU_CACHE_CONFIG_STATS_ENABLE;
1012                 val &= ~SMMU_CACHE_CONFIG_STATS_TEST;
1013                 smmu_write(smmu, val, offs);
1014                 break;
1015         case _RESET:
1016                 val |= SMMU_CACHE_CONFIG_STATS_TEST;
1017                 smmu_write(smmu, val, offs);
1018                 val &= ~SMMU_CACHE_CONFIG_STATS_TEST;
1019                 smmu_write(smmu, val, offs);
1020                 break;
1021         default:
1022                 BUG();
1023                 break;
1024         }
1025
1026         dev_dbg(smmu->dev, "%s() %08x, %08x @%08x\n", __func__,
1027                 val, smmu_read(smmu, offs), offs);
1028
1029         return count;
1030 }
1031
1032 static int smmu_debugfs_stats_show(struct seq_file *s, void *v)
1033 {
1034         struct smmu_debugfs_info *info;
1035         struct smmu_device *smmu;
1036         struct dentry *dent;
1037         int i;
1038         const char * const stats[] = { "hit", "miss", };
1039
1040         dent = d_find_alias(s->private);
1041         info = dent->d_inode->i_private;
1042         smmu = info->smmu;
1043
1044         for (i = 0; i < ARRAY_SIZE(stats); i++) {
1045                 u32 val;
1046                 size_t offs;
1047
1048                 offs = SMMU_STATS_CACHE_COUNT(info->mc, info->cache, i);
1049                 val = smmu_read(smmu, offs);
1050                 seq_printf(s, "%s:%08x ", stats[i], val);
1051
1052                 dev_dbg(smmu->dev, "%s() %s %08x @%08x\n", __func__,
1053                         stats[i], val, offs);
1054         }
1055         seq_printf(s, "\n");
1056         dput(dent);
1057
1058         return 0;
1059 }
1060
1061 static int smmu_debugfs_stats_open(struct inode *inode, struct file *file)
1062 {
1063         return single_open(file, smmu_debugfs_stats_show, inode);
1064 }
1065
1066 static const struct file_operations smmu_debugfs_stats_fops = {
1067         .open           = smmu_debugfs_stats_open,
1068         .read           = seq_read,
1069         .llseek         = seq_lseek,
1070         .release        = single_release,
1071         .write          = smmu_debugfs_stats_write,
1072 };
1073
1074 static void smmu_debugfs_delete(struct smmu_device *smmu)
1075 {
1076         debugfs_remove_recursive(smmu->debugfs_root);
1077         kfree(smmu->debugfs_info);
1078 }
1079
1080 static void smmu_debugfs_create(struct smmu_device *smmu)
1081 {
1082         int i;
1083         size_t bytes;
1084         struct dentry *root;
1085
1086         bytes = ARRAY_SIZE(smmu_debugfs_mc) * ARRAY_SIZE(smmu_debugfs_cache) *
1087                 sizeof(*smmu->debugfs_info);
1088         smmu->debugfs_info = kmalloc(bytes, GFP_KERNEL);
1089         if (!smmu->debugfs_info)
1090                 return;
1091
1092         root = debugfs_create_dir(dev_name(smmu->dev), NULL);
1093         if (!root)
1094                 goto err_out;
1095         smmu->debugfs_root = root;
1096
1097         for (i = 0; i < ARRAY_SIZE(smmu_debugfs_mc); i++) {
1098                 int j;
1099                 struct dentry *mc;
1100
1101                 mc = debugfs_create_dir(smmu_debugfs_mc[i], root);
1102                 if (!mc)
1103                         goto err_out;
1104
1105                 for (j = 0; j < ARRAY_SIZE(smmu_debugfs_cache); j++) {
1106                         struct dentry *cache;
1107                         struct smmu_debugfs_info *info;
1108
1109                         info = smmu->debugfs_info;
1110                         info += i * ARRAY_SIZE(smmu_debugfs_mc) + j;
1111                         info->smmu = smmu;
1112                         info->mc = i;
1113                         info->cache = j;
1114
1115                         cache = debugfs_create_file(smmu_debugfs_cache[j],
1116                                                     S_IWUGO | S_IRUGO, mc,
1117                                                     (void *)info,
1118                                                     &smmu_debugfs_stats_fops);
1119                         if (!cache)
1120                                 goto err_out;
1121                 }
1122         }
1123
1124         return;
1125
1126 err_out:
1127         smmu_debugfs_delete(smmu);
1128 }
1129
1130 static int tegra_smmu_suspend(struct device *dev)
1131 {
1132         struct smmu_device *smmu = dev_get_drvdata(dev);
1133
1134         smmu->translation_enable_0 = smmu_read(smmu, SMMU_TRANSLATION_ENABLE_0);
1135         smmu->translation_enable_1 = smmu_read(smmu, SMMU_TRANSLATION_ENABLE_1);
1136         smmu->translation_enable_2 = smmu_read(smmu, SMMU_TRANSLATION_ENABLE_2);
1137         smmu->asid_security = smmu_read(smmu, SMMU_ASID_SECURITY);
1138         return 0;
1139 }
1140
1141 static int tegra_smmu_resume(struct device *dev)
1142 {
1143         struct smmu_device *smmu = dev_get_drvdata(dev);
1144         unsigned long flags;
1145         int err;
1146
1147         spin_lock_irqsave(&smmu->lock, flags);
1148         err = smmu_setup_regs(smmu);
1149         spin_unlock_irqrestore(&smmu->lock, flags);
1150         return err;
1151 }
1152
1153 static int tegra_smmu_probe(struct platform_device *pdev)
1154 {
1155         struct smmu_device *smmu;
1156         struct device *dev = &pdev->dev;
1157         int i, asids, err = 0;
1158         dma_addr_t uninitialized_var(base);
1159         size_t bytes, uninitialized_var(size);
1160
1161         if (smmu_handle)
1162                 return -EIO;
1163
1164         BUILD_BUG_ON(PAGE_SHIFT != SMMU_PAGE_SHIFT);
1165
1166         if (of_property_read_u32(dev->of_node, "nvidia,#asids", &asids))
1167                 return -ENODEV;
1168
1169         bytes = sizeof(*smmu) + asids * sizeof(*smmu->as);
1170         smmu = devm_kzalloc(dev, bytes, GFP_KERNEL);
1171         if (!smmu) {
1172                 dev_err(dev, "failed to allocate smmu_device\n");
1173                 return -ENOMEM;
1174         }
1175
1176         smmu->nregs = pdev->num_resources;
1177         smmu->regs = devm_kzalloc(dev, 2 * smmu->nregs * sizeof(*smmu->regs),
1178                                   GFP_KERNEL);
1179         smmu->rege = smmu->regs + smmu->nregs;
1180         if (!smmu->regs)
1181                 return -ENOMEM;
1182         for (i = 0; i < smmu->nregs; i++) {
1183                 struct resource *res;
1184
1185                 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
1186                 if (!res)
1187                         return -ENODEV;
1188                 smmu->regs[i] = devm_request_and_ioremap(&pdev->dev, res);
1189                 if (!smmu->regs[i])
1190                         return -EBUSY;
1191                 smmu->rege[i] = smmu->regs[i] + resource_size(res) - 1;
1192         }
1193         /* Same as "mc" 1st regiter block start address */
1194         smmu->regbase = (void __iomem *)((u32)smmu->regs[0] & ~PAGE_MASK);
1195
1196         err = of_get_dma_window(dev->of_node, NULL, 0, NULL, &base, &size);
1197         if (err)
1198                 return -ENODEV;
1199
1200         if (size & SMMU_PAGE_MASK)
1201                 return -EINVAL;
1202
1203         size >>= SMMU_PAGE_SHIFT;
1204         if (!size)
1205                 return -EINVAL;
1206
1207         smmu->ahb = of_parse_phandle(dev->of_node, "nvidia,ahb", 0);
1208         if (!smmu->ahb)
1209                 return -ENODEV;
1210
1211         smmu->dev = dev;
1212         smmu->num_as = asids;
1213         smmu->iovmm_base = base;
1214         smmu->page_count = size;
1215
1216         smmu->translation_enable_0 = ~0;
1217         smmu->translation_enable_1 = ~0;
1218         smmu->translation_enable_2 = ~0;
1219         smmu->asid_security = 0;
1220
1221         for (i = 0; i < smmu->num_as; i++) {
1222                 struct smmu_as *as = &smmu->as[i];
1223
1224                 as->smmu = smmu;
1225                 as->asid = i;
1226                 as->pdir_attr = _PDIR_ATTR;
1227                 as->pde_attr = _PDE_ATTR;
1228                 as->pte_attr = _PTE_ATTR;
1229
1230                 spin_lock_init(&as->lock);
1231                 spin_lock_init(&as->client_lock);
1232                 INIT_LIST_HEAD(&as->client);
1233         }
1234         spin_lock_init(&smmu->lock);
1235         err = smmu_setup_regs(smmu);
1236         if (err)
1237                 return err;
1238         platform_set_drvdata(pdev, smmu);
1239
1240         smmu->avp_vector_page = alloc_page(GFP_KERNEL);
1241         if (!smmu->avp_vector_page)
1242                 return -ENOMEM;
1243
1244         smmu_debugfs_create(smmu);
1245         smmu_handle = smmu;
1246         bus_set_iommu(&platform_bus_type, &smmu_iommu_ops);
1247         return 0;
1248 }
1249
1250 static int tegra_smmu_remove(struct platform_device *pdev)
1251 {
1252         struct smmu_device *smmu = platform_get_drvdata(pdev);
1253         int i;
1254
1255         smmu_debugfs_delete(smmu);
1256
1257         smmu_write(smmu, SMMU_CONFIG_DISABLE, SMMU_CONFIG);
1258         for (i = 0; i < smmu->num_as; i++)
1259                 free_pdir(&smmu->as[i]);
1260         __free_page(smmu->avp_vector_page);
1261         smmu_handle = NULL;
1262         return 0;
1263 }
1264
1265 const struct dev_pm_ops tegra_smmu_pm_ops = {
1266         .suspend        = tegra_smmu_suspend,
1267         .resume         = tegra_smmu_resume,
1268 };
1269
1270 #ifdef CONFIG_OF
1271 static struct of_device_id tegra_smmu_of_match[] = {
1272         { .compatible = "nvidia,tegra30-smmu", },
1273         { },
1274 };
1275 MODULE_DEVICE_TABLE(of, tegra_smmu_of_match);
1276 #endif
1277
1278 static struct platform_driver tegra_smmu_driver = {
1279         .probe          = tegra_smmu_probe,
1280         .remove         = tegra_smmu_remove,
1281         .driver = {
1282                 .owner  = THIS_MODULE,
1283                 .name   = "tegra-smmu",
1284                 .pm     = &tegra_smmu_pm_ops,
1285                 .of_match_table = of_match_ptr(tegra_smmu_of_match),
1286         },
1287 };
1288
1289 static int tegra_smmu_init(void)
1290 {
1291         return platform_driver_register(&tegra_smmu_driver);
1292 }
1293
1294 static void __exit tegra_smmu_exit(void)
1295 {
1296         platform_driver_unregister(&tegra_smmu_driver);
1297 }
1298
1299 subsys_initcall(tegra_smmu_init);
1300 module_exit(tegra_smmu_exit);
1301
1302 MODULE_DESCRIPTION("IOMMU API for SMMU in Tegra30");
1303 MODULE_AUTHOR("Hiroshi DOYU <hdoyu@nvidia.com>");
1304 MODULE_ALIAS("platform:tegra-smmu");
1305 MODULE_LICENSE("GPL v2");