8 select IRQ_DOMAIN_HIERARCHY
9 select MULTI_IRQ_HANDLER
14 depends on PCI && PCI_MSI
15 select PCI_MSI_IRQ_DOMAIN
23 select MULTI_IRQ_HANDLER
24 select IRQ_DOMAIN_HIERARCHY
28 select PCI_MSI_IRQ_DOMAIN
33 select IRQ_DOMAIN_HIERARCHY
34 select GENERIC_IRQ_CHIP
39 select MULTI_IRQ_HANDLER
43 default 4 if ARCH_S5PV210
47 The maximum number of VICs available in the system, for
52 select GENERIC_IRQ_CHIP
54 select MULTI_IRQ_HANDLER
59 select GENERIC_IRQ_CHIP
61 select MULTI_IRQ_HANDLER
70 select GENERIC_IRQ_CHIP
75 select GENERIC_IRQ_CHIP
80 select GENERIC_IRQ_CHIP
85 select GENERIC_IRQ_CHIP
90 select GENERIC_IRQ_CHIP
95 select GENERIC_IRQ_CHIP
98 config CLPS711X_IRQCHIP
100 depends on ARCH_CLPS711X
102 select MULTI_IRQ_HANDLER
112 select GENERIC_IRQ_CHIP
118 select MULTI_IRQ_HANDLER
120 config RENESAS_INTC_IRQPIN
126 select GENERIC_IRQ_CHIP
134 Enables SysCfg Controlled IRQs on STi based platforms.
139 select GENERIC_IRQ_CHIP
141 config VERSATILE_FPGA_IRQ
145 config VERSATILE_FPGA_IRQ_NR
148 depends on VERSATILE_FPGA_IRQ
157 Support for a CROSSBAR ip that precedes the main interrupt controller.
158 The primary irqchip invokes the crossbar's callback which inturn allocates
159 a free irq and configures the IP. Thus the peripheral interrupts are
160 routed to one of the free irqchip interrupt lines.
163 tristate "Keystone 2 IRQ controller IP"
164 depends on ARCH_KEYSTONE
166 Support for Texas Instruments Keystone 2 IRQ controller IP which
167 is part of the Keystone 2 IPC mechanism
175 depends on MACH_INGENIC
178 config RENESAS_H8300H_INTC
182 config RENESAS_H8S_INTC
190 Enables the wakeup IRQs for IMX platforms with GPCv2 block