8 select IRQ_DOMAIN_HIERARCHY
9 select MULTI_IRQ_HANDLER
17 select MULTI_IRQ_HANDLER
18 select IRQ_DOMAIN_HIERARCHY
22 select PCI_MSI_IRQ_DOMAIN
27 select GENERIC_IRQ_CHIP
32 select MULTI_IRQ_HANDLER
36 default 4 if ARCH_S5PV210
40 The maximum number of VICs available in the system, for
45 select GENERIC_IRQ_CHIP
47 select MULTI_IRQ_HANDLER
52 select GENERIC_IRQ_CHIP
54 select MULTI_IRQ_HANDLER
60 select GENERIC_IRQ_CHIP
69 select GENERIC_IRQ_CHIP
72 config CLPS711X_IRQCHIP
74 depends on ARCH_CLPS711X
76 select MULTI_IRQ_HANDLER
86 select GENERIC_IRQ_CHIP
92 select MULTI_IRQ_HANDLER
94 config RENESAS_INTC_IRQPIN
105 select GENERIC_IRQ_CHIP
107 config VERSATILE_FPGA_IRQ
111 config VERSATILE_FPGA_IRQ_NR
114 depends on VERSATILE_FPGA_IRQ
123 Support for a CROSSBAR ip that precedes the main interrupt controller.
124 The primary irqchip invokes the crossbar's callback which inturn allocates
125 a free irq and configures the IP. Thus the peripheral interrupts are
126 routed to one of the free irqchip interrupt lines.
129 tristate "Keystone 2 IRQ controller IP"
130 depends on ARCH_KEYSTONE
132 Support for Texas Instruments Keystone 2 IRQ controller IP which
133 is part of the Keystone 2 IPC mechanism