8 select IRQ_DOMAIN_HIERARCHY
9 select MULTI_IRQ_HANDLER
14 depends on PCI && PCI_MSI
15 select PCI_MSI_IRQ_DOMAIN
23 select MULTI_IRQ_HANDLER
24 select IRQ_DOMAIN_HIERARCHY
28 select PCI_MSI_IRQ_DOMAIN
33 select GENERIC_IRQ_CHIP
38 select MULTI_IRQ_HANDLER
42 default 4 if ARCH_S5PV210
46 The maximum number of VICs available in the system, for
51 select GENERIC_IRQ_CHIP
53 select MULTI_IRQ_HANDLER
58 select GENERIC_IRQ_CHIP
60 select MULTI_IRQ_HANDLER
65 select GENERIC_IRQ_CHIP
70 select GENERIC_IRQ_CHIP
75 select GENERIC_IRQ_CHIP
80 select GENERIC_IRQ_CHIP
85 select GENERIC_IRQ_CHIP
88 config CLPS711X_IRQCHIP
90 depends on ARCH_CLPS711X
92 select MULTI_IRQ_HANDLER
102 select GENERIC_IRQ_CHIP
108 select MULTI_IRQ_HANDLER
110 config RENESAS_INTC_IRQPIN
121 select GENERIC_IRQ_CHIP
123 config VERSATILE_FPGA_IRQ
127 config VERSATILE_FPGA_IRQ_NR
130 depends on VERSATILE_FPGA_IRQ
139 Support for a CROSSBAR ip that precedes the main interrupt controller.
140 The primary irqchip invokes the crossbar's callback which inturn allocates
141 a free irq and configures the IP. Thus the peripheral interrupts are
142 routed to one of the free irqchip interrupt lines.
145 tristate "Keystone 2 IRQ controller IP"
146 depends on ARCH_KEYSTONE
148 Support for Texas Instruments Keystone 2 IRQ controller IP which
149 is part of the Keystone 2 IPC mechanism