8 select IRQ_DOMAIN_HIERARCHY
9 select MULTI_IRQ_HANDLER
14 depends on PCI && PCI_MSI
15 select PCI_MSI_IRQ_DOMAIN
23 select MULTI_IRQ_HANDLER
24 select IRQ_DOMAIN_HIERARCHY
25 select PARTITION_PERCPU
29 select PCI_MSI_IRQ_DOMAIN
34 select IRQ_DOMAIN_HIERARCHY
35 select GENERIC_IRQ_CHIP
40 select MULTI_IRQ_HANDLER
44 default 4 if ARCH_S5PV210
48 The maximum number of VICs available in the system, for
53 select GENERIC_IRQ_CHIP
55 select MULTI_IRQ_HANDLER
60 select GENERIC_IRQ_CHIP
62 select MULTI_IRQ_HANDLER
71 select GENERIC_IRQ_CHIP
76 select GENERIC_IRQ_CHIP
81 select GENERIC_IRQ_CHIP
86 select GENERIC_IRQ_CHIP
91 select GENERIC_IRQ_CHIP
96 select GENERIC_IRQ_CHIP
99 config CLPS711X_IRQCHIP
101 depends on ARCH_CLPS711X
103 select MULTI_IRQ_HANDLER
113 select GENERIC_IRQ_CHIP
119 select MULTI_IRQ_HANDLER
121 config RENESAS_INTC_IRQPIN
127 select GENERIC_IRQ_CHIP
135 Enables SysCfg Controlled IRQs on STi based platforms.
140 select GENERIC_IRQ_CHIP
142 config VERSATILE_FPGA_IRQ
146 config VERSATILE_FPGA_IRQ_NR
149 depends on VERSATILE_FPGA_IRQ
158 Support for a CROSSBAR ip that precedes the main interrupt controller.
159 The primary irqchip invokes the crossbar's callback which inturn allocates
160 a free irq and configures the IP. Thus the peripheral interrupts are
161 routed to one of the free irqchip interrupt lines.
164 tristate "Keystone 2 IRQ controller IP"
165 depends on ARCH_KEYSTONE
167 Support for Texas Instruments Keystone 2 IRQ controller IP which
168 is part of the Keystone 2 IPC mechanism
176 depends on MACH_INGENIC
179 config RENESAS_H8300H_INTC
183 config RENESAS_H8S_INTC
191 Enables the wakeup IRQs for IMX platforms with GPCv2 block
194 def_bool y if MACH_ASM9260 || ARCH_MXS
198 config PARTITION_PERCPU