2 * Marvell Armada 370 and Armada XP SoC IRQ handling
4 * Copyright (C) 2012 Marvell
6 * Lior Amsalem <alior@marvell.com>
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 * Ben Dooks <ben.dooks@codethink.co.uk>
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/init.h>
19 #include <linux/irq.h>
20 #include <linux/interrupt.h>
21 #include <linux/irqchip.h>
22 #include <linux/irqchip/chained_irq.h>
23 #include <linux/cpu.h>
25 #include <linux/of_address.h>
26 #include <linux/of_irq.h>
27 #include <linux/of_pci.h>
28 #include <linux/irqdomain.h>
29 #include <linux/slab.h>
30 #include <linux/syscore_ops.h>
31 #include <linux/msi.h>
32 #include <asm/mach/arch.h>
33 #include <asm/exception.h>
34 #include <asm/smp_plat.h>
35 #include <asm/mach/irq.h>
37 /* Interrupt Controller Registers Map */
38 #define ARMADA_370_XP_INT_SET_MASK_OFFS (0x48)
39 #define ARMADA_370_XP_INT_CLEAR_MASK_OFFS (0x4C)
40 #define ARMADA_370_XP_INT_FABRIC_MASK_OFFS (0x54)
41 #define ARMADA_370_XP_INT_CAUSE_PERF(cpu) (1 << cpu)
43 #define ARMADA_370_XP_INT_CONTROL (0x00)
44 #define ARMADA_370_XP_INT_SET_ENABLE_OFFS (0x30)
45 #define ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS (0x34)
46 #define ARMADA_370_XP_INT_SOURCE_CTL(irq) (0x100 + irq*4)
47 #define ARMADA_370_XP_INT_SOURCE_CPU_MASK 0xF
48 #define ARMADA_370_XP_INT_IRQ_FIQ_MASK(cpuid) ((BIT(0) | BIT(8)) << cpuid)
50 #define ARMADA_370_XP_CPU_INTACK_OFFS (0x44)
51 #define ARMADA_375_PPI_CAUSE (0x10)
53 #define ARMADA_370_XP_SW_TRIG_INT_OFFS (0x4)
54 #define ARMADA_370_XP_IN_DRBEL_MSK_OFFS (0xc)
55 #define ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS (0x8)
57 #define ARMADA_370_XP_MAX_PER_CPU_IRQS (28)
59 #define IPI_DOORBELL_START (0)
60 #define IPI_DOORBELL_END (8)
61 #define IPI_DOORBELL_MASK 0xFF
62 #define PCI_MSI_DOORBELL_START (16)
63 #define PCI_MSI_DOORBELL_NR (16)
64 #define PCI_MSI_DOORBELL_END (32)
65 #define PCI_MSI_DOORBELL_MASK 0xFFFF0000
67 static void __iomem *per_cpu_int_base;
68 static void __iomem *main_int_base;
69 static struct irq_domain *armada_370_xp_mpic_domain;
70 static u32 doorbell_mask_reg;
71 static int parent_irq;
73 static struct irq_domain *armada_370_xp_msi_domain;
74 static DECLARE_BITMAP(msi_used, PCI_MSI_DOORBELL_NR);
75 static DEFINE_MUTEX(msi_used_lock);
76 static phys_addr_t msi_doorbell_addr;
79 static inline bool is_percpu_irq(irq_hw_number_t irq)
81 if (irq <= ARMADA_370_XP_MAX_PER_CPU_IRQS)
89 * For shared global interrupts, mask/unmask global enable bit
90 * For CPU interrupts, mask/unmask the calling CPU's bit
92 static void armada_370_xp_irq_mask(struct irq_data *d)
94 irq_hw_number_t hwirq = irqd_to_hwirq(d);
96 if (!is_percpu_irq(hwirq))
97 writel(hwirq, main_int_base +
98 ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS);
100 writel(hwirq, per_cpu_int_base +
101 ARMADA_370_XP_INT_SET_MASK_OFFS);
104 static void armada_370_xp_irq_unmask(struct irq_data *d)
106 irq_hw_number_t hwirq = irqd_to_hwirq(d);
108 if (!is_percpu_irq(hwirq))
109 writel(hwirq, main_int_base +
110 ARMADA_370_XP_INT_SET_ENABLE_OFFS);
112 writel(hwirq, per_cpu_int_base +
113 ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
116 #ifdef CONFIG_PCI_MSI
118 static int armada_370_xp_alloc_msi(void)
122 mutex_lock(&msi_used_lock);
123 hwirq = find_first_zero_bit(&msi_used, PCI_MSI_DOORBELL_NR);
124 if (hwirq >= PCI_MSI_DOORBELL_NR)
127 set_bit(hwirq, msi_used);
128 mutex_unlock(&msi_used_lock);
133 static void armada_370_xp_free_msi(int hwirq)
135 mutex_lock(&msi_used_lock);
136 if (!test_bit(hwirq, msi_used))
137 pr_err("trying to free unused MSI#%d\n", hwirq);
139 clear_bit(hwirq, msi_used);
140 mutex_unlock(&msi_used_lock);
143 static int armada_370_xp_setup_msi_irq(struct msi_controller *chip,
144 struct pci_dev *pdev,
145 struct msi_desc *desc)
150 /* We support MSI, but not MSI-X */
151 if (desc->msi_attrib.is_msix)
154 hwirq = armada_370_xp_alloc_msi();
158 virq = irq_create_mapping(armada_370_xp_msi_domain, hwirq);
160 armada_370_xp_free_msi(hwirq);
164 irq_set_msi_desc(virq, desc);
166 msg.address_lo = msi_doorbell_addr;
168 msg.data = 0xf00 | (hwirq + 16);
170 pci_write_msi_msg(virq, &msg);
174 static void armada_370_xp_teardown_msi_irq(struct msi_controller *chip,
177 struct irq_data *d = irq_get_irq_data(irq);
178 unsigned long hwirq = d->hwirq;
180 irq_dispose_mapping(irq);
181 armada_370_xp_free_msi(hwirq);
184 static struct irq_chip armada_370_xp_msi_irq_chip = {
185 .name = "armada_370_xp_msi_irq",
186 .irq_enable = pci_msi_unmask_irq,
187 .irq_disable = pci_msi_mask_irq,
188 .irq_mask = pci_msi_mask_irq,
189 .irq_unmask = pci_msi_unmask_irq,
192 static int armada_370_xp_msi_map(struct irq_domain *domain, unsigned int virq,
195 irq_set_chip_and_handler(virq, &armada_370_xp_msi_irq_chip,
201 static const struct irq_domain_ops armada_370_xp_msi_irq_ops = {
202 .map = armada_370_xp_msi_map,
205 static int armada_370_xp_msi_init(struct device_node *node,
206 phys_addr_t main_int_phys_base)
208 struct msi_controller *msi_chip;
212 msi_doorbell_addr = main_int_phys_base +
213 ARMADA_370_XP_SW_TRIG_INT_OFFS;
215 msi_chip = kzalloc(sizeof(*msi_chip), GFP_KERNEL);
219 msi_chip->setup_irq = armada_370_xp_setup_msi_irq;
220 msi_chip->teardown_irq = armada_370_xp_teardown_msi_irq;
221 msi_chip->of_node = node;
223 armada_370_xp_msi_domain =
224 irq_domain_add_linear(NULL, PCI_MSI_DOORBELL_NR,
225 &armada_370_xp_msi_irq_ops,
227 if (!armada_370_xp_msi_domain) {
232 ret = of_pci_msi_chip_add(msi_chip);
234 irq_domain_remove(armada_370_xp_msi_domain);
239 reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS)
240 | PCI_MSI_DOORBELL_MASK;
242 writel(reg, per_cpu_int_base +
243 ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
245 /* Unmask IPI interrupt */
246 writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
251 static inline int armada_370_xp_msi_init(struct device_node *node,
252 phys_addr_t main_int_phys_base)
259 static DEFINE_RAW_SPINLOCK(irq_controller_lock);
261 static int armada_xp_set_affinity(struct irq_data *d,
262 const struct cpumask *mask_val, bool force)
264 irq_hw_number_t hwirq = irqd_to_hwirq(d);
265 unsigned long reg, mask;
268 /* Select a single core from the affinity mask which is online */
269 cpu = cpumask_any_and(mask_val, cpu_online_mask);
270 mask = 1UL << cpu_logical_map(cpu);
272 raw_spin_lock(&irq_controller_lock);
273 reg = readl(main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq));
274 reg = (reg & (~ARMADA_370_XP_INT_SOURCE_CPU_MASK)) | mask;
275 writel(reg, main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq));
276 raw_spin_unlock(&irq_controller_lock);
278 return IRQ_SET_MASK_OK;
282 static struct irq_chip armada_370_xp_irq_chip = {
283 .name = "armada_370_xp_irq",
284 .irq_mask = armada_370_xp_irq_mask,
285 .irq_mask_ack = armada_370_xp_irq_mask,
286 .irq_unmask = armada_370_xp_irq_unmask,
288 .irq_set_affinity = armada_xp_set_affinity,
290 .flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND,
293 static int armada_370_xp_mpic_irq_map(struct irq_domain *h,
294 unsigned int virq, irq_hw_number_t hw)
296 armada_370_xp_irq_mask(irq_get_irq_data(virq));
297 if (!is_percpu_irq(hw))
298 writel(hw, per_cpu_int_base +
299 ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
301 writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE_OFFS);
302 irq_set_status_flags(virq, IRQ_LEVEL);
304 if (is_percpu_irq(hw)) {
305 irq_set_percpu_devid(virq);
306 irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
307 handle_percpu_devid_irq);
310 irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
318 static void armada_xp_mpic_smp_cpu_init(void)
323 control = readl(main_int_base + ARMADA_370_XP_INT_CONTROL);
324 nr_irqs = (control >> 2) & 0x3ff;
326 for (i = 0; i < nr_irqs; i++)
327 writel(i, per_cpu_int_base + ARMADA_370_XP_INT_SET_MASK_OFFS);
329 /* Clear pending IPIs */
330 writel(0, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
332 /* Enable first 8 IPIs */
333 writel(IPI_DOORBELL_MASK, per_cpu_int_base +
334 ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
336 /* Unmask IPI interrupt */
337 writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
340 static void armada_xp_mpic_perf_init(void)
342 unsigned long cpuid = cpu_logical_map(smp_processor_id());
344 /* Enable Performance Counter Overflow interrupts */
345 writel(ARMADA_370_XP_INT_CAUSE_PERF(cpuid),
346 per_cpu_int_base + ARMADA_370_XP_INT_FABRIC_MASK_OFFS);
350 static void armada_mpic_send_doorbell(const struct cpumask *mask,
354 unsigned long map = 0;
356 /* Convert our logical CPU mask into a physical one. */
357 for_each_cpu(cpu, mask)
358 map |= 1 << cpu_logical_map(cpu);
361 * Ensure that stores to Normal memory are visible to the
362 * other CPUs before issuing the IPI.
367 writel((map << 8) | irq, main_int_base +
368 ARMADA_370_XP_SW_TRIG_INT_OFFS);
371 static int armada_xp_mpic_secondary_init(struct notifier_block *nfb,
372 unsigned long action, void *hcpu)
374 if (action == CPU_STARTING || action == CPU_STARTING_FROZEN) {
375 armada_xp_mpic_perf_init();
376 armada_xp_mpic_smp_cpu_init();
382 static struct notifier_block armada_370_xp_mpic_cpu_notifier = {
383 .notifier_call = armada_xp_mpic_secondary_init,
387 static int mpic_cascaded_secondary_init(struct notifier_block *nfb,
388 unsigned long action, void *hcpu)
390 if (action == CPU_STARTING || action == CPU_STARTING_FROZEN) {
391 armada_xp_mpic_perf_init();
392 enable_percpu_irq(parent_irq, IRQ_TYPE_NONE);
398 static struct notifier_block mpic_cascaded_cpu_notifier = {
399 .notifier_call = mpic_cascaded_secondary_init,
402 #endif /* CONFIG_SMP */
404 static const struct irq_domain_ops armada_370_xp_mpic_irq_ops = {
405 .map = armada_370_xp_mpic_irq_map,
406 .xlate = irq_domain_xlate_onecell,
409 #ifdef CONFIG_PCI_MSI
410 static void armada_370_xp_handle_msi_irq(struct pt_regs *regs, bool is_chained)
414 msimask = readl_relaxed(per_cpu_int_base +
415 ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS)
416 & PCI_MSI_DOORBELL_MASK;
418 writel(~msimask, per_cpu_int_base +
419 ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
421 for (msinr = PCI_MSI_DOORBELL_START;
422 msinr < PCI_MSI_DOORBELL_END; msinr++) {
425 if (!(msimask & BIT(msinr)))
429 irq = irq_find_mapping(armada_370_xp_msi_domain,
431 generic_handle_irq(irq);
434 handle_domain_irq(armada_370_xp_msi_domain,
440 static void armada_370_xp_handle_msi_irq(struct pt_regs *r, bool b) {}
443 static void armada_370_xp_mpic_handle_cascade_irq(struct irq_desc *desc)
445 struct irq_chip *chip = irq_desc_get_chip(desc);
446 unsigned long irqmap, irqn, irqsrc, cpuid;
447 unsigned int cascade_irq;
449 chained_irq_enter(chip, desc);
451 irqmap = readl_relaxed(per_cpu_int_base + ARMADA_375_PPI_CAUSE);
452 cpuid = cpu_logical_map(smp_processor_id());
454 for_each_set_bit(irqn, &irqmap, BITS_PER_LONG) {
455 irqsrc = readl_relaxed(main_int_base +
456 ARMADA_370_XP_INT_SOURCE_CTL(irqn));
458 /* Check if the interrupt is not masked on current CPU.
459 * Test IRQ (0-1) and FIQ (8-9) mask bits.
461 if (!(irqsrc & ARMADA_370_XP_INT_IRQ_FIQ_MASK(cpuid)))
465 armada_370_xp_handle_msi_irq(NULL, true);
469 cascade_irq = irq_find_mapping(armada_370_xp_mpic_domain, irqn);
470 generic_handle_irq(cascade_irq);
473 chained_irq_exit(chip, desc);
476 static void __exception_irq_entry
477 armada_370_xp_handle_irq(struct pt_regs *regs)
482 irqstat = readl_relaxed(per_cpu_int_base +
483 ARMADA_370_XP_CPU_INTACK_OFFS);
484 irqnr = irqstat & 0x3FF;
490 handle_domain_irq(armada_370_xp_mpic_domain,
497 armada_370_xp_handle_msi_irq(regs, false);
504 ipimask = readl_relaxed(per_cpu_int_base +
505 ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS)
508 writel(~ipimask, per_cpu_int_base +
509 ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
511 /* Handle all pending doorbells */
512 for (ipinr = IPI_DOORBELL_START;
513 ipinr < IPI_DOORBELL_END; ipinr++) {
514 if (ipimask & (0x1 << ipinr))
515 handle_IPI(ipinr, regs);
524 static int armada_370_xp_mpic_suspend(void)
526 doorbell_mask_reg = readl(per_cpu_int_base +
527 ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
531 static void armada_370_xp_mpic_resume(void)
536 /* Re-enable interrupts */
537 nirqs = (readl(main_int_base + ARMADA_370_XP_INT_CONTROL) >> 2) & 0x3ff;
538 for (irq = 0; irq < nirqs; irq++) {
539 struct irq_data *data;
542 virq = irq_linear_revmap(armada_370_xp_mpic_domain, irq);
546 if (!is_percpu_irq(irq))
547 writel(irq, per_cpu_int_base +
548 ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
550 writel(irq, main_int_base +
551 ARMADA_370_XP_INT_SET_ENABLE_OFFS);
553 data = irq_get_irq_data(virq);
554 if (!irqd_irq_disabled(data))
555 armada_370_xp_irq_unmask(data);
558 /* Reconfigure doorbells for IPIs and MSIs */
559 writel(doorbell_mask_reg,
560 per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
561 if (doorbell_mask_reg & IPI_DOORBELL_MASK)
562 writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
563 if (doorbell_mask_reg & PCI_MSI_DOORBELL_MASK)
564 writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
567 struct syscore_ops armada_370_xp_mpic_syscore_ops = {
568 .suspend = armada_370_xp_mpic_suspend,
569 .resume = armada_370_xp_mpic_resume,
572 static int __init armada_370_xp_mpic_of_init(struct device_node *node,
573 struct device_node *parent)
575 struct resource main_int_res, per_cpu_int_res;
579 BUG_ON(of_address_to_resource(node, 0, &main_int_res));
580 BUG_ON(of_address_to_resource(node, 1, &per_cpu_int_res));
582 BUG_ON(!request_mem_region(main_int_res.start,
583 resource_size(&main_int_res),
585 BUG_ON(!request_mem_region(per_cpu_int_res.start,
586 resource_size(&per_cpu_int_res),
589 main_int_base = ioremap(main_int_res.start,
590 resource_size(&main_int_res));
591 BUG_ON(!main_int_base);
593 per_cpu_int_base = ioremap(per_cpu_int_res.start,
594 resource_size(&per_cpu_int_res));
595 BUG_ON(!per_cpu_int_base);
597 control = readl(main_int_base + ARMADA_370_XP_INT_CONTROL);
598 nr_irqs = (control >> 2) & 0x3ff;
600 for (i = 0; i < nr_irqs; i++)
601 writel(i, main_int_base + ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS);
603 armada_370_xp_mpic_domain =
604 irq_domain_add_linear(node, nr_irqs,
605 &armada_370_xp_mpic_irq_ops, NULL);
607 BUG_ON(!armada_370_xp_mpic_domain);
609 /* Setup for the boot CPU */
610 armada_xp_mpic_perf_init();
611 armada_xp_mpic_smp_cpu_init();
613 armada_370_xp_msi_init(node, main_int_res.start);
615 parent_irq = irq_of_parse_and_map(node, 0);
616 if (parent_irq <= 0) {
617 irq_set_default_host(armada_370_xp_mpic_domain);
618 set_handle_irq(armada_370_xp_handle_irq);
620 set_smp_cross_call(armada_mpic_send_doorbell);
621 register_cpu_notifier(&armada_370_xp_mpic_cpu_notifier);
625 register_cpu_notifier(&mpic_cascaded_cpu_notifier);
627 irq_set_chained_handler(parent_irq,
628 armada_370_xp_mpic_handle_cascade_irq);
631 register_syscore_ops(&armada_370_xp_mpic_syscore_ops);
636 IRQCHIP_DECLARE(armada_370_xp_mpic, "marvell,mpic", armada_370_xp_mpic_of_init);