2 * Marvell Armada 370 and Armada XP SoC IRQ handling
4 * Copyright (C) 2012 Marvell
6 * Lior Amsalem <alior@marvell.com>
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 * Ben Dooks <ben.dooks@codethink.co.uk>
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/init.h>
19 #include <linux/irq.h>
20 #include <linux/interrupt.h>
21 #include <linux/irqchip/chained_irq.h>
23 #include <linux/of_address.h>
24 #include <linux/of_irq.h>
25 #include <linux/of_pci.h>
26 #include <linux/irqdomain.h>
27 #include <linux/slab.h>
28 #include <linux/msi.h>
29 #include <asm/mach/arch.h>
30 #include <asm/exception.h>
31 #include <asm/smp_plat.h>
32 #include <asm/mach/irq.h>
36 /* Interrupt Controller Registers Map */
37 #define ARMADA_370_XP_INT_SET_MASK_OFFS (0x48)
38 #define ARMADA_370_XP_INT_CLEAR_MASK_OFFS (0x4C)
40 #define ARMADA_370_XP_INT_CONTROL (0x00)
41 #define ARMADA_370_XP_INT_SET_ENABLE_OFFS (0x30)
42 #define ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS (0x34)
43 #define ARMADA_370_XP_INT_SOURCE_CTL(irq) (0x100 + irq*4)
44 #define ARMADA_370_XP_INT_SOURCE_CPU_MASK 0xF
46 #define ARMADA_370_XP_CPU_INTACK_OFFS (0x44)
47 #define ARMADA_375_PPI_CAUSE (0x10)
49 #define ARMADA_370_XP_SW_TRIG_INT_OFFS (0x4)
50 #define ARMADA_370_XP_IN_DRBEL_MSK_OFFS (0xc)
51 #define ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS (0x8)
53 #define ARMADA_370_XP_MAX_PER_CPU_IRQS (28)
55 #define ARMADA_370_XP_TIMER0_PER_CPU_IRQ (5)
57 #define IPI_DOORBELL_START (0)
58 #define IPI_DOORBELL_END (8)
59 #define IPI_DOORBELL_MASK 0xFF
60 #define PCI_MSI_DOORBELL_START (16)
61 #define PCI_MSI_DOORBELL_NR (16)
62 #define PCI_MSI_DOORBELL_END (32)
63 #define PCI_MSI_DOORBELL_MASK 0xFFFF0000
65 static void __iomem *per_cpu_int_base;
66 static void __iomem *main_int_base;
67 static struct irq_domain *armada_370_xp_mpic_domain;
69 static struct irq_domain *armada_370_xp_msi_domain;
70 static DECLARE_BITMAP(msi_used, PCI_MSI_DOORBELL_NR);
71 static DEFINE_MUTEX(msi_used_lock);
72 static phys_addr_t msi_doorbell_addr;
77 * For shared global interrupts, mask/unmask global enable bit
78 * For CPU interrupts, mask/unmask the calling CPU's bit
80 static void armada_370_xp_irq_mask(struct irq_data *d)
82 irq_hw_number_t hwirq = irqd_to_hwirq(d);
84 if (hwirq != ARMADA_370_XP_TIMER0_PER_CPU_IRQ)
85 writel(hwirq, main_int_base +
86 ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS);
88 writel(hwirq, per_cpu_int_base +
89 ARMADA_370_XP_INT_SET_MASK_OFFS);
92 static void armada_370_xp_irq_unmask(struct irq_data *d)
94 irq_hw_number_t hwirq = irqd_to_hwirq(d);
96 if (hwirq != ARMADA_370_XP_TIMER0_PER_CPU_IRQ)
97 writel(hwirq, main_int_base +
98 ARMADA_370_XP_INT_SET_ENABLE_OFFS);
100 writel(hwirq, per_cpu_int_base +
101 ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
104 #ifdef CONFIG_PCI_MSI
106 static int armada_370_xp_alloc_msi(void)
110 mutex_lock(&msi_used_lock);
111 hwirq = find_first_zero_bit(&msi_used, PCI_MSI_DOORBELL_NR);
112 if (hwirq >= PCI_MSI_DOORBELL_NR)
115 set_bit(hwirq, msi_used);
116 mutex_unlock(&msi_used_lock);
121 static void armada_370_xp_free_msi(int hwirq)
123 mutex_lock(&msi_used_lock);
124 if (!test_bit(hwirq, msi_used))
125 pr_err("trying to free unused MSI#%d\n", hwirq);
127 clear_bit(hwirq, msi_used);
128 mutex_unlock(&msi_used_lock);
131 static int armada_370_xp_setup_msi_irq(struct msi_chip *chip,
132 struct pci_dev *pdev,
133 struct msi_desc *desc)
136 irq_hw_number_t hwirq;
139 hwirq = armada_370_xp_alloc_msi();
143 virq = irq_create_mapping(armada_370_xp_msi_domain, hwirq);
145 armada_370_xp_free_msi(hwirq);
149 irq_set_msi_desc(virq, desc);
151 msg.address_lo = msi_doorbell_addr;
153 msg.data = 0xf00 | (hwirq + 16);
155 write_msi_msg(virq, &msg);
159 static void armada_370_xp_teardown_msi_irq(struct msi_chip *chip,
162 struct irq_data *d = irq_get_irq_data(irq);
163 irq_dispose_mapping(irq);
164 armada_370_xp_free_msi(d->hwirq);
167 static struct irq_chip armada_370_xp_msi_irq_chip = {
168 .name = "armada_370_xp_msi_irq",
169 .irq_enable = unmask_msi_irq,
170 .irq_disable = mask_msi_irq,
171 .irq_mask = mask_msi_irq,
172 .irq_unmask = unmask_msi_irq,
175 static int armada_370_xp_msi_map(struct irq_domain *domain, unsigned int virq,
178 irq_set_chip_and_handler(virq, &armada_370_xp_msi_irq_chip,
180 set_irq_flags(virq, IRQF_VALID);
185 static const struct irq_domain_ops armada_370_xp_msi_irq_ops = {
186 .map = armada_370_xp_msi_map,
189 static int armada_370_xp_msi_init(struct device_node *node,
190 phys_addr_t main_int_phys_base)
192 struct msi_chip *msi_chip;
196 msi_doorbell_addr = main_int_phys_base +
197 ARMADA_370_XP_SW_TRIG_INT_OFFS;
199 msi_chip = kzalloc(sizeof(*msi_chip), GFP_KERNEL);
203 msi_chip->setup_irq = armada_370_xp_setup_msi_irq;
204 msi_chip->teardown_irq = armada_370_xp_teardown_msi_irq;
205 msi_chip->of_node = node;
207 armada_370_xp_msi_domain =
208 irq_domain_add_linear(NULL, PCI_MSI_DOORBELL_NR,
209 &armada_370_xp_msi_irq_ops,
211 if (!armada_370_xp_msi_domain) {
216 ret = of_pci_msi_chip_add(msi_chip);
218 irq_domain_remove(armada_370_xp_msi_domain);
223 reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS)
224 | PCI_MSI_DOORBELL_MASK;
226 writel(reg, per_cpu_int_base +
227 ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
229 /* Unmask IPI interrupt */
230 writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
235 static inline int armada_370_xp_msi_init(struct device_node *node,
236 phys_addr_t main_int_phys_base)
243 static DEFINE_RAW_SPINLOCK(irq_controller_lock);
245 static int armada_xp_set_affinity(struct irq_data *d,
246 const struct cpumask *mask_val, bool force)
248 irq_hw_number_t hwirq = irqd_to_hwirq(d);
249 unsigned long reg, mask;
252 /* Select a single core from the affinity mask which is online */
253 cpu = cpumask_any_and(mask_val, cpu_online_mask);
254 mask = 1UL << cpu_logical_map(cpu);
256 raw_spin_lock(&irq_controller_lock);
257 reg = readl(main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq));
258 reg = (reg & (~ARMADA_370_XP_INT_SOURCE_CPU_MASK)) | mask;
259 writel(reg, main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq));
260 raw_spin_unlock(&irq_controller_lock);
266 static struct irq_chip armada_370_xp_irq_chip = {
267 .name = "armada_370_xp_irq",
268 .irq_mask = armada_370_xp_irq_mask,
269 .irq_mask_ack = armada_370_xp_irq_mask,
270 .irq_unmask = armada_370_xp_irq_unmask,
272 .irq_set_affinity = armada_xp_set_affinity,
276 static int armada_370_xp_mpic_irq_map(struct irq_domain *h,
277 unsigned int virq, irq_hw_number_t hw)
279 armada_370_xp_irq_mask(irq_get_irq_data(virq));
280 if (hw != ARMADA_370_XP_TIMER0_PER_CPU_IRQ)
281 writel(hw, per_cpu_int_base +
282 ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
284 writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE_OFFS);
285 irq_set_status_flags(virq, IRQ_LEVEL);
287 if (hw == ARMADA_370_XP_TIMER0_PER_CPU_IRQ) {
288 irq_set_percpu_devid(virq);
289 irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
290 handle_percpu_devid_irq);
293 irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
296 set_irq_flags(virq, IRQF_VALID | IRQF_PROBE);
302 void armada_mpic_send_doorbell(const struct cpumask *mask, unsigned int irq)
305 unsigned long map = 0;
307 /* Convert our logical CPU mask into a physical one. */
308 for_each_cpu(cpu, mask)
309 map |= 1 << cpu_logical_map(cpu);
312 * Ensure that stores to Normal memory are visible to the
313 * other CPUs before issuing the IPI.
318 writel((map << 8) | irq, main_int_base +
319 ARMADA_370_XP_SW_TRIG_INT_OFFS);
322 void armada_xp_mpic_smp_cpu_init(void)
324 /* Clear pending IPIs */
325 writel(0, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
327 /* Enable first 8 IPIs */
328 writel(IPI_DOORBELL_MASK, per_cpu_int_base +
329 ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
331 /* Unmask IPI interrupt */
332 writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
334 #endif /* CONFIG_SMP */
336 static struct irq_domain_ops armada_370_xp_mpic_irq_ops = {
337 .map = armada_370_xp_mpic_irq_map,
338 .xlate = irq_domain_xlate_onecell,
341 #ifdef CONFIG_PCI_MSI
342 static void armada_370_xp_handle_msi_irq(struct pt_regs *regs, bool is_chained)
346 msimask = readl_relaxed(per_cpu_int_base +
347 ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS)
348 & PCI_MSI_DOORBELL_MASK;
350 writel(~msimask, per_cpu_int_base +
351 ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
353 for (msinr = PCI_MSI_DOORBELL_START;
354 msinr < PCI_MSI_DOORBELL_END; msinr++) {
357 if (!(msimask & BIT(msinr)))
360 irq = irq_find_mapping(armada_370_xp_msi_domain,
364 generic_handle_irq(irq);
366 handle_IRQ(irq, regs);
370 static void armada_370_xp_handle_msi_irq(struct pt_regs *r, bool b) {}
373 static void armada_370_xp_mpic_handle_cascade_irq(unsigned int irq,
374 struct irq_desc *desc)
376 struct irq_chip *chip = irq_get_chip(irq);
377 unsigned long irqmap, irqn;
378 unsigned int cascade_irq;
380 chained_irq_enter(chip, desc);
382 irqmap = readl_relaxed(per_cpu_int_base + ARMADA_375_PPI_CAUSE);
384 if (irqmap & BIT(0)) {
385 armada_370_xp_handle_msi_irq(NULL, true);
389 for_each_set_bit(irqn, &irqmap, BITS_PER_LONG) {
390 cascade_irq = irq_find_mapping(armada_370_xp_mpic_domain, irqn);
391 generic_handle_irq(cascade_irq);
394 chained_irq_exit(chip, desc);
397 static void __exception_irq_entry
398 armada_370_xp_handle_irq(struct pt_regs *regs)
403 irqstat = readl_relaxed(per_cpu_int_base +
404 ARMADA_370_XP_CPU_INTACK_OFFS);
405 irqnr = irqstat & 0x3FF;
411 irqnr = irq_find_mapping(armada_370_xp_mpic_domain,
413 handle_IRQ(irqnr, regs);
419 armada_370_xp_handle_msi_irq(regs, false);
426 ipimask = readl_relaxed(per_cpu_int_base +
427 ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS)
430 writel(~ipimask, per_cpu_int_base +
431 ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
433 /* Handle all pending doorbells */
434 for (ipinr = IPI_DOORBELL_START;
435 ipinr < IPI_DOORBELL_END; ipinr++) {
436 if (ipimask & (0x1 << ipinr))
437 handle_IPI(ipinr, regs);
446 static int __init armada_370_xp_mpic_of_init(struct device_node *node,
447 struct device_node *parent)
449 struct resource main_int_res, per_cpu_int_res;
453 BUG_ON(of_address_to_resource(node, 0, &main_int_res));
454 BUG_ON(of_address_to_resource(node, 1, &per_cpu_int_res));
456 BUG_ON(!request_mem_region(main_int_res.start,
457 resource_size(&main_int_res),
459 BUG_ON(!request_mem_region(per_cpu_int_res.start,
460 resource_size(&per_cpu_int_res),
463 main_int_base = ioremap(main_int_res.start,
464 resource_size(&main_int_res));
465 BUG_ON(!main_int_base);
467 per_cpu_int_base = ioremap(per_cpu_int_res.start,
468 resource_size(&per_cpu_int_res));
469 BUG_ON(!per_cpu_int_base);
471 control = readl(main_int_base + ARMADA_370_XP_INT_CONTROL);
473 armada_370_xp_mpic_domain =
474 irq_domain_add_linear(node, (control >> 2) & 0x3ff,
475 &armada_370_xp_mpic_irq_ops, NULL);
477 BUG_ON(!armada_370_xp_mpic_domain);
480 armada_xp_mpic_smp_cpu_init();
483 armada_370_xp_msi_init(node, main_int_res.start);
485 parent_irq = irq_of_parse_and_map(node, 0);
486 if (parent_irq <= 0) {
487 irq_set_default_host(armada_370_xp_mpic_domain);
488 set_handle_irq(armada_370_xp_handle_irq);
490 irq_set_chained_handler(parent_irq,
491 armada_370_xp_mpic_handle_cascade_irq);
497 IRQCHIP_DECLARE(armada_370_xp_mpic, "marvell,mpic", armada_370_xp_mpic_of_init);