2 * Broadcom BCM7038 style Level 1 interrupt controller driver
4 * Copyright (C) 2014 Broadcom Corporation
5 * Author: Kevin Cernekee
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
14 #include <linux/bitops.h>
15 #include <linux/kconfig.h>
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/interrupt.h>
20 #include <linux/ioport.h>
21 #include <linux/irq.h>
22 #include <linux/irqdomain.h>
23 #include <linux/module.h>
25 #include <linux/of_irq.h>
26 #include <linux/of_address.h>
27 #include <linux/of_platform.h>
28 #include <linux/platform_device.h>
29 #include <linux/slab.h>
30 #include <linux/smp.h>
31 #include <linux/types.h>
32 #include <linux/irqchip.h>
33 #include <linux/irqchip/chained_irq.h>
35 #define IRQS_PER_WORD 32
36 #define REG_BYTES_PER_IRQ_WORD (sizeof(u32) * 4)
39 struct bcm7038_l1_cpu;
41 struct bcm7038_l1_chip {
44 struct irq_domain *domain;
45 struct bcm7038_l1_cpu *cpus[NR_CPUS];
46 u8 affinity[MAX_WORDS * IRQS_PER_WORD];
49 struct bcm7038_l1_cpu {
50 void __iomem *map_base;
55 * STATUS/MASK_STATUS/MASK_SET/MASK_CLEAR are packed one right after another:
58 * 0x1000_1400: W0_STATUS
59 * 0x1000_1404: W1_STATUS
60 * 0x1000_1408: W0_MASK_STATUS
61 * 0x1000_140c: W1_MASK_STATUS
62 * 0x1000_1410: W0_MASK_SET
63 * 0x1000_1414: W1_MASK_SET
64 * 0x1000_1418: W0_MASK_CLEAR
65 * 0x1000_141c: W1_MASK_CLEAR
68 * 0xf03e_1500: W0_STATUS
69 * 0xf03e_1504: W1_STATUS
70 * 0xf03e_1508: W2_STATUS
71 * 0xf03e_150c: W3_STATUS
72 * 0xf03e_1510: W4_STATUS
73 * 0xf03e_1514: W0_MASK_STATUS
74 * 0xf03e_1518: W1_MASK_STATUS
78 static inline unsigned int reg_status(struct bcm7038_l1_chip *intc,
81 return (0 * intc->n_words + word) * sizeof(u32);
84 static inline unsigned int reg_mask_status(struct bcm7038_l1_chip *intc,
87 return (1 * intc->n_words + word) * sizeof(u32);
90 static inline unsigned int reg_mask_set(struct bcm7038_l1_chip *intc,
93 return (2 * intc->n_words + word) * sizeof(u32);
96 static inline unsigned int reg_mask_clr(struct bcm7038_l1_chip *intc,
99 return (3 * intc->n_words + word) * sizeof(u32);
102 static inline u32 l1_readl(void __iomem *reg)
104 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
105 return ioread32be(reg);
110 static inline void l1_writel(u32 val, void __iomem *reg)
112 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
113 iowrite32be(val, reg);
118 static void bcm7038_l1_irq_handle(unsigned int irq, struct irq_desc *desc)
120 struct bcm7038_l1_chip *intc = irq_desc_get_handler_data(desc);
121 struct bcm7038_l1_cpu *cpu;
122 struct irq_chip *chip = irq_desc_get_chip(desc);
126 cpu = intc->cpus[cpu_logical_map(smp_processor_id())];
131 chained_irq_enter(chip, desc);
133 for (idx = 0; idx < intc->n_words; idx++) {
134 int base = idx * IRQS_PER_WORD;
135 unsigned long pending, flags;
138 raw_spin_lock_irqsave(&intc->lock, flags);
139 pending = l1_readl(cpu->map_base + reg_status(intc, idx)) &
140 ~cpu->mask_cache[idx];
141 raw_spin_unlock_irqrestore(&intc->lock, flags);
143 for_each_set_bit(hwirq, &pending, IRQS_PER_WORD) {
144 generic_handle_irq(irq_find_mapping(intc->domain,
149 chained_irq_exit(chip, desc);
152 static void __bcm7038_l1_unmask(struct irq_data *d, unsigned int cpu_idx)
154 struct bcm7038_l1_chip *intc = irq_data_get_irq_chip_data(d);
155 u32 word = d->hwirq / IRQS_PER_WORD;
156 u32 mask = BIT(d->hwirq % IRQS_PER_WORD);
158 intc->cpus[cpu_idx]->mask_cache[word] &= ~mask;
159 l1_writel(mask, intc->cpus[cpu_idx]->map_base +
160 reg_mask_clr(intc, word));
163 static void __bcm7038_l1_mask(struct irq_data *d, unsigned int cpu_idx)
165 struct bcm7038_l1_chip *intc = irq_data_get_irq_chip_data(d);
166 u32 word = d->hwirq / IRQS_PER_WORD;
167 u32 mask = BIT(d->hwirq % IRQS_PER_WORD);
169 intc->cpus[cpu_idx]->mask_cache[word] |= mask;
170 l1_writel(mask, intc->cpus[cpu_idx]->map_base +
171 reg_mask_set(intc, word));
174 static void bcm7038_l1_unmask(struct irq_data *d)
176 struct bcm7038_l1_chip *intc = irq_data_get_irq_chip_data(d);
179 raw_spin_lock_irqsave(&intc->lock, flags);
180 __bcm7038_l1_unmask(d, intc->affinity[d->hwirq]);
181 raw_spin_unlock_irqrestore(&intc->lock, flags);
184 static void bcm7038_l1_mask(struct irq_data *d)
186 struct bcm7038_l1_chip *intc = irq_data_get_irq_chip_data(d);
189 raw_spin_lock_irqsave(&intc->lock, flags);
190 __bcm7038_l1_mask(d, intc->affinity[d->hwirq]);
191 raw_spin_unlock_irqrestore(&intc->lock, flags);
194 static int bcm7038_l1_set_affinity(struct irq_data *d,
195 const struct cpumask *dest,
198 struct bcm7038_l1_chip *intc = irq_data_get_irq_chip_data(d);
200 irq_hw_number_t hw = d->hwirq;
201 u32 word = hw / IRQS_PER_WORD;
202 u32 mask = BIT(hw % IRQS_PER_WORD);
203 unsigned int first_cpu = cpumask_any_and(dest, cpu_online_mask);
206 raw_spin_lock_irqsave(&intc->lock, flags);
208 was_disabled = !!(intc->cpus[intc->affinity[hw]]->mask_cache[word] &
210 __bcm7038_l1_mask(d, intc->affinity[hw]);
211 intc->affinity[hw] = first_cpu;
213 __bcm7038_l1_unmask(d, first_cpu);
215 raw_spin_unlock_irqrestore(&intc->lock, flags);
219 static int __init bcm7038_l1_init_one(struct device_node *dn,
221 struct bcm7038_l1_chip *intc)
225 struct bcm7038_l1_cpu *cpu;
226 unsigned int i, n_words, parent_irq;
228 if (of_address_to_resource(dn, idx, &res))
230 sz = resource_size(&res);
231 n_words = sz / REG_BYTES_PER_IRQ_WORD;
233 if (n_words > MAX_WORDS)
235 else if (!intc->n_words)
236 intc->n_words = n_words;
237 else if (intc->n_words != n_words)
240 cpu = intc->cpus[idx] = kzalloc(sizeof(*cpu) + n_words * sizeof(u32),
245 cpu->map_base = ioremap(res.start, sz);
249 for (i = 0; i < n_words; i++) {
250 l1_writel(0xffffffff, cpu->map_base + reg_mask_set(intc, i));
251 cpu->mask_cache[i] = 0xffffffff;
254 parent_irq = irq_of_parse_and_map(dn, idx);
256 pr_err("failed to map parent interrupt %d\n", parent_irq);
259 irq_set_handler_data(parent_irq, intc);
260 irq_set_chained_handler(parent_irq, bcm7038_l1_irq_handle);
265 static struct irq_chip bcm7038_l1_irq_chip = {
266 .name = "bcm7038-l1",
267 .irq_mask = bcm7038_l1_mask,
268 .irq_unmask = bcm7038_l1_unmask,
269 .irq_set_affinity = bcm7038_l1_set_affinity,
272 static int bcm7038_l1_map(struct irq_domain *d, unsigned int virq,
273 irq_hw_number_t hw_irq)
275 irq_set_chip_and_handler(virq, &bcm7038_l1_irq_chip, handle_level_irq);
276 irq_set_chip_data(virq, d->host_data);
280 static const struct irq_domain_ops bcm7038_l1_domain_ops = {
281 .xlate = irq_domain_xlate_onecell,
282 .map = bcm7038_l1_map,
285 int __init bcm7038_l1_of_init(struct device_node *dn,
286 struct device_node *parent)
288 struct bcm7038_l1_chip *intc;
291 intc = kzalloc(sizeof(*intc), GFP_KERNEL);
295 raw_spin_lock_init(&intc->lock);
296 for_each_possible_cpu(idx) {
297 ret = bcm7038_l1_init_one(dn, idx, intc);
301 pr_err("failed to remap intc L1 registers\n");
306 intc->domain = irq_domain_add_linear(dn, IRQS_PER_WORD * intc->n_words,
307 &bcm7038_l1_domain_ops,
314 pr_info("registered BCM7038 L1 intc (mem: 0x%p, IRQs: %d)\n",
315 intc->cpus[0]->map_base, IRQS_PER_WORD * intc->n_words);
320 for_each_possible_cpu(idx) {
321 struct bcm7038_l1_cpu *cpu = intc->cpus[idx];
325 iounmap(cpu->map_base);
334 IRQCHIP_DECLARE(bcm7038_l1, "brcm,bcm7038-l1-intc", bcm7038_l1_of_init);