2 * Copyright (C) 2013, 2014 ARM Limited, All Rights Reserved.
3 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 #include <linux/cpu.h>
19 #include <linux/cpu_pm.h>
20 #include <linux/delay.h>
21 #include <linux/interrupt.h>
23 #include <linux/of_address.h>
24 #include <linux/of_irq.h>
25 #include <linux/percpu.h>
26 #include <linux/slab.h>
28 #include <linux/irqchip.h>
29 #include <linux/irqchip/arm-gic-v3.h>
31 #include <asm/cputype.h>
32 #include <asm/exception.h>
33 #include <asm/smp_plat.h>
36 #include "irq-gic-common.h"
38 struct redist_region {
39 void __iomem *redist_base;
40 phys_addr_t phys_base;
43 struct gic_chip_data {
44 void __iomem *dist_base;
45 struct redist_region *redist_regions;
47 struct irq_domain *domain;
49 u32 nr_redist_regions;
53 static struct gic_chip_data gic_data __read_mostly;
54 static struct static_key supports_deactivate = STATIC_KEY_INIT_TRUE;
56 #define gic_data_rdist() (this_cpu_ptr(gic_data.rdists.rdist))
57 #define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base)
58 #define gic_data_rdist_sgi_base() (gic_data_rdist_rd_base() + SZ_64K)
60 /* Our default, arbitrary priority value. Linux only uses one anyway. */
61 #define DEFAULT_PMR_VALUE 0xf0
63 static inline unsigned int gic_irq(struct irq_data *d)
68 static inline int gic_irq_in_rdist(struct irq_data *d)
70 return gic_irq(d) < 32;
73 static inline void __iomem *gic_dist_base(struct irq_data *d)
75 if (gic_irq_in_rdist(d)) /* SGI+PPI -> SGI_base for this CPU */
76 return gic_data_rdist_sgi_base();
78 if (d->hwirq <= 1023) /* SPI -> dist_base */
79 return gic_data.dist_base;
84 static void gic_do_wait_for_rwp(void __iomem *base)
86 u32 count = 1000000; /* 1s! */
88 while (readl_relaxed(base + GICD_CTLR) & GICD_CTLR_RWP) {
91 pr_err_ratelimited("RWP timeout, gone fishing\n");
99 /* Wait for completion of a distributor change */
100 static void gic_dist_wait_for_rwp(void)
102 gic_do_wait_for_rwp(gic_data.dist_base);
105 /* Wait for completion of a redistributor change */
106 static void gic_redist_wait_for_rwp(void)
108 gic_do_wait_for_rwp(gic_data_rdist_rd_base());
111 /* Low level accessors */
112 static u64 __maybe_unused gic_read_iar(void)
116 asm volatile("mrs_s %0, " __stringify(ICC_IAR1_EL1) : "=r" (irqstat));
120 static void __maybe_unused gic_write_pmr(u64 val)
122 asm volatile("msr_s " __stringify(ICC_PMR_EL1) ", %0" : : "r" (val));
125 static void __maybe_unused gic_write_ctlr(u64 val)
127 asm volatile("msr_s " __stringify(ICC_CTLR_EL1) ", %0" : : "r" (val));
131 static void __maybe_unused gic_write_grpen1(u64 val)
133 asm volatile("msr_s " __stringify(ICC_GRPEN1_EL1) ", %0" : : "r" (val));
137 static void __maybe_unused gic_write_sgi1r(u64 val)
139 asm volatile("msr_s " __stringify(ICC_SGI1R_EL1) ", %0" : : "r" (val));
142 static void gic_enable_sre(void)
146 asm volatile("mrs_s %0, " __stringify(ICC_SRE_EL1) : "=r" (val));
147 val |= ICC_SRE_EL1_SRE;
148 asm volatile("msr_s " __stringify(ICC_SRE_EL1) ", %0" : : "r" (val));
152 * Need to check that the SRE bit has actually been set. If
153 * not, it means that SRE is disabled at EL2. We're going to
154 * die painfully, and there is nothing we can do about it.
156 * Kindly inform the luser.
158 asm volatile("mrs_s %0, " __stringify(ICC_SRE_EL1) : "=r" (val));
159 if (!(val & ICC_SRE_EL1_SRE))
160 pr_err("GIC: unable to set SRE (disabled at EL2), panic ahead\n");
163 static void gic_enable_redist(bool enable)
166 u32 count = 1000000; /* 1s! */
169 rbase = gic_data_rdist_rd_base();
171 val = readl_relaxed(rbase + GICR_WAKER);
173 /* Wake up this CPU redistributor */
174 val &= ~GICR_WAKER_ProcessorSleep;
176 val |= GICR_WAKER_ProcessorSleep;
177 writel_relaxed(val, rbase + GICR_WAKER);
179 if (!enable) { /* Check that GICR_WAKER is writeable */
180 val = readl_relaxed(rbase + GICR_WAKER);
181 if (!(val & GICR_WAKER_ProcessorSleep))
182 return; /* No PM support in this redistributor */
186 val = readl_relaxed(rbase + GICR_WAKER);
187 if (enable ^ (val & GICR_WAKER_ChildrenAsleep))
193 pr_err_ratelimited("redistributor failed to %s...\n",
194 enable ? "wakeup" : "sleep");
198 * Routines to disable, enable, EOI and route interrupts
200 static int gic_peek_irq(struct irq_data *d, u32 offset)
202 u32 mask = 1 << (gic_irq(d) % 32);
205 if (gic_irq_in_rdist(d))
206 base = gic_data_rdist_sgi_base();
208 base = gic_data.dist_base;
210 return !!(readl_relaxed(base + offset + (gic_irq(d) / 32) * 4) & mask);
213 static void gic_poke_irq(struct irq_data *d, u32 offset)
215 u32 mask = 1 << (gic_irq(d) % 32);
216 void (*rwp_wait)(void);
219 if (gic_irq_in_rdist(d)) {
220 base = gic_data_rdist_sgi_base();
221 rwp_wait = gic_redist_wait_for_rwp;
223 base = gic_data.dist_base;
224 rwp_wait = gic_dist_wait_for_rwp;
227 writel_relaxed(mask, base + offset + (gic_irq(d) / 32) * 4);
231 static void gic_mask_irq(struct irq_data *d)
233 gic_poke_irq(d, GICD_ICENABLER);
236 static void gic_eoimode1_mask_irq(struct irq_data *d)
240 * When masking a forwarded interrupt, make sure it is
241 * deactivated as well.
243 * This ensures that an interrupt that is getting
244 * disabled/masked will not get "stuck", because there is
245 * noone to deactivate it (guest is being terminated).
247 if (irqd_is_forwarded_to_vcpu(d))
248 gic_poke_irq(d, GICD_ICACTIVER);
251 static void gic_unmask_irq(struct irq_data *d)
253 gic_poke_irq(d, GICD_ISENABLER);
256 static int gic_irq_set_irqchip_state(struct irq_data *d,
257 enum irqchip_irq_state which, bool val)
261 if (d->hwirq >= gic_data.irq_nr) /* PPI/SPI only */
265 case IRQCHIP_STATE_PENDING:
266 reg = val ? GICD_ISPENDR : GICD_ICPENDR;
269 case IRQCHIP_STATE_ACTIVE:
270 reg = val ? GICD_ISACTIVER : GICD_ICACTIVER;
273 case IRQCHIP_STATE_MASKED:
274 reg = val ? GICD_ICENABLER : GICD_ISENABLER;
281 gic_poke_irq(d, reg);
285 static int gic_irq_get_irqchip_state(struct irq_data *d,
286 enum irqchip_irq_state which, bool *val)
288 if (d->hwirq >= gic_data.irq_nr) /* PPI/SPI only */
292 case IRQCHIP_STATE_PENDING:
293 *val = gic_peek_irq(d, GICD_ISPENDR);
296 case IRQCHIP_STATE_ACTIVE:
297 *val = gic_peek_irq(d, GICD_ISACTIVER);
300 case IRQCHIP_STATE_MASKED:
301 *val = !gic_peek_irq(d, GICD_ISENABLER);
311 static void gic_eoi_irq(struct irq_data *d)
313 gic_write_eoir(gic_irq(d));
316 static void gic_eoimode1_eoi_irq(struct irq_data *d)
319 * No need to deactivate an LPI, or an interrupt that
320 * is is getting forwarded to a vcpu.
322 if (gic_irq(d) >= 8192 || irqd_is_forwarded_to_vcpu(d))
324 gic_write_dir(gic_irq(d));
327 static int gic_set_type(struct irq_data *d, unsigned int type)
329 unsigned int irq = gic_irq(d);
330 void (*rwp_wait)(void);
333 /* Interrupt configuration for SGIs can't be changed */
337 /* SPIs have restrictions on the supported types */
338 if (irq >= 32 && type != IRQ_TYPE_LEVEL_HIGH &&
339 type != IRQ_TYPE_EDGE_RISING)
342 if (gic_irq_in_rdist(d)) {
343 base = gic_data_rdist_sgi_base();
344 rwp_wait = gic_redist_wait_for_rwp;
346 base = gic_data.dist_base;
347 rwp_wait = gic_dist_wait_for_rwp;
350 return gic_configure_irq(irq, type, base, rwp_wait);
353 static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu)
356 irqd_set_forwarded_to_vcpu(d);
358 irqd_clr_forwarded_to_vcpu(d);
362 static u64 gic_mpidr_to_affinity(u64 mpidr)
366 aff = (MPIDR_AFFINITY_LEVEL(mpidr, 3) << 32 |
367 MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 |
368 MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 |
369 MPIDR_AFFINITY_LEVEL(mpidr, 0));
374 static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
379 irqnr = gic_read_iar();
381 if (likely(irqnr > 15 && irqnr < 1020) || irqnr >= 8192) {
384 if (static_key_true(&supports_deactivate))
385 gic_write_eoir(irqnr);
387 err = handle_domain_irq(gic_data.domain, irqnr, regs);
389 WARN_ONCE(true, "Unexpected interrupt received!\n");
390 if (static_key_true(&supports_deactivate)) {
392 gic_write_dir(irqnr);
394 gic_write_eoir(irqnr);
400 gic_write_eoir(irqnr);
401 if (static_key_true(&supports_deactivate))
402 gic_write_dir(irqnr);
404 handle_IPI(irqnr, regs);
406 WARN_ONCE(true, "Unexpected SGI received!\n");
410 } while (irqnr != ICC_IAR1_EL1_SPURIOUS);
413 static void __init gic_dist_init(void)
417 void __iomem *base = gic_data.dist_base;
419 /* Disable the distributor */
420 writel_relaxed(0, base + GICD_CTLR);
421 gic_dist_wait_for_rwp();
423 gic_dist_config(base, gic_data.irq_nr, gic_dist_wait_for_rwp);
425 /* Enable distributor with ARE, Group1 */
426 writel_relaxed(GICD_CTLR_ARE_NS | GICD_CTLR_ENABLE_G1A | GICD_CTLR_ENABLE_G1,
430 * Set all global interrupts to the boot CPU only. ARE must be
433 affinity = gic_mpidr_to_affinity(cpu_logical_map(smp_processor_id()));
434 for (i = 32; i < gic_data.irq_nr; i++)
435 writeq_relaxed(affinity, base + GICD_IROUTER + i * 8);
438 static int gic_populate_rdist(void)
440 u64 mpidr = cpu_logical_map(smp_processor_id());
446 * Convert affinity to a 32bit value that can be matched to
447 * GICR_TYPER bits [63:32].
449 aff = (MPIDR_AFFINITY_LEVEL(mpidr, 3) << 24 |
450 MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 |
451 MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 |
452 MPIDR_AFFINITY_LEVEL(mpidr, 0));
454 for (i = 0; i < gic_data.nr_redist_regions; i++) {
455 void __iomem *ptr = gic_data.redist_regions[i].redist_base;
458 reg = readl_relaxed(ptr + GICR_PIDR2) & GIC_PIDR2_ARCH_MASK;
459 if (reg != GIC_PIDR2_ARCH_GICv3 &&
460 reg != GIC_PIDR2_ARCH_GICv4) { /* We're in trouble... */
461 pr_warn("No redistributor present @%p\n", ptr);
466 typer = readq_relaxed(ptr + GICR_TYPER);
467 if ((typer >> 32) == aff) {
468 u64 offset = ptr - gic_data.redist_regions[i].redist_base;
469 gic_data_rdist_rd_base() = ptr;
470 gic_data_rdist()->phys_base = gic_data.redist_regions[i].phys_base + offset;
471 pr_info("CPU%d: found redistributor %llx region %d:%pa\n",
473 (unsigned long long)mpidr,
474 i, &gic_data_rdist()->phys_base);
478 if (gic_data.redist_stride) {
479 ptr += gic_data.redist_stride;
481 ptr += SZ_64K * 2; /* Skip RD_base + SGI_base */
482 if (typer & GICR_TYPER_VLPIS)
483 ptr += SZ_64K * 2; /* Skip VLPI_base + reserved page */
485 } while (!(typer & GICR_TYPER_LAST));
488 /* We couldn't even deal with ourselves... */
489 WARN(true, "CPU%d: mpidr %llx has no re-distributor!\n",
490 smp_processor_id(), (unsigned long long)mpidr);
494 static void gic_cpu_sys_reg_init(void)
496 /* Enable system registers */
499 /* Set priority mask register */
500 gic_write_pmr(DEFAULT_PMR_VALUE);
502 if (static_key_true(&supports_deactivate)) {
503 /* EOI drops priority only (mode 1) */
504 gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop);
506 /* EOI deactivates interrupt too (mode 0) */
507 gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop_dir);
510 /* ... and let's hit the road... */
514 static int gic_dist_supports_lpis(void)
516 return !!(readl_relaxed(gic_data.dist_base + GICD_TYPER) & GICD_TYPER_LPIS);
519 static void gic_cpu_init(void)
523 /* Register ourselves with the rest of the world */
524 if (gic_populate_rdist())
527 gic_enable_redist(true);
529 rbase = gic_data_rdist_sgi_base();
531 gic_cpu_config(rbase, gic_redist_wait_for_rwp);
533 /* Give LPIs a spin */
534 if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis())
537 /* initialise system registers */
538 gic_cpu_sys_reg_init();
542 static int gic_secondary_init(struct notifier_block *nfb,
543 unsigned long action, void *hcpu)
545 if (action == CPU_STARTING || action == CPU_STARTING_FROZEN)
551 * Notifier for enabling the GIC CPU interface. Set an arbitrarily high
552 * priority because the GIC needs to be up before the ARM generic timers.
554 static struct notifier_block gic_cpu_notifier = {
555 .notifier_call = gic_secondary_init,
559 static u16 gic_compute_target_list(int *base_cpu, const struct cpumask *mask,
563 u64 mpidr = cpu_logical_map(cpu);
566 while (cpu < nr_cpu_ids) {
568 * If we ever get a cluster of more than 16 CPUs, just
569 * scream and skip that CPU.
571 if (WARN_ON((mpidr & 0xff) >= 16))
574 tlist |= 1 << (mpidr & 0xf);
576 cpu = cpumask_next(cpu, mask);
577 if (cpu >= nr_cpu_ids)
580 mpidr = cpu_logical_map(cpu);
582 if (cluster_id != (mpidr & ~0xffUL)) {
592 #define MPIDR_TO_SGI_AFFINITY(cluster_id, level) \
593 (MPIDR_AFFINITY_LEVEL(cluster_id, level) \
594 << ICC_SGI1R_AFFINITY_## level ##_SHIFT)
596 static void gic_send_sgi(u64 cluster_id, u16 tlist, unsigned int irq)
600 val = (MPIDR_TO_SGI_AFFINITY(cluster_id, 3) |
601 MPIDR_TO_SGI_AFFINITY(cluster_id, 2) |
602 irq << ICC_SGI1R_SGI_ID_SHIFT |
603 MPIDR_TO_SGI_AFFINITY(cluster_id, 1) |
604 tlist << ICC_SGI1R_TARGET_LIST_SHIFT);
606 pr_debug("CPU%d: ICC_SGI1R_EL1 %llx\n", smp_processor_id(), val);
607 gic_write_sgi1r(val);
610 static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
614 if (WARN_ON(irq >= 16))
618 * Ensure that stores to Normal memory are visible to the
619 * other CPUs before issuing the IPI.
623 for_each_cpu(cpu, mask) {
624 u64 cluster_id = cpu_logical_map(cpu) & ~0xffUL;
627 tlist = gic_compute_target_list(&cpu, mask, cluster_id);
628 gic_send_sgi(cluster_id, tlist, irq);
631 /* Force the above writes to ICC_SGI1R_EL1 to be executed */
635 static void gic_smp_init(void)
637 set_smp_cross_call(gic_raise_softirq);
638 register_cpu_notifier(&gic_cpu_notifier);
641 static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
644 unsigned int cpu = cpumask_any_and(mask_val, cpu_online_mask);
649 if (gic_irq_in_rdist(d))
652 /* If interrupt was enabled, disable it first */
653 enabled = gic_peek_irq(d, GICD_ISENABLER);
657 reg = gic_dist_base(d) + GICD_IROUTER + (gic_irq(d) * 8);
658 val = gic_mpidr_to_affinity(cpu_logical_map(cpu));
660 writeq_relaxed(val, reg);
663 * If the interrupt was enabled, enabled it again. Otherwise,
664 * just wait for the distributor to have digested our changes.
669 gic_dist_wait_for_rwp();
671 return IRQ_SET_MASK_OK;
674 #define gic_set_affinity NULL
675 #define gic_smp_init() do { } while(0)
679 static int gic_cpu_pm_notifier(struct notifier_block *self,
680 unsigned long cmd, void *v)
682 if (cmd == CPU_PM_EXIT) {
683 gic_enable_redist(true);
684 gic_cpu_sys_reg_init();
685 } else if (cmd == CPU_PM_ENTER) {
687 gic_enable_redist(false);
692 static struct notifier_block gic_cpu_pm_notifier_block = {
693 .notifier_call = gic_cpu_pm_notifier,
696 static void gic_cpu_pm_init(void)
698 cpu_pm_register_notifier(&gic_cpu_pm_notifier_block);
702 static inline void gic_cpu_pm_init(void) { }
703 #endif /* CONFIG_CPU_PM */
705 static struct irq_chip gic_chip = {
707 .irq_mask = gic_mask_irq,
708 .irq_unmask = gic_unmask_irq,
709 .irq_eoi = gic_eoi_irq,
710 .irq_set_type = gic_set_type,
711 .irq_set_affinity = gic_set_affinity,
712 .irq_get_irqchip_state = gic_irq_get_irqchip_state,
713 .irq_set_irqchip_state = gic_irq_set_irqchip_state,
714 .flags = IRQCHIP_SET_TYPE_MASKED,
717 static struct irq_chip gic_eoimode1_chip = {
719 .irq_mask = gic_eoimode1_mask_irq,
720 .irq_unmask = gic_unmask_irq,
721 .irq_eoi = gic_eoimode1_eoi_irq,
722 .irq_set_type = gic_set_type,
723 .irq_set_affinity = gic_set_affinity,
724 .irq_get_irqchip_state = gic_irq_get_irqchip_state,
725 .irq_set_irqchip_state = gic_irq_set_irqchip_state,
726 .irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity,
727 .flags = IRQCHIP_SET_TYPE_MASKED,
730 #define GIC_ID_NR (1U << gic_data.rdists.id_bits)
732 static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq,
735 struct irq_chip *chip = &gic_chip;
737 if (static_key_true(&supports_deactivate))
738 chip = &gic_eoimode1_chip;
740 /* SGIs are private to the core kernel */
744 if (hw >= gic_data.irq_nr && hw < 8192)
752 irq_set_percpu_devid(irq);
753 irq_domain_set_info(d, irq, hw, chip, d->host_data,
754 handle_percpu_devid_irq, NULL, NULL);
755 irq_set_status_flags(irq, IRQ_NOAUTOEN);
758 if (hw >= 32 && hw < gic_data.irq_nr) {
759 irq_domain_set_info(d, irq, hw, chip, d->host_data,
760 handle_fasteoi_irq, NULL, NULL);
764 if (hw >= 8192 && hw < GIC_ID_NR) {
765 if (!gic_dist_supports_lpis())
767 irq_domain_set_info(d, irq, hw, chip, d->host_data,
768 handle_fasteoi_irq, NULL, NULL);
774 static int gic_irq_domain_xlate(struct irq_domain *d,
775 struct device_node *controller,
776 const u32 *intspec, unsigned int intsize,
777 unsigned long *out_hwirq, unsigned int *out_type)
779 if (d->of_node != controller)
786 *out_hwirq = intspec[1] + 32;
789 *out_hwirq = intspec[1] + 16;
791 case GIC_IRQ_TYPE_LPI: /* LPI */
792 *out_hwirq = intspec[1];
798 *out_type = intspec[2] & IRQ_TYPE_SENSE_MASK;
802 static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
803 unsigned int nr_irqs, void *arg)
806 irq_hw_number_t hwirq;
807 unsigned int type = IRQ_TYPE_NONE;
808 struct of_phandle_args *irq_data = arg;
810 ret = gic_irq_domain_xlate(domain, irq_data->np, irq_data->args,
811 irq_data->args_count, &hwirq, &type);
815 for (i = 0; i < nr_irqs; i++)
816 gic_irq_domain_map(domain, virq + i, hwirq + i);
821 static void gic_irq_domain_free(struct irq_domain *domain, unsigned int virq,
822 unsigned int nr_irqs)
826 for (i = 0; i < nr_irqs; i++) {
827 struct irq_data *d = irq_domain_get_irq_data(domain, virq + i);
828 irq_set_handler(virq + i, NULL);
829 irq_domain_reset_irq_data(d);
833 static const struct irq_domain_ops gic_irq_domain_ops = {
834 .xlate = gic_irq_domain_xlate,
835 .alloc = gic_irq_domain_alloc,
836 .free = gic_irq_domain_free,
839 static int __init gic_of_init(struct device_node *node, struct device_node *parent)
841 void __iomem *dist_base;
842 struct redist_region *rdist_regs;
844 u32 nr_redist_regions;
851 dist_base = of_iomap(node, 0);
853 pr_err("%s: unable to map gic dist registers\n",
858 reg = readl_relaxed(dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK;
859 if (reg != GIC_PIDR2_ARCH_GICv3 && reg != GIC_PIDR2_ARCH_GICv4) {
860 pr_err("%s: no distributor detected, giving up\n",
866 if (of_property_read_u32(node, "#redistributor-regions", &nr_redist_regions))
867 nr_redist_regions = 1;
869 rdist_regs = kzalloc(sizeof(*rdist_regs) * nr_redist_regions, GFP_KERNEL);
875 for (i = 0; i < nr_redist_regions; i++) {
879 ret = of_address_to_resource(node, 1 + i, &res);
880 rdist_regs[i].redist_base = of_iomap(node, 1 + i);
881 if (ret || !rdist_regs[i].redist_base) {
882 pr_err("%s: couldn't map region %d\n",
885 goto out_unmap_rdist;
887 rdist_regs[i].phys_base = res.start;
890 if (of_property_read_u64(node, "redistributor-stride", &redist_stride))
893 if (!is_hyp_mode_available())
894 static_key_slow_dec(&supports_deactivate);
896 if (static_key_true(&supports_deactivate))
897 pr_info("GIC: Using split EOI/Deactivate mode\n");
899 gic_data.dist_base = dist_base;
900 gic_data.redist_regions = rdist_regs;
901 gic_data.nr_redist_regions = nr_redist_regions;
902 gic_data.redist_stride = redist_stride;
905 * Find out how many interrupts are supported.
906 * The GIC only supports up to 1020 interrupt sources (SGI+PPI+SPI)
908 typer = readl_relaxed(gic_data.dist_base + GICD_TYPER);
909 gic_data.rdists.id_bits = GICD_TYPER_ID_BITS(typer);
910 gic_irqs = GICD_TYPER_IRQS(typer);
913 gic_data.irq_nr = gic_irqs;
915 gic_data.domain = irq_domain_add_tree(node, &gic_irq_domain_ops,
917 gic_data.rdists.rdist = alloc_percpu(typeof(*gic_data.rdists.rdist));
919 if (WARN_ON(!gic_data.domain) || WARN_ON(!gic_data.rdists.rdist)) {
924 set_handle_irq(gic_handle_irq);
926 if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis())
927 its_init(node, &gic_data.rdists, gic_data.domain);
938 irq_domain_remove(gic_data.domain);
939 free_percpu(gic_data.rdists.rdist);
941 for (i = 0; i < nr_redist_regions; i++)
942 if (rdist_regs[i].redist_base)
943 iounmap(rdist_regs[i].redist_base);
950 IRQCHIP_DECLARE(gic_v3, "arm,gic-v3", gic_of_init);