2 * Copyright (C) 2002 ARM Limited, All Rights Reserved.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
8 * Interrupt architecture for the GIC:
10 * o There is one Interrupt Distributor, which receives interrupts
11 * from system devices and sends them to the Interrupt Controllers.
13 * o There is one CPU Interface per CPU, which sends interrupts sent
14 * by the Distributor, and interrupts generated locally, to the
15 * associated CPU. The base address of the CPU interface is usually
16 * aliased so that the same address points to different chips depending
17 * on the CPU it is accessed from.
19 * Note that IRQs 0-31 are special - they are local to each CPU.
20 * As such, the enable set/clear, pending set/clear and active bit
21 * registers are banked per-cpu for these sources.
23 #include <linux/init.h>
24 #include <linux/kernel.h>
25 #include <linux/err.h>
26 #include <linux/module.h>
27 #include <linux/list.h>
28 #include <linux/smp.h>
29 #include <linux/cpu.h>
30 #include <linux/cpu_pm.h>
31 #include <linux/cpumask.h>
34 #include <linux/of_address.h>
35 #include <linux/of_irq.h>
36 #include <linux/irqdomain.h>
37 #include <linux/interrupt.h>
38 #include <linux/percpu.h>
39 #include <linux/slab.h>
40 #include <linux/irqchip/chained_irq.h>
41 #include <linux/irqchip/arm-gic.h>
43 #include <asm/cputype.h>
45 #include <asm/exception.h>
46 #include <asm/smp_plat.h>
48 #include "irq-gic-common.h"
52 void __iomem *common_base;
53 void __percpu * __iomem *percpu_base;
56 struct gic_chip_data {
57 union gic_base dist_base;
58 union gic_base cpu_base;
60 u32 saved_spi_enable[DIV_ROUND_UP(1020, 32)];
61 u32 saved_spi_conf[DIV_ROUND_UP(1020, 16)];
62 u32 saved_spi_target[DIV_ROUND_UP(1020, 4)];
63 u32 __percpu *saved_ppi_enable;
64 u32 __percpu *saved_ppi_conf;
66 struct irq_domain *domain;
67 unsigned int gic_irqs;
68 #ifdef CONFIG_GIC_NON_BANKED
69 void __iomem *(*get_base)(union gic_base *);
73 static DEFINE_RAW_SPINLOCK(irq_controller_lock);
76 * The GIC mapping of CPU interfaces does not necessarily match
77 * the logical CPU numbering. Let's use a mapping as returned
80 #define NR_GIC_CPU_IF 8
81 static u8 gic_cpu_map[NR_GIC_CPU_IF] __read_mostly;
84 * Supported arch specific GIC irq extension.
85 * Default make them NULL.
87 struct irq_chip gic_arch_extn = {
91 .irq_retrigger = NULL,
100 static struct gic_chip_data gic_data[MAX_GIC_NR] __read_mostly;
102 #ifdef CONFIG_GIC_NON_BANKED
103 static void __iomem *gic_get_percpu_base(union gic_base *base)
105 return raw_cpu_read(*base->percpu_base);
108 static void __iomem *gic_get_common_base(union gic_base *base)
110 return base->common_base;
113 static inline void __iomem *gic_data_dist_base(struct gic_chip_data *data)
115 return data->get_base(&data->dist_base);
118 static inline void __iomem *gic_data_cpu_base(struct gic_chip_data *data)
120 return data->get_base(&data->cpu_base);
123 static inline void gic_set_base_accessor(struct gic_chip_data *data,
124 void __iomem *(*f)(union gic_base *))
129 #define gic_data_dist_base(d) ((d)->dist_base.common_base)
130 #define gic_data_cpu_base(d) ((d)->cpu_base.common_base)
131 #define gic_set_base_accessor(d, f)
134 static inline void __iomem *gic_dist_base(struct irq_data *d)
136 struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
137 return gic_data_dist_base(gic_data);
140 static inline void __iomem *gic_cpu_base(struct irq_data *d)
142 struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
143 return gic_data_cpu_base(gic_data);
146 static inline unsigned int gic_irq(struct irq_data *d)
152 * Routines to acknowledge, disable and enable interrupts
154 static void gic_mask_irq(struct irq_data *d)
156 u32 mask = 1 << (gic_irq(d) % 32);
158 raw_spin_lock(&irq_controller_lock);
159 writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_CLEAR + (gic_irq(d) / 32) * 4);
160 if (gic_arch_extn.irq_mask)
161 gic_arch_extn.irq_mask(d);
162 raw_spin_unlock(&irq_controller_lock);
165 static void gic_unmask_irq(struct irq_data *d)
167 u32 mask = 1 << (gic_irq(d) % 32);
169 raw_spin_lock(&irq_controller_lock);
170 if (gic_arch_extn.irq_unmask)
171 gic_arch_extn.irq_unmask(d);
172 writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_SET + (gic_irq(d) / 32) * 4);
173 raw_spin_unlock(&irq_controller_lock);
176 static void gic_eoi_irq(struct irq_data *d)
178 if (gic_arch_extn.irq_eoi) {
179 raw_spin_lock(&irq_controller_lock);
180 gic_arch_extn.irq_eoi(d);
181 raw_spin_unlock(&irq_controller_lock);
184 writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI);
187 static int gic_set_type(struct irq_data *d, unsigned int type)
189 void __iomem *base = gic_dist_base(d);
190 unsigned int gicirq = gic_irq(d);
193 /* Interrupt configuration for SGIs can't be changed */
197 /* SPIs have restrictions on the supported types */
198 if (gicirq >= 32 && type != IRQ_TYPE_LEVEL_HIGH &&
199 type != IRQ_TYPE_EDGE_RISING)
202 raw_spin_lock(&irq_controller_lock);
204 if (gic_arch_extn.irq_set_type)
205 gic_arch_extn.irq_set_type(d, type);
207 ret = gic_configure_irq(gicirq, type, base, NULL);
209 raw_spin_unlock(&irq_controller_lock);
214 static int gic_retrigger(struct irq_data *d)
216 if (gic_arch_extn.irq_retrigger)
217 return gic_arch_extn.irq_retrigger(d);
219 /* the genirq layer expects 0 if we can't retrigger in hardware */
224 static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
227 void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + (gic_irq(d) & ~3);
228 unsigned int cpu, shift = (gic_irq(d) % 4) * 8;
232 cpu = cpumask_any_and(mask_val, cpu_online_mask);
234 cpu = cpumask_first(mask_val);
236 if (cpu >= NR_GIC_CPU_IF || cpu >= nr_cpu_ids)
239 raw_spin_lock(&irq_controller_lock);
240 mask = 0xff << shift;
241 bit = gic_cpu_map[cpu] << shift;
242 val = readl_relaxed(reg) & ~mask;
243 writel_relaxed(val | bit, reg);
244 raw_spin_unlock(&irq_controller_lock);
246 return IRQ_SET_MASK_OK;
251 static int gic_set_wake(struct irq_data *d, unsigned int on)
255 if (gic_arch_extn.irq_set_wake)
256 ret = gic_arch_extn.irq_set_wake(d, on);
262 #define gic_set_wake NULL
265 static void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
268 struct gic_chip_data *gic = &gic_data[0];
269 void __iomem *cpu_base = gic_data_cpu_base(gic);
272 irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK);
273 irqnr = irqstat & GICC_IAR_INT_ID_MASK;
275 if (likely(irqnr > 15 && irqnr < 1021)) {
276 handle_domain_irq(gic->domain, irqnr, regs);
280 writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI);
282 handle_IPI(irqnr, regs);
290 static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
292 struct gic_chip_data *chip_data = irq_get_handler_data(irq);
293 struct irq_chip *chip = irq_get_chip(irq);
294 unsigned int cascade_irq, gic_irq;
295 unsigned long status;
297 chained_irq_enter(chip, desc);
299 raw_spin_lock(&irq_controller_lock);
300 status = readl_relaxed(gic_data_cpu_base(chip_data) + GIC_CPU_INTACK);
301 raw_spin_unlock(&irq_controller_lock);
303 gic_irq = (status & GICC_IAR_INT_ID_MASK);
304 if (gic_irq == GICC_INT_SPURIOUS)
307 cascade_irq = irq_find_mapping(chip_data->domain, gic_irq);
308 if (unlikely(gic_irq < 32 || gic_irq > 1020))
309 handle_bad_irq(cascade_irq, desc);
311 generic_handle_irq(cascade_irq);
314 chained_irq_exit(chip, desc);
317 static struct irq_chip gic_chip = {
319 .irq_mask = gic_mask_irq,
320 .irq_unmask = gic_unmask_irq,
321 .irq_eoi = gic_eoi_irq,
322 .irq_set_type = gic_set_type,
323 .irq_retrigger = gic_retrigger,
325 .irq_set_affinity = gic_set_affinity,
327 .irq_set_wake = gic_set_wake,
330 void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq)
332 if (gic_nr >= MAX_GIC_NR)
334 if (irq_set_handler_data(irq, &gic_data[gic_nr]) != 0)
336 irq_set_chained_handler(irq, gic_handle_cascade_irq);
339 static u8 gic_get_cpumask(struct gic_chip_data *gic)
341 void __iomem *base = gic_data_dist_base(gic);
344 for (i = mask = 0; i < 32; i += 4) {
345 mask = readl_relaxed(base + GIC_DIST_TARGET + i);
353 pr_crit("GIC CPU mask not found - kernel will fail to boot.\n");
358 static void gic_cpu_if_up(void)
360 void __iomem *cpu_base = gic_data_cpu_base(&gic_data[0]);
364 * Preserve bypass disable bits to be written back later
366 bypass = readl(cpu_base + GIC_CPU_CTRL);
367 bypass &= GICC_DIS_BYPASS_MASK;
369 writel_relaxed(bypass | GICC_ENABLE, cpu_base + GIC_CPU_CTRL);
373 static void __init gic_dist_init(struct gic_chip_data *gic)
377 unsigned int gic_irqs = gic->gic_irqs;
378 void __iomem *base = gic_data_dist_base(gic);
380 writel_relaxed(GICD_DISABLE, base + GIC_DIST_CTRL);
383 * Set all global interrupts to this CPU only.
385 cpumask = gic_get_cpumask(gic);
386 cpumask |= cpumask << 8;
387 cpumask |= cpumask << 16;
388 for (i = 32; i < gic_irqs; i += 4)
389 writel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4 / 4);
391 gic_dist_config(base, gic_irqs, NULL);
393 writel_relaxed(GICD_ENABLE, base + GIC_DIST_CTRL);
396 static void gic_cpu_init(struct gic_chip_data *gic)
398 void __iomem *dist_base = gic_data_dist_base(gic);
399 void __iomem *base = gic_data_cpu_base(gic);
400 unsigned int cpu_mask, cpu = smp_processor_id();
404 * Get what the GIC says our CPU mask is.
406 BUG_ON(cpu >= NR_GIC_CPU_IF);
407 cpu_mask = gic_get_cpumask(gic);
408 gic_cpu_map[cpu] = cpu_mask;
411 * Clear our mask from the other map entries in case they're
414 for (i = 0; i < NR_GIC_CPU_IF; i++)
416 gic_cpu_map[i] &= ~cpu_mask;
418 gic_cpu_config(dist_base, NULL);
420 writel_relaxed(GICC_INT_PRI_THRESHOLD, base + GIC_CPU_PRIMASK);
424 void gic_cpu_if_down(void)
426 void __iomem *cpu_base = gic_data_cpu_base(&gic_data[0]);
429 val = readl(cpu_base + GIC_CPU_CTRL);
431 writel_relaxed(val, cpu_base + GIC_CPU_CTRL);
436 * Saves the GIC distributor registers during suspend or idle. Must be called
437 * with interrupts disabled but before powering down the GIC. After calling
438 * this function, no interrupts will be delivered by the GIC, and another
439 * platform-specific wakeup source must be enabled.
441 static void gic_dist_save(unsigned int gic_nr)
443 unsigned int gic_irqs;
444 void __iomem *dist_base;
447 if (gic_nr >= MAX_GIC_NR)
450 gic_irqs = gic_data[gic_nr].gic_irqs;
451 dist_base = gic_data_dist_base(&gic_data[gic_nr]);
456 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++)
457 gic_data[gic_nr].saved_spi_conf[i] =
458 readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4);
460 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
461 gic_data[gic_nr].saved_spi_target[i] =
462 readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4);
464 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++)
465 gic_data[gic_nr].saved_spi_enable[i] =
466 readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4);
470 * Restores the GIC distributor registers during resume or when coming out of
471 * idle. Must be called before enabling interrupts. If a level interrupt
472 * that occured while the GIC was suspended is still present, it will be
473 * handled normally, but any edge interrupts that occured will not be seen by
474 * the GIC and need to be handled by the platform-specific wakeup source.
476 static void gic_dist_restore(unsigned int gic_nr)
478 unsigned int gic_irqs;
480 void __iomem *dist_base;
482 if (gic_nr >= MAX_GIC_NR)
485 gic_irqs = gic_data[gic_nr].gic_irqs;
486 dist_base = gic_data_dist_base(&gic_data[gic_nr]);
491 writel_relaxed(GICD_DISABLE, dist_base + GIC_DIST_CTRL);
493 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++)
494 writel_relaxed(gic_data[gic_nr].saved_spi_conf[i],
495 dist_base + GIC_DIST_CONFIG + i * 4);
497 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
498 writel_relaxed(GICD_INT_DEF_PRI_X4,
499 dist_base + GIC_DIST_PRI + i * 4);
501 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
502 writel_relaxed(gic_data[gic_nr].saved_spi_target[i],
503 dist_base + GIC_DIST_TARGET + i * 4);
505 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++)
506 writel_relaxed(gic_data[gic_nr].saved_spi_enable[i],
507 dist_base + GIC_DIST_ENABLE_SET + i * 4);
509 writel_relaxed(GICD_ENABLE, dist_base + GIC_DIST_CTRL);
512 static void gic_cpu_save(unsigned int gic_nr)
516 void __iomem *dist_base;
517 void __iomem *cpu_base;
519 if (gic_nr >= MAX_GIC_NR)
522 dist_base = gic_data_dist_base(&gic_data[gic_nr]);
523 cpu_base = gic_data_cpu_base(&gic_data[gic_nr]);
525 if (!dist_base || !cpu_base)
528 ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_enable);
529 for (i = 0; i < DIV_ROUND_UP(32, 32); i++)
530 ptr[i] = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4);
532 ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_conf);
533 for (i = 0; i < DIV_ROUND_UP(32, 16); i++)
534 ptr[i] = readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4);
538 static void gic_cpu_restore(unsigned int gic_nr)
542 void __iomem *dist_base;
543 void __iomem *cpu_base;
545 if (gic_nr >= MAX_GIC_NR)
548 dist_base = gic_data_dist_base(&gic_data[gic_nr]);
549 cpu_base = gic_data_cpu_base(&gic_data[gic_nr]);
551 if (!dist_base || !cpu_base)
554 ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_enable);
555 for (i = 0; i < DIV_ROUND_UP(32, 32); i++)
556 writel_relaxed(ptr[i], dist_base + GIC_DIST_ENABLE_SET + i * 4);
558 ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_conf);
559 for (i = 0; i < DIV_ROUND_UP(32, 16); i++)
560 writel_relaxed(ptr[i], dist_base + GIC_DIST_CONFIG + i * 4);
562 for (i = 0; i < DIV_ROUND_UP(32, 4); i++)
563 writel_relaxed(GICD_INT_DEF_PRI_X4,
564 dist_base + GIC_DIST_PRI + i * 4);
566 writel_relaxed(GICC_INT_PRI_THRESHOLD, cpu_base + GIC_CPU_PRIMASK);
570 static int gic_notifier(struct notifier_block *self, unsigned long cmd, void *v)
574 for (i = 0; i < MAX_GIC_NR; i++) {
575 #ifdef CONFIG_GIC_NON_BANKED
576 /* Skip over unused GICs */
577 if (!gic_data[i].get_base)
584 case CPU_PM_ENTER_FAILED:
588 case CPU_CLUSTER_PM_ENTER:
591 case CPU_CLUSTER_PM_ENTER_FAILED:
592 case CPU_CLUSTER_PM_EXIT:
601 static struct notifier_block gic_notifier_block = {
602 .notifier_call = gic_notifier,
605 static void __init gic_pm_init(struct gic_chip_data *gic)
607 gic->saved_ppi_enable = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4,
609 BUG_ON(!gic->saved_ppi_enable);
611 gic->saved_ppi_conf = __alloc_percpu(DIV_ROUND_UP(32, 16) * 4,
613 BUG_ON(!gic->saved_ppi_conf);
615 if (gic == &gic_data[0])
616 cpu_pm_register_notifier(&gic_notifier_block);
619 static void __init gic_pm_init(struct gic_chip_data *gic)
625 static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
628 unsigned long flags, map = 0;
630 raw_spin_lock_irqsave(&irq_controller_lock, flags);
632 /* Convert our logical CPU mask into a physical one. */
633 for_each_cpu(cpu, mask)
634 map |= gic_cpu_map[cpu];
637 * Ensure that stores to Normal memory are visible to the
638 * other CPUs before they observe us issuing the IPI.
642 /* this always happens on GIC0 */
643 writel_relaxed(map << 16 | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
645 raw_spin_unlock_irqrestore(&irq_controller_lock, flags);
649 #ifdef CONFIG_BL_SWITCHER
651 * gic_send_sgi - send a SGI directly to given CPU interface number
653 * cpu_id: the ID for the destination CPU interface
654 * irq: the IPI number to send a SGI for
656 void gic_send_sgi(unsigned int cpu_id, unsigned int irq)
658 BUG_ON(cpu_id >= NR_GIC_CPU_IF);
659 cpu_id = 1 << cpu_id;
660 /* this always happens on GIC0 */
661 writel_relaxed((cpu_id << 16) | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
665 * gic_get_cpu_id - get the CPU interface ID for the specified CPU
667 * @cpu: the logical CPU number to get the GIC ID for.
669 * Return the CPU interface ID for the given logical CPU number,
670 * or -1 if the CPU number is too large or the interface ID is
671 * unknown (more than one bit set).
673 int gic_get_cpu_id(unsigned int cpu)
675 unsigned int cpu_bit;
677 if (cpu >= NR_GIC_CPU_IF)
679 cpu_bit = gic_cpu_map[cpu];
680 if (cpu_bit & (cpu_bit - 1))
682 return __ffs(cpu_bit);
686 * gic_migrate_target - migrate IRQs to another CPU interface
688 * @new_cpu_id: the CPU target ID to migrate IRQs to
690 * Migrate all peripheral interrupts with a target matching the current CPU
691 * to the interface corresponding to @new_cpu_id. The CPU interface mapping
692 * is also updated. Targets to other CPU interfaces are unchanged.
693 * This must be called with IRQs locally disabled.
695 void gic_migrate_target(unsigned int new_cpu_id)
697 unsigned int cur_cpu_id, gic_irqs, gic_nr = 0;
698 void __iomem *dist_base;
699 int i, ror_val, cpu = smp_processor_id();
700 u32 val, cur_target_mask, active_mask;
702 if (gic_nr >= MAX_GIC_NR)
705 dist_base = gic_data_dist_base(&gic_data[gic_nr]);
708 gic_irqs = gic_data[gic_nr].gic_irqs;
710 cur_cpu_id = __ffs(gic_cpu_map[cpu]);
711 cur_target_mask = 0x01010101 << cur_cpu_id;
712 ror_val = (cur_cpu_id - new_cpu_id) & 31;
714 raw_spin_lock(&irq_controller_lock);
716 /* Update the target interface for this logical CPU */
717 gic_cpu_map[cpu] = 1 << new_cpu_id;
720 * Find all the peripheral interrupts targetting the current
721 * CPU interface and migrate them to the new CPU interface.
722 * We skip DIST_TARGET 0 to 7 as they are read-only.
724 for (i = 8; i < DIV_ROUND_UP(gic_irqs, 4); i++) {
725 val = readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4);
726 active_mask = val & cur_target_mask;
729 val |= ror32(active_mask, ror_val);
730 writel_relaxed(val, dist_base + GIC_DIST_TARGET + i*4);
734 raw_spin_unlock(&irq_controller_lock);
737 * Now let's migrate and clear any potential SGIs that might be
738 * pending for us (cur_cpu_id). Since GIC_DIST_SGI_PENDING_SET
739 * is a banked register, we can only forward the SGI using
740 * GIC_DIST_SOFTINT. The original SGI source is lost but Linux
741 * doesn't use that information anyway.
743 * For the same reason we do not adjust SGI source information
744 * for previously sent SGIs by us to other CPUs either.
746 for (i = 0; i < 16; i += 4) {
748 val = readl_relaxed(dist_base + GIC_DIST_SGI_PENDING_SET + i);
751 writel_relaxed(val, dist_base + GIC_DIST_SGI_PENDING_CLEAR + i);
752 for (j = i; j < i + 4; j++) {
754 writel_relaxed((1 << (new_cpu_id + 16)) | j,
755 dist_base + GIC_DIST_SOFTINT);
762 * gic_get_sgir_physaddr - get the physical address for the SGI register
764 * REturn the physical address of the SGI register to be used
765 * by some early assembly code when the kernel is not yet available.
767 static unsigned long gic_dist_physaddr;
769 unsigned long gic_get_sgir_physaddr(void)
771 if (!gic_dist_physaddr)
773 return gic_dist_physaddr + GIC_DIST_SOFTINT;
776 void __init gic_init_physaddr(struct device_node *node)
779 if (of_address_to_resource(node, 0, &res) == 0) {
780 gic_dist_physaddr = res.start;
781 pr_info("GIC physical location is %#lx\n", gic_dist_physaddr);
786 #define gic_init_physaddr(node) do { } while (0)
789 static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq,
793 irq_set_percpu_devid(irq);
794 irq_domain_set_info(d, irq, hw, &gic_chip, d->host_data,
795 handle_percpu_devid_irq, NULL, NULL);
796 set_irq_flags(irq, IRQF_VALID | IRQF_NOAUTOEN);
798 irq_domain_set_info(d, irq, hw, &gic_chip, d->host_data,
799 handle_fasteoi_irq, NULL, NULL);
800 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
802 gic_routable_irq_domain_ops->map(d, irq, hw);
807 static void gic_irq_domain_unmap(struct irq_domain *d, unsigned int irq)
809 gic_routable_irq_domain_ops->unmap(d, irq);
812 static int gic_irq_domain_xlate(struct irq_domain *d,
813 struct device_node *controller,
814 const u32 *intspec, unsigned int intsize,
815 unsigned long *out_hwirq, unsigned int *out_type)
817 unsigned long ret = 0;
819 if (d->of_node != controller)
824 /* Get the interrupt number and add 16 to skip over SGIs */
825 *out_hwirq = intspec[1] + 16;
827 /* For SPIs, we need to add 16 more to get the GIC irq ID number */
829 ret = gic_routable_irq_domain_ops->xlate(d, controller,
835 if (IS_ERR_VALUE(ret))
839 *out_type = intspec[2] & IRQ_TYPE_SENSE_MASK;
845 static int gic_secondary_init(struct notifier_block *nfb, unsigned long action,
848 if (action == CPU_STARTING || action == CPU_STARTING_FROZEN)
849 gic_cpu_init(&gic_data[0]);
854 * Notifier for enabling the GIC CPU interface. Set an arbitrarily high
855 * priority because the GIC needs to be up before the ARM generic timers.
857 static struct notifier_block gic_cpu_notifier = {
858 .notifier_call = gic_secondary_init,
863 static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
864 unsigned int nr_irqs, void *arg)
867 irq_hw_number_t hwirq;
868 unsigned int type = IRQ_TYPE_NONE;
869 struct of_phandle_args *irq_data = arg;
871 ret = gic_irq_domain_xlate(domain, irq_data->np, irq_data->args,
872 irq_data->args_count, &hwirq, &type);
876 for (i = 0; i < nr_irqs; i++)
877 gic_irq_domain_map(domain, virq + i, hwirq + i);
882 static const struct irq_domain_ops gic_irq_domain_hierarchy_ops = {
883 .xlate = gic_irq_domain_xlate,
884 .alloc = gic_irq_domain_alloc,
885 .free = irq_domain_free_irqs_top,
888 static const struct irq_domain_ops gic_irq_domain_ops = {
889 .map = gic_irq_domain_map,
890 .unmap = gic_irq_domain_unmap,
891 .xlate = gic_irq_domain_xlate,
894 /* Default functions for routable irq domain */
895 static int gic_routable_irq_domain_map(struct irq_domain *d, unsigned int irq,
901 static void gic_routable_irq_domain_unmap(struct irq_domain *d,
906 static int gic_routable_irq_domain_xlate(struct irq_domain *d,
907 struct device_node *controller,
908 const u32 *intspec, unsigned int intsize,
909 unsigned long *out_hwirq,
910 unsigned int *out_type)
916 static const struct irq_domain_ops gic_default_routable_irq_domain_ops = {
917 .map = gic_routable_irq_domain_map,
918 .unmap = gic_routable_irq_domain_unmap,
919 .xlate = gic_routable_irq_domain_xlate,
922 const struct irq_domain_ops *gic_routable_irq_domain_ops =
923 &gic_default_routable_irq_domain_ops;
925 void __init gic_init_bases(unsigned int gic_nr, int irq_start,
926 void __iomem *dist_base, void __iomem *cpu_base,
927 u32 percpu_offset, struct device_node *node)
929 irq_hw_number_t hwirq_base;
930 struct gic_chip_data *gic;
931 int gic_irqs, irq_base, i;
932 int nr_routable_irqs;
934 BUG_ON(gic_nr >= MAX_GIC_NR);
936 gic = &gic_data[gic_nr];
937 #ifdef CONFIG_GIC_NON_BANKED
938 if (percpu_offset) { /* Frankein-GIC without banked registers... */
941 gic->dist_base.percpu_base = alloc_percpu(void __iomem *);
942 gic->cpu_base.percpu_base = alloc_percpu(void __iomem *);
943 if (WARN_ON(!gic->dist_base.percpu_base ||
944 !gic->cpu_base.percpu_base)) {
945 free_percpu(gic->dist_base.percpu_base);
946 free_percpu(gic->cpu_base.percpu_base);
950 for_each_possible_cpu(cpu) {
951 u32 mpidr = cpu_logical_map(cpu);
952 u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
953 unsigned long offset = percpu_offset * core_id;
954 *per_cpu_ptr(gic->dist_base.percpu_base, cpu) = dist_base + offset;
955 *per_cpu_ptr(gic->cpu_base.percpu_base, cpu) = cpu_base + offset;
958 gic_set_base_accessor(gic, gic_get_percpu_base);
961 { /* Normal, sane GIC... */
963 "GIC_NON_BANKED not enabled, ignoring %08x offset!",
965 gic->dist_base.common_base = dist_base;
966 gic->cpu_base.common_base = cpu_base;
967 gic_set_base_accessor(gic, gic_get_common_base);
971 * Initialize the CPU interface map to all CPUs.
972 * It will be refined as each CPU probes its ID.
974 for (i = 0; i < NR_GIC_CPU_IF; i++)
975 gic_cpu_map[i] = 0xff;
978 * Find out how many interrupts are supported.
979 * The GIC only supports up to 1020 interrupt sources.
981 gic_irqs = readl_relaxed(gic_data_dist_base(gic) + GIC_DIST_CTR) & 0x1f;
982 gic_irqs = (gic_irqs + 1) * 32;
985 gic->gic_irqs = gic_irqs;
987 if (node) { /* DT case */
988 const struct irq_domain_ops *ops = &gic_irq_domain_hierarchy_ops;
990 if (!of_property_read_u32(node, "arm,routable-irqs",
991 &nr_routable_irqs)) {
992 ops = &gic_irq_domain_ops;
993 gic_irqs = nr_routable_irqs;
996 gic->domain = irq_domain_add_linear(node, gic_irqs, ops, gic);
997 } else { /* Non-DT case */
999 * For primary GICs, skip over SGIs.
1000 * For secondary GICs, skip over PPIs, too.
1002 if (gic_nr == 0 && (irq_start & 31) > 0) {
1004 if (irq_start != -1)
1005 irq_start = (irq_start & ~31) + 16;
1010 gic_irqs -= hwirq_base; /* calculate # of irqs to allocate */
1012 irq_base = irq_alloc_descs(irq_start, 16, gic_irqs,
1014 if (IS_ERR_VALUE(irq_base)) {
1015 WARN(1, "Cannot allocate irq_descs @ IRQ%d, assuming pre-allocated\n",
1017 irq_base = irq_start;
1020 gic->domain = irq_domain_add_legacy(node, gic_irqs, irq_base,
1021 hwirq_base, &gic_irq_domain_ops, gic);
1024 if (WARN_ON(!gic->domain))
1029 set_smp_cross_call(gic_raise_softirq);
1030 register_cpu_notifier(&gic_cpu_notifier);
1032 set_handle_irq(gic_handle_irq);
1035 gic_chip.flags |= gic_arch_extn.flags;
1042 static int gic_cnt __initdata;
1045 gic_of_init(struct device_node *node, struct device_node *parent)
1047 void __iomem *cpu_base;
1048 void __iomem *dist_base;
1055 dist_base = of_iomap(node, 0);
1056 WARN(!dist_base, "unable to map gic dist registers\n");
1058 cpu_base = of_iomap(node, 1);
1059 WARN(!cpu_base, "unable to map gic cpu registers\n");
1061 if (of_property_read_u32(node, "cpu-offset", &percpu_offset))
1064 gic_init_bases(gic_cnt, -1, dist_base, cpu_base, percpu_offset, node);
1066 gic_init_physaddr(node);
1069 irq = irq_of_parse_and_map(node, 0);
1070 gic_cascade_irq(gic_cnt, irq);
1073 if (IS_ENABLED(CONFIG_ARM_GIC_V2M))
1074 gicv2m_of_init(node, gic_data[gic_cnt].domain);
1079 IRQCHIP_DECLARE(gic_400, "arm,gic-400", gic_of_init);
1080 IRQCHIP_DECLARE(arm11mp_gic, "arm,arm11mp-gic", gic_of_init);
1081 IRQCHIP_DECLARE(arm1176jzf_dc_gic, "arm,arm1176jzf-devchip-gic", gic_of_init);
1082 IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init);
1083 IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init);
1084 IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init);
1085 IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init);
1086 IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init);