2 * Copyright (C) 2002 ARM Limited, All Rights Reserved.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
8 * Interrupt architecture for the GIC:
10 * o There is one Interrupt Distributor, which receives interrupts
11 * from system devices and sends them to the Interrupt Controllers.
13 * o There is one CPU Interface per CPU, which sends interrupts sent
14 * by the Distributor, and interrupts generated locally, to the
15 * associated CPU. The base address of the CPU interface is usually
16 * aliased so that the same address points to different chips depending
17 * on the CPU it is accessed from.
19 * Note that IRQs 0-31 are special - they are local to each CPU.
20 * As such, the enable set/clear, pending set/clear and active bit
21 * registers are banked per-cpu for these sources.
23 #include <linux/init.h>
24 #include <linux/kernel.h>
25 #include <linux/err.h>
26 #include <linux/module.h>
27 #include <linux/list.h>
28 #include <linux/smp.h>
29 #include <linux/cpu.h>
30 #include <linux/cpu_pm.h>
31 #include <linux/cpumask.h>
34 #include <linux/of_address.h>
35 #include <linux/of_irq.h>
36 #include <linux/irqdomain.h>
37 #include <linux/interrupt.h>
38 #include <linux/percpu.h>
39 #include <linux/slab.h>
40 #include <linux/irqchip/chained_irq.h>
41 #include <linux/irqchip/arm-gic.h>
43 #include <asm/cputype.h>
45 #include <asm/exception.h>
46 #include <asm/smp_plat.h>
48 #include "irq-gic-common.h"
52 void __iomem *common_base;
53 void __percpu * __iomem *percpu_base;
56 struct gic_chip_data {
57 union gic_base dist_base;
58 union gic_base cpu_base;
60 u32 saved_spi_enable[DIV_ROUND_UP(1020, 32)];
61 u32 saved_spi_conf[DIV_ROUND_UP(1020, 16)];
62 u32 saved_spi_target[DIV_ROUND_UP(1020, 4)];
63 u32 __percpu *saved_ppi_enable;
64 u32 __percpu *saved_ppi_conf;
66 struct irq_domain *domain;
67 unsigned int gic_irqs;
68 #ifdef CONFIG_GIC_NON_BANKED
69 void __iomem *(*get_base)(union gic_base *);
73 static DEFINE_RAW_SPINLOCK(irq_controller_lock);
76 * The GIC mapping of CPU interfaces does not necessarily match
77 * the logical CPU numbering. Let's use a mapping as returned
80 #define NR_GIC_CPU_IF 8
81 static u8 gic_cpu_map[NR_GIC_CPU_IF] __read_mostly;
84 * Supported arch specific GIC irq extension.
85 * Default make them NULL.
87 struct irq_chip gic_arch_extn = {
91 .irq_retrigger = NULL,
100 static struct gic_chip_data gic_data[MAX_GIC_NR] __read_mostly;
102 #ifdef CONFIG_GIC_NON_BANKED
103 static void __iomem *gic_get_percpu_base(union gic_base *base)
105 return *__this_cpu_ptr(base->percpu_base);
108 static void __iomem *gic_get_common_base(union gic_base *base)
110 return base->common_base;
113 static inline void __iomem *gic_data_dist_base(struct gic_chip_data *data)
115 return data->get_base(&data->dist_base);
118 static inline void __iomem *gic_data_cpu_base(struct gic_chip_data *data)
120 return data->get_base(&data->cpu_base);
123 static inline void gic_set_base_accessor(struct gic_chip_data *data,
124 void __iomem *(*f)(union gic_base *))
129 #define gic_data_dist_base(d) ((d)->dist_base.common_base)
130 #define gic_data_cpu_base(d) ((d)->cpu_base.common_base)
131 #define gic_set_base_accessor(d, f)
134 static inline void __iomem *gic_dist_base(struct irq_data *d)
136 struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
137 return gic_data_dist_base(gic_data);
140 static inline void __iomem *gic_cpu_base(struct irq_data *d)
142 struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
143 return gic_data_cpu_base(gic_data);
146 static inline unsigned int gic_irq(struct irq_data *d)
152 * Routines to acknowledge, disable and enable interrupts
154 static void gic_mask_irq(struct irq_data *d)
156 u32 mask = 1 << (gic_irq(d) % 32);
158 raw_spin_lock(&irq_controller_lock);
159 writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_CLEAR + (gic_irq(d) / 32) * 4);
160 if (gic_arch_extn.irq_mask)
161 gic_arch_extn.irq_mask(d);
162 raw_spin_unlock(&irq_controller_lock);
165 static void gic_unmask_irq(struct irq_data *d)
167 u32 mask = 1 << (gic_irq(d) % 32);
169 raw_spin_lock(&irq_controller_lock);
170 if (gic_arch_extn.irq_unmask)
171 gic_arch_extn.irq_unmask(d);
172 writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_SET + (gic_irq(d) / 32) * 4);
173 raw_spin_unlock(&irq_controller_lock);
176 static void gic_eoi_irq(struct irq_data *d)
178 if (gic_arch_extn.irq_eoi) {
179 raw_spin_lock(&irq_controller_lock);
180 gic_arch_extn.irq_eoi(d);
181 raw_spin_unlock(&irq_controller_lock);
184 writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI);
187 static int gic_set_type(struct irq_data *d, unsigned int type)
189 void __iomem *base = gic_dist_base(d);
190 unsigned int gicirq = gic_irq(d);
192 /* Interrupt configuration for SGIs can't be changed */
196 if (type != IRQ_TYPE_LEVEL_HIGH && type != IRQ_TYPE_EDGE_RISING)
199 raw_spin_lock(&irq_controller_lock);
201 if (gic_arch_extn.irq_set_type)
202 gic_arch_extn.irq_set_type(d, type);
204 gic_configure_irq(gicirq, type, base, NULL);
206 raw_spin_unlock(&irq_controller_lock);
211 static int gic_retrigger(struct irq_data *d)
213 if (gic_arch_extn.irq_retrigger)
214 return gic_arch_extn.irq_retrigger(d);
216 /* the genirq layer expects 0 if we can't retrigger in hardware */
221 static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
224 void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + (gic_irq(d) & ~3);
225 unsigned int cpu, shift = (gic_irq(d) % 4) * 8;
229 cpu = cpumask_any_and(mask_val, cpu_online_mask);
231 cpu = cpumask_first(mask_val);
233 if (cpu >= NR_GIC_CPU_IF || cpu >= nr_cpu_ids)
236 raw_spin_lock(&irq_controller_lock);
237 mask = 0xff << shift;
238 bit = gic_cpu_map[cpu] << shift;
239 val = readl_relaxed(reg) & ~mask;
240 writel_relaxed(val | bit, reg);
241 raw_spin_unlock(&irq_controller_lock);
243 return IRQ_SET_MASK_OK;
248 static int gic_set_wake(struct irq_data *d, unsigned int on)
252 if (gic_arch_extn.irq_set_wake)
253 ret = gic_arch_extn.irq_set_wake(d, on);
259 #define gic_set_wake NULL
262 static void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
265 struct gic_chip_data *gic = &gic_data[0];
266 void __iomem *cpu_base = gic_data_cpu_base(gic);
269 irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK);
270 irqnr = irqstat & GICC_IAR_INT_ID_MASK;
272 if (likely(irqnr > 15 && irqnr < 1021)) {
273 irqnr = irq_find_mapping(gic->domain, irqnr);
274 handle_IRQ(irqnr, regs);
278 writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI);
280 handle_IPI(irqnr, regs);
288 static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
290 struct gic_chip_data *chip_data = irq_get_handler_data(irq);
291 struct irq_chip *chip = irq_get_chip(irq);
292 unsigned int cascade_irq, gic_irq;
293 unsigned long status;
295 chained_irq_enter(chip, desc);
297 raw_spin_lock(&irq_controller_lock);
298 status = readl_relaxed(gic_data_cpu_base(chip_data) + GIC_CPU_INTACK);
299 raw_spin_unlock(&irq_controller_lock);
301 gic_irq = (status & 0x3ff);
305 cascade_irq = irq_find_mapping(chip_data->domain, gic_irq);
306 if (unlikely(gic_irq < 32 || gic_irq > 1020))
307 handle_bad_irq(cascade_irq, desc);
309 generic_handle_irq(cascade_irq);
312 chained_irq_exit(chip, desc);
315 static struct irq_chip gic_chip = {
317 .irq_mask = gic_mask_irq,
318 .irq_unmask = gic_unmask_irq,
319 .irq_eoi = gic_eoi_irq,
320 .irq_set_type = gic_set_type,
321 .irq_retrigger = gic_retrigger,
323 .irq_set_affinity = gic_set_affinity,
325 .irq_set_wake = gic_set_wake,
328 void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq)
330 if (gic_nr >= MAX_GIC_NR)
332 if (irq_set_handler_data(irq, &gic_data[gic_nr]) != 0)
334 irq_set_chained_handler(irq, gic_handle_cascade_irq);
337 static u8 gic_get_cpumask(struct gic_chip_data *gic)
339 void __iomem *base = gic_data_dist_base(gic);
342 for (i = mask = 0; i < 32; i += 4) {
343 mask = readl_relaxed(base + GIC_DIST_TARGET + i);
351 pr_crit("GIC CPU mask not found - kernel will fail to boot.\n");
356 static void __init gic_dist_init(struct gic_chip_data *gic)
360 unsigned int gic_irqs = gic->gic_irqs;
361 void __iomem *base = gic_data_dist_base(gic);
363 writel_relaxed(0, base + GIC_DIST_CTRL);
366 * Set all global interrupts to this CPU only.
368 cpumask = gic_get_cpumask(gic);
369 cpumask |= cpumask << 8;
370 cpumask |= cpumask << 16;
371 for (i = 32; i < gic_irqs; i += 4)
372 writel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4 / 4);
374 gic_dist_config(base, gic_irqs, NULL);
376 writel_relaxed(1, base + GIC_DIST_CTRL);
379 static void gic_cpu_init(struct gic_chip_data *gic)
381 void __iomem *dist_base = gic_data_dist_base(gic);
382 void __iomem *base = gic_data_cpu_base(gic);
383 unsigned int cpu_mask, cpu = smp_processor_id();
387 * Get what the GIC says our CPU mask is.
389 BUG_ON(cpu >= NR_GIC_CPU_IF);
390 cpu_mask = gic_get_cpumask(gic);
391 gic_cpu_map[cpu] = cpu_mask;
394 * Clear our mask from the other map entries in case they're
397 for (i = 0; i < NR_GIC_CPU_IF; i++)
399 gic_cpu_map[i] &= ~cpu_mask;
401 gic_cpu_config(dist_base, NULL);
403 writel_relaxed(0xf0, base + GIC_CPU_PRIMASK);
404 writel_relaxed(1, base + GIC_CPU_CTRL);
407 void gic_cpu_if_down(void)
409 void __iomem *cpu_base = gic_data_cpu_base(&gic_data[0]);
410 writel_relaxed(0, cpu_base + GIC_CPU_CTRL);
415 * Saves the GIC distributor registers during suspend or idle. Must be called
416 * with interrupts disabled but before powering down the GIC. After calling
417 * this function, no interrupts will be delivered by the GIC, and another
418 * platform-specific wakeup source must be enabled.
420 static void gic_dist_save(unsigned int gic_nr)
422 unsigned int gic_irqs;
423 void __iomem *dist_base;
426 if (gic_nr >= MAX_GIC_NR)
429 gic_irqs = gic_data[gic_nr].gic_irqs;
430 dist_base = gic_data_dist_base(&gic_data[gic_nr]);
435 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++)
436 gic_data[gic_nr].saved_spi_conf[i] =
437 readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4);
439 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
440 gic_data[gic_nr].saved_spi_target[i] =
441 readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4);
443 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++)
444 gic_data[gic_nr].saved_spi_enable[i] =
445 readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4);
449 * Restores the GIC distributor registers during resume or when coming out of
450 * idle. Must be called before enabling interrupts. If a level interrupt
451 * that occured while the GIC was suspended is still present, it will be
452 * handled normally, but any edge interrupts that occured will not be seen by
453 * the GIC and need to be handled by the platform-specific wakeup source.
455 static void gic_dist_restore(unsigned int gic_nr)
457 unsigned int gic_irqs;
459 void __iomem *dist_base;
461 if (gic_nr >= MAX_GIC_NR)
464 gic_irqs = gic_data[gic_nr].gic_irqs;
465 dist_base = gic_data_dist_base(&gic_data[gic_nr]);
470 writel_relaxed(0, dist_base + GIC_DIST_CTRL);
472 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++)
473 writel_relaxed(gic_data[gic_nr].saved_spi_conf[i],
474 dist_base + GIC_DIST_CONFIG + i * 4);
476 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
477 writel_relaxed(0xa0a0a0a0,
478 dist_base + GIC_DIST_PRI + i * 4);
480 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
481 writel_relaxed(gic_data[gic_nr].saved_spi_target[i],
482 dist_base + GIC_DIST_TARGET + i * 4);
484 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++)
485 writel_relaxed(gic_data[gic_nr].saved_spi_enable[i],
486 dist_base + GIC_DIST_ENABLE_SET + i * 4);
488 writel_relaxed(1, dist_base + GIC_DIST_CTRL);
491 static void gic_cpu_save(unsigned int gic_nr)
495 void __iomem *dist_base;
496 void __iomem *cpu_base;
498 if (gic_nr >= MAX_GIC_NR)
501 dist_base = gic_data_dist_base(&gic_data[gic_nr]);
502 cpu_base = gic_data_cpu_base(&gic_data[gic_nr]);
504 if (!dist_base || !cpu_base)
507 ptr = __this_cpu_ptr(gic_data[gic_nr].saved_ppi_enable);
508 for (i = 0; i < DIV_ROUND_UP(32, 32); i++)
509 ptr[i] = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4);
511 ptr = __this_cpu_ptr(gic_data[gic_nr].saved_ppi_conf);
512 for (i = 0; i < DIV_ROUND_UP(32, 16); i++)
513 ptr[i] = readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4);
517 static void gic_cpu_restore(unsigned int gic_nr)
521 void __iomem *dist_base;
522 void __iomem *cpu_base;
524 if (gic_nr >= MAX_GIC_NR)
527 dist_base = gic_data_dist_base(&gic_data[gic_nr]);
528 cpu_base = gic_data_cpu_base(&gic_data[gic_nr]);
530 if (!dist_base || !cpu_base)
533 ptr = __this_cpu_ptr(gic_data[gic_nr].saved_ppi_enable);
534 for (i = 0; i < DIV_ROUND_UP(32, 32); i++)
535 writel_relaxed(ptr[i], dist_base + GIC_DIST_ENABLE_SET + i * 4);
537 ptr = __this_cpu_ptr(gic_data[gic_nr].saved_ppi_conf);
538 for (i = 0; i < DIV_ROUND_UP(32, 16); i++)
539 writel_relaxed(ptr[i], dist_base + GIC_DIST_CONFIG + i * 4);
541 for (i = 0; i < DIV_ROUND_UP(32, 4); i++)
542 writel_relaxed(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4);
544 writel_relaxed(0xf0, cpu_base + GIC_CPU_PRIMASK);
545 writel_relaxed(1, cpu_base + GIC_CPU_CTRL);
548 static int gic_notifier(struct notifier_block *self, unsigned long cmd, void *v)
552 for (i = 0; i < MAX_GIC_NR; i++) {
553 #ifdef CONFIG_GIC_NON_BANKED
554 /* Skip over unused GICs */
555 if (!gic_data[i].get_base)
562 case CPU_PM_ENTER_FAILED:
566 case CPU_CLUSTER_PM_ENTER:
569 case CPU_CLUSTER_PM_ENTER_FAILED:
570 case CPU_CLUSTER_PM_EXIT:
579 static struct notifier_block gic_notifier_block = {
580 .notifier_call = gic_notifier,
583 static void __init gic_pm_init(struct gic_chip_data *gic)
585 gic->saved_ppi_enable = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4,
587 BUG_ON(!gic->saved_ppi_enable);
589 gic->saved_ppi_conf = __alloc_percpu(DIV_ROUND_UP(32, 16) * 4,
591 BUG_ON(!gic->saved_ppi_conf);
593 if (gic == &gic_data[0])
594 cpu_pm_register_notifier(&gic_notifier_block);
597 static void __init gic_pm_init(struct gic_chip_data *gic)
603 static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
606 unsigned long flags, map = 0;
608 raw_spin_lock_irqsave(&irq_controller_lock, flags);
610 /* Convert our logical CPU mask into a physical one. */
611 for_each_cpu(cpu, mask)
612 map |= gic_cpu_map[cpu];
615 * Ensure that stores to Normal memory are visible to the
616 * other CPUs before they observe us issuing the IPI.
620 /* this always happens on GIC0 */
621 writel_relaxed(map << 16 | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
623 raw_spin_unlock_irqrestore(&irq_controller_lock, flags);
627 #ifdef CONFIG_BL_SWITCHER
629 * gic_send_sgi - send a SGI directly to given CPU interface number
631 * cpu_id: the ID for the destination CPU interface
632 * irq: the IPI number to send a SGI for
634 void gic_send_sgi(unsigned int cpu_id, unsigned int irq)
636 BUG_ON(cpu_id >= NR_GIC_CPU_IF);
637 cpu_id = 1 << cpu_id;
638 /* this always happens on GIC0 */
639 writel_relaxed((cpu_id << 16) | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
643 * gic_get_cpu_id - get the CPU interface ID for the specified CPU
645 * @cpu: the logical CPU number to get the GIC ID for.
647 * Return the CPU interface ID for the given logical CPU number,
648 * or -1 if the CPU number is too large or the interface ID is
649 * unknown (more than one bit set).
651 int gic_get_cpu_id(unsigned int cpu)
653 unsigned int cpu_bit;
655 if (cpu >= NR_GIC_CPU_IF)
657 cpu_bit = gic_cpu_map[cpu];
658 if (cpu_bit & (cpu_bit - 1))
660 return __ffs(cpu_bit);
664 * gic_migrate_target - migrate IRQs to another CPU interface
666 * @new_cpu_id: the CPU target ID to migrate IRQs to
668 * Migrate all peripheral interrupts with a target matching the current CPU
669 * to the interface corresponding to @new_cpu_id. The CPU interface mapping
670 * is also updated. Targets to other CPU interfaces are unchanged.
671 * This must be called with IRQs locally disabled.
673 void gic_migrate_target(unsigned int new_cpu_id)
675 unsigned int cur_cpu_id, gic_irqs, gic_nr = 0;
676 void __iomem *dist_base;
677 int i, ror_val, cpu = smp_processor_id();
678 u32 val, cur_target_mask, active_mask;
680 if (gic_nr >= MAX_GIC_NR)
683 dist_base = gic_data_dist_base(&gic_data[gic_nr]);
686 gic_irqs = gic_data[gic_nr].gic_irqs;
688 cur_cpu_id = __ffs(gic_cpu_map[cpu]);
689 cur_target_mask = 0x01010101 << cur_cpu_id;
690 ror_val = (cur_cpu_id - new_cpu_id) & 31;
692 raw_spin_lock(&irq_controller_lock);
694 /* Update the target interface for this logical CPU */
695 gic_cpu_map[cpu] = 1 << new_cpu_id;
698 * Find all the peripheral interrupts targetting the current
699 * CPU interface and migrate them to the new CPU interface.
700 * We skip DIST_TARGET 0 to 7 as they are read-only.
702 for (i = 8; i < DIV_ROUND_UP(gic_irqs, 4); i++) {
703 val = readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4);
704 active_mask = val & cur_target_mask;
707 val |= ror32(active_mask, ror_val);
708 writel_relaxed(val, dist_base + GIC_DIST_TARGET + i*4);
712 raw_spin_unlock(&irq_controller_lock);
715 * Now let's migrate and clear any potential SGIs that might be
716 * pending for us (cur_cpu_id). Since GIC_DIST_SGI_PENDING_SET
717 * is a banked register, we can only forward the SGI using
718 * GIC_DIST_SOFTINT. The original SGI source is lost but Linux
719 * doesn't use that information anyway.
721 * For the same reason we do not adjust SGI source information
722 * for previously sent SGIs by us to other CPUs either.
724 for (i = 0; i < 16; i += 4) {
726 val = readl_relaxed(dist_base + GIC_DIST_SGI_PENDING_SET + i);
729 writel_relaxed(val, dist_base + GIC_DIST_SGI_PENDING_CLEAR + i);
730 for (j = i; j < i + 4; j++) {
732 writel_relaxed((1 << (new_cpu_id + 16)) | j,
733 dist_base + GIC_DIST_SOFTINT);
740 * gic_get_sgir_physaddr - get the physical address for the SGI register
742 * REturn the physical address of the SGI register to be used
743 * by some early assembly code when the kernel is not yet available.
745 static unsigned long gic_dist_physaddr;
747 unsigned long gic_get_sgir_physaddr(void)
749 if (!gic_dist_physaddr)
751 return gic_dist_physaddr + GIC_DIST_SOFTINT;
754 void __init gic_init_physaddr(struct device_node *node)
757 if (of_address_to_resource(node, 0, &res) == 0) {
758 gic_dist_physaddr = res.start;
759 pr_info("GIC physical location is %#lx\n", gic_dist_physaddr);
764 #define gic_init_physaddr(node) do { } while (0)
767 static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq,
771 irq_set_percpu_devid(irq);
772 irq_set_chip_and_handler(irq, &gic_chip,
773 handle_percpu_devid_irq);
774 set_irq_flags(irq, IRQF_VALID | IRQF_NOAUTOEN);
776 irq_set_chip_and_handler(irq, &gic_chip,
778 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
780 gic_routable_irq_domain_ops->map(d, irq, hw);
782 irq_set_chip_data(irq, d->host_data);
786 static void gic_irq_domain_unmap(struct irq_domain *d, unsigned int irq)
788 gic_routable_irq_domain_ops->unmap(d, irq);
791 static int gic_irq_domain_xlate(struct irq_domain *d,
792 struct device_node *controller,
793 const u32 *intspec, unsigned int intsize,
794 unsigned long *out_hwirq, unsigned int *out_type)
796 unsigned long ret = 0;
798 if (d->of_node != controller)
803 /* Get the interrupt number and add 16 to skip over SGIs */
804 *out_hwirq = intspec[1] + 16;
806 /* For SPIs, we need to add 16 more to get the GIC irq ID number */
808 ret = gic_routable_irq_domain_ops->xlate(d, controller,
814 if (IS_ERR_VALUE(ret))
818 *out_type = intspec[2] & IRQ_TYPE_SENSE_MASK;
824 static int gic_secondary_init(struct notifier_block *nfb, unsigned long action,
827 if (action == CPU_STARTING || action == CPU_STARTING_FROZEN)
828 gic_cpu_init(&gic_data[0]);
833 * Notifier for enabling the GIC CPU interface. Set an arbitrarily high
834 * priority because the GIC needs to be up before the ARM generic timers.
836 static struct notifier_block gic_cpu_notifier = {
837 .notifier_call = gic_secondary_init,
842 static const struct irq_domain_ops gic_irq_domain_ops = {
843 .map = gic_irq_domain_map,
844 .unmap = gic_irq_domain_unmap,
845 .xlate = gic_irq_domain_xlate,
848 /* Default functions for routable irq domain */
849 static int gic_routable_irq_domain_map(struct irq_domain *d, unsigned int irq,
855 static void gic_routable_irq_domain_unmap(struct irq_domain *d,
860 static int gic_routable_irq_domain_xlate(struct irq_domain *d,
861 struct device_node *controller,
862 const u32 *intspec, unsigned int intsize,
863 unsigned long *out_hwirq,
864 unsigned int *out_type)
870 static const struct irq_domain_ops gic_default_routable_irq_domain_ops = {
871 .map = gic_routable_irq_domain_map,
872 .unmap = gic_routable_irq_domain_unmap,
873 .xlate = gic_routable_irq_domain_xlate,
876 const struct irq_domain_ops *gic_routable_irq_domain_ops =
877 &gic_default_routable_irq_domain_ops;
879 void __init gic_init_bases(unsigned int gic_nr, int irq_start,
880 void __iomem *dist_base, void __iomem *cpu_base,
881 u32 percpu_offset, struct device_node *node)
883 irq_hw_number_t hwirq_base;
884 struct gic_chip_data *gic;
885 int gic_irqs, irq_base, i;
886 int nr_routable_irqs;
888 BUG_ON(gic_nr >= MAX_GIC_NR);
890 gic = &gic_data[gic_nr];
891 #ifdef CONFIG_GIC_NON_BANKED
892 if (percpu_offset) { /* Frankein-GIC without banked registers... */
895 gic->dist_base.percpu_base = alloc_percpu(void __iomem *);
896 gic->cpu_base.percpu_base = alloc_percpu(void __iomem *);
897 if (WARN_ON(!gic->dist_base.percpu_base ||
898 !gic->cpu_base.percpu_base)) {
899 free_percpu(gic->dist_base.percpu_base);
900 free_percpu(gic->cpu_base.percpu_base);
904 for_each_possible_cpu(cpu) {
905 u32 mpidr = cpu_logical_map(cpu);
906 u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
907 unsigned long offset = percpu_offset * core_id;
908 *per_cpu_ptr(gic->dist_base.percpu_base, cpu) = dist_base + offset;
909 *per_cpu_ptr(gic->cpu_base.percpu_base, cpu) = cpu_base + offset;
912 gic_set_base_accessor(gic, gic_get_percpu_base);
915 { /* Normal, sane GIC... */
917 "GIC_NON_BANKED not enabled, ignoring %08x offset!",
919 gic->dist_base.common_base = dist_base;
920 gic->cpu_base.common_base = cpu_base;
921 gic_set_base_accessor(gic, gic_get_common_base);
925 * Initialize the CPU interface map to all CPUs.
926 * It will be refined as each CPU probes its ID.
928 for (i = 0; i < NR_GIC_CPU_IF; i++)
929 gic_cpu_map[i] = 0xff;
932 * For primary GICs, skip over SGIs.
933 * For secondary GICs, skip over PPIs, too.
935 if (gic_nr == 0 && (irq_start & 31) > 0) {
938 irq_start = (irq_start & ~31) + 16;
944 * Find out how many interrupts are supported.
945 * The GIC only supports up to 1020 interrupt sources.
947 gic_irqs = readl_relaxed(gic_data_dist_base(gic) + GIC_DIST_CTR) & 0x1f;
948 gic_irqs = (gic_irqs + 1) * 32;
951 gic->gic_irqs = gic_irqs;
953 gic_irqs -= hwirq_base; /* calculate # of irqs to allocate */
955 if (of_property_read_u32(node, "arm,routable-irqs",
956 &nr_routable_irqs)) {
957 irq_base = irq_alloc_descs(irq_start, 16, gic_irqs,
959 if (IS_ERR_VALUE(irq_base)) {
960 WARN(1, "Cannot allocate irq_descs @ IRQ%d, assuming pre-allocated\n",
962 irq_base = irq_start;
965 gic->domain = irq_domain_add_legacy(node, gic_irqs, irq_base,
966 hwirq_base, &gic_irq_domain_ops, gic);
968 gic->domain = irq_domain_add_linear(node, nr_routable_irqs,
973 if (WARN_ON(!gic->domain))
978 set_smp_cross_call(gic_raise_softirq);
979 register_cpu_notifier(&gic_cpu_notifier);
981 set_handle_irq(gic_handle_irq);
984 gic_chip.flags |= gic_arch_extn.flags;
991 static int gic_cnt __initdata;
994 gic_of_init(struct device_node *node, struct device_node *parent)
996 void __iomem *cpu_base;
997 void __iomem *dist_base;
1004 dist_base = of_iomap(node, 0);
1005 WARN(!dist_base, "unable to map gic dist registers\n");
1007 cpu_base = of_iomap(node, 1);
1008 WARN(!cpu_base, "unable to map gic cpu registers\n");
1010 if (of_property_read_u32(node, "cpu-offset", &percpu_offset))
1013 gic_init_bases(gic_cnt, -1, dist_base, cpu_base, percpu_offset, node);
1015 gic_init_physaddr(node);
1018 irq = irq_of_parse_and_map(node, 0);
1019 gic_cascade_irq(gic_cnt, irq);
1024 IRQCHIP_DECLARE(gic_400, "arm,gic-400", gic_of_init);
1025 IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init);
1026 IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init);
1027 IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init);
1028 IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init);
1029 IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init);