2 * Copyright (C) 2002 ARM Limited, All Rights Reserved.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
8 * Interrupt architecture for the GIC:
10 * o There is one Interrupt Distributor, which receives interrupts
11 * from system devices and sends them to the Interrupt Controllers.
13 * o There is one CPU Interface per CPU, which sends interrupts sent
14 * by the Distributor, and interrupts generated locally, to the
15 * associated CPU. The base address of the CPU interface is usually
16 * aliased so that the same address points to different chips depending
17 * on the CPU it is accessed from.
19 * Note that IRQs 0-31 are special - they are local to each CPU.
20 * As such, the enable set/clear, pending set/clear and active bit
21 * registers are banked per-cpu for these sources.
23 #include <linux/init.h>
24 #include <linux/kernel.h>
25 #include <linux/err.h>
26 #include <linux/module.h>
27 #include <linux/list.h>
28 #include <linux/smp.h>
29 #include <linux/cpu.h>
30 #include <linux/cpu_pm.h>
31 #include <linux/cpumask.h>
34 #include <linux/of_address.h>
35 #include <linux/of_irq.h>
36 #include <linux/acpi.h>
37 #include <linux/irqdomain.h>
38 #include <linux/interrupt.h>
39 #include <linux/percpu.h>
40 #include <linux/slab.h>
41 #include <linux/irqchip.h>
42 #include <linux/irqchip/chained_irq.h>
43 #include <linux/irqchip/arm-gic.h>
45 #include <asm/cputype.h>
47 #include <asm/exception.h>
48 #include <asm/smp_plat.h>
51 #include "irq-gic-common.h"
54 void __iomem *common_base;
55 void __percpu * __iomem *percpu_base;
58 struct gic_chip_data {
59 union gic_base dist_base;
60 union gic_base cpu_base;
62 u32 saved_spi_enable[DIV_ROUND_UP(1020, 32)];
63 u32 saved_spi_conf[DIV_ROUND_UP(1020, 16)];
64 u32 saved_spi_target[DIV_ROUND_UP(1020, 4)];
65 u32 __percpu *saved_ppi_enable;
66 u32 __percpu *saved_ppi_conf;
68 struct irq_domain *domain;
69 unsigned int gic_irqs;
70 #ifdef CONFIG_GIC_NON_BANKED
71 void __iomem *(*get_base)(union gic_base *);
75 static DEFINE_RAW_SPINLOCK(irq_controller_lock);
78 * The GIC mapping of CPU interfaces does not necessarily match
79 * the logical CPU numbering. Let's use a mapping as returned
82 #define NR_GIC_CPU_IF 8
83 static u8 gic_cpu_map[NR_GIC_CPU_IF] __read_mostly;
85 static struct static_key supports_deactivate = STATIC_KEY_INIT_TRUE;
91 static struct gic_chip_data gic_data[MAX_GIC_NR] __read_mostly;
93 #ifdef CONFIG_GIC_NON_BANKED
94 static void __iomem *gic_get_percpu_base(union gic_base *base)
96 return raw_cpu_read(*base->percpu_base);
99 static void __iomem *gic_get_common_base(union gic_base *base)
101 return base->common_base;
104 static inline void __iomem *gic_data_dist_base(struct gic_chip_data *data)
106 return data->get_base(&data->dist_base);
109 static inline void __iomem *gic_data_cpu_base(struct gic_chip_data *data)
111 return data->get_base(&data->cpu_base);
114 static inline void gic_set_base_accessor(struct gic_chip_data *data,
115 void __iomem *(*f)(union gic_base *))
120 #define gic_data_dist_base(d) ((d)->dist_base.common_base)
121 #define gic_data_cpu_base(d) ((d)->cpu_base.common_base)
122 #define gic_set_base_accessor(d, f)
125 static inline void __iomem *gic_dist_base(struct irq_data *d)
127 struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
128 return gic_data_dist_base(gic_data);
131 static inline void __iomem *gic_cpu_base(struct irq_data *d)
133 struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
134 return gic_data_cpu_base(gic_data);
137 static inline unsigned int gic_irq(struct irq_data *d)
142 static inline bool cascading_gic_irq(struct irq_data *d)
144 void *data = irq_data_get_irq_handler_data(d);
147 * If handler_data is set, this is a cascading interrupt, and
148 * it cannot possibly be forwarded.
154 * Routines to acknowledge, disable and enable interrupts
156 static void gic_poke_irq(struct irq_data *d, u32 offset)
158 u32 mask = 1 << (gic_irq(d) % 32);
159 writel_relaxed(mask, gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4);
162 static int gic_peek_irq(struct irq_data *d, u32 offset)
164 u32 mask = 1 << (gic_irq(d) % 32);
165 return !!(readl_relaxed(gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4) & mask);
168 static void gic_mask_irq(struct irq_data *d)
170 gic_poke_irq(d, GIC_DIST_ENABLE_CLEAR);
173 static void gic_eoimode1_mask_irq(struct irq_data *d)
177 * When masking a forwarded interrupt, make sure it is
178 * deactivated as well.
180 * This ensures that an interrupt that is getting
181 * disabled/masked will not get "stuck", because there is
182 * noone to deactivate it (guest is being terminated).
184 if (irqd_is_forwarded_to_vcpu(d))
185 gic_poke_irq(d, GIC_DIST_ACTIVE_CLEAR);
188 static void gic_unmask_irq(struct irq_data *d)
190 gic_poke_irq(d, GIC_DIST_ENABLE_SET);
193 static void gic_eoi_irq(struct irq_data *d)
195 writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI);
198 static void gic_eoimode1_eoi_irq(struct irq_data *d)
200 /* Do not deactivate an IRQ forwarded to a vcpu. */
201 if (irqd_is_forwarded_to_vcpu(d))
204 writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_DEACTIVATE);
207 static int gic_irq_set_irqchip_state(struct irq_data *d,
208 enum irqchip_irq_state which, bool val)
213 case IRQCHIP_STATE_PENDING:
214 reg = val ? GIC_DIST_PENDING_SET : GIC_DIST_PENDING_CLEAR;
217 case IRQCHIP_STATE_ACTIVE:
218 reg = val ? GIC_DIST_ACTIVE_SET : GIC_DIST_ACTIVE_CLEAR;
221 case IRQCHIP_STATE_MASKED:
222 reg = val ? GIC_DIST_ENABLE_CLEAR : GIC_DIST_ENABLE_SET;
229 gic_poke_irq(d, reg);
233 static int gic_irq_get_irqchip_state(struct irq_data *d,
234 enum irqchip_irq_state which, bool *val)
237 case IRQCHIP_STATE_PENDING:
238 *val = gic_peek_irq(d, GIC_DIST_PENDING_SET);
241 case IRQCHIP_STATE_ACTIVE:
242 *val = gic_peek_irq(d, GIC_DIST_ACTIVE_SET);
245 case IRQCHIP_STATE_MASKED:
246 *val = !gic_peek_irq(d, GIC_DIST_ENABLE_SET);
256 static int gic_set_type(struct irq_data *d, unsigned int type)
258 void __iomem *base = gic_dist_base(d);
259 unsigned int gicirq = gic_irq(d);
261 /* Interrupt configuration for SGIs can't be changed */
265 /* SPIs have restrictions on the supported types */
266 if (gicirq >= 32 && type != IRQ_TYPE_LEVEL_HIGH &&
267 type != IRQ_TYPE_EDGE_RISING)
270 return gic_configure_irq(gicirq, type, base, NULL);
273 static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu)
275 /* Only interrupts on the primary GIC can be forwarded to a vcpu. */
276 if (cascading_gic_irq(d))
280 irqd_set_forwarded_to_vcpu(d);
282 irqd_clr_forwarded_to_vcpu(d);
287 static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
290 void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + (gic_irq(d) & ~3);
291 unsigned int cpu, shift = (gic_irq(d) % 4) * 8;
296 cpu = cpumask_any_and(mask_val, cpu_online_mask);
298 cpu = cpumask_first(mask_val);
300 if (cpu >= NR_GIC_CPU_IF || cpu >= nr_cpu_ids)
303 raw_spin_lock_irqsave(&irq_controller_lock, flags);
304 mask = 0xff << shift;
305 bit = gic_cpu_map[cpu] << shift;
306 val = readl_relaxed(reg) & ~mask;
307 writel_relaxed(val | bit, reg);
308 raw_spin_unlock_irqrestore(&irq_controller_lock, flags);
310 return IRQ_SET_MASK_OK;
314 static void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
317 struct gic_chip_data *gic = &gic_data[0];
318 void __iomem *cpu_base = gic_data_cpu_base(gic);
321 irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK);
322 irqnr = irqstat & GICC_IAR_INT_ID_MASK;
324 if (likely(irqnr > 15 && irqnr < 1021)) {
325 if (static_key_true(&supports_deactivate))
326 writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI);
327 handle_domain_irq(gic->domain, irqnr, regs);
331 writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI);
332 if (static_key_true(&supports_deactivate))
333 writel_relaxed(irqstat, cpu_base + GIC_CPU_DEACTIVATE);
335 handle_IPI(irqnr, regs);
343 static void gic_handle_cascade_irq(struct irq_desc *desc)
345 struct gic_chip_data *chip_data = irq_desc_get_handler_data(desc);
346 struct irq_chip *chip = irq_desc_get_chip(desc);
347 unsigned int cascade_irq, gic_irq;
348 unsigned long status;
350 chained_irq_enter(chip, desc);
352 raw_spin_lock(&irq_controller_lock);
353 status = readl_relaxed(gic_data_cpu_base(chip_data) + GIC_CPU_INTACK);
354 raw_spin_unlock(&irq_controller_lock);
356 gic_irq = (status & GICC_IAR_INT_ID_MASK);
357 if (gic_irq == GICC_INT_SPURIOUS)
360 cascade_irq = irq_find_mapping(chip_data->domain, gic_irq);
361 if (unlikely(gic_irq < 32 || gic_irq > 1020))
362 handle_bad_irq(desc);
364 generic_handle_irq(cascade_irq);
367 chained_irq_exit(chip, desc);
370 static struct irq_chip gic_chip = {
372 .irq_mask = gic_mask_irq,
373 .irq_unmask = gic_unmask_irq,
374 .irq_eoi = gic_eoi_irq,
375 .irq_set_type = gic_set_type,
377 .irq_set_affinity = gic_set_affinity,
379 .irq_get_irqchip_state = gic_irq_get_irqchip_state,
380 .irq_set_irqchip_state = gic_irq_set_irqchip_state,
381 .flags = IRQCHIP_SET_TYPE_MASKED |
382 IRQCHIP_SKIP_SET_WAKE |
383 IRQCHIP_MASK_ON_SUSPEND,
386 static struct irq_chip gic_eoimode1_chip = {
388 .irq_mask = gic_eoimode1_mask_irq,
389 .irq_unmask = gic_unmask_irq,
390 .irq_eoi = gic_eoimode1_eoi_irq,
391 .irq_set_type = gic_set_type,
393 .irq_set_affinity = gic_set_affinity,
395 .irq_get_irqchip_state = gic_irq_get_irqchip_state,
396 .irq_set_irqchip_state = gic_irq_set_irqchip_state,
397 .irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity,
398 .flags = IRQCHIP_SET_TYPE_MASKED |
399 IRQCHIP_SKIP_SET_WAKE |
400 IRQCHIP_MASK_ON_SUSPEND,
403 void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq)
405 if (gic_nr >= MAX_GIC_NR)
407 irq_set_chained_handler_and_data(irq, gic_handle_cascade_irq,
411 static u8 gic_get_cpumask(struct gic_chip_data *gic)
413 void __iomem *base = gic_data_dist_base(gic);
416 for (i = mask = 0; i < 32; i += 4) {
417 mask = readl_relaxed(base + GIC_DIST_TARGET + i);
424 if (!mask && num_possible_cpus() > 1)
425 pr_crit("GIC CPU mask not found - kernel will fail to boot.\n");
430 static void gic_cpu_if_up(struct gic_chip_data *gic)
432 void __iomem *cpu_base = gic_data_cpu_base(gic);
436 if (static_key_true(&supports_deactivate))
437 mode = GIC_CPU_CTRL_EOImodeNS;
440 * Preserve bypass disable bits to be written back later
442 bypass = readl(cpu_base + GIC_CPU_CTRL);
443 bypass &= GICC_DIS_BYPASS_MASK;
445 writel_relaxed(bypass | mode | GICC_ENABLE, cpu_base + GIC_CPU_CTRL);
449 static void __init gic_dist_init(struct gic_chip_data *gic)
453 unsigned int gic_irqs = gic->gic_irqs;
454 void __iomem *base = gic_data_dist_base(gic);
456 writel_relaxed(GICD_DISABLE, base + GIC_DIST_CTRL);
459 * Set all global interrupts to this CPU only.
461 cpumask = gic_get_cpumask(gic);
462 cpumask |= cpumask << 8;
463 cpumask |= cpumask << 16;
464 for (i = 32; i < gic_irqs; i += 4)
465 writel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4 / 4);
467 gic_dist_config(base, gic_irqs, NULL);
469 writel_relaxed(GICD_ENABLE, base + GIC_DIST_CTRL);
472 static void gic_cpu_init(struct gic_chip_data *gic)
474 void __iomem *dist_base = gic_data_dist_base(gic);
475 void __iomem *base = gic_data_cpu_base(gic);
476 unsigned int cpu_mask, cpu = smp_processor_id();
480 * Setting up the CPU map is only relevant for the primary GIC
481 * because any nested/secondary GICs do not directly interface
484 if (gic == &gic_data[0]) {
486 * Get what the GIC says our CPU mask is.
488 BUG_ON(cpu >= NR_GIC_CPU_IF);
489 cpu_mask = gic_get_cpumask(gic);
490 gic_cpu_map[cpu] = cpu_mask;
493 * Clear our mask from the other map entries in case they're
496 for (i = 0; i < NR_GIC_CPU_IF; i++)
498 gic_cpu_map[i] &= ~cpu_mask;
501 gic_cpu_config(dist_base, NULL);
503 writel_relaxed(GICC_INT_PRI_THRESHOLD, base + GIC_CPU_PRIMASK);
507 int gic_cpu_if_down(unsigned int gic_nr)
509 void __iomem *cpu_base;
512 if (gic_nr >= MAX_GIC_NR)
515 cpu_base = gic_data_cpu_base(&gic_data[gic_nr]);
516 val = readl(cpu_base + GIC_CPU_CTRL);
518 writel_relaxed(val, cpu_base + GIC_CPU_CTRL);
525 * Saves the GIC distributor registers during suspend or idle. Must be called
526 * with interrupts disabled but before powering down the GIC. After calling
527 * this function, no interrupts will be delivered by the GIC, and another
528 * platform-specific wakeup source must be enabled.
530 static void gic_dist_save(unsigned int gic_nr)
532 unsigned int gic_irqs;
533 void __iomem *dist_base;
536 if (gic_nr >= MAX_GIC_NR)
539 gic_irqs = gic_data[gic_nr].gic_irqs;
540 dist_base = gic_data_dist_base(&gic_data[gic_nr]);
545 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++)
546 gic_data[gic_nr].saved_spi_conf[i] =
547 readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4);
549 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
550 gic_data[gic_nr].saved_spi_target[i] =
551 readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4);
553 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++)
554 gic_data[gic_nr].saved_spi_enable[i] =
555 readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4);
559 * Restores the GIC distributor registers during resume or when coming out of
560 * idle. Must be called before enabling interrupts. If a level interrupt
561 * that occured while the GIC was suspended is still present, it will be
562 * handled normally, but any edge interrupts that occured will not be seen by
563 * the GIC and need to be handled by the platform-specific wakeup source.
565 static void gic_dist_restore(unsigned int gic_nr)
567 unsigned int gic_irqs;
569 void __iomem *dist_base;
571 if (gic_nr >= MAX_GIC_NR)
574 gic_irqs = gic_data[gic_nr].gic_irqs;
575 dist_base = gic_data_dist_base(&gic_data[gic_nr]);
580 writel_relaxed(GICD_DISABLE, dist_base + GIC_DIST_CTRL);
582 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++)
583 writel_relaxed(gic_data[gic_nr].saved_spi_conf[i],
584 dist_base + GIC_DIST_CONFIG + i * 4);
586 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
587 writel_relaxed(GICD_INT_DEF_PRI_X4,
588 dist_base + GIC_DIST_PRI + i * 4);
590 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
591 writel_relaxed(gic_data[gic_nr].saved_spi_target[i],
592 dist_base + GIC_DIST_TARGET + i * 4);
594 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++)
595 writel_relaxed(gic_data[gic_nr].saved_spi_enable[i],
596 dist_base + GIC_DIST_ENABLE_SET + i * 4);
598 writel_relaxed(GICD_ENABLE, dist_base + GIC_DIST_CTRL);
601 static void gic_cpu_save(unsigned int gic_nr)
605 void __iomem *dist_base;
606 void __iomem *cpu_base;
608 if (gic_nr >= MAX_GIC_NR)
611 dist_base = gic_data_dist_base(&gic_data[gic_nr]);
612 cpu_base = gic_data_cpu_base(&gic_data[gic_nr]);
614 if (!dist_base || !cpu_base)
617 ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_enable);
618 for (i = 0; i < DIV_ROUND_UP(32, 32); i++)
619 ptr[i] = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4);
621 ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_conf);
622 for (i = 0; i < DIV_ROUND_UP(32, 16); i++)
623 ptr[i] = readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4);
627 static void gic_cpu_restore(unsigned int gic_nr)
631 void __iomem *dist_base;
632 void __iomem *cpu_base;
634 if (gic_nr >= MAX_GIC_NR)
637 dist_base = gic_data_dist_base(&gic_data[gic_nr]);
638 cpu_base = gic_data_cpu_base(&gic_data[gic_nr]);
640 if (!dist_base || !cpu_base)
643 ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_enable);
644 for (i = 0; i < DIV_ROUND_UP(32, 32); i++)
645 writel_relaxed(ptr[i], dist_base + GIC_DIST_ENABLE_SET + i * 4);
647 ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_conf);
648 for (i = 0; i < DIV_ROUND_UP(32, 16); i++)
649 writel_relaxed(ptr[i], dist_base + GIC_DIST_CONFIG + i * 4);
651 for (i = 0; i < DIV_ROUND_UP(32, 4); i++)
652 writel_relaxed(GICD_INT_DEF_PRI_X4,
653 dist_base + GIC_DIST_PRI + i * 4);
655 writel_relaxed(GICC_INT_PRI_THRESHOLD, cpu_base + GIC_CPU_PRIMASK);
656 gic_cpu_if_up(&gic_data[gic_nr]);
659 static int gic_notifier(struct notifier_block *self, unsigned long cmd, void *v)
663 for (i = 0; i < MAX_GIC_NR; i++) {
664 #ifdef CONFIG_GIC_NON_BANKED
665 /* Skip over unused GICs */
666 if (!gic_data[i].get_base)
673 case CPU_PM_ENTER_FAILED:
677 case CPU_CLUSTER_PM_ENTER:
680 case CPU_CLUSTER_PM_ENTER_FAILED:
681 case CPU_CLUSTER_PM_EXIT:
690 static struct notifier_block gic_notifier_block = {
691 .notifier_call = gic_notifier,
694 static void __init gic_pm_init(struct gic_chip_data *gic)
696 gic->saved_ppi_enable = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4,
698 BUG_ON(!gic->saved_ppi_enable);
700 gic->saved_ppi_conf = __alloc_percpu(DIV_ROUND_UP(32, 16) * 4,
702 BUG_ON(!gic->saved_ppi_conf);
704 if (gic == &gic_data[0])
705 cpu_pm_register_notifier(&gic_notifier_block);
708 static void __init gic_pm_init(struct gic_chip_data *gic)
714 static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
717 unsigned long flags, map = 0;
719 raw_spin_lock_irqsave(&irq_controller_lock, flags);
721 /* Convert our logical CPU mask into a physical one. */
722 for_each_cpu(cpu, mask)
723 map |= gic_cpu_map[cpu];
726 * Ensure that stores to Normal memory are visible to the
727 * other CPUs before they observe us issuing the IPI.
731 /* this always happens on GIC0 */
732 writel_relaxed(map << 16 | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
734 raw_spin_unlock_irqrestore(&irq_controller_lock, flags);
738 #ifdef CONFIG_BL_SWITCHER
740 * gic_send_sgi - send a SGI directly to given CPU interface number
742 * cpu_id: the ID for the destination CPU interface
743 * irq: the IPI number to send a SGI for
745 void gic_send_sgi(unsigned int cpu_id, unsigned int irq)
747 BUG_ON(cpu_id >= NR_GIC_CPU_IF);
748 cpu_id = 1 << cpu_id;
749 /* this always happens on GIC0 */
750 writel_relaxed((cpu_id << 16) | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
754 * gic_get_cpu_id - get the CPU interface ID for the specified CPU
756 * @cpu: the logical CPU number to get the GIC ID for.
758 * Return the CPU interface ID for the given logical CPU number,
759 * or -1 if the CPU number is too large or the interface ID is
760 * unknown (more than one bit set).
762 int gic_get_cpu_id(unsigned int cpu)
764 unsigned int cpu_bit;
766 if (cpu >= NR_GIC_CPU_IF)
768 cpu_bit = gic_cpu_map[cpu];
769 if (cpu_bit & (cpu_bit - 1))
771 return __ffs(cpu_bit);
775 * gic_migrate_target - migrate IRQs to another CPU interface
777 * @new_cpu_id: the CPU target ID to migrate IRQs to
779 * Migrate all peripheral interrupts with a target matching the current CPU
780 * to the interface corresponding to @new_cpu_id. The CPU interface mapping
781 * is also updated. Targets to other CPU interfaces are unchanged.
782 * This must be called with IRQs locally disabled.
784 void gic_migrate_target(unsigned int new_cpu_id)
786 unsigned int cur_cpu_id, gic_irqs, gic_nr = 0;
787 void __iomem *dist_base;
788 int i, ror_val, cpu = smp_processor_id();
789 u32 val, cur_target_mask, active_mask;
791 if (gic_nr >= MAX_GIC_NR)
794 dist_base = gic_data_dist_base(&gic_data[gic_nr]);
797 gic_irqs = gic_data[gic_nr].gic_irqs;
799 cur_cpu_id = __ffs(gic_cpu_map[cpu]);
800 cur_target_mask = 0x01010101 << cur_cpu_id;
801 ror_val = (cur_cpu_id - new_cpu_id) & 31;
803 raw_spin_lock(&irq_controller_lock);
805 /* Update the target interface for this logical CPU */
806 gic_cpu_map[cpu] = 1 << new_cpu_id;
809 * Find all the peripheral interrupts targetting the current
810 * CPU interface and migrate them to the new CPU interface.
811 * We skip DIST_TARGET 0 to 7 as they are read-only.
813 for (i = 8; i < DIV_ROUND_UP(gic_irqs, 4); i++) {
814 val = readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4);
815 active_mask = val & cur_target_mask;
818 val |= ror32(active_mask, ror_val);
819 writel_relaxed(val, dist_base + GIC_DIST_TARGET + i*4);
823 raw_spin_unlock(&irq_controller_lock);
826 * Now let's migrate and clear any potential SGIs that might be
827 * pending for us (cur_cpu_id). Since GIC_DIST_SGI_PENDING_SET
828 * is a banked register, we can only forward the SGI using
829 * GIC_DIST_SOFTINT. The original SGI source is lost but Linux
830 * doesn't use that information anyway.
832 * For the same reason we do not adjust SGI source information
833 * for previously sent SGIs by us to other CPUs either.
835 for (i = 0; i < 16; i += 4) {
837 val = readl_relaxed(dist_base + GIC_DIST_SGI_PENDING_SET + i);
840 writel_relaxed(val, dist_base + GIC_DIST_SGI_PENDING_CLEAR + i);
841 for (j = i; j < i + 4; j++) {
843 writel_relaxed((1 << (new_cpu_id + 16)) | j,
844 dist_base + GIC_DIST_SOFTINT);
851 * gic_get_sgir_physaddr - get the physical address for the SGI register
853 * REturn the physical address of the SGI register to be used
854 * by some early assembly code when the kernel is not yet available.
856 static unsigned long gic_dist_physaddr;
858 unsigned long gic_get_sgir_physaddr(void)
860 if (!gic_dist_physaddr)
862 return gic_dist_physaddr + GIC_DIST_SOFTINT;
865 void __init gic_init_physaddr(struct device_node *node)
868 if (of_address_to_resource(node, 0, &res) == 0) {
869 gic_dist_physaddr = res.start;
870 pr_info("GIC physical location is %#lx\n", gic_dist_physaddr);
875 #define gic_init_physaddr(node) do { } while (0)
878 static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq,
881 struct irq_chip *chip = &gic_chip;
883 if (static_key_true(&supports_deactivate)) {
884 if (d->host_data == (void *)&gic_data[0])
885 chip = &gic_eoimode1_chip;
889 irq_set_percpu_devid(irq);
890 irq_domain_set_info(d, irq, hw, chip, d->host_data,
891 handle_percpu_devid_irq, NULL, NULL);
892 irq_set_status_flags(irq, IRQ_NOAUTOEN);
894 irq_domain_set_info(d, irq, hw, chip, d->host_data,
895 handle_fasteoi_irq, NULL, NULL);
901 static void gic_irq_domain_unmap(struct irq_domain *d, unsigned int irq)
905 static int gic_irq_domain_xlate(struct irq_domain *d,
906 struct device_node *controller,
907 const u32 *intspec, unsigned int intsize,
908 unsigned long *out_hwirq, unsigned int *out_type)
910 unsigned long ret = 0;
912 if (d->of_node != controller)
917 /* Get the interrupt number and add 16 to skip over SGIs */
918 *out_hwirq = intspec[1] + 16;
920 /* For SPIs, we need to add 16 more to get the GIC irq ID number */
924 *out_type = intspec[2] & IRQ_TYPE_SENSE_MASK;
930 static int gic_secondary_init(struct notifier_block *nfb, unsigned long action,
933 if (action == CPU_STARTING || action == CPU_STARTING_FROZEN)
934 gic_cpu_init(&gic_data[0]);
939 * Notifier for enabling the GIC CPU interface. Set an arbitrarily high
940 * priority because the GIC needs to be up before the ARM generic timers.
942 static struct notifier_block gic_cpu_notifier = {
943 .notifier_call = gic_secondary_init,
948 static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
949 unsigned int nr_irqs, void *arg)
952 irq_hw_number_t hwirq;
953 unsigned int type = IRQ_TYPE_NONE;
954 struct of_phandle_args *irq_data = arg;
956 ret = gic_irq_domain_xlate(domain, irq_data->np, irq_data->args,
957 irq_data->args_count, &hwirq, &type);
961 for (i = 0; i < nr_irqs; i++)
962 gic_irq_domain_map(domain, virq + i, hwirq + i);
967 static const struct irq_domain_ops gic_irq_domain_hierarchy_ops = {
968 .xlate = gic_irq_domain_xlate,
969 .alloc = gic_irq_domain_alloc,
970 .free = irq_domain_free_irqs_top,
973 static const struct irq_domain_ops gic_irq_domain_ops = {
974 .map = gic_irq_domain_map,
975 .unmap = gic_irq_domain_unmap,
976 .xlate = gic_irq_domain_xlate,
979 static void __init __gic_init_bases(unsigned int gic_nr, int irq_start,
980 void __iomem *dist_base, void __iomem *cpu_base,
981 u32 percpu_offset, struct device_node *node)
983 irq_hw_number_t hwirq_base;
984 struct gic_chip_data *gic;
985 int gic_irqs, irq_base, i;
987 BUG_ON(gic_nr >= MAX_GIC_NR);
989 gic = &gic_data[gic_nr];
990 #ifdef CONFIG_GIC_NON_BANKED
991 if (percpu_offset) { /* Frankein-GIC without banked registers... */
994 gic->dist_base.percpu_base = alloc_percpu(void __iomem *);
995 gic->cpu_base.percpu_base = alloc_percpu(void __iomem *);
996 if (WARN_ON(!gic->dist_base.percpu_base ||
997 !gic->cpu_base.percpu_base)) {
998 free_percpu(gic->dist_base.percpu_base);
999 free_percpu(gic->cpu_base.percpu_base);
1003 for_each_possible_cpu(cpu) {
1004 u32 mpidr = cpu_logical_map(cpu);
1005 u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
1006 unsigned long offset = percpu_offset * core_id;
1007 *per_cpu_ptr(gic->dist_base.percpu_base, cpu) = dist_base + offset;
1008 *per_cpu_ptr(gic->cpu_base.percpu_base, cpu) = cpu_base + offset;
1011 gic_set_base_accessor(gic, gic_get_percpu_base);
1014 { /* Normal, sane GIC... */
1016 "GIC_NON_BANKED not enabled, ignoring %08x offset!",
1018 gic->dist_base.common_base = dist_base;
1019 gic->cpu_base.common_base = cpu_base;
1020 gic_set_base_accessor(gic, gic_get_common_base);
1024 * Find out how many interrupts are supported.
1025 * The GIC only supports up to 1020 interrupt sources.
1027 gic_irqs = readl_relaxed(gic_data_dist_base(gic) + GIC_DIST_CTR) & 0x1f;
1028 gic_irqs = (gic_irqs + 1) * 32;
1029 if (gic_irqs > 1020)
1031 gic->gic_irqs = gic_irqs;
1033 if (node) { /* DT case */
1034 gic->domain = irq_domain_add_linear(node, gic_irqs,
1035 &gic_irq_domain_hierarchy_ops,
1037 } else { /* Non-DT case */
1039 * For primary GICs, skip over SGIs.
1040 * For secondary GICs, skip over PPIs, too.
1042 if (gic_nr == 0 && (irq_start & 31) > 0) {
1044 if (irq_start != -1)
1045 irq_start = (irq_start & ~31) + 16;
1050 gic_irqs -= hwirq_base; /* calculate # of irqs to allocate */
1052 irq_base = irq_alloc_descs(irq_start, 16, gic_irqs,
1054 if (IS_ERR_VALUE(irq_base)) {
1055 WARN(1, "Cannot allocate irq_descs @ IRQ%d, assuming pre-allocated\n",
1057 irq_base = irq_start;
1060 gic->domain = irq_domain_add_legacy(node, gic_irqs, irq_base,
1061 hwirq_base, &gic_irq_domain_ops, gic);
1064 if (WARN_ON(!gic->domain))
1069 * Initialize the CPU interface map to all CPUs.
1070 * It will be refined as each CPU probes its ID.
1071 * This is only necessary for the primary GIC.
1073 for (i = 0; i < NR_GIC_CPU_IF; i++)
1074 gic_cpu_map[i] = 0xff;
1076 set_smp_cross_call(gic_raise_softirq);
1077 register_cpu_notifier(&gic_cpu_notifier);
1079 set_handle_irq(gic_handle_irq);
1080 if (static_key_true(&supports_deactivate))
1081 pr_info("GIC: Using split EOI/Deactivate mode\n");
1089 void __init gic_init_bases(unsigned int gic_nr, int irq_start,
1090 void __iomem *dist_base, void __iomem *cpu_base,
1091 u32 percpu_offset, struct device_node *node)
1094 * Non-DT/ACPI systems won't run a hypervisor, so let's not
1095 * bother with these...
1097 static_key_slow_dec(&supports_deactivate);
1098 __gic_init_bases(gic_nr, irq_start, dist_base, cpu_base,
1099 percpu_offset, node);
1103 static int gic_cnt __initdata;
1105 static bool gic_check_eoimode(struct device_node *node, void __iomem **base)
1107 struct resource cpuif_res;
1109 of_address_to_resource(node, 1, &cpuif_res);
1111 if (!is_hyp_mode_available())
1113 if (resource_size(&cpuif_res) < SZ_8K)
1115 if (resource_size(&cpuif_res) == SZ_128K) {
1116 u32 val_low, val_high;
1119 * Verify that we have the first 4kB of a GIC400
1120 * aliased over the first 64kB by checking the
1121 * GICC_IIDR register on both ends.
1123 val_low = readl_relaxed(*base + GIC_CPU_IDENT);
1124 val_high = readl_relaxed(*base + GIC_CPU_IDENT + 0xf000);
1125 if ((val_low & 0xffff0fff) != 0x0202043B ||
1126 val_low != val_high)
1130 * Move the base up by 60kB, so that we have a 8kB
1131 * contiguous region, which allows us to use GICC_DIR
1132 * at its normal offset. Please pass me that bucket.
1135 cpuif_res.start += 0xf000;
1136 pr_warn("GIC: Adjusting CPU interface base to %pa",
1144 gic_of_init(struct device_node *node, struct device_node *parent)
1146 void __iomem *cpu_base;
1147 void __iomem *dist_base;
1154 dist_base = of_iomap(node, 0);
1155 WARN(!dist_base, "unable to map gic dist registers\n");
1157 cpu_base = of_iomap(node, 1);
1158 WARN(!cpu_base, "unable to map gic cpu registers\n");
1161 * Disable split EOI/Deactivate if either HYP is not available
1162 * or the CPU interface is too small.
1164 if (gic_cnt == 0 && !gic_check_eoimode(node, &cpu_base))
1165 static_key_slow_dec(&supports_deactivate);
1167 if (of_property_read_u32(node, "cpu-offset", &percpu_offset))
1170 __gic_init_bases(gic_cnt, -1, dist_base, cpu_base, percpu_offset, node);
1172 gic_init_physaddr(node);
1175 irq = irq_of_parse_and_map(node, 0);
1176 gic_cascade_irq(gic_cnt, irq);
1179 if (IS_ENABLED(CONFIG_ARM_GIC_V2M))
1180 gicv2m_of_init(node, gic_data[gic_cnt].domain);
1185 IRQCHIP_DECLARE(gic_400, "arm,gic-400", gic_of_init);
1186 IRQCHIP_DECLARE(arm11mp_gic, "arm,arm11mp-gic", gic_of_init);
1187 IRQCHIP_DECLARE(arm1176jzf_dc_gic, "arm,arm1176jzf-devchip-gic", gic_of_init);
1188 IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init);
1189 IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init);
1190 IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init);
1191 IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init);
1192 IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init);
1197 static phys_addr_t cpu_phy_base __initdata;
1200 gic_acpi_parse_madt_cpu(struct acpi_subtable_header *header,
1201 const unsigned long end)
1203 struct acpi_madt_generic_interrupt *processor;
1204 phys_addr_t gic_cpu_base;
1205 static int cpu_base_assigned;
1207 processor = (struct acpi_madt_generic_interrupt *)header;
1209 if (BAD_MADT_GICC_ENTRY(processor, end))
1213 * There is no support for non-banked GICv1/2 register in ACPI spec.
1214 * All CPU interface addresses have to be the same.
1216 gic_cpu_base = processor->base_address;
1217 if (cpu_base_assigned && gic_cpu_base != cpu_phy_base)
1220 cpu_phy_base = gic_cpu_base;
1221 cpu_base_assigned = 1;
1225 /* The things you have to do to just *count* something... */
1226 static int __init acpi_dummy_func(struct acpi_subtable_header *header,
1227 const unsigned long end)
1232 static bool __init acpi_gic_redist_is_present(void)
1234 return acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR,
1235 acpi_dummy_func, 0) > 0;
1238 static bool __init gic_validate_dist(struct acpi_subtable_header *header,
1239 struct acpi_probe_entry *ape)
1241 struct acpi_madt_generic_distributor *dist;
1242 dist = (struct acpi_madt_generic_distributor *)header;
1244 return (dist->version == ape->driver_data &&
1245 (dist->version != ACPI_MADT_GIC_VERSION_NONE ||
1246 !acpi_gic_redist_is_present()));
1249 #define ACPI_GICV2_DIST_MEM_SIZE (SZ_4K)
1250 #define ACPI_GIC_CPU_IF_MEM_SIZE (SZ_8K)
1252 static int __init gic_v2_acpi_init(struct acpi_subtable_header *header,
1253 const unsigned long end)
1255 struct acpi_madt_generic_distributor *dist;
1256 void __iomem *cpu_base, *dist_base;
1259 /* Collect CPU base addresses */
1260 count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT,
1261 gic_acpi_parse_madt_cpu, 0);
1263 pr_err("No valid GICC entries exist\n");
1267 cpu_base = ioremap(cpu_phy_base, ACPI_GIC_CPU_IF_MEM_SIZE);
1269 pr_err("Unable to map GICC registers\n");
1273 dist = (struct acpi_madt_generic_distributor *)header;
1274 dist_base = ioremap(dist->base_address, ACPI_GICV2_DIST_MEM_SIZE);
1276 pr_err("Unable to map GICD registers\n");
1282 * Disable split EOI/Deactivate if HYP is not available. ACPI
1283 * guarantees that we'll always have a GICv2, so the CPU
1284 * interface will always be the right size.
1286 if (!is_hyp_mode_available())
1287 static_key_slow_dec(&supports_deactivate);
1290 * Initialize zero GIC instance (no multi-GIC support). Also, set GIC
1291 * as default IRQ domain to allow for GSI registration and GSI to IRQ
1292 * number translation (see acpi_register_gsi() and acpi_gsi_to_irq()).
1294 __gic_init_bases(0, -1, dist_base, cpu_base, 0, NULL);
1295 irq_set_default_host(gic_data[0].domain);
1297 acpi_irq_model = ACPI_IRQ_MODEL_GIC;
1300 IRQCHIP_ACPI_DECLARE(gic_v2, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR,
1301 gic_validate_dist, ACPI_MADT_GIC_VERSION_V2,
1303 IRQCHIP_ACPI_DECLARE(gic_v2_maybe, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR,
1304 gic_validate_dist, ACPI_MADT_GIC_VERSION_NONE,