2 * Copyright (C) 2002 ARM Limited, All Rights Reserved.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
8 * Interrupt architecture for the GIC:
10 * o There is one Interrupt Distributor, which receives interrupts
11 * from system devices and sends them to the Interrupt Controllers.
13 * o There is one CPU Interface per CPU, which sends interrupts sent
14 * by the Distributor, and interrupts generated locally, to the
15 * associated CPU. The base address of the CPU interface is usually
16 * aliased so that the same address points to different chips depending
17 * on the CPU it is accessed from.
19 * Note that IRQs 0-31 are special - they are local to each CPU.
20 * As such, the enable set/clear, pending set/clear and active bit
21 * registers are banked per-cpu for these sources.
23 #include <linux/init.h>
24 #include <linux/kernel.h>
25 #include <linux/err.h>
26 #include <linux/module.h>
27 #include <linux/list.h>
28 #include <linux/smp.h>
29 #include <linux/cpu.h>
30 #include <linux/cpu_pm.h>
31 #include <linux/cpumask.h>
34 #include <linux/of_address.h>
35 #include <linux/of_irq.h>
36 #include <linux/acpi.h>
37 #include <linux/irqdomain.h>
38 #include <linux/interrupt.h>
39 #include <linux/percpu.h>
40 #include <linux/slab.h>
41 #include <linux/irqchip.h>
42 #include <linux/irqchip/chained_irq.h>
43 #include <linux/irqchip/arm-gic.h>
44 #include <linux/irqchip/arm-gic-acpi.h>
46 #include <asm/cputype.h>
48 #include <asm/exception.h>
49 #include <asm/smp_plat.h>
52 #include "irq-gic-common.h"
55 #include <asm/cpufeature.h>
57 static void gic_check_cpu_features(void)
59 WARN_TAINT_ONCE(cpus_have_cap(ARM64_HAS_SYSREG_GIC_CPUIF),
60 TAINT_CPU_OUT_OF_SPEC,
61 "GICv3 system registers enabled, broken firmware!\n");
64 #define gic_check_cpu_features() do { } while(0)
68 void __iomem *common_base;
69 void __percpu * __iomem *percpu_base;
72 struct gic_chip_data {
73 union gic_base dist_base;
74 union gic_base cpu_base;
76 u32 saved_spi_enable[DIV_ROUND_UP(1020, 32)];
77 u32 saved_spi_conf[DIV_ROUND_UP(1020, 16)];
78 u32 saved_spi_target[DIV_ROUND_UP(1020, 4)];
79 u32 __percpu *saved_ppi_enable;
80 u32 __percpu *saved_ppi_conf;
82 struct irq_domain *domain;
83 unsigned int gic_irqs;
84 #ifdef CONFIG_GIC_NON_BANKED
85 void __iomem *(*get_base)(union gic_base *);
89 static DEFINE_RAW_SPINLOCK(irq_controller_lock);
92 * The GIC mapping of CPU interfaces does not necessarily match
93 * the logical CPU numbering. Let's use a mapping as returned
96 #define NR_GIC_CPU_IF 8
97 static u8 gic_cpu_map[NR_GIC_CPU_IF] __read_mostly;
99 static struct static_key supports_deactivate = STATIC_KEY_INIT_TRUE;
105 static struct gic_chip_data gic_data[MAX_GIC_NR] __read_mostly;
107 #ifdef CONFIG_GIC_NON_BANKED
108 static void __iomem *gic_get_percpu_base(union gic_base *base)
110 return raw_cpu_read(*base->percpu_base);
113 static void __iomem *gic_get_common_base(union gic_base *base)
115 return base->common_base;
118 static inline void __iomem *gic_data_dist_base(struct gic_chip_data *data)
120 return data->get_base(&data->dist_base);
123 static inline void __iomem *gic_data_cpu_base(struct gic_chip_data *data)
125 return data->get_base(&data->cpu_base);
128 static inline void gic_set_base_accessor(struct gic_chip_data *data,
129 void __iomem *(*f)(union gic_base *))
134 #define gic_data_dist_base(d) ((d)->dist_base.common_base)
135 #define gic_data_cpu_base(d) ((d)->cpu_base.common_base)
136 #define gic_set_base_accessor(d, f)
139 static inline void __iomem *gic_dist_base(struct irq_data *d)
141 struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
142 return gic_data_dist_base(gic_data);
145 static inline void __iomem *gic_cpu_base(struct irq_data *d)
147 struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
148 return gic_data_cpu_base(gic_data);
151 static inline unsigned int gic_irq(struct irq_data *d)
156 static inline bool cascading_gic_irq(struct irq_data *d)
158 void *data = irq_data_get_irq_handler_data(d);
161 * If handler_data is set, this is a cascading interrupt, and
162 * it cannot possibly be forwarded.
168 * Routines to acknowledge, disable and enable interrupts
170 static void gic_poke_irq(struct irq_data *d, u32 offset)
172 u32 mask = 1 << (gic_irq(d) % 32);
173 writel_relaxed(mask, gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4);
176 static int gic_peek_irq(struct irq_data *d, u32 offset)
178 u32 mask = 1 << (gic_irq(d) % 32);
179 return !!(readl_relaxed(gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4) & mask);
182 static void gic_mask_irq(struct irq_data *d)
184 gic_poke_irq(d, GIC_DIST_ENABLE_CLEAR);
187 static void gic_eoimode1_mask_irq(struct irq_data *d)
191 * When masking a forwarded interrupt, make sure it is
192 * deactivated as well.
194 * This ensures that an interrupt that is getting
195 * disabled/masked will not get "stuck", because there is
196 * noone to deactivate it (guest is being terminated).
198 if (irqd_is_forwarded_to_vcpu(d))
199 gic_poke_irq(d, GIC_DIST_ACTIVE_CLEAR);
202 static void gic_unmask_irq(struct irq_data *d)
204 gic_poke_irq(d, GIC_DIST_ENABLE_SET);
207 static void gic_eoi_irq(struct irq_data *d)
209 writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI);
212 static void gic_eoimode1_eoi_irq(struct irq_data *d)
214 /* Do not deactivate an IRQ forwarded to a vcpu. */
215 if (irqd_is_forwarded_to_vcpu(d))
218 writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_DEACTIVATE);
221 static int gic_irq_set_irqchip_state(struct irq_data *d,
222 enum irqchip_irq_state which, bool val)
227 case IRQCHIP_STATE_PENDING:
228 reg = val ? GIC_DIST_PENDING_SET : GIC_DIST_PENDING_CLEAR;
231 case IRQCHIP_STATE_ACTIVE:
232 reg = val ? GIC_DIST_ACTIVE_SET : GIC_DIST_ACTIVE_CLEAR;
235 case IRQCHIP_STATE_MASKED:
236 reg = val ? GIC_DIST_ENABLE_CLEAR : GIC_DIST_ENABLE_SET;
243 gic_poke_irq(d, reg);
247 static int gic_irq_get_irqchip_state(struct irq_data *d,
248 enum irqchip_irq_state which, bool *val)
251 case IRQCHIP_STATE_PENDING:
252 *val = gic_peek_irq(d, GIC_DIST_PENDING_SET);
255 case IRQCHIP_STATE_ACTIVE:
256 *val = gic_peek_irq(d, GIC_DIST_ACTIVE_SET);
259 case IRQCHIP_STATE_MASKED:
260 *val = !gic_peek_irq(d, GIC_DIST_ENABLE_SET);
270 static int gic_set_type(struct irq_data *d, unsigned int type)
272 void __iomem *base = gic_dist_base(d);
273 unsigned int gicirq = gic_irq(d);
275 /* Interrupt configuration for SGIs can't be changed */
279 /* SPIs have restrictions on the supported types */
280 if (gicirq >= 32 && type != IRQ_TYPE_LEVEL_HIGH &&
281 type != IRQ_TYPE_EDGE_RISING)
284 return gic_configure_irq(gicirq, type, base, NULL);
287 static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu)
289 /* Only interrupts on the primary GIC can be forwarded to a vcpu. */
290 if (cascading_gic_irq(d))
294 irqd_set_forwarded_to_vcpu(d);
296 irqd_clr_forwarded_to_vcpu(d);
301 static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
304 void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + (gic_irq(d) & ~3);
305 unsigned int cpu, shift = (gic_irq(d) % 4) * 8;
310 cpu = cpumask_any_and(mask_val, cpu_online_mask);
312 cpu = cpumask_first(mask_val);
314 if (cpu >= NR_GIC_CPU_IF || cpu >= nr_cpu_ids)
317 raw_spin_lock_irqsave(&irq_controller_lock, flags);
318 mask = 0xff << shift;
319 bit = gic_cpu_map[cpu] << shift;
320 val = readl_relaxed(reg) & ~mask;
321 writel_relaxed(val | bit, reg);
322 raw_spin_unlock_irqrestore(&irq_controller_lock, flags);
324 return IRQ_SET_MASK_OK;
328 static void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
331 struct gic_chip_data *gic = &gic_data[0];
332 void __iomem *cpu_base = gic_data_cpu_base(gic);
335 irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK);
336 irqnr = irqstat & GICC_IAR_INT_ID_MASK;
338 if (likely(irqnr > 15 && irqnr < 1021)) {
339 if (static_key_true(&supports_deactivate))
340 writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI);
341 handle_domain_irq(gic->domain, irqnr, regs);
345 writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI);
346 if (static_key_true(&supports_deactivate))
347 writel_relaxed(irqstat, cpu_base + GIC_CPU_DEACTIVATE);
349 handle_IPI(irqnr, regs);
357 static void gic_handle_cascade_irq(struct irq_desc *desc)
359 struct gic_chip_data *chip_data = irq_desc_get_handler_data(desc);
360 struct irq_chip *chip = irq_desc_get_chip(desc);
361 unsigned int cascade_irq, gic_irq;
362 unsigned long status;
364 chained_irq_enter(chip, desc);
366 raw_spin_lock(&irq_controller_lock);
367 status = readl_relaxed(gic_data_cpu_base(chip_data) + GIC_CPU_INTACK);
368 raw_spin_unlock(&irq_controller_lock);
370 gic_irq = (status & GICC_IAR_INT_ID_MASK);
371 if (gic_irq == GICC_INT_SPURIOUS)
374 cascade_irq = irq_find_mapping(chip_data->domain, gic_irq);
375 if (unlikely(gic_irq < 32 || gic_irq > 1020))
376 handle_bad_irq(desc);
378 generic_handle_irq(cascade_irq);
381 chained_irq_exit(chip, desc);
384 static struct irq_chip gic_chip = {
386 .irq_mask = gic_mask_irq,
387 .irq_unmask = gic_unmask_irq,
388 .irq_eoi = gic_eoi_irq,
389 .irq_set_type = gic_set_type,
391 .irq_set_affinity = gic_set_affinity,
393 .irq_get_irqchip_state = gic_irq_get_irqchip_state,
394 .irq_set_irqchip_state = gic_irq_set_irqchip_state,
395 .flags = IRQCHIP_SET_TYPE_MASKED |
396 IRQCHIP_SKIP_SET_WAKE |
397 IRQCHIP_MASK_ON_SUSPEND,
400 static struct irq_chip gic_eoimode1_chip = {
402 .irq_mask = gic_eoimode1_mask_irq,
403 .irq_unmask = gic_unmask_irq,
404 .irq_eoi = gic_eoimode1_eoi_irq,
405 .irq_set_type = gic_set_type,
407 .irq_set_affinity = gic_set_affinity,
409 .irq_get_irqchip_state = gic_irq_get_irqchip_state,
410 .irq_set_irqchip_state = gic_irq_set_irqchip_state,
411 .irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity,
412 .flags = IRQCHIP_SET_TYPE_MASKED |
413 IRQCHIP_SKIP_SET_WAKE |
414 IRQCHIP_MASK_ON_SUSPEND,
417 void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq)
419 if (gic_nr >= MAX_GIC_NR)
421 irq_set_chained_handler_and_data(irq, gic_handle_cascade_irq,
425 static u8 gic_get_cpumask(struct gic_chip_data *gic)
427 void __iomem *base = gic_data_dist_base(gic);
430 for (i = mask = 0; i < 32; i += 4) {
431 mask = readl_relaxed(base + GIC_DIST_TARGET + i);
438 if (!mask && num_possible_cpus() > 1)
439 pr_crit("GIC CPU mask not found - kernel will fail to boot.\n");
444 static void gic_cpu_if_up(struct gic_chip_data *gic)
446 void __iomem *cpu_base = gic_data_cpu_base(gic);
450 if (static_key_true(&supports_deactivate))
451 mode = GIC_CPU_CTRL_EOImodeNS;
454 * Preserve bypass disable bits to be written back later
456 bypass = readl(cpu_base + GIC_CPU_CTRL);
457 bypass &= GICC_DIS_BYPASS_MASK;
459 writel_relaxed(bypass | mode | GICC_ENABLE, cpu_base + GIC_CPU_CTRL);
463 static void __init gic_dist_init(struct gic_chip_data *gic)
467 unsigned int gic_irqs = gic->gic_irqs;
468 void __iomem *base = gic_data_dist_base(gic);
470 writel_relaxed(GICD_DISABLE, base + GIC_DIST_CTRL);
473 * Set all global interrupts to this CPU only.
475 cpumask = gic_get_cpumask(gic);
476 cpumask |= cpumask << 8;
477 cpumask |= cpumask << 16;
478 for (i = 32; i < gic_irqs; i += 4)
479 writel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4 / 4);
481 gic_dist_config(base, gic_irqs, NULL);
483 writel_relaxed(GICD_ENABLE, base + GIC_DIST_CTRL);
486 static void gic_cpu_init(struct gic_chip_data *gic)
488 void __iomem *dist_base = gic_data_dist_base(gic);
489 void __iomem *base = gic_data_cpu_base(gic);
490 unsigned int cpu_mask, cpu = smp_processor_id();
494 * Setting up the CPU map is only relevant for the primary GIC
495 * because any nested/secondary GICs do not directly interface
498 if (gic == &gic_data[0]) {
500 * Get what the GIC says our CPU mask is.
502 BUG_ON(cpu >= NR_GIC_CPU_IF);
503 cpu_mask = gic_get_cpumask(gic);
504 gic_cpu_map[cpu] = cpu_mask;
507 * Clear our mask from the other map entries in case they're
510 for (i = 0; i < NR_GIC_CPU_IF; i++)
512 gic_cpu_map[i] &= ~cpu_mask;
515 gic_cpu_config(dist_base, NULL);
517 writel_relaxed(GICC_INT_PRI_THRESHOLD, base + GIC_CPU_PRIMASK);
521 int gic_cpu_if_down(unsigned int gic_nr)
523 void __iomem *cpu_base;
526 if (gic_nr >= MAX_GIC_NR)
529 cpu_base = gic_data_cpu_base(&gic_data[gic_nr]);
530 val = readl(cpu_base + GIC_CPU_CTRL);
532 writel_relaxed(val, cpu_base + GIC_CPU_CTRL);
539 * Saves the GIC distributor registers during suspend or idle. Must be called
540 * with interrupts disabled but before powering down the GIC. After calling
541 * this function, no interrupts will be delivered by the GIC, and another
542 * platform-specific wakeup source must be enabled.
544 static void gic_dist_save(unsigned int gic_nr)
546 unsigned int gic_irqs;
547 void __iomem *dist_base;
550 if (gic_nr >= MAX_GIC_NR)
553 gic_irqs = gic_data[gic_nr].gic_irqs;
554 dist_base = gic_data_dist_base(&gic_data[gic_nr]);
559 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++)
560 gic_data[gic_nr].saved_spi_conf[i] =
561 readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4);
563 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
564 gic_data[gic_nr].saved_spi_target[i] =
565 readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4);
567 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++)
568 gic_data[gic_nr].saved_spi_enable[i] =
569 readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4);
573 * Restores the GIC distributor registers during resume or when coming out of
574 * idle. Must be called before enabling interrupts. If a level interrupt
575 * that occured while the GIC was suspended is still present, it will be
576 * handled normally, but any edge interrupts that occured will not be seen by
577 * the GIC and need to be handled by the platform-specific wakeup source.
579 static void gic_dist_restore(unsigned int gic_nr)
581 unsigned int gic_irqs;
583 void __iomem *dist_base;
585 if (gic_nr >= MAX_GIC_NR)
588 gic_irqs = gic_data[gic_nr].gic_irqs;
589 dist_base = gic_data_dist_base(&gic_data[gic_nr]);
594 writel_relaxed(GICD_DISABLE, dist_base + GIC_DIST_CTRL);
596 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++)
597 writel_relaxed(gic_data[gic_nr].saved_spi_conf[i],
598 dist_base + GIC_DIST_CONFIG + i * 4);
600 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
601 writel_relaxed(GICD_INT_DEF_PRI_X4,
602 dist_base + GIC_DIST_PRI + i * 4);
604 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
605 writel_relaxed(gic_data[gic_nr].saved_spi_target[i],
606 dist_base + GIC_DIST_TARGET + i * 4);
608 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++)
609 writel_relaxed(gic_data[gic_nr].saved_spi_enable[i],
610 dist_base + GIC_DIST_ENABLE_SET + i * 4);
612 writel_relaxed(GICD_ENABLE, dist_base + GIC_DIST_CTRL);
615 static void gic_cpu_save(unsigned int gic_nr)
619 void __iomem *dist_base;
620 void __iomem *cpu_base;
622 if (gic_nr >= MAX_GIC_NR)
625 dist_base = gic_data_dist_base(&gic_data[gic_nr]);
626 cpu_base = gic_data_cpu_base(&gic_data[gic_nr]);
628 if (!dist_base || !cpu_base)
631 ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_enable);
632 for (i = 0; i < DIV_ROUND_UP(32, 32); i++)
633 ptr[i] = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4);
635 ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_conf);
636 for (i = 0; i < DIV_ROUND_UP(32, 16); i++)
637 ptr[i] = readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4);
641 static void gic_cpu_restore(unsigned int gic_nr)
645 void __iomem *dist_base;
646 void __iomem *cpu_base;
648 if (gic_nr >= MAX_GIC_NR)
651 dist_base = gic_data_dist_base(&gic_data[gic_nr]);
652 cpu_base = gic_data_cpu_base(&gic_data[gic_nr]);
654 if (!dist_base || !cpu_base)
657 ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_enable);
658 for (i = 0; i < DIV_ROUND_UP(32, 32); i++)
659 writel_relaxed(ptr[i], dist_base + GIC_DIST_ENABLE_SET + i * 4);
661 ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_conf);
662 for (i = 0; i < DIV_ROUND_UP(32, 16); i++)
663 writel_relaxed(ptr[i], dist_base + GIC_DIST_CONFIG + i * 4);
665 for (i = 0; i < DIV_ROUND_UP(32, 4); i++)
666 writel_relaxed(GICD_INT_DEF_PRI_X4,
667 dist_base + GIC_DIST_PRI + i * 4);
669 writel_relaxed(GICC_INT_PRI_THRESHOLD, cpu_base + GIC_CPU_PRIMASK);
670 gic_cpu_if_up(&gic_data[gic_nr]);
673 static int gic_notifier(struct notifier_block *self, unsigned long cmd, void *v)
677 for (i = 0; i < MAX_GIC_NR; i++) {
678 #ifdef CONFIG_GIC_NON_BANKED
679 /* Skip over unused GICs */
680 if (!gic_data[i].get_base)
687 case CPU_PM_ENTER_FAILED:
691 case CPU_CLUSTER_PM_ENTER:
694 case CPU_CLUSTER_PM_ENTER_FAILED:
695 case CPU_CLUSTER_PM_EXIT:
704 static struct notifier_block gic_notifier_block = {
705 .notifier_call = gic_notifier,
708 static void __init gic_pm_init(struct gic_chip_data *gic)
710 gic->saved_ppi_enable = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4,
712 BUG_ON(!gic->saved_ppi_enable);
714 gic->saved_ppi_conf = __alloc_percpu(DIV_ROUND_UP(32, 16) * 4,
716 BUG_ON(!gic->saved_ppi_conf);
718 if (gic == &gic_data[0])
719 cpu_pm_register_notifier(&gic_notifier_block);
722 static void __init gic_pm_init(struct gic_chip_data *gic)
728 static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
731 unsigned long flags, map = 0;
733 raw_spin_lock_irqsave(&irq_controller_lock, flags);
735 /* Convert our logical CPU mask into a physical one. */
736 for_each_cpu(cpu, mask)
737 map |= gic_cpu_map[cpu];
740 * Ensure that stores to Normal memory are visible to the
741 * other CPUs before they observe us issuing the IPI.
745 /* this always happens on GIC0 */
746 writel_relaxed(map << 16 | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
748 raw_spin_unlock_irqrestore(&irq_controller_lock, flags);
752 #ifdef CONFIG_BL_SWITCHER
754 * gic_send_sgi - send a SGI directly to given CPU interface number
756 * cpu_id: the ID for the destination CPU interface
757 * irq: the IPI number to send a SGI for
759 void gic_send_sgi(unsigned int cpu_id, unsigned int irq)
761 BUG_ON(cpu_id >= NR_GIC_CPU_IF);
762 cpu_id = 1 << cpu_id;
763 /* this always happens on GIC0 */
764 writel_relaxed((cpu_id << 16) | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
768 * gic_get_cpu_id - get the CPU interface ID for the specified CPU
770 * @cpu: the logical CPU number to get the GIC ID for.
772 * Return the CPU interface ID for the given logical CPU number,
773 * or -1 if the CPU number is too large or the interface ID is
774 * unknown (more than one bit set).
776 int gic_get_cpu_id(unsigned int cpu)
778 unsigned int cpu_bit;
780 if (cpu >= NR_GIC_CPU_IF)
782 cpu_bit = gic_cpu_map[cpu];
783 if (cpu_bit & (cpu_bit - 1))
785 return __ffs(cpu_bit);
789 * gic_migrate_target - migrate IRQs to another CPU interface
791 * @new_cpu_id: the CPU target ID to migrate IRQs to
793 * Migrate all peripheral interrupts with a target matching the current CPU
794 * to the interface corresponding to @new_cpu_id. The CPU interface mapping
795 * is also updated. Targets to other CPU interfaces are unchanged.
796 * This must be called with IRQs locally disabled.
798 void gic_migrate_target(unsigned int new_cpu_id)
800 unsigned int cur_cpu_id, gic_irqs, gic_nr = 0;
801 void __iomem *dist_base;
802 int i, ror_val, cpu = smp_processor_id();
803 u32 val, cur_target_mask, active_mask;
805 if (gic_nr >= MAX_GIC_NR)
808 dist_base = gic_data_dist_base(&gic_data[gic_nr]);
811 gic_irqs = gic_data[gic_nr].gic_irqs;
813 cur_cpu_id = __ffs(gic_cpu_map[cpu]);
814 cur_target_mask = 0x01010101 << cur_cpu_id;
815 ror_val = (cur_cpu_id - new_cpu_id) & 31;
817 raw_spin_lock(&irq_controller_lock);
819 /* Update the target interface for this logical CPU */
820 gic_cpu_map[cpu] = 1 << new_cpu_id;
823 * Find all the peripheral interrupts targetting the current
824 * CPU interface and migrate them to the new CPU interface.
825 * We skip DIST_TARGET 0 to 7 as they are read-only.
827 for (i = 8; i < DIV_ROUND_UP(gic_irqs, 4); i++) {
828 val = readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4);
829 active_mask = val & cur_target_mask;
832 val |= ror32(active_mask, ror_val);
833 writel_relaxed(val, dist_base + GIC_DIST_TARGET + i*4);
837 raw_spin_unlock(&irq_controller_lock);
840 * Now let's migrate and clear any potential SGIs that might be
841 * pending for us (cur_cpu_id). Since GIC_DIST_SGI_PENDING_SET
842 * is a banked register, we can only forward the SGI using
843 * GIC_DIST_SOFTINT. The original SGI source is lost but Linux
844 * doesn't use that information anyway.
846 * For the same reason we do not adjust SGI source information
847 * for previously sent SGIs by us to other CPUs either.
849 for (i = 0; i < 16; i += 4) {
851 val = readl_relaxed(dist_base + GIC_DIST_SGI_PENDING_SET + i);
854 writel_relaxed(val, dist_base + GIC_DIST_SGI_PENDING_CLEAR + i);
855 for (j = i; j < i + 4; j++) {
857 writel_relaxed((1 << (new_cpu_id + 16)) | j,
858 dist_base + GIC_DIST_SOFTINT);
865 * gic_get_sgir_physaddr - get the physical address for the SGI register
867 * REturn the physical address of the SGI register to be used
868 * by some early assembly code when the kernel is not yet available.
870 static unsigned long gic_dist_physaddr;
872 unsigned long gic_get_sgir_physaddr(void)
874 if (!gic_dist_physaddr)
876 return gic_dist_physaddr + GIC_DIST_SOFTINT;
879 void __init gic_init_physaddr(struct device_node *node)
882 if (of_address_to_resource(node, 0, &res) == 0) {
883 gic_dist_physaddr = res.start;
884 pr_info("GIC physical location is %#lx\n", gic_dist_physaddr);
889 #define gic_init_physaddr(node) do { } while (0)
892 static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq,
895 struct irq_chip *chip = &gic_chip;
897 if (static_key_true(&supports_deactivate)) {
898 if (d->host_data == (void *)&gic_data[0])
899 chip = &gic_eoimode1_chip;
903 irq_set_percpu_devid(irq);
904 irq_domain_set_info(d, irq, hw, chip, d->host_data,
905 handle_percpu_devid_irq, NULL, NULL);
906 irq_set_status_flags(irq, IRQ_NOAUTOEN);
908 irq_domain_set_info(d, irq, hw, chip, d->host_data,
909 handle_fasteoi_irq, NULL, NULL);
915 static void gic_irq_domain_unmap(struct irq_domain *d, unsigned int irq)
919 static int gic_irq_domain_xlate(struct irq_domain *d,
920 struct device_node *controller,
921 const u32 *intspec, unsigned int intsize,
922 unsigned long *out_hwirq, unsigned int *out_type)
924 unsigned long ret = 0;
926 if (d->of_node != controller)
931 /* Get the interrupt number and add 16 to skip over SGIs */
932 *out_hwirq = intspec[1] + 16;
934 /* For SPIs, we need to add 16 more to get the GIC irq ID number */
938 *out_type = intspec[2] & IRQ_TYPE_SENSE_MASK;
944 static int gic_secondary_init(struct notifier_block *nfb, unsigned long action,
947 if (action == CPU_STARTING || action == CPU_STARTING_FROZEN)
948 gic_cpu_init(&gic_data[0]);
953 * Notifier for enabling the GIC CPU interface. Set an arbitrarily high
954 * priority because the GIC needs to be up before the ARM generic timers.
956 static struct notifier_block gic_cpu_notifier = {
957 .notifier_call = gic_secondary_init,
962 static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
963 unsigned int nr_irqs, void *arg)
966 irq_hw_number_t hwirq;
967 unsigned int type = IRQ_TYPE_NONE;
968 struct of_phandle_args *irq_data = arg;
970 ret = gic_irq_domain_xlate(domain, irq_data->np, irq_data->args,
971 irq_data->args_count, &hwirq, &type);
975 for (i = 0; i < nr_irqs; i++)
976 gic_irq_domain_map(domain, virq + i, hwirq + i);
981 static const struct irq_domain_ops gic_irq_domain_hierarchy_ops = {
982 .xlate = gic_irq_domain_xlate,
983 .alloc = gic_irq_domain_alloc,
984 .free = irq_domain_free_irqs_top,
987 static const struct irq_domain_ops gic_irq_domain_ops = {
988 .map = gic_irq_domain_map,
989 .unmap = gic_irq_domain_unmap,
990 .xlate = gic_irq_domain_xlate,
993 static void __init __gic_init_bases(unsigned int gic_nr, int irq_start,
994 void __iomem *dist_base, void __iomem *cpu_base,
995 u32 percpu_offset, struct device_node *node)
997 irq_hw_number_t hwirq_base;
998 struct gic_chip_data *gic;
999 int gic_irqs, irq_base, i;
1001 BUG_ON(gic_nr >= MAX_GIC_NR);
1003 gic_check_cpu_features();
1005 gic = &gic_data[gic_nr];
1006 #ifdef CONFIG_GIC_NON_BANKED
1007 if (percpu_offset) { /* Frankein-GIC without banked registers... */
1010 gic->dist_base.percpu_base = alloc_percpu(void __iomem *);
1011 gic->cpu_base.percpu_base = alloc_percpu(void __iomem *);
1012 if (WARN_ON(!gic->dist_base.percpu_base ||
1013 !gic->cpu_base.percpu_base)) {
1014 free_percpu(gic->dist_base.percpu_base);
1015 free_percpu(gic->cpu_base.percpu_base);
1019 for_each_possible_cpu(cpu) {
1020 u32 mpidr = cpu_logical_map(cpu);
1021 u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
1022 unsigned long offset = percpu_offset * core_id;
1023 *per_cpu_ptr(gic->dist_base.percpu_base, cpu) = dist_base + offset;
1024 *per_cpu_ptr(gic->cpu_base.percpu_base, cpu) = cpu_base + offset;
1027 gic_set_base_accessor(gic, gic_get_percpu_base);
1030 { /* Normal, sane GIC... */
1032 "GIC_NON_BANKED not enabled, ignoring %08x offset!",
1034 gic->dist_base.common_base = dist_base;
1035 gic->cpu_base.common_base = cpu_base;
1036 gic_set_base_accessor(gic, gic_get_common_base);
1040 * Find out how many interrupts are supported.
1041 * The GIC only supports up to 1020 interrupt sources.
1043 gic_irqs = readl_relaxed(gic_data_dist_base(gic) + GIC_DIST_CTR) & 0x1f;
1044 gic_irqs = (gic_irqs + 1) * 32;
1045 if (gic_irqs > 1020)
1047 gic->gic_irqs = gic_irqs;
1049 if (node) { /* DT case */
1050 gic->domain = irq_domain_add_linear(node, gic_irqs,
1051 &gic_irq_domain_hierarchy_ops,
1053 } else { /* Non-DT case */
1055 * For primary GICs, skip over SGIs.
1056 * For secondary GICs, skip over PPIs, too.
1058 if (gic_nr == 0 && (irq_start & 31) > 0) {
1060 if (irq_start != -1)
1061 irq_start = (irq_start & ~31) + 16;
1066 gic_irqs -= hwirq_base; /* calculate # of irqs to allocate */
1068 irq_base = irq_alloc_descs(irq_start, 16, gic_irqs,
1070 if (IS_ERR_VALUE(irq_base)) {
1071 WARN(1, "Cannot allocate irq_descs @ IRQ%d, assuming pre-allocated\n",
1073 irq_base = irq_start;
1076 gic->domain = irq_domain_add_legacy(node, gic_irqs, irq_base,
1077 hwirq_base, &gic_irq_domain_ops, gic);
1080 if (WARN_ON(!gic->domain))
1085 * Initialize the CPU interface map to all CPUs.
1086 * It will be refined as each CPU probes its ID.
1087 * This is only necessary for the primary GIC.
1089 for (i = 0; i < NR_GIC_CPU_IF; i++)
1090 gic_cpu_map[i] = 0xff;
1092 set_smp_cross_call(gic_raise_softirq);
1093 register_cpu_notifier(&gic_cpu_notifier);
1095 set_handle_irq(gic_handle_irq);
1096 if (static_key_true(&supports_deactivate))
1097 pr_info("GIC: Using split EOI/Deactivate mode\n");
1105 void __init gic_init_bases(unsigned int gic_nr, int irq_start,
1106 void __iomem *dist_base, void __iomem *cpu_base,
1107 u32 percpu_offset, struct device_node *node)
1110 * Non-DT/ACPI systems won't run a hypervisor, so let's not
1111 * bother with these...
1113 static_key_slow_dec(&supports_deactivate);
1114 __gic_init_bases(gic_nr, irq_start, dist_base, cpu_base,
1115 percpu_offset, node);
1119 static int gic_cnt __initdata;
1121 static bool gic_check_eoimode(struct device_node *node, void __iomem **base)
1123 struct resource cpuif_res;
1125 of_address_to_resource(node, 1, &cpuif_res);
1127 if (!is_hyp_mode_available())
1129 if (resource_size(&cpuif_res) < SZ_8K)
1131 if (resource_size(&cpuif_res) == SZ_128K) {
1132 u32 val_low, val_high;
1135 * Verify that we have the first 4kB of a GIC400
1136 * aliased over the first 64kB by checking the
1137 * GICC_IIDR register on both ends.
1139 val_low = readl_relaxed(*base + GIC_CPU_IDENT);
1140 val_high = readl_relaxed(*base + GIC_CPU_IDENT + 0xf000);
1141 if ((val_low & 0xffff0fff) != 0x0202043B ||
1142 val_low != val_high)
1146 * Move the base up by 60kB, so that we have a 8kB
1147 * contiguous region, which allows us to use GICC_DIR
1148 * at its normal offset. Please pass me that bucket.
1151 cpuif_res.start += 0xf000;
1152 pr_warn("GIC: Adjusting CPU interface base to %pa",
1160 gic_of_init(struct device_node *node, struct device_node *parent)
1162 void __iomem *cpu_base;
1163 void __iomem *dist_base;
1170 dist_base = of_iomap(node, 0);
1171 WARN(!dist_base, "unable to map gic dist registers\n");
1173 cpu_base = of_iomap(node, 1);
1174 WARN(!cpu_base, "unable to map gic cpu registers\n");
1177 * Disable split EOI/Deactivate if either HYP is not available
1178 * or the CPU interface is too small.
1180 if (gic_cnt == 0 && !gic_check_eoimode(node, &cpu_base))
1181 static_key_slow_dec(&supports_deactivate);
1183 if (of_property_read_u32(node, "cpu-offset", &percpu_offset))
1186 __gic_init_bases(gic_cnt, -1, dist_base, cpu_base, percpu_offset, node);
1188 gic_init_physaddr(node);
1191 irq = irq_of_parse_and_map(node, 0);
1192 gic_cascade_irq(gic_cnt, irq);
1195 if (IS_ENABLED(CONFIG_ARM_GIC_V2M))
1196 gicv2m_of_init(node, gic_data[gic_cnt].domain);
1201 IRQCHIP_DECLARE(gic_400, "arm,gic-400", gic_of_init);
1202 IRQCHIP_DECLARE(arm11mp_gic, "arm,arm11mp-gic", gic_of_init);
1203 IRQCHIP_DECLARE(arm1176jzf_dc_gic, "arm,arm1176jzf-devchip-gic", gic_of_init);
1204 IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init);
1205 IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init);
1206 IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init);
1207 IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init);
1208 IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init);
1209 IRQCHIP_DECLARE(pl390, "arm,pl390", gic_of_init);
1214 static phys_addr_t dist_phy_base, cpu_phy_base __initdata;
1217 gic_acpi_parse_madt_cpu(struct acpi_subtable_header *header,
1218 const unsigned long end)
1220 struct acpi_madt_generic_interrupt *processor;
1221 phys_addr_t gic_cpu_base;
1222 static int cpu_base_assigned;
1224 processor = (struct acpi_madt_generic_interrupt *)header;
1226 if (BAD_MADT_GICC_ENTRY(processor, end))
1230 * There is no support for non-banked GICv1/2 register in ACPI spec.
1231 * All CPU interface addresses have to be the same.
1233 gic_cpu_base = processor->base_address;
1234 if (cpu_base_assigned && gic_cpu_base != cpu_phy_base)
1237 cpu_phy_base = gic_cpu_base;
1238 cpu_base_assigned = 1;
1243 gic_acpi_parse_madt_distributor(struct acpi_subtable_header *header,
1244 const unsigned long end)
1246 struct acpi_madt_generic_distributor *dist;
1248 dist = (struct acpi_madt_generic_distributor *)header;
1250 if (BAD_MADT_ENTRY(dist, end))
1253 dist_phy_base = dist->base_address;
1258 gic_v2_acpi_init(struct acpi_table_header *table)
1260 void __iomem *cpu_base, *dist_base;
1263 /* Collect CPU base addresses */
1264 count = acpi_parse_entries(ACPI_SIG_MADT,
1265 sizeof(struct acpi_table_madt),
1266 gic_acpi_parse_madt_cpu, table,
1267 ACPI_MADT_TYPE_GENERIC_INTERRUPT, 0);
1269 pr_err("No valid GICC entries exist\n");
1274 * Find distributor base address. We expect one distributor entry since
1275 * ACPI 5.1 spec neither support multi-GIC instances nor GIC cascade.
1277 count = acpi_parse_entries(ACPI_SIG_MADT,
1278 sizeof(struct acpi_table_madt),
1279 gic_acpi_parse_madt_distributor, table,
1280 ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, 0);
1282 pr_err("No valid GICD entries exist\n");
1284 } else if (count > 1) {
1285 pr_err("More than one GICD entry detected\n");
1289 cpu_base = ioremap(cpu_phy_base, ACPI_GIC_CPU_IF_MEM_SIZE);
1291 pr_err("Unable to map GICC registers\n");
1295 dist_base = ioremap(dist_phy_base, ACPI_GICV2_DIST_MEM_SIZE);
1297 pr_err("Unable to map GICD registers\n");
1303 * Disable split EOI/Deactivate if HYP is not available. ACPI
1304 * guarantees that we'll always have a GICv2, so the CPU
1305 * interface will always be the right size.
1307 if (!is_hyp_mode_available())
1308 static_key_slow_dec(&supports_deactivate);
1311 * Initialize zero GIC instance (no multi-GIC support). Also, set GIC
1312 * as default IRQ domain to allow for GSI registration and GSI to IRQ
1313 * number translation (see acpi_register_gsi() and acpi_gsi_to_irq()).
1315 __gic_init_bases(0, -1, dist_base, cpu_base, 0, NULL);
1316 irq_set_default_host(gic_data[0].domain);
1318 acpi_irq_model = ACPI_IRQ_MODEL_GIC;