2 * Copyright (C) 2002 ARM Limited, All Rights Reserved.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
8 * Interrupt architecture for the GIC:
10 * o There is one Interrupt Distributor, which receives interrupts
11 * from system devices and sends them to the Interrupt Controllers.
13 * o There is one CPU Interface per CPU, which sends interrupts sent
14 * by the Distributor, and interrupts generated locally, to the
15 * associated CPU. The base address of the CPU interface is usually
16 * aliased so that the same address points to different chips depending
17 * on the CPU it is accessed from.
19 * Note that IRQs 0-31 are special - they are local to each CPU.
20 * As such, the enable set/clear, pending set/clear and active bit
21 * registers are banked per-cpu for these sources.
23 #include <linux/init.h>
24 #include <linux/kernel.h>
25 #include <linux/err.h>
26 #include <linux/module.h>
27 #include <linux/list.h>
28 #include <linux/smp.h>
29 #include <linux/cpu.h>
30 #include <linux/cpu_pm.h>
31 #include <linux/cpumask.h>
34 #include <linux/of_address.h>
35 #include <linux/of_irq.h>
36 #include <linux/acpi.h>
37 #include <linux/irqdomain.h>
38 #include <linux/interrupt.h>
39 #include <linux/percpu.h>
40 #include <linux/slab.h>
41 #include <linux/irqchip.h>
42 #include <linux/irqchip/chained_irq.h>
43 #include <linux/irqchip/arm-gic.h>
44 #include <linux/irqchip/arm-gic-acpi.h>
46 #include <asm/cputype.h>
48 #include <asm/exception.h>
49 #include <asm/smp_plat.h>
52 #include "irq-gic-common.h"
55 void __iomem *common_base;
56 void __percpu * __iomem *percpu_base;
59 struct gic_chip_data {
60 union gic_base dist_base;
61 union gic_base cpu_base;
63 u32 saved_spi_enable[DIV_ROUND_UP(1020, 32)];
64 u32 saved_spi_conf[DIV_ROUND_UP(1020, 16)];
65 u32 saved_spi_target[DIV_ROUND_UP(1020, 4)];
66 u32 __percpu *saved_ppi_enable;
67 u32 __percpu *saved_ppi_conf;
69 struct irq_domain *domain;
70 unsigned int gic_irqs;
71 #ifdef CONFIG_GIC_NON_BANKED
72 void __iomem *(*get_base)(union gic_base *);
76 static DEFINE_RAW_SPINLOCK(irq_controller_lock);
79 * The GIC mapping of CPU interfaces does not necessarily match
80 * the logical CPU numbering. Let's use a mapping as returned
83 #define NR_GIC_CPU_IF 8
84 static u8 gic_cpu_map[NR_GIC_CPU_IF] __read_mostly;
86 static struct static_key supports_deactivate = STATIC_KEY_INIT_TRUE;
92 static struct gic_chip_data gic_data[MAX_GIC_NR] __read_mostly;
94 #ifdef CONFIG_GIC_NON_BANKED
95 static void __iomem *gic_get_percpu_base(union gic_base *base)
97 return raw_cpu_read(*base->percpu_base);
100 static void __iomem *gic_get_common_base(union gic_base *base)
102 return base->common_base;
105 static inline void __iomem *gic_data_dist_base(struct gic_chip_data *data)
107 return data->get_base(&data->dist_base);
110 static inline void __iomem *gic_data_cpu_base(struct gic_chip_data *data)
112 return data->get_base(&data->cpu_base);
115 static inline void gic_set_base_accessor(struct gic_chip_data *data,
116 void __iomem *(*f)(union gic_base *))
121 #define gic_data_dist_base(d) ((d)->dist_base.common_base)
122 #define gic_data_cpu_base(d) ((d)->cpu_base.common_base)
123 #define gic_set_base_accessor(d, f)
126 static inline void __iomem *gic_dist_base(struct irq_data *d)
128 struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
129 return gic_data_dist_base(gic_data);
132 static inline void __iomem *gic_cpu_base(struct irq_data *d)
134 struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
135 return gic_data_cpu_base(gic_data);
138 static inline unsigned int gic_irq(struct irq_data *d)
143 static inline bool cascading_gic_irq(struct irq_data *d)
145 void *data = irq_data_get_irq_handler_data(d);
148 * If handler_data is set, this is a cascading interrupt, and
149 * it cannot possibly be forwarded.
155 * Routines to acknowledge, disable and enable interrupts
157 static void gic_poke_irq(struct irq_data *d, u32 offset)
159 u32 mask = 1 << (gic_irq(d) % 32);
160 writel_relaxed(mask, gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4);
163 static int gic_peek_irq(struct irq_data *d, u32 offset)
165 u32 mask = 1 << (gic_irq(d) % 32);
166 return !!(readl_relaxed(gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4) & mask);
169 static void gic_mask_irq(struct irq_data *d)
171 gic_poke_irq(d, GIC_DIST_ENABLE_CLEAR);
174 static void gic_eoimode1_mask_irq(struct irq_data *d)
178 * When masking a forwarded interrupt, make sure it is
179 * deactivated as well.
181 * This ensures that an interrupt that is getting
182 * disabled/masked will not get "stuck", because there is
183 * noone to deactivate it (guest is being terminated).
185 if (irqd_is_forwarded_to_vcpu(d))
186 gic_poke_irq(d, GIC_DIST_ACTIVE_CLEAR);
189 static void gic_unmask_irq(struct irq_data *d)
191 gic_poke_irq(d, GIC_DIST_ENABLE_SET);
194 static void gic_eoi_irq(struct irq_data *d)
196 writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI);
199 static void gic_eoimode1_eoi_irq(struct irq_data *d)
201 /* Do not deactivate an IRQ forwarded to a vcpu. */
202 if (irqd_is_forwarded_to_vcpu(d))
205 writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_DEACTIVATE);
208 static int gic_irq_set_irqchip_state(struct irq_data *d,
209 enum irqchip_irq_state which, bool val)
214 case IRQCHIP_STATE_PENDING:
215 reg = val ? GIC_DIST_PENDING_SET : GIC_DIST_PENDING_CLEAR;
218 case IRQCHIP_STATE_ACTIVE:
219 reg = val ? GIC_DIST_ACTIVE_SET : GIC_DIST_ACTIVE_CLEAR;
222 case IRQCHIP_STATE_MASKED:
223 reg = val ? GIC_DIST_ENABLE_CLEAR : GIC_DIST_ENABLE_SET;
230 gic_poke_irq(d, reg);
234 static int gic_irq_get_irqchip_state(struct irq_data *d,
235 enum irqchip_irq_state which, bool *val)
238 case IRQCHIP_STATE_PENDING:
239 *val = gic_peek_irq(d, GIC_DIST_PENDING_SET);
242 case IRQCHIP_STATE_ACTIVE:
243 *val = gic_peek_irq(d, GIC_DIST_ACTIVE_SET);
246 case IRQCHIP_STATE_MASKED:
247 *val = !gic_peek_irq(d, GIC_DIST_ENABLE_SET);
257 static int gic_set_type(struct irq_data *d, unsigned int type)
259 void __iomem *base = gic_dist_base(d);
260 unsigned int gicirq = gic_irq(d);
262 /* Interrupt configuration for SGIs can't be changed */
266 /* SPIs have restrictions on the supported types */
267 if (gicirq >= 32 && type != IRQ_TYPE_LEVEL_HIGH &&
268 type != IRQ_TYPE_EDGE_RISING)
271 return gic_configure_irq(gicirq, type, base, NULL);
274 static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu)
276 /* Only interrupts on the primary GIC can be forwarded to a vcpu. */
277 if (cascading_gic_irq(d))
281 irqd_set_forwarded_to_vcpu(d);
283 irqd_clr_forwarded_to_vcpu(d);
288 static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
291 void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + (gic_irq(d) & ~3);
292 unsigned int cpu, shift = (gic_irq(d) % 4) * 8;
297 cpu = cpumask_any_and(mask_val, cpu_online_mask);
299 cpu = cpumask_first(mask_val);
301 if (cpu >= NR_GIC_CPU_IF || cpu >= nr_cpu_ids)
304 raw_spin_lock_irqsave(&irq_controller_lock, flags);
305 mask = 0xff << shift;
306 bit = gic_cpu_map[cpu] << shift;
307 val = readl_relaxed(reg) & ~mask;
308 writel_relaxed(val | bit, reg);
309 raw_spin_unlock_irqrestore(&irq_controller_lock, flags);
311 return IRQ_SET_MASK_OK;
315 static void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
318 struct gic_chip_data *gic = &gic_data[0];
319 void __iomem *cpu_base = gic_data_cpu_base(gic);
322 irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK);
323 irqnr = irqstat & GICC_IAR_INT_ID_MASK;
325 if (likely(irqnr > 15 && irqnr < 1021)) {
326 if (static_key_true(&supports_deactivate))
327 writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI);
328 handle_domain_irq(gic->domain, irqnr, regs);
332 writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI);
333 if (static_key_true(&supports_deactivate))
334 writel_relaxed(irqstat, cpu_base + GIC_CPU_DEACTIVATE);
336 handle_IPI(irqnr, regs);
344 static void gic_handle_cascade_irq(struct irq_desc *desc)
346 struct gic_chip_data *chip_data = irq_desc_get_handler_data(desc);
347 struct irq_chip *chip = irq_desc_get_chip(desc);
348 unsigned int cascade_irq, gic_irq;
349 unsigned long status;
351 chained_irq_enter(chip, desc);
353 raw_spin_lock(&irq_controller_lock);
354 status = readl_relaxed(gic_data_cpu_base(chip_data) + GIC_CPU_INTACK);
355 raw_spin_unlock(&irq_controller_lock);
357 gic_irq = (status & GICC_IAR_INT_ID_MASK);
358 if (gic_irq == GICC_INT_SPURIOUS)
361 cascade_irq = irq_find_mapping(chip_data->domain, gic_irq);
362 if (unlikely(gic_irq < 32 || gic_irq > 1020))
363 handle_bad_irq(desc);
365 generic_handle_irq(cascade_irq);
368 chained_irq_exit(chip, desc);
371 static struct irq_chip gic_chip = {
373 .irq_mask = gic_mask_irq,
374 .irq_unmask = gic_unmask_irq,
375 .irq_eoi = gic_eoi_irq,
376 .irq_set_type = gic_set_type,
378 .irq_set_affinity = gic_set_affinity,
380 .irq_get_irqchip_state = gic_irq_get_irqchip_state,
381 .irq_set_irqchip_state = gic_irq_set_irqchip_state,
382 .flags = IRQCHIP_SET_TYPE_MASKED |
383 IRQCHIP_SKIP_SET_WAKE |
384 IRQCHIP_MASK_ON_SUSPEND,
387 static struct irq_chip gic_eoimode1_chip = {
389 .irq_mask = gic_eoimode1_mask_irq,
390 .irq_unmask = gic_unmask_irq,
391 .irq_eoi = gic_eoimode1_eoi_irq,
392 .irq_set_type = gic_set_type,
394 .irq_set_affinity = gic_set_affinity,
396 .irq_get_irqchip_state = gic_irq_get_irqchip_state,
397 .irq_set_irqchip_state = gic_irq_set_irqchip_state,
398 .irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity,
399 .flags = IRQCHIP_SET_TYPE_MASKED |
400 IRQCHIP_SKIP_SET_WAKE |
401 IRQCHIP_MASK_ON_SUSPEND,
404 void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq)
406 if (gic_nr >= MAX_GIC_NR)
408 irq_set_chained_handler_and_data(irq, gic_handle_cascade_irq,
412 static u8 gic_get_cpumask(struct gic_chip_data *gic)
414 void __iomem *base = gic_data_dist_base(gic);
417 for (i = mask = 0; i < 32; i += 4) {
418 mask = readl_relaxed(base + GIC_DIST_TARGET + i);
425 if (!mask && num_possible_cpus() > 1)
426 pr_crit("GIC CPU mask not found - kernel will fail to boot.\n");
431 static void gic_cpu_if_up(struct gic_chip_data *gic)
433 void __iomem *cpu_base = gic_data_cpu_base(gic);
437 if (static_key_true(&supports_deactivate))
438 mode = GIC_CPU_CTRL_EOImodeNS;
441 * Preserve bypass disable bits to be written back later
443 bypass = readl(cpu_base + GIC_CPU_CTRL);
444 bypass &= GICC_DIS_BYPASS_MASK;
446 writel_relaxed(bypass | mode | GICC_ENABLE, cpu_base + GIC_CPU_CTRL);
450 static void __init gic_dist_init(struct gic_chip_data *gic)
454 unsigned int gic_irqs = gic->gic_irqs;
455 void __iomem *base = gic_data_dist_base(gic);
457 writel_relaxed(GICD_DISABLE, base + GIC_DIST_CTRL);
460 * Set all global interrupts to this CPU only.
462 cpumask = gic_get_cpumask(gic);
463 cpumask |= cpumask << 8;
464 cpumask |= cpumask << 16;
465 for (i = 32; i < gic_irqs; i += 4)
466 writel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4 / 4);
468 gic_dist_config(base, gic_irqs, NULL);
470 writel_relaxed(GICD_ENABLE, base + GIC_DIST_CTRL);
473 static void gic_cpu_init(struct gic_chip_data *gic)
475 void __iomem *dist_base = gic_data_dist_base(gic);
476 void __iomem *base = gic_data_cpu_base(gic);
477 unsigned int cpu_mask, cpu = smp_processor_id();
481 * Setting up the CPU map is only relevant for the primary GIC
482 * because any nested/secondary GICs do not directly interface
485 if (gic == &gic_data[0]) {
487 * Get what the GIC says our CPU mask is.
489 BUG_ON(cpu >= NR_GIC_CPU_IF);
490 cpu_mask = gic_get_cpumask(gic);
491 gic_cpu_map[cpu] = cpu_mask;
494 * Clear our mask from the other map entries in case they're
497 for (i = 0; i < NR_GIC_CPU_IF; i++)
499 gic_cpu_map[i] &= ~cpu_mask;
502 gic_cpu_config(dist_base, NULL);
504 writel_relaxed(GICC_INT_PRI_THRESHOLD, base + GIC_CPU_PRIMASK);
508 int gic_cpu_if_down(unsigned int gic_nr)
510 void __iomem *cpu_base;
513 if (gic_nr >= MAX_GIC_NR)
516 cpu_base = gic_data_cpu_base(&gic_data[gic_nr]);
517 val = readl(cpu_base + GIC_CPU_CTRL);
519 writel_relaxed(val, cpu_base + GIC_CPU_CTRL);
526 * Saves the GIC distributor registers during suspend or idle. Must be called
527 * with interrupts disabled but before powering down the GIC. After calling
528 * this function, no interrupts will be delivered by the GIC, and another
529 * platform-specific wakeup source must be enabled.
531 static void gic_dist_save(unsigned int gic_nr)
533 unsigned int gic_irqs;
534 void __iomem *dist_base;
537 if (gic_nr >= MAX_GIC_NR)
540 gic_irqs = gic_data[gic_nr].gic_irqs;
541 dist_base = gic_data_dist_base(&gic_data[gic_nr]);
546 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++)
547 gic_data[gic_nr].saved_spi_conf[i] =
548 readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4);
550 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
551 gic_data[gic_nr].saved_spi_target[i] =
552 readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4);
554 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++)
555 gic_data[gic_nr].saved_spi_enable[i] =
556 readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4);
560 * Restores the GIC distributor registers during resume or when coming out of
561 * idle. Must be called before enabling interrupts. If a level interrupt
562 * that occured while the GIC was suspended is still present, it will be
563 * handled normally, but any edge interrupts that occured will not be seen by
564 * the GIC and need to be handled by the platform-specific wakeup source.
566 static void gic_dist_restore(unsigned int gic_nr)
568 unsigned int gic_irqs;
570 void __iomem *dist_base;
572 if (gic_nr >= MAX_GIC_NR)
575 gic_irqs = gic_data[gic_nr].gic_irqs;
576 dist_base = gic_data_dist_base(&gic_data[gic_nr]);
581 writel_relaxed(GICD_DISABLE, dist_base + GIC_DIST_CTRL);
583 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++)
584 writel_relaxed(gic_data[gic_nr].saved_spi_conf[i],
585 dist_base + GIC_DIST_CONFIG + i * 4);
587 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
588 writel_relaxed(GICD_INT_DEF_PRI_X4,
589 dist_base + GIC_DIST_PRI + i * 4);
591 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
592 writel_relaxed(gic_data[gic_nr].saved_spi_target[i],
593 dist_base + GIC_DIST_TARGET + i * 4);
595 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++)
596 writel_relaxed(gic_data[gic_nr].saved_spi_enable[i],
597 dist_base + GIC_DIST_ENABLE_SET + i * 4);
599 writel_relaxed(GICD_ENABLE, dist_base + GIC_DIST_CTRL);
602 static void gic_cpu_save(unsigned int gic_nr)
606 void __iomem *dist_base;
607 void __iomem *cpu_base;
609 if (gic_nr >= MAX_GIC_NR)
612 dist_base = gic_data_dist_base(&gic_data[gic_nr]);
613 cpu_base = gic_data_cpu_base(&gic_data[gic_nr]);
615 if (!dist_base || !cpu_base)
618 ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_enable);
619 for (i = 0; i < DIV_ROUND_UP(32, 32); i++)
620 ptr[i] = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4);
622 ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_conf);
623 for (i = 0; i < DIV_ROUND_UP(32, 16); i++)
624 ptr[i] = readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4);
628 static void gic_cpu_restore(unsigned int gic_nr)
632 void __iomem *dist_base;
633 void __iomem *cpu_base;
635 if (gic_nr >= MAX_GIC_NR)
638 dist_base = gic_data_dist_base(&gic_data[gic_nr]);
639 cpu_base = gic_data_cpu_base(&gic_data[gic_nr]);
641 if (!dist_base || !cpu_base)
644 ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_enable);
645 for (i = 0; i < DIV_ROUND_UP(32, 32); i++)
646 writel_relaxed(ptr[i], dist_base + GIC_DIST_ENABLE_SET + i * 4);
648 ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_conf);
649 for (i = 0; i < DIV_ROUND_UP(32, 16); i++)
650 writel_relaxed(ptr[i], dist_base + GIC_DIST_CONFIG + i * 4);
652 for (i = 0; i < DIV_ROUND_UP(32, 4); i++)
653 writel_relaxed(GICD_INT_DEF_PRI_X4,
654 dist_base + GIC_DIST_PRI + i * 4);
656 writel_relaxed(GICC_INT_PRI_THRESHOLD, cpu_base + GIC_CPU_PRIMASK);
657 gic_cpu_if_up(&gic_data[gic_nr]);
660 static int gic_notifier(struct notifier_block *self, unsigned long cmd, void *v)
664 for (i = 0; i < MAX_GIC_NR; i++) {
665 #ifdef CONFIG_GIC_NON_BANKED
666 /* Skip over unused GICs */
667 if (!gic_data[i].get_base)
674 case CPU_PM_ENTER_FAILED:
678 case CPU_CLUSTER_PM_ENTER:
681 case CPU_CLUSTER_PM_ENTER_FAILED:
682 case CPU_CLUSTER_PM_EXIT:
691 static struct notifier_block gic_notifier_block = {
692 .notifier_call = gic_notifier,
695 static void __init gic_pm_init(struct gic_chip_data *gic)
697 gic->saved_ppi_enable = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4,
699 BUG_ON(!gic->saved_ppi_enable);
701 gic->saved_ppi_conf = __alloc_percpu(DIV_ROUND_UP(32, 16) * 4,
703 BUG_ON(!gic->saved_ppi_conf);
705 if (gic == &gic_data[0])
706 cpu_pm_register_notifier(&gic_notifier_block);
709 static void __init gic_pm_init(struct gic_chip_data *gic)
715 static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
718 unsigned long flags, map = 0;
720 raw_spin_lock_irqsave(&irq_controller_lock, flags);
722 /* Convert our logical CPU mask into a physical one. */
723 for_each_cpu(cpu, mask)
724 map |= gic_cpu_map[cpu];
727 * Ensure that stores to Normal memory are visible to the
728 * other CPUs before they observe us issuing the IPI.
732 /* this always happens on GIC0 */
733 writel_relaxed(map << 16 | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
735 raw_spin_unlock_irqrestore(&irq_controller_lock, flags);
739 #ifdef CONFIG_BL_SWITCHER
741 * gic_send_sgi - send a SGI directly to given CPU interface number
743 * cpu_id: the ID for the destination CPU interface
744 * irq: the IPI number to send a SGI for
746 void gic_send_sgi(unsigned int cpu_id, unsigned int irq)
748 BUG_ON(cpu_id >= NR_GIC_CPU_IF);
749 cpu_id = 1 << cpu_id;
750 /* this always happens on GIC0 */
751 writel_relaxed((cpu_id << 16) | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
755 * gic_get_cpu_id - get the CPU interface ID for the specified CPU
757 * @cpu: the logical CPU number to get the GIC ID for.
759 * Return the CPU interface ID for the given logical CPU number,
760 * or -1 if the CPU number is too large or the interface ID is
761 * unknown (more than one bit set).
763 int gic_get_cpu_id(unsigned int cpu)
765 unsigned int cpu_bit;
767 if (cpu >= NR_GIC_CPU_IF)
769 cpu_bit = gic_cpu_map[cpu];
770 if (cpu_bit & (cpu_bit - 1))
772 return __ffs(cpu_bit);
776 * gic_migrate_target - migrate IRQs to another CPU interface
778 * @new_cpu_id: the CPU target ID to migrate IRQs to
780 * Migrate all peripheral interrupts with a target matching the current CPU
781 * to the interface corresponding to @new_cpu_id. The CPU interface mapping
782 * is also updated. Targets to other CPU interfaces are unchanged.
783 * This must be called with IRQs locally disabled.
785 void gic_migrate_target(unsigned int new_cpu_id)
787 unsigned int cur_cpu_id, gic_irqs, gic_nr = 0;
788 void __iomem *dist_base;
789 int i, ror_val, cpu = smp_processor_id();
790 u32 val, cur_target_mask, active_mask;
792 if (gic_nr >= MAX_GIC_NR)
795 dist_base = gic_data_dist_base(&gic_data[gic_nr]);
798 gic_irqs = gic_data[gic_nr].gic_irqs;
800 cur_cpu_id = __ffs(gic_cpu_map[cpu]);
801 cur_target_mask = 0x01010101 << cur_cpu_id;
802 ror_val = (cur_cpu_id - new_cpu_id) & 31;
804 raw_spin_lock(&irq_controller_lock);
806 /* Update the target interface for this logical CPU */
807 gic_cpu_map[cpu] = 1 << new_cpu_id;
810 * Find all the peripheral interrupts targetting the current
811 * CPU interface and migrate them to the new CPU interface.
812 * We skip DIST_TARGET 0 to 7 as they are read-only.
814 for (i = 8; i < DIV_ROUND_UP(gic_irqs, 4); i++) {
815 val = readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4);
816 active_mask = val & cur_target_mask;
819 val |= ror32(active_mask, ror_val);
820 writel_relaxed(val, dist_base + GIC_DIST_TARGET + i*4);
824 raw_spin_unlock(&irq_controller_lock);
827 * Now let's migrate and clear any potential SGIs that might be
828 * pending for us (cur_cpu_id). Since GIC_DIST_SGI_PENDING_SET
829 * is a banked register, we can only forward the SGI using
830 * GIC_DIST_SOFTINT. The original SGI source is lost but Linux
831 * doesn't use that information anyway.
833 * For the same reason we do not adjust SGI source information
834 * for previously sent SGIs by us to other CPUs either.
836 for (i = 0; i < 16; i += 4) {
838 val = readl_relaxed(dist_base + GIC_DIST_SGI_PENDING_SET + i);
841 writel_relaxed(val, dist_base + GIC_DIST_SGI_PENDING_CLEAR + i);
842 for (j = i; j < i + 4; j++) {
844 writel_relaxed((1 << (new_cpu_id + 16)) | j,
845 dist_base + GIC_DIST_SOFTINT);
852 * gic_get_sgir_physaddr - get the physical address for the SGI register
854 * REturn the physical address of the SGI register to be used
855 * by some early assembly code when the kernel is not yet available.
857 static unsigned long gic_dist_physaddr;
859 unsigned long gic_get_sgir_physaddr(void)
861 if (!gic_dist_physaddr)
863 return gic_dist_physaddr + GIC_DIST_SOFTINT;
866 void __init gic_init_physaddr(struct device_node *node)
869 if (of_address_to_resource(node, 0, &res) == 0) {
870 gic_dist_physaddr = res.start;
871 pr_info("GIC physical location is %#lx\n", gic_dist_physaddr);
876 #define gic_init_physaddr(node) do { } while (0)
879 static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq,
882 struct irq_chip *chip = &gic_chip;
884 if (static_key_true(&supports_deactivate)) {
885 if (d->host_data == (void *)&gic_data[0])
886 chip = &gic_eoimode1_chip;
890 irq_set_percpu_devid(irq);
891 irq_domain_set_info(d, irq, hw, chip, d->host_data,
892 handle_percpu_devid_irq, NULL, NULL);
893 irq_set_status_flags(irq, IRQ_NOAUTOEN);
895 irq_domain_set_info(d, irq, hw, chip, d->host_data,
896 handle_fasteoi_irq, NULL, NULL);
902 static void gic_irq_domain_unmap(struct irq_domain *d, unsigned int irq)
906 static int gic_irq_domain_xlate(struct irq_domain *d,
907 struct device_node *controller,
908 const u32 *intspec, unsigned int intsize,
909 unsigned long *out_hwirq, unsigned int *out_type)
911 unsigned long ret = 0;
913 if (d->of_node != controller)
918 /* Get the interrupt number and add 16 to skip over SGIs */
919 *out_hwirq = intspec[1] + 16;
921 /* For SPIs, we need to add 16 more to get the GIC irq ID number */
925 *out_type = intspec[2] & IRQ_TYPE_SENSE_MASK;
931 static int gic_secondary_init(struct notifier_block *nfb, unsigned long action,
934 if (action == CPU_STARTING || action == CPU_STARTING_FROZEN)
935 gic_cpu_init(&gic_data[0]);
940 * Notifier for enabling the GIC CPU interface. Set an arbitrarily high
941 * priority because the GIC needs to be up before the ARM generic timers.
943 static struct notifier_block gic_cpu_notifier = {
944 .notifier_call = gic_secondary_init,
949 static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
950 unsigned int nr_irqs, void *arg)
953 irq_hw_number_t hwirq;
954 unsigned int type = IRQ_TYPE_NONE;
955 struct of_phandle_args *irq_data = arg;
957 ret = gic_irq_domain_xlate(domain, irq_data->np, irq_data->args,
958 irq_data->args_count, &hwirq, &type);
962 for (i = 0; i < nr_irqs; i++)
963 gic_irq_domain_map(domain, virq + i, hwirq + i);
968 static const struct irq_domain_ops gic_irq_domain_hierarchy_ops = {
969 .xlate = gic_irq_domain_xlate,
970 .alloc = gic_irq_domain_alloc,
971 .free = irq_domain_free_irqs_top,
974 static const struct irq_domain_ops gic_irq_domain_ops = {
975 .map = gic_irq_domain_map,
976 .unmap = gic_irq_domain_unmap,
977 .xlate = gic_irq_domain_xlate,
980 static void __init __gic_init_bases(unsigned int gic_nr, int irq_start,
981 void __iomem *dist_base, void __iomem *cpu_base,
982 u32 percpu_offset, struct device_node *node)
984 irq_hw_number_t hwirq_base;
985 struct gic_chip_data *gic;
986 int gic_irqs, irq_base, i;
988 BUG_ON(gic_nr >= MAX_GIC_NR);
990 gic = &gic_data[gic_nr];
991 #ifdef CONFIG_GIC_NON_BANKED
992 if (percpu_offset) { /* Frankein-GIC without banked registers... */
995 gic->dist_base.percpu_base = alloc_percpu(void __iomem *);
996 gic->cpu_base.percpu_base = alloc_percpu(void __iomem *);
997 if (WARN_ON(!gic->dist_base.percpu_base ||
998 !gic->cpu_base.percpu_base)) {
999 free_percpu(gic->dist_base.percpu_base);
1000 free_percpu(gic->cpu_base.percpu_base);
1004 for_each_possible_cpu(cpu) {
1005 u32 mpidr = cpu_logical_map(cpu);
1006 u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
1007 unsigned long offset = percpu_offset * core_id;
1008 *per_cpu_ptr(gic->dist_base.percpu_base, cpu) = dist_base + offset;
1009 *per_cpu_ptr(gic->cpu_base.percpu_base, cpu) = cpu_base + offset;
1012 gic_set_base_accessor(gic, gic_get_percpu_base);
1015 { /* Normal, sane GIC... */
1017 "GIC_NON_BANKED not enabled, ignoring %08x offset!",
1019 gic->dist_base.common_base = dist_base;
1020 gic->cpu_base.common_base = cpu_base;
1021 gic_set_base_accessor(gic, gic_get_common_base);
1025 * Find out how many interrupts are supported.
1026 * The GIC only supports up to 1020 interrupt sources.
1028 gic_irqs = readl_relaxed(gic_data_dist_base(gic) + GIC_DIST_CTR) & 0x1f;
1029 gic_irqs = (gic_irqs + 1) * 32;
1030 if (gic_irqs > 1020)
1032 gic->gic_irqs = gic_irqs;
1034 if (node) { /* DT case */
1035 gic->domain = irq_domain_add_linear(node, gic_irqs,
1036 &gic_irq_domain_hierarchy_ops,
1038 } else { /* Non-DT case */
1040 * For primary GICs, skip over SGIs.
1041 * For secondary GICs, skip over PPIs, too.
1043 if (gic_nr == 0 && (irq_start & 31) > 0) {
1045 if (irq_start != -1)
1046 irq_start = (irq_start & ~31) + 16;
1051 gic_irqs -= hwirq_base; /* calculate # of irqs to allocate */
1053 irq_base = irq_alloc_descs(irq_start, 16, gic_irqs,
1055 if (IS_ERR_VALUE(irq_base)) {
1056 WARN(1, "Cannot allocate irq_descs @ IRQ%d, assuming pre-allocated\n",
1058 irq_base = irq_start;
1061 gic->domain = irq_domain_add_legacy(node, gic_irqs, irq_base,
1062 hwirq_base, &gic_irq_domain_ops, gic);
1065 if (WARN_ON(!gic->domain))
1070 * Initialize the CPU interface map to all CPUs.
1071 * It will be refined as each CPU probes its ID.
1072 * This is only necessary for the primary GIC.
1074 for (i = 0; i < NR_GIC_CPU_IF; i++)
1075 gic_cpu_map[i] = 0xff;
1077 set_smp_cross_call(gic_raise_softirq);
1078 register_cpu_notifier(&gic_cpu_notifier);
1080 set_handle_irq(gic_handle_irq);
1081 if (static_key_true(&supports_deactivate))
1082 pr_info("GIC: Using split EOI/Deactivate mode\n");
1090 void __init gic_init_bases(unsigned int gic_nr, int irq_start,
1091 void __iomem *dist_base, void __iomem *cpu_base,
1092 u32 percpu_offset, struct device_node *node)
1095 * Non-DT/ACPI systems won't run a hypervisor, so let's not
1096 * bother with these...
1098 static_key_slow_dec(&supports_deactivate);
1099 __gic_init_bases(gic_nr, irq_start, dist_base, cpu_base,
1100 percpu_offset, node);
1104 static int gic_cnt __initdata;
1106 static bool gic_check_eoimode(struct device_node *node, void __iomem **base)
1108 struct resource cpuif_res;
1110 of_address_to_resource(node, 1, &cpuif_res);
1112 if (!is_hyp_mode_available())
1114 if (resource_size(&cpuif_res) < SZ_8K)
1116 if (resource_size(&cpuif_res) == SZ_128K) {
1117 u32 val_low, val_high;
1120 * Verify that we have the first 4kB of a GIC400
1121 * aliased over the first 64kB by checking the
1122 * GICC_IIDR register on both ends.
1124 val_low = readl_relaxed(*base + GIC_CPU_IDENT);
1125 val_high = readl_relaxed(*base + GIC_CPU_IDENT + 0xf000);
1126 if ((val_low & 0xffff0fff) != 0x0202043B ||
1127 val_low != val_high)
1131 * Move the base up by 60kB, so that we have a 8kB
1132 * contiguous region, which allows us to use GICC_DIR
1133 * at its normal offset. Please pass me that bucket.
1136 cpuif_res.start += 0xf000;
1137 pr_warn("GIC: Adjusting CPU interface base to %pa",
1145 gic_of_init(struct device_node *node, struct device_node *parent)
1147 void __iomem *cpu_base;
1148 void __iomem *dist_base;
1155 dist_base = of_iomap(node, 0);
1156 WARN(!dist_base, "unable to map gic dist registers\n");
1158 cpu_base = of_iomap(node, 1);
1159 WARN(!cpu_base, "unable to map gic cpu registers\n");
1162 * Disable split EOI/Deactivate if either HYP is not available
1163 * or the CPU interface is too small.
1165 if (gic_cnt == 0 && !gic_check_eoimode(node, &cpu_base))
1166 static_key_slow_dec(&supports_deactivate);
1168 if (of_property_read_u32(node, "cpu-offset", &percpu_offset))
1171 __gic_init_bases(gic_cnt, -1, dist_base, cpu_base, percpu_offset, node);
1173 gic_init_physaddr(node);
1176 irq = irq_of_parse_and_map(node, 0);
1177 gic_cascade_irq(gic_cnt, irq);
1180 if (IS_ENABLED(CONFIG_ARM_GIC_V2M))
1181 gicv2m_of_init(node, gic_data[gic_cnt].domain);
1186 IRQCHIP_DECLARE(gic_400, "arm,gic-400", gic_of_init);
1187 IRQCHIP_DECLARE(arm11mp_gic, "arm,arm11mp-gic", gic_of_init);
1188 IRQCHIP_DECLARE(arm1176jzf_dc_gic, "arm,arm1176jzf-devchip-gic", gic_of_init);
1189 IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init);
1190 IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init);
1191 IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init);
1192 IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init);
1193 IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init);
1198 static phys_addr_t dist_phy_base, cpu_phy_base __initdata;
1201 gic_acpi_parse_madt_cpu(struct acpi_subtable_header *header,
1202 const unsigned long end)
1204 struct acpi_madt_generic_interrupt *processor;
1205 phys_addr_t gic_cpu_base;
1206 static int cpu_base_assigned;
1208 processor = (struct acpi_madt_generic_interrupt *)header;
1210 if (BAD_MADT_GICC_ENTRY(processor, end))
1214 * There is no support for non-banked GICv1/2 register in ACPI spec.
1215 * All CPU interface addresses have to be the same.
1217 gic_cpu_base = processor->base_address;
1218 if (cpu_base_assigned && gic_cpu_base != cpu_phy_base)
1221 cpu_phy_base = gic_cpu_base;
1222 cpu_base_assigned = 1;
1227 gic_acpi_parse_madt_distributor(struct acpi_subtable_header *header,
1228 const unsigned long end)
1230 struct acpi_madt_generic_distributor *dist;
1232 dist = (struct acpi_madt_generic_distributor *)header;
1234 if (BAD_MADT_ENTRY(dist, end))
1237 dist_phy_base = dist->base_address;
1242 gic_v2_acpi_init(struct acpi_table_header *table)
1244 void __iomem *cpu_base, *dist_base;
1247 /* Collect CPU base addresses */
1248 count = acpi_parse_entries(ACPI_SIG_MADT,
1249 sizeof(struct acpi_table_madt),
1250 gic_acpi_parse_madt_cpu, table,
1251 ACPI_MADT_TYPE_GENERIC_INTERRUPT, 0);
1253 pr_err("No valid GICC entries exist\n");
1258 * Find distributor base address. We expect one distributor entry since
1259 * ACPI 5.1 spec neither support multi-GIC instances nor GIC cascade.
1261 count = acpi_parse_entries(ACPI_SIG_MADT,
1262 sizeof(struct acpi_table_madt),
1263 gic_acpi_parse_madt_distributor, table,
1264 ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, 0);
1266 pr_err("No valid GICD entries exist\n");
1268 } else if (count > 1) {
1269 pr_err("More than one GICD entry detected\n");
1273 cpu_base = ioremap(cpu_phy_base, ACPI_GIC_CPU_IF_MEM_SIZE);
1275 pr_err("Unable to map GICC registers\n");
1279 dist_base = ioremap(dist_phy_base, ACPI_GICV2_DIST_MEM_SIZE);
1281 pr_err("Unable to map GICD registers\n");
1287 * Disable split EOI/Deactivate if HYP is not available. ACPI
1288 * guarantees that we'll always have a GICv2, so the CPU
1289 * interface will always be the right size.
1291 if (!is_hyp_mode_available())
1292 static_key_slow_dec(&supports_deactivate);
1295 * Initialize zero GIC instance (no multi-GIC support). Also, set GIC
1296 * as default IRQ domain to allow for GSI registration and GSI to IRQ
1297 * number translation (see acpi_register_gsi() and acpi_gsi_to_irq()).
1299 __gic_init_bases(0, -1, dist_base, cpu_base, 0, NULL);
1300 irq_set_default_host(gic_data[0].domain);
1302 acpi_irq_model = ACPI_IRQ_MODEL_GIC;