4 * Copyright (C) 2002-2014 ARM Limited.
5 * Copyright (c) 2013-2014 Hisilicon Ltd.
6 * Copyright (c) 2013-2014 Linaro Ltd.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * Interrupt architecture for the HIP04 INTC:
14 * o There is one Interrupt Distributor, which receives interrupts
15 * from system devices and sends them to the Interrupt Controllers.
17 * o There is one CPU Interface per CPU, which sends interrupts sent
18 * by the Distributor, and interrupts generated locally, to the
19 * associated CPU. The base address of the CPU interface is usually
20 * aliased so that the same address points to different chips depending
21 * on the CPU it is accessed from.
23 * Note that IRQs 0-31 are special - they are local to each CPU.
24 * As such, the enable set/clear, pending set/clear and active bit
25 * registers are banked per-cpu for these sources.
28 #include <linux/init.h>
29 #include <linux/kernel.h>
30 #include <linux/err.h>
31 #include <linux/module.h>
32 #include <linux/list.h>
33 #include <linux/smp.h>
34 #include <linux/cpu.h>
35 #include <linux/cpu_pm.h>
36 #include <linux/cpumask.h>
39 #include <linux/of_address.h>
40 #include <linux/of_irq.h>
41 #include <linux/irqdomain.h>
42 #include <linux/interrupt.h>
43 #include <linux/slab.h>
44 #include <linux/irqchip.h>
45 #include <linux/irqchip/arm-gic.h>
48 #include <asm/exception.h>
49 #include <asm/smp_plat.h>
51 #include "irq-gic-common.h"
53 #define HIP04_MAX_IRQS 510
55 struct hip04_irq_data {
56 void __iomem *dist_base;
57 void __iomem *cpu_base;
58 struct irq_domain *domain;
62 static DEFINE_RAW_SPINLOCK(irq_controller_lock);
65 * The GIC mapping of CPU interfaces does not necessarily match
66 * the logical CPU numbering. Let's use a mapping as returned
69 #define NR_HIP04_CPU_IF 16
70 static u16 hip04_cpu_map[NR_HIP04_CPU_IF] __read_mostly;
72 static struct hip04_irq_data hip04_data __read_mostly;
74 static inline void __iomem *hip04_dist_base(struct irq_data *d)
76 struct hip04_irq_data *hip04_data = irq_data_get_irq_chip_data(d);
77 return hip04_data->dist_base;
80 static inline void __iomem *hip04_cpu_base(struct irq_data *d)
82 struct hip04_irq_data *hip04_data = irq_data_get_irq_chip_data(d);
83 return hip04_data->cpu_base;
86 static inline unsigned int hip04_irq(struct irq_data *d)
92 * Routines to acknowledge, disable and enable interrupts
94 static void hip04_mask_irq(struct irq_data *d)
96 u32 mask = 1 << (hip04_irq(d) % 32);
98 raw_spin_lock(&irq_controller_lock);
99 writel_relaxed(mask, hip04_dist_base(d) + GIC_DIST_ENABLE_CLEAR +
100 (hip04_irq(d) / 32) * 4);
101 raw_spin_unlock(&irq_controller_lock);
104 static void hip04_unmask_irq(struct irq_data *d)
106 u32 mask = 1 << (hip04_irq(d) % 32);
108 raw_spin_lock(&irq_controller_lock);
109 writel_relaxed(mask, hip04_dist_base(d) + GIC_DIST_ENABLE_SET +
110 (hip04_irq(d) / 32) * 4);
111 raw_spin_unlock(&irq_controller_lock);
114 static void hip04_eoi_irq(struct irq_data *d)
116 writel_relaxed(hip04_irq(d), hip04_cpu_base(d) + GIC_CPU_EOI);
119 static int hip04_irq_set_type(struct irq_data *d, unsigned int type)
121 void __iomem *base = hip04_dist_base(d);
122 unsigned int irq = hip04_irq(d);
125 /* Interrupt configuration for SGIs can't be changed */
129 /* SPIs have restrictions on the supported types */
130 if (irq >= 32 && type != IRQ_TYPE_LEVEL_HIGH &&
131 type != IRQ_TYPE_EDGE_RISING)
134 raw_spin_lock(&irq_controller_lock);
136 ret = gic_configure_irq(irq, type, base, NULL);
138 raw_spin_unlock(&irq_controller_lock);
144 static int hip04_irq_set_affinity(struct irq_data *d,
145 const struct cpumask *mask_val,
149 unsigned int cpu, shift = (hip04_irq(d) % 2) * 16;
153 cpu = cpumask_any_and(mask_val, cpu_online_mask);
155 cpu = cpumask_first(mask_val);
157 if (cpu >= NR_HIP04_CPU_IF || cpu >= nr_cpu_ids)
160 raw_spin_lock(&irq_controller_lock);
161 reg = hip04_dist_base(d) + GIC_DIST_TARGET + ((hip04_irq(d) * 2) & ~3);
162 mask = 0xffff << shift;
163 bit = hip04_cpu_map[cpu] << shift;
164 val = readl_relaxed(reg) & ~mask;
165 writel_relaxed(val | bit, reg);
166 raw_spin_unlock(&irq_controller_lock);
168 return IRQ_SET_MASK_OK;
172 static void __exception_irq_entry hip04_handle_irq(struct pt_regs *regs)
175 void __iomem *cpu_base = hip04_data.cpu_base;
178 irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK);
179 irqnr = irqstat & GICC_IAR_INT_ID_MASK;
181 if (likely(irqnr > 15 && irqnr <= HIP04_MAX_IRQS)) {
182 handle_domain_irq(hip04_data.domain, irqnr, regs);
186 writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI);
188 handle_IPI(irqnr, regs);
196 static struct irq_chip hip04_irq_chip = {
197 .name = "HIP04 INTC",
198 .irq_mask = hip04_mask_irq,
199 .irq_unmask = hip04_unmask_irq,
200 .irq_eoi = hip04_eoi_irq,
201 .irq_set_type = hip04_irq_set_type,
203 .irq_set_affinity = hip04_irq_set_affinity,
205 .flags = IRQCHIP_SET_TYPE_MASKED,
208 static u16 hip04_get_cpumask(struct hip04_irq_data *intc)
210 void __iomem *base = intc->dist_base;
213 for (i = mask = 0; i < 32; i += 2) {
214 mask = readl_relaxed(base + GIC_DIST_TARGET + i * 2);
221 pr_crit("GIC CPU mask not found - kernel will fail to boot.\n");
226 static void __init hip04_irq_dist_init(struct hip04_irq_data *intc)
230 unsigned int nr_irqs = intc->nr_irqs;
231 void __iomem *base = intc->dist_base;
233 writel_relaxed(0, base + GIC_DIST_CTRL);
236 * Set all global interrupts to this CPU only.
238 cpumask = hip04_get_cpumask(intc);
239 cpumask |= cpumask << 16;
240 for (i = 32; i < nr_irqs; i += 2)
241 writel_relaxed(cpumask, base + GIC_DIST_TARGET + ((i * 2) & ~3));
243 gic_dist_config(base, nr_irqs, NULL);
245 writel_relaxed(1, base + GIC_DIST_CTRL);
248 static void hip04_irq_cpu_init(struct hip04_irq_data *intc)
250 void __iomem *dist_base = intc->dist_base;
251 void __iomem *base = intc->cpu_base;
252 unsigned int cpu_mask, cpu = smp_processor_id();
256 * Get what the GIC says our CPU mask is.
258 BUG_ON(cpu >= NR_HIP04_CPU_IF);
259 cpu_mask = hip04_get_cpumask(intc);
260 hip04_cpu_map[cpu] = cpu_mask;
263 * Clear our mask from the other map entries in case they're
266 for (i = 0; i < NR_HIP04_CPU_IF; i++)
268 hip04_cpu_map[i] &= ~cpu_mask;
270 gic_cpu_config(dist_base, NULL);
272 writel_relaxed(0xf0, base + GIC_CPU_PRIMASK);
273 writel_relaxed(1, base + GIC_CPU_CTRL);
277 static void hip04_raise_softirq(const struct cpumask *mask, unsigned int irq)
280 unsigned long flags, map = 0;
282 raw_spin_lock_irqsave(&irq_controller_lock, flags);
284 /* Convert our logical CPU mask into a physical one. */
285 for_each_cpu(cpu, mask)
286 map |= hip04_cpu_map[cpu];
289 * Ensure that stores to Normal memory are visible to the
290 * other CPUs before they observe us issuing the IPI.
294 /* this always happens on GIC0 */
295 writel_relaxed(map << 8 | irq, hip04_data.dist_base + GIC_DIST_SOFTINT);
297 raw_spin_unlock_irqrestore(&irq_controller_lock, flags);
301 static int hip04_irq_domain_map(struct irq_domain *d, unsigned int irq,
305 irq_set_percpu_devid(irq);
306 irq_set_chip_and_handler(irq, &hip04_irq_chip,
307 handle_percpu_devid_irq);
308 set_irq_flags(irq, IRQF_VALID | IRQF_NOAUTOEN);
310 irq_set_chip_and_handler(irq, &hip04_irq_chip,
312 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
314 irq_set_chip_data(irq, d->host_data);
318 static int hip04_irq_domain_xlate(struct irq_domain *d,
319 struct device_node *controller,
320 const u32 *intspec, unsigned int intsize,
321 unsigned long *out_hwirq,
322 unsigned int *out_type)
324 unsigned long ret = 0;
326 if (d->of_node != controller)
331 /* Get the interrupt number and add 16 to skip over SGIs */
332 *out_hwirq = intspec[1] + 16;
334 /* For SPIs, we need to add 16 more to get the irq ID number */
338 *out_type = intspec[2] & IRQ_TYPE_SENSE_MASK;
344 static int hip04_irq_secondary_init(struct notifier_block *nfb,
345 unsigned long action,
348 if (action == CPU_STARTING || action == CPU_STARTING_FROZEN)
349 hip04_irq_cpu_init(&hip04_data);
354 * Notifier for enabling the INTC CPU interface. Set an arbitrarily high
355 * priority because the GIC needs to be up before the ARM generic timers.
357 static struct notifier_block hip04_irq_cpu_notifier = {
358 .notifier_call = hip04_irq_secondary_init,
363 static const struct irq_domain_ops hip04_irq_domain_ops = {
364 .map = hip04_irq_domain_map,
365 .xlate = hip04_irq_domain_xlate,
369 hip04_of_init(struct device_node *node, struct device_node *parent)
371 irq_hw_number_t hwirq_base = 16;
372 int nr_irqs, irq_base, i;
377 hip04_data.dist_base = of_iomap(node, 0);
378 WARN(!hip04_data.dist_base, "fail to map hip04 intc dist registers\n");
380 hip04_data.cpu_base = of_iomap(node, 1);
381 WARN(!hip04_data.cpu_base, "unable to map hip04 intc cpu registers\n");
384 * Initialize the CPU interface map to all CPUs.
385 * It will be refined as each CPU probes its ID.
387 for (i = 0; i < NR_HIP04_CPU_IF; i++)
388 hip04_cpu_map[i] = 0xffff;
391 * Find out how many interrupts are supported.
392 * The HIP04 INTC only supports up to 510 interrupt sources.
394 nr_irqs = readl_relaxed(hip04_data.dist_base + GIC_DIST_CTR) & 0x1f;
395 nr_irqs = (nr_irqs + 1) * 32;
396 if (nr_irqs > HIP04_MAX_IRQS)
397 nr_irqs = HIP04_MAX_IRQS;
398 hip04_data.nr_irqs = nr_irqs;
400 nr_irqs -= hwirq_base; /* calculate # of irqs to allocate */
402 irq_base = irq_alloc_descs(-1, hwirq_base, nr_irqs, numa_node_id());
403 if (IS_ERR_VALUE(irq_base)) {
404 pr_err("failed to allocate IRQ numbers\n");
408 hip04_data.domain = irq_domain_add_legacy(node, nr_irqs, irq_base,
410 &hip04_irq_domain_ops,
413 if (WARN_ON(!hip04_data.domain))
417 set_smp_cross_call(hip04_raise_softirq);
418 register_cpu_notifier(&hip04_irq_cpu_notifier);
420 set_handle_irq(hip04_handle_irq);
422 hip04_irq_dist_init(&hip04_data);
423 hip04_irq_cpu_init(&hip04_data);
427 IRQCHIP_DECLARE(hip04_intc, "hisilicon,hip04-intc", hip04_of_init);