drivers/irqchip/irq-mips-gic.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 2008 Ralf Baechle (ralf@linux-mips.org)
   7  * Copyright (C) 2012 MIPS Technologies, Inc.  All rights reserved.
   8  */
   9 #include <linux/bitmap.h>
  10 #include <linux/clocksource.h>
  11 #include <linux/init.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/irq.h>
  14 #include <linux/irqchip/mips-gic.h>
  15 #include <linux/of_address.h>
  16 #include <linux/sched.h>
  17 #include <linux/smp.h>
  18
  19 #include <asm/mips-cm.h>
  20 #include <asm/setup.h>
  21 #include <asm/traps.h>
  22
  23 #include <dt-bindings/interrupt-controller/mips-gic.h>
  24
  25 #include "irqchip.h"
  26
  27 unsigned int gic_present;
  28
  29 struct gic_pcpu_mask {
  30         DECLARE_BITMAP(pcpu_mask, GIC_MAX_INTRS);
  31 };
  32
  33 static void __iomem *gic_base;
  34 static struct gic_pcpu_mask pcpu_masks[NR_CPUS];
  35 static DEFINE_SPINLOCK(gic_lock);
  36 static struct irq_domain *gic_irq_domain;
  37 static int gic_shared_intrs;
  38 static int gic_vpes;
  39 static unsigned int gic_cpu_pin;
  40 static unsigned int timer_cpu_pin;
  41 static struct irq_chip gic_level_irq_controller, gic_edge_irq_controller;
  42
  43 static void __gic_irq_dispatch(void);
  44
  45 static inline u32 gic_read32(unsigned int reg)
  46 {
  47         return __raw_readl(gic_base + reg);
  48 }
  49
  50 static inline u64 gic_read64(unsigned int reg)
  51 {
  52         return __raw_readq(gic_base + reg);
  53 }
  54
  55 static inline unsigned long gic_read(unsigned int reg)
  56 {
  57         if (!mips_cm_is64)
  58                 return gic_read32(reg);
  59         else
  60                 return gic_read64(reg);
  61 }
  62
  63 static inline void gic_write32(unsigned int reg, u32 val)
  64 {
  65         return __raw_writel(val, gic_base + reg);
  66 }
  67
  68 static inline void gic_write64(unsigned int reg, u64 val)
  69 {
  70         return __raw_writeq(val, gic_base + reg);
  71 }
  72
  73 static inline void gic_write(unsigned int reg, unsigned long val)
  74 {
  75         if (!mips_cm_is64)
  76                 return gic_write32(reg, (u32)val);
  77         else
  78                 return gic_write64(reg, (u64)val);
  79 }
  80
  81 static inline void gic_update_bits(unsigned int reg, unsigned long mask,
  82                                    unsigned long val)
  83 {
  84         unsigned long regval;
  85
  86         regval = gic_read(reg);
  87         regval &= ~mask;
  88         regval |= val;
  89         gic_write(reg, regval);
  90 }
  91
  92 static inline void gic_reset_mask(unsigned int intr)
  93 {
  94         gic_write(GIC_REG(SHARED, GIC_SH_RMASK) + GIC_INTR_OFS(intr),
  95                   1ul << GIC_INTR_BIT(intr));
  96 }
  97
  98 static inline void gic_set_mask(unsigned int intr)
  99 {
 100         gic_write(GIC_REG(SHARED, GIC_SH_SMASK) + GIC_INTR_OFS(intr),
 101                   1ul << GIC_INTR_BIT(intr));
 102 }
 103
 104 static inline void gic_set_polarity(unsigned int intr, unsigned int pol)
 105 {
 106         gic_update_bits(GIC_REG(SHARED, GIC_SH_SET_POLARITY) +
 107                         GIC_INTR_OFS(intr), 1ul << GIC_INTR_BIT(intr),
 108                         (unsigned long)pol << GIC_INTR_BIT(intr));
 109 }
 110
 111 static inline void gic_set_trigger(unsigned int intr, unsigned int trig)
 112 {
 113         gic_update_bits(GIC_REG(SHARED, GIC_SH_SET_TRIGGER) +
 114                         GIC_INTR_OFS(intr), 1ul << GIC_INTR_BIT(intr),
 115                         (unsigned long)trig << GIC_INTR_BIT(intr));
 116 }
 117
 118 static inline void gic_set_dual_edge(unsigned int intr, unsigned int dual)
 119 {
 120         gic_update_bits(GIC_REG(SHARED, GIC_SH_SET_DUAL) + GIC_INTR_OFS(intr),
 121                         1ul << GIC_INTR_BIT(intr),
 122                         (unsigned long)dual << GIC_INTR_BIT(intr));
 123 }
 124
 125 static inline void gic_map_to_pin(unsigned int intr, unsigned int pin)
 126 {
 127         gic_write32(GIC_REG(SHARED, GIC_SH_INTR_MAP_TO_PIN_BASE) +
 128                     GIC_SH_MAP_TO_PIN(intr), GIC_MAP_TO_PIN_MSK | pin);
 129 }
 130
 131 static inline void gic_map_to_vpe(unsigned int intr, unsigned int vpe)
 132 {
 133         gic_write(GIC_REG(SHARED, GIC_SH_INTR_MAP_TO_VPE_BASE) +
 134                   GIC_SH_MAP_TO_VPE_REG_OFF(intr, vpe),
 135                   GIC_SH_MAP_TO_VPE_REG_BIT(vpe));
 136 }
 137
 138 #ifdef CONFIG_CLKSRC_MIPS_GIC
 139 cycle_t gic_read_count(void)
 140 {
 141         unsigned int hi, hi2, lo;
 142
 143         if (mips_cm_is64)
 144                 return (cycle_t)gic_read(GIC_REG(SHARED, GIC_SH_COUNTER));
 145
 146         do {
 147                 hi = gic_read32(GIC_REG(SHARED, GIC_SH_COUNTER_63_32));
 148                 lo = gic_read32(GIC_REG(SHARED, GIC_SH_COUNTER_31_00));
 149                 hi2 = gic_read32(GIC_REG(SHARED, GIC_SH_COUNTER_63_32));
 150         } while (hi2 != hi);
 151
 152         return (((cycle_t) hi) << 32) + lo;
 153 }
 154
 155 unsigned int gic_get_count_width(void)
 156 {
 157         unsigned int bits, config;
 158
 159         config = gic_read(GIC_REG(SHARED, GIC_SH_CONFIG));
 160         bits = 32 + 4 * ((config & GIC_SH_CONFIG_COUNTBITS_MSK) >>
 161                          GIC_SH_CONFIG_COUNTBITS_SHF);
 162
 163         return bits;
 164 }
 165
 166 void gic_write_compare(cycle_t cnt)
 167 {
 168         if (mips_cm_is64) {
 169                 gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE), cnt);
 170         } else {
 171                 gic_write32(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_HI),
 172                                         (int)(cnt >> 32));
 173                 gic_write32(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_LO),
 174                                         (int)(cnt & 0xffffffff));
 175         }
 176 }
 177
 178 void gic_write_cpu_compare(cycle_t cnt, int cpu)
 179 {
 180         unsigned long flags;
 181
 182         local_irq_save(flags);
 183
 184         gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), cpu);
 185
 186         if (mips_cm_is64) {
 187                 gic_write(GIC_REG(VPE_OTHER, GIC_VPE_COMPARE), cnt);
 188         } else {
 189                 gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_COMPARE_HI),
 190                                         (int)(cnt >> 32));
 191                 gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_COMPARE_LO),
 192                                         (int)(cnt & 0xffffffff));
 193         }
 194
 195         local_irq_restore(flags);
 196 }
 197
 198 cycle_t gic_read_compare(void)
 199 {
 200         unsigned int hi, lo;
 201
 202         if (mips_cm_is64)
 203                 return (cycle_t)gic_read(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE));
 204
 205         hi = gic_read32(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_HI));
 206         lo = gic_read32(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_LO));
 207
 208         return (((cycle_t) hi) << 32) + lo;
 209 }
 210
 211 void gic_start_count(void)
 212 {
 213         u32 gicconfig;
 214
 215         /* Start the counter */
 216         gicconfig = gic_read(GIC_REG(SHARED, GIC_SH_CONFIG));
 217         gicconfig &= ~(1 << GIC_SH_CONFIG_COUNTSTOP_SHF);
 218         gic_write(GIC_REG(SHARED, GIC_SH_CONFIG), gicconfig);
 219 }
 220
 221 void gic_stop_count(void)
 222 {
 223         u32 gicconfig;
 224
 225         /* Stop the counter */
 226         gicconfig = gic_read(GIC_REG(SHARED, GIC_SH_CONFIG));
 227         gicconfig |= 1 << GIC_SH_CONFIG_COUNTSTOP_SHF;
 228         gic_write(GIC_REG(SHARED, GIC_SH_CONFIG), gicconfig);
 229 }
 230
 231 #endif
 232
 233 static bool gic_local_irq_is_routable(int intr)
 234 {
 235         u32 vpe_ctl;
 236
 237         /* All local interrupts are routable in EIC mode. */
 238         if (cpu_has_veic)
 239                 return true;
 240
 241         vpe_ctl = gic_read32(GIC_REG(VPE_LOCAL, GIC_VPE_CTL));
 242         switch (intr) {
 243         case GIC_LOCAL_INT_TIMER:
 244                 return vpe_ctl & GIC_VPE_CTL_TIMER_RTBL_MSK;
 245         case GIC_LOCAL_INT_PERFCTR:
 246                 return vpe_ctl & GIC_VPE_CTL_PERFCNT_RTBL_MSK;
 247         case GIC_LOCAL_INT_FDC:
 248                 return vpe_ctl & GIC_VPE_CTL_FDC_RTBL_MSK;
 249         case GIC_LOCAL_INT_SWINT0:
 250         case GIC_LOCAL_INT_SWINT1:
 251                 return vpe_ctl & GIC_VPE_CTL_SWINT_RTBL_MSK;
 252         default:
 253                 return true;
 254         }
 255 }
 256
 257 static void gic_bind_eic_interrupt(int irq, int set)
 258 {
 259         /* Convert irq vector # to hw int # */
 260         irq -= GIC_PIN_TO_VEC_OFFSET;
 261
 262         /* Set irq to use shadow set */
 263         gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_EIC_SHADOW_SET_BASE) +
 264                   GIC_VPE_EIC_SS(irq), set);
 265 }
 266
 267 void gic_send_ipi(unsigned int intr)
 268 {
 269         gic_write(GIC_REG(SHARED, GIC_SH_WEDGE), GIC_SH_WEDGE_SET(intr));
 270 }
 271
 272 int gic_get_c0_compare_int(void)
 273 {
 274         if (!gic_local_irq_is_routable(GIC_LOCAL_INT_TIMER))
 275                 return MIPS_CPU_IRQ_BASE + cp0_compare_irq;
 276         return irq_create_mapping(gic_irq_domain,
 277                                   GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_TIMER));
 278 }
 279
 280 int gic_get_c0_perfcount_int(void)
 281 {
 282         if (!gic_local_irq_is_routable(GIC_LOCAL_INT_PERFCTR)) {
 283                 /* Is the performance counter shared with the timer? */
 284                 if (cp0_perfcount_irq < 0)
 285                         return -1;
 286                 return MIPS_CPU_IRQ_BASE + cp0_perfcount_irq;
 287         }
 288         return irq_create_mapping(gic_irq_domain,
 289                                   GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_PERFCTR));
 290 }
 291
 292 int gic_get_c0_fdc_int(void)
 293 {
 294         if (!gic_local_irq_is_routable(GIC_LOCAL_INT_FDC)) {
 295                 /* Is the FDC IRQ even present? */
 296                 if (cp0_fdc_irq < 0)
 297                         return -1;
 298                 return MIPS_CPU_IRQ_BASE + cp0_fdc_irq;
 299         }
 300
 301         return irq_create_mapping(gic_irq_domain,
 302                                   GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_FDC));
 303 }
 304
 305 static void gic_handle_shared_int(bool chained)
 306 {
 307         unsigned int i, intr, virq, gic_reg_step = mips_cm_is64 ? 8 : 4;
 308         unsigned long *pcpu_mask;
 309         unsigned long pending_reg, intrmask_reg;
 310         DECLARE_BITMAP(pending, GIC_MAX_INTRS);
 311         DECLARE_BITMAP(intrmask, GIC_MAX_INTRS);
 312
 313         /* Get per-cpu bitmaps */
 314         pcpu_mask = pcpu_masks[smp_processor_id()].pcpu_mask;
 315
 316         pending_reg = GIC_REG(SHARED, GIC_SH_PEND);
 317         intrmask_reg = GIC_REG(SHARED, GIC_SH_MASK);
 318
 319         for (i = 0; i < BITS_TO_LONGS(gic_shared_intrs); i++) {
 320                 pending[i] = gic_read(pending_reg);
 321                 intrmask[i] = gic_read(intrmask_reg);
 322                 pending_reg += gic_reg_step;
 323                 intrmask_reg += gic_reg_step;
 324         }
 325
 326         bitmap_and(pending, pending, intrmask, gic_shared_intrs);
 327         bitmap_and(pending, pending, pcpu_mask, gic_shared_intrs);
 328
 329         intr = find_first_bit(pending, gic_shared_intrs);
 330         while (intr != gic_shared_intrs) {
 331                 virq = irq_linear_revmap(gic_irq_domain,
 332                                          GIC_SHARED_TO_HWIRQ(intr));
 333                 if (chained)
 334                         generic_handle_irq(virq);
 335                 else
 336                         do_IRQ(virq);
 337
 338                 /* go to next pending bit */
 339                 bitmap_clear(pending, intr, 1);
 340                 intr = find_first_bit(pending, gic_shared_intrs);
 341         }
 342 }
 343
 344 static void gic_mask_irq(struct irq_data *d)
 345 {
 346         gic_reset_mask(GIC_HWIRQ_TO_SHARED(d->hwirq));
 347 }
 348
 349 static void gic_unmask_irq(struct irq_data *d)
 350 {
 351         gic_set_mask(GIC_HWIRQ_TO_SHARED(d->hwirq));
 352 }
 353
 354 static void gic_ack_irq(struct irq_data *d)
 355 {
 356         unsigned int irq = GIC_HWIRQ_TO_SHARED(d->hwirq);
 357
 358         gic_write(GIC_REG(SHARED, GIC_SH_WEDGE), GIC_SH_WEDGE_CLR(irq));
 359 }
 360
 361 static int gic_set_type(struct irq_data *d, unsigned int type)
 362 {
 363         unsigned int irq = GIC_HWIRQ_TO_SHARED(d->hwirq);
 364         unsigned long flags;
 365         bool is_edge;
 366
 367         spin_lock_irqsave(&gic_lock, flags);
 368         switch (type & IRQ_TYPE_SENSE_MASK) {
 369         case IRQ_TYPE_EDGE_FALLING:
 370                 gic_set_polarity(irq, GIC_POL_NEG);
 371                 gic_set_trigger(irq, GIC_TRIG_EDGE);
 372                 gic_set_dual_edge(irq, GIC_TRIG_DUAL_DISABLE);
 373                 is_edge = true;
 374                 break;
 375         case IRQ_TYPE_EDGE_RISING:
 376                 gic_set_polarity(irq, GIC_POL_POS);
 377                 gic_set_trigger(irq, GIC_TRIG_EDGE);
 378                 gic_set_dual_edge(irq, GIC_TRIG_DUAL_DISABLE);
 379                 is_edge = true;
 380                 break;
 381         case IRQ_TYPE_EDGE_BOTH:
 382                 /* polarity is irrelevant in this case */
 383                 gic_set_trigger(irq, GIC_TRIG_EDGE);
 384                 gic_set_dual_edge(irq, GIC_TRIG_DUAL_ENABLE);
 385                 is_edge = true;
 386                 break;
 387         case IRQ_TYPE_LEVEL_LOW:
 388                 gic_set_polarity(irq, GIC_POL_NEG);
 389                 gic_set_trigger(irq, GIC_TRIG_LEVEL);
 390                 gic_set_dual_edge(irq, GIC_TRIG_DUAL_DISABLE);
 391                 is_edge = false;
 392                 break;
 393         case IRQ_TYPE_LEVEL_HIGH:
 394         default:
 395                 gic_set_polarity(irq, GIC_POL_POS);
 396                 gic_set_trigger(irq, GIC_TRIG_LEVEL);
 397                 gic_set_dual_edge(irq, GIC_TRIG_DUAL_DISABLE);
 398                 is_edge = false;
 399                 break;
 400         }
 401
 402         if (is_edge) {
 403                 __irq_set_chip_handler_name_locked(d->irq,
 404                                                    &gic_edge_irq_controller,
 405                                                    handle_edge_irq, NULL);
 406         } else {
 407                 __irq_set_chip_handler_name_locked(d->irq,
 408                                                    &gic_level_irq_controller,
 409                                                    handle_level_irq, NULL);
 410         }
 411         spin_unlock_irqrestore(&gic_lock, flags);
 412
 413         return 0;
 414 }
 415
 416 #ifdef CONFIG_SMP
 417 static int gic_set_affinity(struct irq_data *d, const struct cpumask *cpumask,
 418                             bool force)
 419 {
 420         unsigned int irq = GIC_HWIRQ_TO_SHARED(d->hwirq);
 421         cpumask_t       tmp = CPU_MASK_NONE;
 422         unsigned long   flags;
 423         int             i;
 424
 425         cpumask_and(&tmp, cpumask, cpu_online_mask);
 426         if (cpumask_empty(&tmp))
 427                 return -EINVAL;
 428
 429         /* Assumption : cpumask refers to a single CPU */
 430         spin_lock_irqsave(&gic_lock, flags);
 431
 432         /* Re-route this IRQ */
 433         gic_map_to_vpe(irq, cpumask_first(&tmp));
 434
 435         /* Update the pcpu_masks */
 436         for (i = 0; i < NR_CPUS; i++)
 437                 clear_bit(irq, pcpu_masks[i].pcpu_mask);
 438         set_bit(irq, pcpu_masks[cpumask_first(&tmp)].pcpu_mask);
 439
 440         cpumask_copy(d->affinity, cpumask);
 441         spin_unlock_irqrestore(&gic_lock, flags);
 442
 443         return IRQ_SET_MASK_OK_NOCOPY;
 444 }
 445 #endif
 446
 447 static struct irq_chip gic_level_irq_controller = {
 448         .name                   =       "MIPS GIC",
 449         .irq_mask               =       gic_mask_irq,
 450         .irq_unmask             =       gic_unmask_irq,
 451         .irq_set_type           =       gic_set_type,
 452 #ifdef CONFIG_SMP
 453         .irq_set_affinity       =       gic_set_affinity,
 454 #endif
 455 };
 456
 457 static struct irq_chip gic_edge_irq_controller = {
 458         .name                   =       "MIPS GIC",
 459         .irq_ack                =       gic_ack_irq,
 460         .irq_mask               =       gic_mask_irq,
 461         .irq_unmask             =       gic_unmask_irq,
 462         .irq_set_type           =       gic_set_type,
 463 #ifdef CONFIG_SMP
 464         .irq_set_affinity       =       gic_set_affinity,
 465 #endif
 466 };
 467
 468 static void gic_handle_local_int(bool chained)
 469 {
 470         unsigned long pending, masked;
 471         unsigned int intr, virq;
 472
 473         pending = gic_read32(GIC_REG(VPE_LOCAL, GIC_VPE_PEND));
 474         masked = gic_read32(GIC_REG(VPE_LOCAL, GIC_VPE_MASK));
 475
 476         bitmap_and(&pending, &pending, &masked, GIC_NUM_LOCAL_INTRS);
 477
 478         intr = find_first_bit(&pending, GIC_NUM_LOCAL_INTRS);
 479         while (intr != GIC_NUM_LOCAL_INTRS) {
 480                 virq = irq_linear_revmap(gic_irq_domain,
 481                                          GIC_LOCAL_TO_HWIRQ(intr));
 482                 if (chained)
 483                         generic_handle_irq(virq);
 484                 else
 485                         do_IRQ(virq);
 486
 487                 /* go to next pending bit */
 488                 bitmap_clear(&pending, intr, 1);
 489                 intr = find_first_bit(&pending, GIC_NUM_LOCAL_INTRS);
 490         }
 491 }
 492
 493 static void gic_mask_local_irq(struct irq_data *d)
 494 {
 495         int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq);
 496
 497         gic_write32(GIC_REG(VPE_LOCAL, GIC_VPE_RMASK), 1 << intr);
 498 }
 499
 500 static void gic_unmask_local_irq(struct irq_data *d)
 501 {
 502         int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq);
 503
 504         gic_write32(GIC_REG(VPE_LOCAL, GIC_VPE_SMASK), 1 << intr);
 505 }
 506
 507 static struct irq_chip gic_local_irq_controller = {
 508         .name                   =       "MIPS GIC Local",
 509         .irq_mask               =       gic_mask_local_irq,
 510         .irq_unmask             =       gic_unmask_local_irq,
 511 };
 512
 513 static void gic_mask_local_irq_all_vpes(struct irq_data *d)
 514 {
 515         int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq);
 516         int i;
 517         unsigned long flags;
 518
 519         spin_lock_irqsave(&gic_lock, flags);
 520         for (i = 0; i < gic_vpes; i++) {
 521                 gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), i);
 522                 gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_RMASK), 1 << intr);
 523         }
 524         spin_unlock_irqrestore(&gic_lock, flags);
 525 }
 526
 527 static void gic_unmask_local_irq_all_vpes(struct irq_data *d)
 528 {
 529         int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq);
 530         int i;
 531         unsigned long flags;
 532
 533         spin_lock_irqsave(&gic_lock, flags);
 534         for (i = 0; i < gic_vpes; i++) {
 535                 gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), i);
 536                 gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_SMASK), 1 << intr);
 537         }
 538         spin_unlock_irqrestore(&gic_lock, flags);
 539 }
 540
 541 static struct irq_chip gic_all_vpes_local_irq_controller = {
 542         .name                   =       "MIPS GIC Local",
 543         .irq_mask               =       gic_mask_local_irq_all_vpes,
 544         .irq_unmask             =       gic_unmask_local_irq_all_vpes,
 545 };
 546
 547 static void __gic_irq_dispatch(void)
 548 {
 549         gic_handle_local_int(false);
 550         gic_handle_shared_int(false);
 551 }
 552
 553 static void gic_irq_dispatch(unsigned int irq, struct irq_desc *desc)
 554 {
 555         gic_handle_local_int(true);
 556         gic_handle_shared_int(true);
 557 }
 558
 559 #ifdef CONFIG_MIPS_GIC_IPI
 560 static int gic_resched_int_base;
 561 static int gic_call_int_base;
 562
 563 unsigned int plat_ipi_resched_int_xlate(unsigned int cpu)
 564 {
 565         return gic_resched_int_base + cpu;
 566 }
 567
 568 unsigned int plat_ipi_call_int_xlate(unsigned int cpu)
 569 {
 570         return gic_call_int_base + cpu;
 571 }
 572
 573 static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id)
 574 {
 575         scheduler_ipi();
 576
 577         return IRQ_HANDLED;
 578 }
 579
 580 static irqreturn_t ipi_call_interrupt(int irq, void *dev_id)
 581 {
 582         generic_smp_call_function_interrupt();
 583
 584         return IRQ_HANDLED;
 585 }
 586
 587 static struct irqaction irq_resched = {
 588         .handler        = ipi_resched_interrupt,
 589         .flags          = IRQF_PERCPU,
 590         .name           = "IPI resched"
 591 };
 592
 593 static struct irqaction irq_call = {
 594         .handler        = ipi_call_interrupt,
 595         .flags          = IRQF_PERCPU,
 596         .name           = "IPI call"
 597 };
 598
 599 static __init void gic_ipi_init_one(unsigned int intr, int cpu,
 600                                     struct irqaction *action)
 601 {
 602         int virq = irq_create_mapping(gic_irq_domain,
 603                                       GIC_SHARED_TO_HWIRQ(intr));
 604         int i;
 605
 606         gic_map_to_vpe(intr, cpu);
 607         for (i = 0; i < NR_CPUS; i++)
 608                 clear_bit(intr, pcpu_masks[i].pcpu_mask);
 609         set_bit(intr, pcpu_masks[cpu].pcpu_mask);
 610
 611         irq_set_irq_type(virq, IRQ_TYPE_EDGE_RISING);
 612
 613         irq_set_handler(virq, handle_percpu_irq);
 614         setup_irq(virq, action);
 615 }
 616
 617 static __init void gic_ipi_init(void)
 618 {
 619         int i;
 620
 621         /* Use last 2 * NR_CPUS interrupts as IPIs */
 622         gic_resched_int_base = gic_shared_intrs - nr_cpu_ids;
 623         gic_call_int_base = gic_resched_int_base - nr_cpu_ids;
 624
 625         for (i = 0; i < nr_cpu_ids; i++) {
 626                 gic_ipi_init_one(gic_call_int_base + i, i, &irq_call);
 627                 gic_ipi_init_one(gic_resched_int_base + i, i, &irq_resched);
 628         }
 629 }
 630 #else
 631 static inline void gic_ipi_init(void)
 632 {
 633 }
 634 #endif
 635
 636 static void __init gic_basic_init(void)
 637 {
 638         unsigned int i;
 639
 640         board_bind_eic_interrupt = &gic_bind_eic_interrupt;
 641
 642         /* Setup defaults */
 643         for (i = 0; i < gic_shared_intrs; i++) {
 644                 gic_set_polarity(i, GIC_POL_POS);
 645                 gic_set_trigger(i, GIC_TRIG_LEVEL);
 646                 gic_reset_mask(i);
 647         }
 648
 649         for (i = 0; i < gic_vpes; i++) {
 650                 unsigned int j;
 651
 652                 gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), i);
 653                 for (j = 0; j < GIC_NUM_LOCAL_INTRS; j++) {
 654                         if (!gic_local_irq_is_routable(j))
 655                                 continue;
 656                         gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_RMASK), 1 << j);
 657                 }
 658         }
 659 }
 660
 661 static int gic_local_irq_domain_map(struct irq_domain *d, unsigned int virq,
 662                                     irq_hw_number_t hw)
 663 {
 664         int intr = GIC_HWIRQ_TO_LOCAL(hw);
 665         int ret = 0;
 666         int i;
 667         unsigned long flags;
 668
 669         if (!gic_local_irq_is_routable(intr))
 670                 return -EPERM;
 671
 672         /*
 673          * HACK: These are all really percpu interrupts, but the rest
 674          * of the MIPS kernel code does not use the percpu IRQ API for
 675          * the CP0 timer and performance counter interrupts.
 676          */
 677         switch (intr) {
 678         case GIC_LOCAL_INT_TIMER:
 679         case GIC_LOCAL_INT_PERFCTR:
 680         case GIC_LOCAL_INT_FDC:
 681                 irq_set_chip_and_handler(virq,
 682                                          &gic_all_vpes_local_irq_controller,
 683                                          handle_percpu_irq);
 684                 break;
 685         default:
 686                 irq_set_chip_and_handler(virq,
 687                                          &gic_local_irq_controller,
 688                                          handle_percpu_devid_irq);
 689                 irq_set_percpu_devid(virq);
 690                 break;
 691         }
 692
 693         spin_lock_irqsave(&gic_lock, flags);
 694         for (i = 0; i < gic_vpes; i++) {
 695                 u32 val = GIC_MAP_TO_PIN_MSK | gic_cpu_pin;
 696
 697                 gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), i);
 698
 699                 switch (intr) {
 700                 case GIC_LOCAL_INT_WD:
 701                         gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_WD_MAP), val);
 702                         break;
 703                 case GIC_LOCAL_INT_COMPARE:
 704                         gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_COMPARE_MAP),
 705                                     val);
 706                         break;
 707                 case GIC_LOCAL_INT_TIMER:
 708                         /* CONFIG_MIPS_CMP workaround (see __gic_init) */
 709                         val = GIC_MAP_TO_PIN_MSK | timer_cpu_pin;
 710                         gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_TIMER_MAP),
 711                                     val);
 712                         break;
 713                 case GIC_LOCAL_INT_PERFCTR:
 714                         gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_PERFCTR_MAP),
 715                                     val);
 716                         break;
 717                 case GIC_LOCAL_INT_SWINT0:
 718                         gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_SWINT0_MAP),
 719                                     val);
 720                         break;
 721                 case GIC_LOCAL_INT_SWINT1:
 722                         gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_SWINT1_MAP),
 723                                     val);
 724                         break;
 725                 case GIC_LOCAL_INT_FDC:
 726                         gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_FDC_MAP), val);
 727                         break;
 728                 default:
 729                         pr_err("Invalid local IRQ %d\n", intr);
 730                         ret = -EINVAL;
 731                         break;
 732                 }
 733         }
 734         spin_unlock_irqrestore(&gic_lock, flags);
 735
 736         return ret;
 737 }
 738
 739 static int gic_shared_irq_domain_map(struct irq_domain *d, unsigned int virq,
 740                                      irq_hw_number_t hw)
 741 {
 742         int intr = GIC_HWIRQ_TO_SHARED(hw);
 743         unsigned long flags;
 744
 745         irq_set_chip_and_handler(virq, &gic_level_irq_controller,
 746                                  handle_level_irq);
 747
 748         spin_lock_irqsave(&gic_lock, flags);
 749         gic_map_to_pin(intr, gic_cpu_pin);
 750         /* Map to VPE 0 by default */
 751         gic_map_to_vpe(intr, 0);
 752         set_bit(intr, pcpu_masks[0].pcpu_mask);
 753         spin_unlock_irqrestore(&gic_lock, flags);
 754
 755         return 0;
 756 }
 757
 758 static int gic_irq_domain_map(struct irq_domain *d, unsigned int virq,
 759                               irq_hw_number_t hw)
 760 {
 761         if (GIC_HWIRQ_TO_LOCAL(hw) < GIC_NUM_LOCAL_INTRS)
 762                 return gic_local_irq_domain_map(d, virq, hw);
 763         return gic_shared_irq_domain_map(d, virq, hw);
 764 }
 765
 766 static int gic_irq_domain_xlate(struct irq_domain *d, struct device_node *ctrlr,
 767                                 const u32 *intspec, unsigned int intsize,
 768                                 irq_hw_number_t *out_hwirq,
 769                                 unsigned int *out_type)
 770 {
 771         if (intsize != 3)
 772                 return -EINVAL;
 773
 774         if (intspec[0] == GIC_SHARED)
 775                 *out_hwirq = GIC_SHARED_TO_HWIRQ(intspec[1]);
 776         else if (intspec[0] == GIC_LOCAL)
 777                 *out_hwirq = GIC_LOCAL_TO_HWIRQ(intspec[1]);
 778         else
 779                 return -EINVAL;
 780         *out_type = intspec[2] & IRQ_TYPE_SENSE_MASK;
 781
 782         return 0;
 783 }
 784
 785 static const struct irq_domain_ops gic_irq_domain_ops = {
 786         .map = gic_irq_domain_map,
 787         .xlate = gic_irq_domain_xlate,
 788 };
 789
 790 static void __init __gic_init(unsigned long gic_base_addr,
 791                               unsigned long gic_addrspace_size,
 792                               unsigned int cpu_vec, unsigned int irqbase,
 793                               struct device_node *node)
 794 {
 795         unsigned int gicconfig;
 796
 797         gic_base = ioremap_nocache(gic_base_addr, gic_addrspace_size);
 798
 799         gicconfig = gic_read(GIC_REG(SHARED, GIC_SH_CONFIG));
 800         gic_shared_intrs = (gicconfig & GIC_SH_CONFIG_NUMINTRS_MSK) >>
 801                    GIC_SH_CONFIG_NUMINTRS_SHF;
 802         gic_shared_intrs = ((gic_shared_intrs + 1) * 8);
 803
 804         gic_vpes = (gicconfig & GIC_SH_CONFIG_NUMVPES_MSK) >>
 805                   GIC_SH_CONFIG_NUMVPES_SHF;
 806         gic_vpes = gic_vpes + 1;
 807
 808         if (cpu_has_veic) {
 809                 /* Always use vector 1 in EIC mode */
 810                 gic_cpu_pin = 0;
 811                 timer_cpu_pin = gic_cpu_pin;
 812                 set_vi_handler(gic_cpu_pin + GIC_PIN_TO_VEC_OFFSET,
 813                                __gic_irq_dispatch);
 814         } else {
 815                 gic_cpu_pin = cpu_vec - GIC_CPU_PIN_OFFSET;
 816                 irq_set_chained_handler(MIPS_CPU_IRQ_BASE + cpu_vec,
 817                                         gic_irq_dispatch);
 818                 /*
 819                  * With the CMP implementation of SMP (deprecated), other CPUs
 820                  * are started by the bootloader and put into a timer based
 821                  * waiting poll loop. We must not re-route those CPU's local
 822                  * timer interrupts as the wait instruction will never finish,
 823                  * so just handle whatever CPU interrupt it is routed to by
 824                  * default.
 825                  *
 826                  * This workaround should be removed when CMP support is
 827                  * dropped.
 828                  */
 829                 if (IS_ENABLED(CONFIG_MIPS_CMP) &&
 830                     gic_local_irq_is_routable(GIC_LOCAL_INT_TIMER)) {
 831                         timer_cpu_pin = gic_read32(GIC_REG(VPE_LOCAL,
 832                                                          GIC_VPE_TIMER_MAP)) &
 833                                         GIC_MAP_MSK;
 834                         irq_set_chained_handler(MIPS_CPU_IRQ_BASE +
 835                                                 GIC_CPU_PIN_OFFSET +
 836                                                 timer_cpu_pin,
 837                                                 gic_irq_dispatch);
 838                 } else {
 839                         timer_cpu_pin = gic_cpu_pin;
 840                 }
 841         }
 842
 843         gic_irq_domain = irq_domain_add_simple(node, GIC_NUM_LOCAL_INTRS +
 844                                                gic_shared_intrs, irqbase,
 845                                                &gic_irq_domain_ops, NULL);
 846         if (!gic_irq_domain)
 847                 panic("Failed to add GIC IRQ domain");
 848
 849         gic_basic_init();
 850
 851         gic_ipi_init();
 852 }
 853
 854 void __init gic_init(unsigned long gic_base_addr,
 855                      unsigned long gic_addrspace_size,
 856                      unsigned int cpu_vec, unsigned int irqbase)
 857 {
 858         __gic_init(gic_base_addr, gic_addrspace_size, cpu_vec, irqbase, NULL);
 859 }
 860
 861 static int __init gic_of_init(struct device_node *node,
 862                               struct device_node *parent)
 863 {
 864         struct resource res;
 865         unsigned int cpu_vec, i = 0, reserved = 0;
 866         phys_addr_t gic_base;
 867         size_t gic_len;
 868
 869         /* Find the first available CPU vector. */
 870         while (!of_property_read_u32_index(node, "mti,reserved-cpu-vectors",
 871                                            i++, &cpu_vec))
 872                 reserved |= BIT(cpu_vec);
 873         for (cpu_vec = 2; cpu_vec < 8; cpu_vec++) {
 874                 if (!(reserved & BIT(cpu_vec)))
 875                         break;
 876         }
 877         if (cpu_vec == 8) {
 878                 pr_err("No CPU vectors available for GIC\n");
 879                 return -ENODEV;
 880         }
 881
 882         if (of_address_to_resource(node, 0, &res)) {
 883                 /*
 884                  * Probe the CM for the GIC base address if not specified
 885                  * in the device-tree.
 886                  */
 887                 if (mips_cm_present()) {
 888                         gic_base = read_gcr_gic_base() &
 889                                 ~CM_GCR_GIC_BASE_GICEN_MSK;
 890                         gic_len = 0x20000;
 891                 } else {
 892                         pr_err("Failed to get GIC memory range\n");
 893                         return -ENODEV;
 894                 }
 895         } else {
 896                 gic_base = res.start;
 897                 gic_len = resource_size(&res);
 898         }
 899
 900         if (mips_cm_present())
 901                 write_gcr_gic_base(gic_base | CM_GCR_GIC_BASE_GICEN_MSK);
 902         gic_present = true;
 903
 904         __gic_init(gic_base, gic_len, cpu_vec, 0, node);
 905
 906         return 0;
 907 }
 908 IRQCHIP_DECLARE(mips_gic, "mti,gic", gic_of_init);