2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2008 Ralf Baechle (ralf@linux-mips.org)
7 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
9 #include <linux/bitmap.h>
10 #include <linux/clocksource.h>
11 #include <linux/init.h>
12 #include <linux/interrupt.h>
13 #include <linux/irq.h>
14 #include <linux/irqchip.h>
15 #include <linux/irqchip/mips-gic.h>
16 #include <linux/of_address.h>
17 #include <linux/sched.h>
18 #include <linux/smp.h>
20 #include <asm/mips-cm.h>
21 #include <asm/setup.h>
22 #include <asm/traps.h>
24 #include <dt-bindings/interrupt-controller/mips-gic.h>
26 unsigned int gic_present;
28 struct gic_pcpu_mask {
29 DECLARE_BITMAP(pcpu_mask, GIC_MAX_INTRS);
32 static void __iomem *gic_base;
33 static struct gic_pcpu_mask pcpu_masks[NR_CPUS];
34 static DEFINE_SPINLOCK(gic_lock);
35 static struct irq_domain *gic_irq_domain;
36 static int gic_shared_intrs;
38 static unsigned int gic_cpu_pin;
39 static unsigned int timer_cpu_pin;
40 static struct irq_chip gic_level_irq_controller, gic_edge_irq_controller;
42 static void __gic_irq_dispatch(void);
44 static inline unsigned int gic_read(unsigned int reg)
46 return __raw_readl(gic_base + reg);
49 static inline void gic_write(unsigned int reg, unsigned int val)
51 __raw_writel(val, gic_base + reg);
54 static inline void gic_update_bits(unsigned int reg, unsigned int mask,
59 regval = gic_read(reg);
62 gic_write(reg, regval);
65 static inline void gic_reset_mask(unsigned int intr)
67 gic_write(GIC_REG(SHARED, GIC_SH_RMASK) + GIC_INTR_OFS(intr),
68 1 << GIC_INTR_BIT(intr));
71 static inline void gic_set_mask(unsigned int intr)
73 gic_write(GIC_REG(SHARED, GIC_SH_SMASK) + GIC_INTR_OFS(intr),
74 1 << GIC_INTR_BIT(intr));
77 static inline void gic_set_polarity(unsigned int intr, unsigned int pol)
79 gic_update_bits(GIC_REG(SHARED, GIC_SH_SET_POLARITY) +
80 GIC_INTR_OFS(intr), 1 << GIC_INTR_BIT(intr),
81 pol << GIC_INTR_BIT(intr));
84 static inline void gic_set_trigger(unsigned int intr, unsigned int trig)
86 gic_update_bits(GIC_REG(SHARED, GIC_SH_SET_TRIGGER) +
87 GIC_INTR_OFS(intr), 1 << GIC_INTR_BIT(intr),
88 trig << GIC_INTR_BIT(intr));
91 static inline void gic_set_dual_edge(unsigned int intr, unsigned int dual)
93 gic_update_bits(GIC_REG(SHARED, GIC_SH_SET_DUAL) + GIC_INTR_OFS(intr),
94 1 << GIC_INTR_BIT(intr),
95 dual << GIC_INTR_BIT(intr));
98 static inline void gic_map_to_pin(unsigned int intr, unsigned int pin)
100 gic_write(GIC_REG(SHARED, GIC_SH_INTR_MAP_TO_PIN_BASE) +
101 GIC_SH_MAP_TO_PIN(intr), GIC_MAP_TO_PIN_MSK | pin);
104 static inline void gic_map_to_vpe(unsigned int intr, unsigned int vpe)
106 gic_write(GIC_REG(SHARED, GIC_SH_INTR_MAP_TO_VPE_BASE) +
107 GIC_SH_MAP_TO_VPE_REG_OFF(intr, vpe),
108 GIC_SH_MAP_TO_VPE_REG_BIT(vpe));
111 #ifdef CONFIG_CLKSRC_MIPS_GIC
112 cycle_t gic_read_count(void)
114 unsigned int hi, hi2, lo;
117 hi = gic_read(GIC_REG(SHARED, GIC_SH_COUNTER_63_32));
118 lo = gic_read(GIC_REG(SHARED, GIC_SH_COUNTER_31_00));
119 hi2 = gic_read(GIC_REG(SHARED, GIC_SH_COUNTER_63_32));
122 return (((cycle_t) hi) << 32) + lo;
125 unsigned int gic_get_count_width(void)
127 unsigned int bits, config;
129 config = gic_read(GIC_REG(SHARED, GIC_SH_CONFIG));
130 bits = 32 + 4 * ((config & GIC_SH_CONFIG_COUNTBITS_MSK) >>
131 GIC_SH_CONFIG_COUNTBITS_SHF);
136 void gic_write_compare(cycle_t cnt)
138 gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_HI),
140 gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_LO),
141 (int)(cnt & 0xffffffff));
144 void gic_write_cpu_compare(cycle_t cnt, int cpu)
148 local_irq_save(flags);
150 gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), cpu);
151 gic_write(GIC_REG(VPE_OTHER, GIC_VPE_COMPARE_HI),
153 gic_write(GIC_REG(VPE_OTHER, GIC_VPE_COMPARE_LO),
154 (int)(cnt & 0xffffffff));
156 local_irq_restore(flags);
159 cycle_t gic_read_compare(void)
163 hi = gic_read(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_HI));
164 lo = gic_read(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_LO));
166 return (((cycle_t) hi) << 32) + lo;
169 void gic_start_count(void)
173 /* Start the counter */
174 gicconfig = gic_read(GIC_REG(SHARED, GIC_SH_CONFIG));
175 gicconfig &= ~(1 << GIC_SH_CONFIG_COUNTSTOP_SHF);
176 gic_write(GIC_REG(SHARED, GIC_SH_CONFIG), gicconfig);
179 void gic_stop_count(void)
183 /* Stop the counter */
184 gicconfig = gic_read(GIC_REG(SHARED, GIC_SH_CONFIG));
185 gicconfig |= 1 << GIC_SH_CONFIG_COUNTSTOP_SHF;
186 gic_write(GIC_REG(SHARED, GIC_SH_CONFIG), gicconfig);
191 static bool gic_local_irq_is_routable(int intr)
195 /* All local interrupts are routable in EIC mode. */
199 vpe_ctl = gic_read(GIC_REG(VPE_LOCAL, GIC_VPE_CTL));
201 case GIC_LOCAL_INT_TIMER:
202 return vpe_ctl & GIC_VPE_CTL_TIMER_RTBL_MSK;
203 case GIC_LOCAL_INT_PERFCTR:
204 return vpe_ctl & GIC_VPE_CTL_PERFCNT_RTBL_MSK;
205 case GIC_LOCAL_INT_FDC:
206 return vpe_ctl & GIC_VPE_CTL_FDC_RTBL_MSK;
207 case GIC_LOCAL_INT_SWINT0:
208 case GIC_LOCAL_INT_SWINT1:
209 return vpe_ctl & GIC_VPE_CTL_SWINT_RTBL_MSK;
215 static void gic_bind_eic_interrupt(int irq, int set)
217 /* Convert irq vector # to hw int # */
218 irq -= GIC_PIN_TO_VEC_OFFSET;
220 /* Set irq to use shadow set */
221 gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_EIC_SHADOW_SET_BASE) +
222 GIC_VPE_EIC_SS(irq), set);
225 void gic_send_ipi(unsigned int intr)
227 gic_write(GIC_REG(SHARED, GIC_SH_WEDGE), GIC_SH_WEDGE_SET(intr));
230 int gic_get_c0_compare_int(void)
232 if (!gic_local_irq_is_routable(GIC_LOCAL_INT_TIMER))
233 return MIPS_CPU_IRQ_BASE + cp0_compare_irq;
234 return irq_create_mapping(gic_irq_domain,
235 GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_TIMER));
238 int gic_get_c0_perfcount_int(void)
240 if (!gic_local_irq_is_routable(GIC_LOCAL_INT_PERFCTR)) {
241 /* Is the performance counter shared with the timer? */
242 if (cp0_perfcount_irq < 0)
244 return MIPS_CPU_IRQ_BASE + cp0_perfcount_irq;
246 return irq_create_mapping(gic_irq_domain,
247 GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_PERFCTR));
250 int gic_get_c0_fdc_int(void)
252 if (!gic_local_irq_is_routable(GIC_LOCAL_INT_FDC)) {
253 /* Is the FDC IRQ even present? */
256 return MIPS_CPU_IRQ_BASE + cp0_fdc_irq;
259 return irq_create_mapping(gic_irq_domain,
260 GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_FDC));
263 static void gic_handle_shared_int(bool chained)
265 unsigned int i, intr, virq;
266 unsigned long *pcpu_mask;
267 unsigned long pending_reg, intrmask_reg;
268 DECLARE_BITMAP(pending, GIC_MAX_INTRS);
269 DECLARE_BITMAP(intrmask, GIC_MAX_INTRS);
271 /* Get per-cpu bitmaps */
272 pcpu_mask = pcpu_masks[smp_processor_id()].pcpu_mask;
274 pending_reg = GIC_REG(SHARED, GIC_SH_PEND);
275 intrmask_reg = GIC_REG(SHARED, GIC_SH_MASK);
277 for (i = 0; i < BITS_TO_LONGS(gic_shared_intrs); i++) {
278 pending[i] = gic_read(pending_reg);
279 intrmask[i] = gic_read(intrmask_reg);
284 bitmap_and(pending, pending, intrmask, gic_shared_intrs);
285 bitmap_and(pending, pending, pcpu_mask, gic_shared_intrs);
287 intr = find_first_bit(pending, gic_shared_intrs);
288 while (intr != gic_shared_intrs) {
289 virq = irq_linear_revmap(gic_irq_domain,
290 GIC_SHARED_TO_HWIRQ(intr));
292 generic_handle_irq(virq);
296 /* go to next pending bit */
297 bitmap_clear(pending, intr, 1);
298 intr = find_first_bit(pending, gic_shared_intrs);
302 static void gic_mask_irq(struct irq_data *d)
304 gic_reset_mask(GIC_HWIRQ_TO_SHARED(d->hwirq));
307 static void gic_unmask_irq(struct irq_data *d)
309 gic_set_mask(GIC_HWIRQ_TO_SHARED(d->hwirq));
312 static void gic_ack_irq(struct irq_data *d)
314 unsigned int irq = GIC_HWIRQ_TO_SHARED(d->hwirq);
316 gic_write(GIC_REG(SHARED, GIC_SH_WEDGE), GIC_SH_WEDGE_CLR(irq));
319 static int gic_set_type(struct irq_data *d, unsigned int type)
321 unsigned int irq = GIC_HWIRQ_TO_SHARED(d->hwirq);
325 spin_lock_irqsave(&gic_lock, flags);
326 switch (type & IRQ_TYPE_SENSE_MASK) {
327 case IRQ_TYPE_EDGE_FALLING:
328 gic_set_polarity(irq, GIC_POL_NEG);
329 gic_set_trigger(irq, GIC_TRIG_EDGE);
330 gic_set_dual_edge(irq, GIC_TRIG_DUAL_DISABLE);
333 case IRQ_TYPE_EDGE_RISING:
334 gic_set_polarity(irq, GIC_POL_POS);
335 gic_set_trigger(irq, GIC_TRIG_EDGE);
336 gic_set_dual_edge(irq, GIC_TRIG_DUAL_DISABLE);
339 case IRQ_TYPE_EDGE_BOTH:
340 /* polarity is irrelevant in this case */
341 gic_set_trigger(irq, GIC_TRIG_EDGE);
342 gic_set_dual_edge(irq, GIC_TRIG_DUAL_ENABLE);
345 case IRQ_TYPE_LEVEL_LOW:
346 gic_set_polarity(irq, GIC_POL_NEG);
347 gic_set_trigger(irq, GIC_TRIG_LEVEL);
348 gic_set_dual_edge(irq, GIC_TRIG_DUAL_DISABLE);
351 case IRQ_TYPE_LEVEL_HIGH:
353 gic_set_polarity(irq, GIC_POL_POS);
354 gic_set_trigger(irq, GIC_TRIG_LEVEL);
355 gic_set_dual_edge(irq, GIC_TRIG_DUAL_DISABLE);
361 irq_set_chip_handler_name_locked(d, &gic_edge_irq_controller,
362 handle_edge_irq, NULL);
364 irq_set_chip_handler_name_locked(d, &gic_level_irq_controller,
365 handle_level_irq, NULL);
366 spin_unlock_irqrestore(&gic_lock, flags);
372 static int gic_set_affinity(struct irq_data *d, const struct cpumask *cpumask,
375 unsigned int irq = GIC_HWIRQ_TO_SHARED(d->hwirq);
376 cpumask_t tmp = CPU_MASK_NONE;
380 cpumask_and(&tmp, cpumask, cpu_online_mask);
381 if (cpumask_empty(&tmp))
384 /* Assumption : cpumask refers to a single CPU */
385 spin_lock_irqsave(&gic_lock, flags);
387 /* Re-route this IRQ */
388 gic_map_to_vpe(irq, cpumask_first(&tmp));
390 /* Update the pcpu_masks */
391 for (i = 0; i < NR_CPUS; i++)
392 clear_bit(irq, pcpu_masks[i].pcpu_mask);
393 set_bit(irq, pcpu_masks[cpumask_first(&tmp)].pcpu_mask);
395 cpumask_copy(irq_data_get_affinity_mask(d), cpumask);
396 spin_unlock_irqrestore(&gic_lock, flags);
398 return IRQ_SET_MASK_OK_NOCOPY;
402 static struct irq_chip gic_level_irq_controller = {
404 .irq_mask = gic_mask_irq,
405 .irq_unmask = gic_unmask_irq,
406 .irq_set_type = gic_set_type,
408 .irq_set_affinity = gic_set_affinity,
412 static struct irq_chip gic_edge_irq_controller = {
414 .irq_ack = gic_ack_irq,
415 .irq_mask = gic_mask_irq,
416 .irq_unmask = gic_unmask_irq,
417 .irq_set_type = gic_set_type,
419 .irq_set_affinity = gic_set_affinity,
423 static void gic_handle_local_int(bool chained)
425 unsigned long pending, masked;
426 unsigned int intr, virq;
428 pending = gic_read(GIC_REG(VPE_LOCAL, GIC_VPE_PEND));
429 masked = gic_read(GIC_REG(VPE_LOCAL, GIC_VPE_MASK));
431 bitmap_and(&pending, &pending, &masked, GIC_NUM_LOCAL_INTRS);
433 intr = find_first_bit(&pending, GIC_NUM_LOCAL_INTRS);
434 while (intr != GIC_NUM_LOCAL_INTRS) {
435 virq = irq_linear_revmap(gic_irq_domain,
436 GIC_LOCAL_TO_HWIRQ(intr));
438 generic_handle_irq(virq);
442 /* go to next pending bit */
443 bitmap_clear(&pending, intr, 1);
444 intr = find_first_bit(&pending, GIC_NUM_LOCAL_INTRS);
448 static void gic_mask_local_irq(struct irq_data *d)
450 int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq);
452 gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_RMASK), 1 << intr);
455 static void gic_unmask_local_irq(struct irq_data *d)
457 int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq);
459 gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_SMASK), 1 << intr);
462 static struct irq_chip gic_local_irq_controller = {
463 .name = "MIPS GIC Local",
464 .irq_mask = gic_mask_local_irq,
465 .irq_unmask = gic_unmask_local_irq,
468 static void gic_mask_local_irq_all_vpes(struct irq_data *d)
470 int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq);
474 spin_lock_irqsave(&gic_lock, flags);
475 for (i = 0; i < gic_vpes; i++) {
476 gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), i);
477 gic_write(GIC_REG(VPE_OTHER, GIC_VPE_RMASK), 1 << intr);
479 spin_unlock_irqrestore(&gic_lock, flags);
482 static void gic_unmask_local_irq_all_vpes(struct irq_data *d)
484 int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq);
488 spin_lock_irqsave(&gic_lock, flags);
489 for (i = 0; i < gic_vpes; i++) {
490 gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), i);
491 gic_write(GIC_REG(VPE_OTHER, GIC_VPE_SMASK), 1 << intr);
493 spin_unlock_irqrestore(&gic_lock, flags);
496 static struct irq_chip gic_all_vpes_local_irq_controller = {
497 .name = "MIPS GIC Local",
498 .irq_mask = gic_mask_local_irq_all_vpes,
499 .irq_unmask = gic_unmask_local_irq_all_vpes,
502 static void __gic_irq_dispatch(void)
504 gic_handle_local_int(false);
505 gic_handle_shared_int(false);
508 static void gic_irq_dispatch(unsigned int irq, struct irq_desc *desc)
510 gic_handle_local_int(true);
511 gic_handle_shared_int(true);
514 #ifdef CONFIG_MIPS_GIC_IPI
515 static int gic_resched_int_base;
516 static int gic_call_int_base;
518 unsigned int plat_ipi_resched_int_xlate(unsigned int cpu)
520 return gic_resched_int_base + cpu;
523 unsigned int plat_ipi_call_int_xlate(unsigned int cpu)
525 return gic_call_int_base + cpu;
528 static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id)
535 static irqreturn_t ipi_call_interrupt(int irq, void *dev_id)
537 generic_smp_call_function_interrupt();
542 static struct irqaction irq_resched = {
543 .handler = ipi_resched_interrupt,
544 .flags = IRQF_PERCPU,
545 .name = "IPI resched"
548 static struct irqaction irq_call = {
549 .handler = ipi_call_interrupt,
550 .flags = IRQF_PERCPU,
554 static __init void gic_ipi_init_one(unsigned int intr, int cpu,
555 struct irqaction *action)
557 int virq = irq_create_mapping(gic_irq_domain,
558 GIC_SHARED_TO_HWIRQ(intr));
561 gic_map_to_vpe(intr, cpu);
562 for (i = 0; i < NR_CPUS; i++)
563 clear_bit(intr, pcpu_masks[i].pcpu_mask);
564 set_bit(intr, pcpu_masks[cpu].pcpu_mask);
566 irq_set_irq_type(virq, IRQ_TYPE_EDGE_RISING);
568 irq_set_handler(virq, handle_percpu_irq);
569 setup_irq(virq, action);
572 static __init void gic_ipi_init(void)
576 /* Use last 2 * NR_CPUS interrupts as IPIs */
577 gic_resched_int_base = gic_shared_intrs - nr_cpu_ids;
578 gic_call_int_base = gic_resched_int_base - nr_cpu_ids;
580 for (i = 0; i < nr_cpu_ids; i++) {
581 gic_ipi_init_one(gic_call_int_base + i, i, &irq_call);
582 gic_ipi_init_one(gic_resched_int_base + i, i, &irq_resched);
586 static inline void gic_ipi_init(void)
591 static void __init gic_basic_init(void)
595 board_bind_eic_interrupt = &gic_bind_eic_interrupt;
598 for (i = 0; i < gic_shared_intrs; i++) {
599 gic_set_polarity(i, GIC_POL_POS);
600 gic_set_trigger(i, GIC_TRIG_LEVEL);
604 for (i = 0; i < gic_vpes; i++) {
607 gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), i);
608 for (j = 0; j < GIC_NUM_LOCAL_INTRS; j++) {
609 if (!gic_local_irq_is_routable(j))
611 gic_write(GIC_REG(VPE_OTHER, GIC_VPE_RMASK), 1 << j);
616 static int gic_local_irq_domain_map(struct irq_domain *d, unsigned int virq,
619 int intr = GIC_HWIRQ_TO_LOCAL(hw);
624 if (!gic_local_irq_is_routable(intr))
628 * HACK: These are all really percpu interrupts, but the rest
629 * of the MIPS kernel code does not use the percpu IRQ API for
630 * the CP0 timer and performance counter interrupts.
633 case GIC_LOCAL_INT_TIMER:
634 case GIC_LOCAL_INT_PERFCTR:
635 case GIC_LOCAL_INT_FDC:
636 irq_set_chip_and_handler(virq,
637 &gic_all_vpes_local_irq_controller,
641 irq_set_chip_and_handler(virq,
642 &gic_local_irq_controller,
643 handle_percpu_devid_irq);
644 irq_set_percpu_devid(virq);
648 spin_lock_irqsave(&gic_lock, flags);
649 for (i = 0; i < gic_vpes; i++) {
650 u32 val = GIC_MAP_TO_PIN_MSK | gic_cpu_pin;
652 gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), i);
655 case GIC_LOCAL_INT_WD:
656 gic_write(GIC_REG(VPE_OTHER, GIC_VPE_WD_MAP), val);
658 case GIC_LOCAL_INT_COMPARE:
659 gic_write(GIC_REG(VPE_OTHER, GIC_VPE_COMPARE_MAP), val);
661 case GIC_LOCAL_INT_TIMER:
662 /* CONFIG_MIPS_CMP workaround (see __gic_init) */
663 val = GIC_MAP_TO_PIN_MSK | timer_cpu_pin;
664 gic_write(GIC_REG(VPE_OTHER, GIC_VPE_TIMER_MAP), val);
666 case GIC_LOCAL_INT_PERFCTR:
667 gic_write(GIC_REG(VPE_OTHER, GIC_VPE_PERFCTR_MAP), val);
669 case GIC_LOCAL_INT_SWINT0:
670 gic_write(GIC_REG(VPE_OTHER, GIC_VPE_SWINT0_MAP), val);
672 case GIC_LOCAL_INT_SWINT1:
673 gic_write(GIC_REG(VPE_OTHER, GIC_VPE_SWINT1_MAP), val);
675 case GIC_LOCAL_INT_FDC:
676 gic_write(GIC_REG(VPE_OTHER, GIC_VPE_FDC_MAP), val);
679 pr_err("Invalid local IRQ %d\n", intr);
684 spin_unlock_irqrestore(&gic_lock, flags);
689 static int gic_shared_irq_domain_map(struct irq_domain *d, unsigned int virq,
692 int intr = GIC_HWIRQ_TO_SHARED(hw);
695 irq_set_chip_and_handler(virq, &gic_level_irq_controller,
698 spin_lock_irqsave(&gic_lock, flags);
699 gic_map_to_pin(intr, gic_cpu_pin);
700 /* Map to VPE 0 by default */
701 gic_map_to_vpe(intr, 0);
702 set_bit(intr, pcpu_masks[0].pcpu_mask);
703 spin_unlock_irqrestore(&gic_lock, flags);
708 static int gic_irq_domain_map(struct irq_domain *d, unsigned int virq,
711 if (GIC_HWIRQ_TO_LOCAL(hw) < GIC_NUM_LOCAL_INTRS)
712 return gic_local_irq_domain_map(d, virq, hw);
713 return gic_shared_irq_domain_map(d, virq, hw);
716 static int gic_irq_domain_xlate(struct irq_domain *d, struct device_node *ctrlr,
717 const u32 *intspec, unsigned int intsize,
718 irq_hw_number_t *out_hwirq,
719 unsigned int *out_type)
724 if (intspec[0] == GIC_SHARED)
725 *out_hwirq = GIC_SHARED_TO_HWIRQ(intspec[1]);
726 else if (intspec[0] == GIC_LOCAL)
727 *out_hwirq = GIC_LOCAL_TO_HWIRQ(intspec[1]);
730 *out_type = intspec[2] & IRQ_TYPE_SENSE_MASK;
735 static const struct irq_domain_ops gic_irq_domain_ops = {
736 .map = gic_irq_domain_map,
737 .xlate = gic_irq_domain_xlate,
740 static void __init __gic_init(unsigned long gic_base_addr,
741 unsigned long gic_addrspace_size,
742 unsigned int cpu_vec, unsigned int irqbase,
743 struct device_node *node)
745 unsigned int gicconfig;
747 gic_base = ioremap_nocache(gic_base_addr, gic_addrspace_size);
749 gicconfig = gic_read(GIC_REG(SHARED, GIC_SH_CONFIG));
750 gic_shared_intrs = (gicconfig & GIC_SH_CONFIG_NUMINTRS_MSK) >>
751 GIC_SH_CONFIG_NUMINTRS_SHF;
752 gic_shared_intrs = ((gic_shared_intrs + 1) * 8);
754 gic_vpes = (gicconfig & GIC_SH_CONFIG_NUMVPES_MSK) >>
755 GIC_SH_CONFIG_NUMVPES_SHF;
756 gic_vpes = gic_vpes + 1;
759 /* Always use vector 1 in EIC mode */
761 timer_cpu_pin = gic_cpu_pin;
762 set_vi_handler(gic_cpu_pin + GIC_PIN_TO_VEC_OFFSET,
765 gic_cpu_pin = cpu_vec - GIC_CPU_PIN_OFFSET;
766 irq_set_chained_handler(MIPS_CPU_IRQ_BASE + cpu_vec,
769 * With the CMP implementation of SMP (deprecated), other CPUs
770 * are started by the bootloader and put into a timer based
771 * waiting poll loop. We must not re-route those CPU's local
772 * timer interrupts as the wait instruction will never finish,
773 * so just handle whatever CPU interrupt it is routed to by
776 * This workaround should be removed when CMP support is
779 if (IS_ENABLED(CONFIG_MIPS_CMP) &&
780 gic_local_irq_is_routable(GIC_LOCAL_INT_TIMER)) {
781 timer_cpu_pin = gic_read(GIC_REG(VPE_LOCAL,
782 GIC_VPE_TIMER_MAP)) &
784 irq_set_chained_handler(MIPS_CPU_IRQ_BASE +
789 timer_cpu_pin = gic_cpu_pin;
793 gic_irq_domain = irq_domain_add_simple(node, GIC_NUM_LOCAL_INTRS +
794 gic_shared_intrs, irqbase,
795 &gic_irq_domain_ops, NULL);
797 panic("Failed to add GIC IRQ domain");
804 void __init gic_init(unsigned long gic_base_addr,
805 unsigned long gic_addrspace_size,
806 unsigned int cpu_vec, unsigned int irqbase)
808 __gic_init(gic_base_addr, gic_addrspace_size, cpu_vec, irqbase, NULL);
811 static int __init gic_of_init(struct device_node *node,
812 struct device_node *parent)
815 unsigned int cpu_vec, i = 0, reserved = 0;
816 phys_addr_t gic_base;
819 /* Find the first available CPU vector. */
820 while (!of_property_read_u32_index(node, "mti,reserved-cpu-vectors",
822 reserved |= BIT(cpu_vec);
823 for (cpu_vec = 2; cpu_vec < 8; cpu_vec++) {
824 if (!(reserved & BIT(cpu_vec)))
828 pr_err("No CPU vectors available for GIC\n");
832 if (of_address_to_resource(node, 0, &res)) {
834 * Probe the CM for the GIC base address if not specified
835 * in the device-tree.
837 if (mips_cm_present()) {
838 gic_base = read_gcr_gic_base() &
839 ~CM_GCR_GIC_BASE_GICEN_MSK;
842 pr_err("Failed to get GIC memory range\n");
846 gic_base = res.start;
847 gic_len = resource_size(&res);
850 if (mips_cm_present())
851 write_gcr_gic_base(gic_base | CM_GCR_GIC_BASE_GICEN_MSK);
854 __gic_init(gic_base, gic_len, cpu_vec, 0, node);
858 IRQCHIP_DECLARE(mips_gic, "mti,gic", gic_of_init);