2 * see notice in hfc_multi.c
5 #define DEBUG_HFCMULTI_FIFO 0x00010000
6 #define DEBUG_HFCMULTI_CRC 0x00020000
7 #define DEBUG_HFCMULTI_INIT 0x00040000
8 #define DEBUG_HFCMULTI_PLXSD 0x00080000
9 #define DEBUG_HFCMULTI_MODE 0x00100000
10 #define DEBUG_HFCMULTI_MSG 0x00200000
11 #define DEBUG_HFCMULTI_STATE 0x00400000
12 #define DEBUG_HFCMULTI_SYNC 0x01000000
13 #define DEBUG_HFCMULTI_DTMF 0x02000000
14 #define DEBUG_HFCMULTI_LOCK 0x80000000
16 #define PCI_ENA_REGIO 0x01
17 #define PCI_ENA_MEMIO 0x02
20 * NOTE: some registers are assigned multiple times due to different modes
21 * also registers are assigned differen for HFC-4s/8s and HFC-E1
25 #define MAX_FRAME_SIZE 2048
29 struct dchannel *dch; /* link if channel is a D-channel */
30 struct bchannel *bch; /* link if channel is a B-channel */
31 int port; /* the interface port this */
32 /* channel is associated with */
33 int nt_timer; /* -1 if off, 0 if elapsed, >0 if running */
34 int los, ais, slip_tx, slip_rx, rdi; /* current alarms */
36 u_long cfg; /* port configuration */
37 int sync; /* sync state (used by E1) */
38 u_int protocol; /* current protocol */
39 int slot_tx; /* current pcm slot */
40 int bank_tx; /* current pcm bank */
43 int conf; /* conference setting of TX slot */
44 int txpending; /* if there is currently data in */
45 /* the FIFO 0=no, 1=yes, 2=splloop */
46 int rx_off; /* set to turn fifo receive off */
47 int coeff_count; /* curren coeff block */
48 s32 *coeff; /* memory pointer to 8 coeff blocks */
68 /* for each stack these flags are used (cfg) */
69 #define HFC_CFG_NONCAP_TX 1 /* S/T TX interface has less capacity */
70 #define HFC_CFG_DIS_ECHANNEL 2 /* disable E-channel processing */
71 #define HFC_CFG_REG_ECHANNEL 3 /* register E-channel */
72 #define HFC_CFG_OPTICAL 4 /* the E1 interface is optical */
73 #define HFC_CFG_REPORT_LOS 5 /* the card should report loss of signal */
74 #define HFC_CFG_REPORT_AIS 6 /* the card should report alarm ind. sign. */
75 #define HFC_CFG_REPORT_SLIP 7 /* the card should report bit slips */
76 #define HFC_CFG_REPORT_RDI 8 /* the card should report remote alarm */
77 #define HFC_CFG_DTMF 9 /* enable DTMF-detection */
78 #define HFC_CFG_CRC4 10 /* disable CRC-4 Multiframe mode, */
79 /* use double frame instead. */
81 #define HFC_CHIP_EXRAM_128 0 /* external ram 128k */
82 #define HFC_CHIP_EXRAM_512 1 /* external ram 256k */
83 #define HFC_CHIP_REVISION0 2 /* old fifo handling */
84 #define HFC_CHIP_PCM_SLAVE 3 /* PCM is slave */
85 #define HFC_CHIP_PCM_MASTER 4 /* PCM is master */
86 #define HFC_CHIP_RX_SYNC 5 /* disable pll sync for pcm */
87 #define HFC_CHIP_DTMF 6 /* DTMF decoding is enabled */
88 #define HFC_CHIP_ULAW 7 /* ULAW mode */
89 #define HFC_CHIP_CLOCK2 8 /* double clock mode */
90 #define HFC_CHIP_E1CLOCK_GET 9 /* always get clock from E1 interface */
91 #define HFC_CHIP_E1CLOCK_PUT 10 /* always put clock from E1 interface */
92 #define HFC_CHIP_WATCHDOG 11 /* whether we should send signals */
94 #define HFC_CHIP_B410P 12 /* whether we have a b410p with echocan in */
96 #define HFC_CHIP_PLXSD 13 /* whether we have a Speech-Design PLX */
98 #define HFC_IO_MODE_PCIMEM 0x00 /* normal memory mapped IO */
99 #define HFC_IO_MODE_REGIO 0x01 /* PCI io access */
100 #define HFC_IO_MODE_PLXSD 0x02 /* access HFC via PLX9030 */
102 /* table entry in the PCI devices list */
116 struct list_head list;
119 int pcm; /* id of pcm bus */
123 u_int irq; /* irq used by card */
125 struct pci_dev *pci_dev;
126 int io_mode; /* selects mode */
127 #ifdef HFC_REGISTER_DEBUG
128 void (*HFC_outb)(struct hfc_multi *hc, u_char reg,
129 u_char val, const char *function, int line);
130 void (*HFC_outb_nodebug)(struct hfc_multi *hc, u_char reg,
131 u_char val, const char *function, int line);
132 u_char (*HFC_inb)(struct hfc_multi *hc, u_char reg,
133 const char *function, int line);
134 u_char (*HFC_inb_nodebug)(struct hfc_multi *hc, u_char reg,
135 const char *function, int line);
136 u_short (*HFC_inw)(struct hfc_multi *hc, u_char reg,
137 const char *function, int line);
138 u_short (*HFC_inw_nodebug)(struct hfc_multi *hc, u_char reg,
139 const char *function, int line);
140 void (*HFC_wait)(struct hfc_multi *hc,
141 const char *function, int line);
142 void (*HFC_wait_nodebug)(struct hfc_multi *hc,
143 const char *function, int line);
145 void (*HFC_outb)(struct hfc_multi *hc, u_char reg,
147 void (*HFC_outb_nodebug)(struct hfc_multi *hc, u_char reg,
149 u_char (*HFC_inb)(struct hfc_multi *hc, u_char reg);
150 u_char (*HFC_inb_nodebug)(struct hfc_multi *hc, u_char reg);
151 u_short (*HFC_inw)(struct hfc_multi *hc, u_char reg);
152 u_short (*HFC_inw_nodebug)(struct hfc_multi *hc, u_char reg);
153 void (*HFC_wait)(struct hfc_multi *hc);
154 void (*HFC_wait_nodebug)(struct hfc_multi *hc);
156 void (*read_fifo)(struct hfc_multi *hc, u_char *data,
158 void (*write_fifo)(struct hfc_multi *hc, u_char *data,
160 u_long pci_origmembase, plx_origmembase, dsp_origmembase;
161 void __iomem *pci_membase; /* PCI memory */
162 void __iomem *plx_membase; /* PLX memory */
163 u_char *dsp_membase; /* DSP on PLX */
164 u_long pci_iobase; /* PCI IO */
165 struct hfcm_hw hw; /* remember data of write-only-registers */
167 u_long chip; /* chip configuration */
168 int masterclk; /* port that provides master clock -1=off */
169 int dtmf; /* flag that dtmf is currently in process */
170 int Flen; /* F-buffer size */
171 int Zlen; /* Z-buffer size (must be int for calculation)*/
172 int max_trans; /* maximum transparent fifo fill */
173 int Zmin; /* Z-buffer offset */
174 int DTMFbase; /* base address of DTMF coefficients */
176 u_int slots; /* number of PCM slots */
177 u_int leds; /* type of leds */
178 u_int ledcount; /* used to animate leds */
179 u_long ledstate; /* save last state of leds */
180 int opticalsupport; /* has the e1 board */
181 /* an optical Interface */
182 int dslot; /* channel # of d-channel (E1) default 16 */
184 u_long wdcount; /* every 500 ms we need to */
185 /* send the watchdog a signal */
186 u_char wdbyte; /* watchdog toggle byte */
187 u_int activity[8]; /* if there is any action on this */
188 /* port (will be cleared after */
189 /* showing led-states) */
190 int e1_state; /* keep track of last state */
191 int e1_getclock; /* if sync is retrieved from interface */
192 int syncronized; /* keep track of existing sync interface */
193 int e1_resync; /* resync jobs */
195 spinlock_t lock; /* the lock */
198 * the channel index is counted from 0, regardless where the channel
199 * is located on the hfc-channel.
200 * the bch->channel is equvalent to the hfc-channel
202 struct hfc_chan chan[32];
203 u_char created[8]; /* what port is created */
204 signed char slot_owner[256]; /* owner channel of slot */
208 #define PLX_GPIO4_DIR_BIT 13
209 #define PLX_GPIO4_BIT 14
210 #define PLX_GPIO5_DIR_BIT 16
211 #define PLX_GPIO5_BIT 17
212 #define PLX_GPIO6_DIR_BIT 19
213 #define PLX_GPIO6_BIT 20
214 #define PLX_GPIO7_DIR_BIT 22
215 #define PLX_GPIO7_BIT 23
216 #define PLX_GPIO8_DIR_BIT 25
217 #define PLX_GPIO8_BIT 26
219 #define PLX_GPIO4 (1 << PLX_GPIO4_BIT)
220 #define PLX_GPIO5 (1 << PLX_GPIO5_BIT)
221 #define PLX_GPIO6 (1 << PLX_GPIO6_BIT)
222 #define PLX_GPIO7 (1 << PLX_GPIO7_BIT)
223 #define PLX_GPIO8 (1 << PLX_GPIO8_BIT)
225 #define PLX_GPIO4_DIR (1 << PLX_GPIO4_DIR_BIT)
226 #define PLX_GPIO5_DIR (1 << PLX_GPIO5_DIR_BIT)
227 #define PLX_GPIO6_DIR (1 << PLX_GPIO6_DIR_BIT)
228 #define PLX_GPIO7_DIR (1 << PLX_GPIO7_DIR_BIT)
229 #define PLX_GPIO8_DIR (1 << PLX_GPIO8_DIR_BIT)
231 #define PLX_TERM_ON PLX_GPIO7
232 #define PLX_SLAVE_EN_N PLX_GPIO5
233 #define PLX_MASTER_EN PLX_GPIO6
234 #define PLX_SYNC_O_EN PLX_GPIO4
235 #define PLX_DSP_RES_N PLX_GPIO8
236 /* GPIO4..8 Enable & Set to OUT, SLAVE_EN_N = 1 */
237 #define PLX_GPIOC_INIT (PLX_GPIO4_DIR | PLX_GPIO5_DIR | PLX_GPIO6_DIR \
238 | PLX_GPIO7_DIR | PLX_GPIO8_DIR | PLX_SLAVE_EN_N)
240 /* PLX Interrupt Control/STATUS */
241 #define PLX_INTCSR_LINTI1_ENABLE 0x01
242 #define PLX_INTCSR_LINTI1_STATUS 0x04
243 #define PLX_INTCSR_LINTI2_ENABLE 0x08
244 #define PLX_INTCSR_LINTI2_STATUS 0x20
245 #define PLX_INTCSR_PCIINT_ENABLE 0x40
248 #define PLX_INTCSR 0x4c
249 #define PLX_CNTRL 0x50
250 #define PLX_GPIOC 0x54
254 * REGISTER SETTING FOR HFC-4S/8S AND HFC-E1
257 /* write only registers */
260 #define R_BRG_PCM_CFG 0x02
261 #define R_RAM_ADDR0 0x08
262 #define R_RAM_ADDR1 0x09
263 #define R_RAM_ADDR2 0x0A
264 #define R_FIRST_FIFO 0x0B
265 #define R_RAM_SZ 0x0C
266 #define R_FIFO_MD 0x0D
267 #define R_INC_RES_FIFO 0x0E
268 #define R_FSM_IDX 0x0F
271 #define R_IRQMSK_MISC 0x11
272 #define R_SCI_MSK 0x12
273 #define R_IRQ_CTRL 0x13
274 #define R_PCM_MD0 0x14
275 #define R_PCM_MD1 0x15
276 #define R_PCM_MD2 0x15
281 #define R_SL_SEL0 0x15
282 #define R_SL_SEL1 0x15
283 #define R_SL_SEL2 0x15
284 #define R_SL_SEL3 0x15
285 #define R_SL_SEL4 0x15
286 #define R_SL_SEL5 0x15
287 #define R_SL_SEL6 0x15
288 #define R_SL_SEL7 0x15
289 #define R_ST_SEL 0x16
290 #define R_ST_SYNC 0x17
291 #define R_CONF_EN 0x18
293 #define R_BERT_WD_MD 0x1B
295 #define R_DTMF_N 0x1D
296 #define R_E1_WR_STA 0x20
297 #define R_E1_RD_STA 0x20
301 #define R_RX_FR0 0x25
302 #define R_RX_FR1 0x26
305 #define R_TX_FR0 0x2C
307 #define R_TX_FR1 0x2D
308 #define R_TX_FR2 0x2E
309 #define R_JATT_ATT 0x2F /* undocumented */
310 #define A_ST_RD_STATE 0x30
311 #define A_ST_WR_STATE 0x30
312 #define R_RX_OFF 0x30
313 #define A_ST_CTRL0 0x31
314 #define R_SYNC_OUT 0x31
315 #define A_ST_CTRL1 0x32
316 #define A_ST_CTRL2 0x33
317 #define A_ST_SQ_WR 0x34
318 #define R_TX_OFF 0x34
319 #define R_SYNC_CTRL 0x35
320 #define A_ST_CLK_DLY 0x37
323 #define A_ST_B1_TX 0x3C
324 #define A_ST_B2_TX 0x3D
325 #define A_ST_D_TX 0x3E
326 #define R_GPIO_OUT0 0x40
327 #define R_GPIO_OUT1 0x41
328 #define R_GPIO_EN0 0x42
329 #define R_GPIO_EN1 0x43
330 #define R_GPIO_SEL 0x44
331 #define R_BRG_CTRL 0x45
332 #define R_PWM_MD 0x46
333 #define R_BRG_MD 0x47
334 #define R_BRG_TIM0 0x48
335 #define R_BRG_TIM1 0x49
336 #define R_BRG_TIM2 0x4A
337 #define R_BRG_TIM3 0x4B
338 #define R_BRG_TIM_SEL01 0x4C
339 #define R_BRG_TIM_SEL23 0x4D
340 #define R_BRG_TIM_SEL45 0x4E
341 #define R_BRG_TIM_SEL67 0x4F
342 #define A_SL_CFG 0xD0
344 #define A_CH_MSK 0xF4
345 #define A_CON_HDLC 0xFA
346 #define A_SUBCH_CFG 0xFB
347 #define A_CHANNEL 0xFC
348 #define A_FIFO_SEQ 0xFD
349 #define A_IRQ_MSK 0xFF
351 /* read only registers */
362 #define R_IRQ_OVIEW 0x10
363 #define R_IRQ_MISC 0x11
364 #define R_IRQ_STATECH 0x12
365 #define R_CONF_OFLOW 0x14
366 #define R_RAM_USE 0x15
367 #define R_CHIP_ID 0x16
368 #define R_BERT_STA 0x17
369 #define R_F0_CNTL 0x18
370 #define R_F0_CNTH 0x19
371 #define R_BERT_EC 0x1A
372 #define R_BERT_ECL 0x1A
373 #define R_BERT_ECH 0x1B
374 #define R_STATUS 0x1C
375 #define R_CHIP_RV 0x1F
377 #define R_SYNC_STA 0x24
378 #define R_RX_SL0_0 0x25
379 #define R_RX_SL0_1 0x26
380 #define R_RX_SL0_2 0x27
381 #define R_JATT_DIR 0x2b /* undocumented */
383 #define A_ST_RD_STA 0x30
384 #define R_FAS_EC 0x30
385 #define R_FAS_ECL 0x30
386 #define R_FAS_ECH 0x31
387 #define R_VIO_EC 0x32
388 #define R_VIO_ECL 0x32
389 #define R_VIO_ECH 0x33
390 #define A_ST_SQ_RD 0x34
391 #define R_CRC_EC 0x34
392 #define R_CRC_ECL 0x34
393 #define R_CRC_ECH 0x35
397 #define R_SA6_SA13_EC 0x38
398 #define R_SA6_SA13_ECL 0x38
399 #define R_SA6_SA13_ECH 0x39
400 #define R_SA6_SA23_EC 0x3A
401 #define R_SA6_SA23_ECL 0x3A
402 #define R_SA6_SA23_ECH 0x3B
403 #define A_ST_B1_RX 0x3C
404 #define A_ST_B2_RX 0x3D
405 #define A_ST_D_RX 0x3E
406 #define A_ST_E_RX 0x3F
407 #define R_GPIO_IN0 0x40
408 #define R_GPIO_IN1 0x41
409 #define R_GPI_IN0 0x44
410 #define R_GPI_IN1 0x45
411 #define R_GPI_IN2 0x46
412 #define R_GPI_IN3 0x47
413 #define R_INT_DATA 0x88
414 #define R_IRQ_FIFO_BL0 0xC8
415 #define R_IRQ_FIFO_BL1 0xC9
416 #define R_IRQ_FIFO_BL2 0xCA
417 #define R_IRQ_FIFO_BL3 0xCB
418 #define R_IRQ_FIFO_BL4 0xCC
419 #define R_IRQ_FIFO_BL5 0xCD
420 #define R_IRQ_FIFO_BL6 0xCE
421 #define R_IRQ_FIFO_BL7 0xCF
423 /* read and write registers */
424 #define A_FIFO_DATA0 0x80
425 #define A_FIFO_DATA1 0x80
426 #define A_FIFO_DATA2 0x80
427 #define A_FIFO_DATA0_NOINC 0x84
428 #define A_FIFO_DATA1_NOINC 0x84
429 #define A_FIFO_DATA2_NOINC 0x84
430 #define R_RAM_DATA 0xC0
434 * BIT SETTING FOR HFC-4S/8S AND HFC-E1
437 /* chapter 2: universal bus interface */
439 #define V_IRQ_SEL 0x01
441 #define V_HFCRES 0x10
442 #define V_PCMRES 0x20
445 #define V_RLD_EPR 0x80
447 #define V_FIFO_LPRIO 0x02
448 #define V_SLOW_RD 0x04
449 #define V_EXT_RAM 0x08
450 #define V_CLK_OFF 0x20
451 #define V_ST_CLK 0x40
453 #define V_RAM_ADDR2 0x01
454 #define V_ADDR_RES 0x40
455 #define V_ADDR_INC 0x80
457 #define V_RAM_SZ 0x01
458 #define V_PWM0_16KHZ 0x10
459 #define V_PWM1_16KHZ 0x20
462 #define V_PNP_IRQ 0x01
463 #define V_CHIP_ID 0x10
465 /* chapter 3: data flow */
467 #define V_FIRST_FIRO_DIR 0x01
468 #define V_FIRST_FIFO_NUM 0x02
470 #define V_FIFO_MD 0x01
471 #define V_CSM_MD 0x04
472 #define V_FSM_MD 0x08
473 #define V_FIFO_SZ 0x10
475 #define V_FIFO_DIR 0x01
476 #define V_FIFO_NUM 0x02
479 #define V_SL_DIR 0x01
480 #define V_SL_NUM 0x02
482 #define V_CH_DIR 0x01
483 #define V_CH_SEL 0x02
484 #define V_ROUTING 0x40
487 #define V_HDLC_TRP 0x02
488 #define V_TRP_IRQ 0x04
489 #define V_DATA_FLOW 0x20
491 #define V_BIT_CNT 0x01
492 #define V_START_BIT 0x08
493 #define V_LOOP_FIFO 0x40
494 #define V_INV_DATA 0x80
496 #define V_CH_DIR0 0x01
497 #define V_CH_NUM0 0x02
499 #define V_NEXT_FIFO_DIR 0x01
500 #define V_NEXT_FIFO_NUM 0x02
501 #define V_SEQ_END 0x40
503 /* chapter 4: FIFO handling and HDLC controller */
507 #define V_RES_LOST 0x04
509 /* chapter 5: S/T interface */
511 #define V_SCI_MSK_ST0 0x01
512 #define V_SCI_MSK_ST1 0x02
513 #define V_SCI_MSK_ST2 0x04
514 #define V_SCI_MSK_ST3 0x08
515 #define V_SCI_MSK_ST4 0x10
516 #define V_SCI_MSK_ST5 0x20
517 #define V_SCI_MSK_ST6 0x40
518 #define V_SCI_MSK_ST7 0x80
520 #define V_ST_SEL 0x01
521 #define V_MULT_ST 0x08
523 #define V_SYNC_SEL 0x01
524 #define V_AUTO_SYNC 0x08
526 #define V_ST_SET_STA 0x01
527 #define V_ST_LD_STA 0x10
528 #define V_ST_ACT 0x20
529 #define V_SET_G2_G3 0x80
534 #define V_D_PRIO 0x08
538 #define V_ST_STOP 0x80
540 #define V_G2_G3_EN 0x01
542 #define V_E_IGNO 0x08
544 #define V_B12_SWAP 0x80
546 #define V_B1_RX_EN 0x01
547 #define V_B2_RX_EN 0x02
548 #define V_ST_TRIS 0x40
550 #define V_ST_CK_DLY 0x01
551 #define V_ST_SMPL 0x10
553 #define V_ST_D_TX 0x40
555 #define V_SCI_ST0 0x01
556 #define V_SCI_ST1 0x02
557 #define V_SCI_ST2 0x04
558 #define V_SCI_ST3 0x08
559 #define V_SCI_ST4 0x10
560 #define V_SCI_ST5 0x20
561 #define V_SCI_ST6 0x40
562 #define V_SCI_ST7 0x80
564 #define V_ST_STA 0x01
565 #define V_FR_SYNC_ST 0x10
566 #define V_TI2_EXP 0x20
571 #define V_MF_RX_RDY 0x10
572 #define V_MF_TX_RDY 0x80
574 #define V_ST_D_RX 0x40
576 #define V_ST_E_RX 0x40
578 /* chapter 5: E1 interface */
581 #define V_E1_SET_STA 0x01
582 #define V_E1_LD_STA 0x10
584 #define V_RX_CODE 0x01
585 #define V_RX_FBAUD 0x04
586 #define V_RX_CMI 0x08
587 #define V_RX_INV_CMI 0x10
588 #define V_RX_INV_CLK 0x20
589 #define V_RX_INV_DATA 0x40
590 #define V_AIS_ITU 0x80
592 #define V_NO_INSYNC 0x01
593 #define V_AUTO_RESYNC 0x02
594 #define V_AUTO_RECO 0x04
595 #define V_SWORD_COND 0x08
596 #define V_SYNC_LOSS 0x10
597 #define V_XCRC_SYNC 0x20
598 #define V_MF_RESYNC 0x40
599 #define V_RESYNC 0x80
602 #define V_RX_MF_SYNC 0x02
603 #define V_RX_SL0_RAM 0x04
604 #define V_ERR_SIM 0x20
605 #define V_RES_NMF 0x40
607 #define V_TX_CODE 0x01
608 #define V_TX_FBAUD 0x04
609 #define V_TX_CMI_CODE 0x08
610 #define V_TX_INV_CMI_CODE 0x10
611 #define V_TX_INV_CLK 0x20
612 #define V_TX_INV_DATA 0x40
613 #define V_OUT_EN 0x80
615 #define V_INV_CLK 0x01
616 #define V_EXCHG_DATA_LI 0x02
617 #define V_AIS_OUT 0x04
620 #define V_AUTO_ERR_RES 0x80
622 #define V_TRP_FAS 0x01
623 #define V_TRP_NFAS 0x02
624 #define V_TRP_RAL 0x04
625 #define V_TRP_SA 0x08
627 #define V_TX_FAS 0x01
628 #define V_TX_NFAS 0x02
629 #define V_TX_RAL 0x04
633 #define V_TRP_SL0 0x02
634 #define V_TX_SL0_RAM 0x04
637 #define V_XS12_ON 0x40
638 #define V_XS15_ON 0x80
641 #define V_RX_INIT 0x04
643 #define V_SYNC_E1_RX 0x01
644 #define V_IPATS0 0x20
645 #define V_IPATS1 0x40
646 #define V_IPATS2 0x80
649 #define V_TX_INIT 0x04
651 #define V_EXT_CLK_SYNC 0x01
652 #define V_SYNC_OFFS 0x02
653 #define V_PCM_SYNC 0x04
654 #define V_NEG_CLK 0x08
657 #define V_JATT_AUTO_DEL 0x20
658 #define V_JATT_AUTO 0x40
660 #define V_JATT_OFF 0x80
662 #define V_E1_STA 0x01
663 #define V_ALT_FR_RX 0x40
664 #define V_ALT_FR_TX 0x80
666 #define V_RX_STA 0x01
667 #define V_FR_SYNC_E1 0x04
668 #define V_SIG_LOS 0x08
669 #define V_MFA_STA 0x10
671 #define V_NO_MF_SYNC 0x80
673 #define V_SI_FAS 0x01
674 #define V_SI_NFAS 0x02
676 #define V_CRC_OK 0x08
682 #define V_SLIP_RX 0x01
683 #define V_FOSLIP_RX 0x08
684 #define V_SLIP_TX 0x10
685 #define V_FOSLIP_TX 0x80
687 /* chapter 6: PCM interface */
689 #define V_PCM_MD 0x01
690 #define V_C4_POL 0x02
691 #define V_F0_NEG 0x04
692 #define V_F0_LEN 0x08
693 #define V_PCM_ADDR 0x10
695 #define V_SL_SEL0 0x01
696 #define V_SH_SEL0 0x80
698 #define V_SL_SEL1 0x01
699 #define V_SH_SEL1 0x80
701 #define V_SL_SEL2 0x01
702 #define V_SH_SEL2 0x80
704 #define V_SL_SEL3 0x01
705 #define V_SH_SEL3 0x80
707 #define V_SL_SEL4 0x01
708 #define V_SH_SEL4 0x80
710 #define V_SL_SEL5 0x01
711 #define V_SH_SEL5 0x80
713 #define V_SL_SEL6 0x01
714 #define V_SH_SEL6 0x80
716 #define V_SL_SEL7 0x01
717 #define V_SH_SEL7 0x80
719 #define V_ODEC_CON 0x01
720 #define V_PLL_ADJ 0x04
721 #define V_PCM_DR 0x10
722 #define V_PCM_LOOP 0x40
724 #define V_SYNC_PLL 0x02
725 #define V_SYNC_SRC 0x04
726 #define V_SYNC_OUT 0x08
727 #define V_ICR_FR_TIME 0x40
728 #define V_EN_PLL 0x80
730 /* chapter 7: pulse width modulation */
732 #define V_EXT_IRQ_EN 0x08
733 #define V_PWM0_MD 0x10
734 #define V_PWM1_MD 0x40
736 /* chapter 8: multiparty audio conferences */
738 #define V_CONF_EN 0x01
741 #define V_CONF_NUM 0x01
742 #define V_NOISE_SUPPR 0x08
743 #define V_ATT_LEV 0x20
744 #define V_CONF_SL 0x80
746 #define V_CONF_OFLOW0 0x01
747 #define V_CONF_OFLOW1 0x02
748 #define V_CONF_OFLOW2 0x04
749 #define V_CONF_OFLOW3 0x08
750 #define V_CONF_OFLOW4 0x10
751 #define V_CONF_OFLOW5 0x20
752 #define V_CONF_OFLOW6 0x40
753 #define V_CONF_OFLOW7 0x80
755 /* chapter 9: DTMF contoller */
757 #define V_DTMF_EN 0x01
758 #define V_HARM_SEL 0x02
759 #define V_DTMF_RX_CH 0x04
760 #define V_DTMF_STOP 0x08
761 #define V_CHBL_SEL 0x10
762 #define V_RST_DTMF 0x40
763 #define V_ULAW_SEL 0x80
765 /* chapter 10: BERT */
767 #define V_PAT_SEQ 0x01
768 #define V_BERT_ERR 0x08
769 #define V_AUTO_WD_RES 0x20
770 #define V_WD_RES 0x80
772 #define V_BERT_SYNC_SRC 0x01
773 #define V_BERT_SYNC 0x10
774 #define V_BERT_INV_DATA 0x20
776 /* chapter 11: auxiliary interface */
778 #define V_BRG_EN 0x01
779 #define V_BRG_MD 0x02
780 #define V_PCM_CLK 0x20
781 #define V_ADDR_WRDLY 0x40
783 #define V_BRG_CS 0x01
784 #define V_BRG_ADDR 0x08
785 #define V_BRG_CS_SRC 0x80
787 #define V_BRG_MD0 0x01
788 #define V_BRG_MD1 0x02
789 #define V_BRG_MD2 0x04
790 #define V_BRG_MD3 0x08
791 #define V_BRG_MD4 0x10
792 #define V_BRG_MD5 0x20
793 #define V_BRG_MD6 0x40
794 #define V_BRG_MD7 0x80
796 #define V_BRG_TIM0_IDLE 0x01
797 #define V_BRG_TIM0_CLK 0x10
799 #define V_BRG_TIM1_IDLE 0x01
800 #define V_BRG_TIM1_CLK 0x10
802 #define V_BRG_TIM2_IDLE 0x01
803 #define V_BRG_TIM2_CLK 0x10
805 #define V_BRG_TIM3_IDLE 0x01
806 #define V_BRG_TIM3_CLK 0x10
807 /* R_BRG_TIM_SEL01 */
808 #define V_BRG_WR_SEL0 0x01
809 #define V_BRG_RD_SEL0 0x04
810 #define V_BRG_WR_SEL1 0x10
811 #define V_BRG_RD_SEL1 0x40
812 /* R_BRG_TIM_SEL23 */
813 #define V_BRG_WR_SEL2 0x01
814 #define V_BRG_RD_SEL2 0x04
815 #define V_BRG_WR_SEL3 0x10
816 #define V_BRG_RD_SEL3 0x40
817 /* R_BRG_TIM_SEL45 */
818 #define V_BRG_WR_SEL4 0x01
819 #define V_BRG_RD_SEL4 0x04
820 #define V_BRG_WR_SEL5 0x10
821 #define V_BRG_RD_SEL5 0x40
822 /* R_BRG_TIM_SEL67 */
823 #define V_BRG_WR_SEL6 0x01
824 #define V_BRG_RD_SEL6 0x04
825 #define V_BRG_WR_SEL7 0x10
826 #define V_BRG_RD_SEL7 0x40
828 /* chapter 12: clock, reset, interrupt, timer and watchdog */
830 #define V_STA_IRQMSK 0x01
831 #define V_TI_IRQMSK 0x02
832 #define V_PROC_IRQMSK 0x04
833 #define V_DTMF_IRQMSK 0x08
834 #define V_IRQ1S_MSK 0x10
835 #define V_SA6_IRQMSK 0x20
836 #define V_RX_EOMF_MSK 0x40
837 #define V_TX_EOMF_MSK 0x80
839 #define V_FIFO_IRQ 0x01
840 #define V_GLOB_IRQ_EN 0x08
841 #define V_IRQ_POL 0x10
847 #define V_BERT_EN 0x02
848 #define V_MIX_IRQ 0x04
850 #define V_IRQ_FIFO_BL0 0x01
851 #define V_IRQ_FIFO_BL1 0x02
852 #define V_IRQ_FIFO_BL2 0x04
853 #define V_IRQ_FIFO_BL3 0x08
854 #define V_IRQ_FIFO_BL4 0x10
855 #define V_IRQ_FIFO_BL5 0x20
856 #define V_IRQ_FIFO_BL6 0x40
857 #define V_IRQ_FIFO_BL7 0x80
859 #define V_STA_IRQ 0x01
860 #define V_TI_IRQ 0x02
861 #define V_IRQ_PROC 0x04
862 #define V_DTMF_IRQ 0x08
864 #define V_SA6_IRQ 0x20
865 #define V_RX_EOMF 0x40
866 #define V_TX_EOMF 0x80
870 #define V_DTMF_STA 0x04
871 #define V_LOST_STA 0x08
872 #define V_SYNC_IN 0x10
873 #define V_EXT_IRQSTA 0x20
874 #define V_MISC_IRQSTA 0x40
875 #define V_FR_IRQSTA 0x80
877 #define V_IRQ_FIFO0_TX 0x01
878 #define V_IRQ_FIFO0_RX 0x02
879 #define V_IRQ_FIFO1_TX 0x04
880 #define V_IRQ_FIFO1_RX 0x08
881 #define V_IRQ_FIFO2_TX 0x10
882 #define V_IRQ_FIFO2_RX 0x20
883 #define V_IRQ_FIFO3_TX 0x40
884 #define V_IRQ_FIFO3_RX 0x80
886 #define V_IRQ_FIFO4_TX 0x01
887 #define V_IRQ_FIFO4_RX 0x02
888 #define V_IRQ_FIFO5_TX 0x04
889 #define V_IRQ_FIFO5_RX 0x08
890 #define V_IRQ_FIFO6_TX 0x10
891 #define V_IRQ_FIFO6_RX 0x20
892 #define V_IRQ_FIFO7_TX 0x40
893 #define V_IRQ_FIFO7_RX 0x80
895 #define V_IRQ_FIFO8_TX 0x01
896 #define V_IRQ_FIFO8_RX 0x02
897 #define V_IRQ_FIFO9_TX 0x04
898 #define V_IRQ_FIFO9_RX 0x08
899 #define V_IRQ_FIFO10_TX 0x10
900 #define V_IRQ_FIFO10_RX 0x20
901 #define V_IRQ_FIFO11_TX 0x40
902 #define V_IRQ_FIFO11_RX 0x80
904 #define V_IRQ_FIFO12_TX 0x01
905 #define V_IRQ_FIFO12_RX 0x02
906 #define V_IRQ_FIFO13_TX 0x04
907 #define V_IRQ_FIFO13_RX 0x08
908 #define V_IRQ_FIFO14_TX 0x10
909 #define V_IRQ_FIFO14_RX 0x20
910 #define V_IRQ_FIFO15_TX 0x40
911 #define V_IRQ_FIFO15_RX 0x80
913 #define V_IRQ_FIFO16_TX 0x01
914 #define V_IRQ_FIFO16_RX 0x02
915 #define V_IRQ_FIFO17_TX 0x04
916 #define V_IRQ_FIFO17_RX 0x08
917 #define V_IRQ_FIFO18_TX 0x10
918 #define V_IRQ_FIFO18_RX 0x20
919 #define V_IRQ_FIFO19_TX 0x40
920 #define V_IRQ_FIFO19_RX 0x80
922 #define V_IRQ_FIFO20_TX 0x01
923 #define V_IRQ_FIFO20_RX 0x02
924 #define V_IRQ_FIFO21_TX 0x04
925 #define V_IRQ_FIFO21_RX 0x08
926 #define V_IRQ_FIFO22_TX 0x10
927 #define V_IRQ_FIFO22_RX 0x20
928 #define V_IRQ_FIFO23_TX 0x40
929 #define V_IRQ_FIFO23_RX 0x80
931 #define V_IRQ_FIFO24_TX 0x01
932 #define V_IRQ_FIFO24_RX 0x02
933 #define V_IRQ_FIFO25_TX 0x04
934 #define V_IRQ_FIFO25_RX 0x08
935 #define V_IRQ_FIFO26_TX 0x10
936 #define V_IRQ_FIFO26_RX 0x20
937 #define V_IRQ_FIFO27_TX 0x40
938 #define V_IRQ_FIFO27_RX 0x80
940 #define V_IRQ_FIFO28_TX 0x01
941 #define V_IRQ_FIFO28_RX 0x02
942 #define V_IRQ_FIFO29_TX 0x04
943 #define V_IRQ_FIFO29_RX 0x08
944 #define V_IRQ_FIFO30_TX 0x10
945 #define V_IRQ_FIFO30_RX 0x20
946 #define V_IRQ_FIFO31_TX 0x40
947 #define V_IRQ_FIFO31_RX 0x80
949 /* chapter 13: general purpose I/O pins (GPIO) and input pins (GPI) */
951 #define V_GPIO_OUT0 0x01
952 #define V_GPIO_OUT1 0x02
953 #define V_GPIO_OUT2 0x04
954 #define V_GPIO_OUT3 0x08
955 #define V_GPIO_OUT4 0x10
956 #define V_GPIO_OUT5 0x20
957 #define V_GPIO_OUT6 0x40
958 #define V_GPIO_OUT7 0x80
960 #define V_GPIO_OUT8 0x01
961 #define V_GPIO_OUT9 0x02
962 #define V_GPIO_OUT10 0x04
963 #define V_GPIO_OUT11 0x08
964 #define V_GPIO_OUT12 0x10
965 #define V_GPIO_OUT13 0x20
966 #define V_GPIO_OUT14 0x40
967 #define V_GPIO_OUT15 0x80
969 #define V_GPIO_EN0 0x01
970 #define V_GPIO_EN1 0x02
971 #define V_GPIO_EN2 0x04
972 #define V_GPIO_EN3 0x08
973 #define V_GPIO_EN4 0x10
974 #define V_GPIO_EN5 0x20
975 #define V_GPIO_EN6 0x40
976 #define V_GPIO_EN7 0x80
978 #define V_GPIO_EN8 0x01
979 #define V_GPIO_EN9 0x02
980 #define V_GPIO_EN10 0x04
981 #define V_GPIO_EN11 0x08
982 #define V_GPIO_EN12 0x10
983 #define V_GPIO_EN13 0x20
984 #define V_GPIO_EN14 0x40
985 #define V_GPIO_EN15 0x80
987 #define V_GPIO_SEL0 0x01
988 #define V_GPIO_SEL1 0x02
989 #define V_GPIO_SEL2 0x04
990 #define V_GPIO_SEL3 0x08
991 #define V_GPIO_SEL4 0x10
992 #define V_GPIO_SEL5 0x20
993 #define V_GPIO_SEL6 0x40
994 #define V_GPIO_SEL7 0x80
996 #define V_GPIO_IN0 0x01
997 #define V_GPIO_IN1 0x02
998 #define V_GPIO_IN2 0x04
999 #define V_GPIO_IN3 0x08
1000 #define V_GPIO_IN4 0x10
1001 #define V_GPIO_IN5 0x20
1002 #define V_GPIO_IN6 0x40
1003 #define V_GPIO_IN7 0x80
1005 #define V_GPIO_IN8 0x01
1006 #define V_GPIO_IN9 0x02
1007 #define V_GPIO_IN10 0x04
1008 #define V_GPIO_IN11 0x08
1009 #define V_GPIO_IN12 0x10
1010 #define V_GPIO_IN13 0x20
1011 #define V_GPIO_IN14 0x40
1012 #define V_GPIO_IN15 0x80
1014 #define V_GPI_IN0 0x01
1015 #define V_GPI_IN1 0x02
1016 #define V_GPI_IN2 0x04
1017 #define V_GPI_IN3 0x08
1018 #define V_GPI_IN4 0x10
1019 #define V_GPI_IN5 0x20
1020 #define V_GPI_IN6 0x40
1021 #define V_GPI_IN7 0x80
1023 #define V_GPI_IN8 0x01
1024 #define V_GPI_IN9 0x02
1025 #define V_GPI_IN10 0x04
1026 #define V_GPI_IN11 0x08
1027 #define V_GPI_IN12 0x10
1028 #define V_GPI_IN13 0x20
1029 #define V_GPI_IN14 0x40
1030 #define V_GPI_IN15 0x80
1032 #define V_GPI_IN16 0x01
1033 #define V_GPI_IN17 0x02
1034 #define V_GPI_IN18 0x04
1035 #define V_GPI_IN19 0x08
1036 #define V_GPI_IN20 0x10
1037 #define V_GPI_IN21 0x20
1038 #define V_GPI_IN22 0x40
1039 #define V_GPI_IN23 0x80
1041 #define V_GPI_IN24 0x01
1042 #define V_GPI_IN25 0x02
1043 #define V_GPI_IN26 0x04
1044 #define V_GPI_IN27 0x08
1045 #define V_GPI_IN28 0x10
1046 #define V_GPI_IN29 0x20
1047 #define V_GPI_IN30 0x40
1048 #define V_GPI_IN31 0x80
1050 /* map of all registers, used for debugging */
1052 #ifdef HFC_REGISTER_DEBUG
1053 struct hfc_register_names {
1056 } hfc_register_names[] = {
1057 /* write registers */
1060 {"R_BRG_PCM_CFG ", 0x02},
1061 {"R_RAM_ADDR0", 0x08},
1062 {"R_RAM_ADDR1", 0x09},
1063 {"R_RAM_ADDR2", 0x0A},
1064 {"R_FIRST_FIFO", 0x0B},
1066 {"R_FIFO_MD", 0x0D},
1067 {"R_INC_RES_FIFO", 0x0E},
1068 {"R_FIFO / R_FSM_IDX", 0x0F},
1070 {"R_IRQMSK_MISC", 0x11},
1071 {"R_SCI_MSK", 0x12},
1072 {"R_IRQ_CTRL", 0x13},
1073 {"R_PCM_MD0", 0x14},
1076 {"R_ST_SYNC", 0x17},
1077 {"R_CONF_EN", 0x18},
1079 {"R_BERT_WD_MD", 0x1B},
1082 {"R_E1_XX_STA", 0x20},
1093 {"R_JATT_ATT", 0x2F},
1094 {"A_ST_xx_STA/R_RX_OFF", 0x30},
1095 {"A_ST_CTRL0/R_SYNC_OUT", 0x31},
1096 {"A_ST_CTRL1", 0x32},
1097 {"A_ST_CTRL2", 0x33},
1098 {"A_ST_SQ_WR", 0x34},
1100 {"R_SYNC_CTRL", 0x35},
1101 {"A_ST_CLK_DLY", 0x37},
1104 {"A_ST_B1_TX", 0x3C},
1105 {"A_ST_B2_TX", 0x3D},
1106 {"A_ST_D_TX", 0x3E},
1107 {"R_GPIO_OUT0", 0x40},
1108 {"R_GPIO_OUT1", 0x41},
1109 {"R_GPIO_EN0", 0x42},
1110 {"R_GPIO_EN1", 0x43},
1111 {"R_GPIO_SEL", 0x44},
1112 {"R_BRG_CTRL", 0x45},
1115 {"R_BRG_TIM0", 0x48},
1116 {"R_BRG_TIM1", 0x49},
1117 {"R_BRG_TIM2", 0x4A},
1118 {"R_BRG_TIM3", 0x4B},
1119 {"R_BRG_TIM_SEL01", 0x4C},
1120 {"R_BRG_TIM_SEL23", 0x4D},
1121 {"R_BRG_TIM_SEL45", 0x4E},
1122 {"R_BRG_TIM_SEL67", 0x4F},
1123 {"A_FIFO_DATA0-2", 0x80},
1124 {"A_FIFO_DATA0-2_NOINC", 0x84},
1125 {"R_RAM_DATA", 0xC0},
1129 {"A_CON_HDLC", 0xFA},
1130 {"A_SUBCH_CFG", 0xFB},
1131 {"A_CHANNEL", 0xFC},
1132 {"A_FIFO_SEQ", 0xFD},
1133 {"A_IRQ_MSK", 0xFF},
1136 /* read registers */
1143 {"R_IRQ_OVIEW", 0x10},
1144 {"R_IRQ_MISC", 0x11},
1145 {"R_IRQ_STATECH", 0x12},
1146 {"R_CONF_OFLOW", 0x14},
1147 {"R_RAM_USE", 0x15},
1148 {"R_CHIP_ID", 0x16},
1149 {"R_BERT_STA", 0x17},
1150 {"R_F0_CNTL", 0x18},
1151 {"R_F0_CNTH", 0x19},
1152 {"R_BERT_ECL", 0x1A},
1153 {"R_BERT_ECH", 0x1B},
1155 {"R_CHIP_RV", 0x1F},
1157 {"R_SYNC_STA", 0x24},
1158 {"R_RX_SL0_0", 0x25},
1159 {"R_RX_SL0_1", 0x26},
1160 {"R_RX_SL0_2", 0x27},
1161 {"R_JATT_DIR", 0x2b},
1163 {"A_ST_RD_STA", 0x30},
1164 {"R_FAS_ECL", 0x30},
1165 {"R_FAS_ECH", 0x31},
1166 {"R_VIO_ECL", 0x32},
1167 {"R_VIO_ECH", 0x33},
1168 {"R_CRC_ECL / A_ST_SQ_RD", 0x34},
1169 {"R_CRC_ECH", 0x35},
1172 {"R_SA6_SA13_ECL", 0x38},
1173 {"R_SA6_SA13_ECH", 0x39},
1174 {"R_SA6_SA23_ECL", 0x3A},
1175 {"R_SA6_SA23_ECH", 0x3B},
1176 {"A_ST_B1_RX", 0x3C},
1177 {"A_ST_B2_RX", 0x3D},
1178 {"A_ST_D_RX", 0x3E},
1179 {"A_ST_E_RX", 0x3F},
1180 {"R_GPIO_IN0", 0x40},
1181 {"R_GPIO_IN1", 0x41},
1182 {"R_GPI_IN0", 0x44},
1183 {"R_GPI_IN1", 0x45},
1184 {"R_GPI_IN2", 0x46},
1185 {"R_GPI_IN3", 0x47},
1186 {"A_FIFO_DATA0-2", 0x80},
1187 {"A_FIFO_DATA0-2_NOINC", 0x84},
1188 {"R_INT_DATA", 0x88},
1189 {"R_RAM_DATA", 0xC0},
1190 {"R_IRQ_FIFO_BL0", 0xC8},
1191 {"R_IRQ_FIFO_BL1", 0xC9},
1192 {"R_IRQ_FIFO_BL2", 0xCA},
1193 {"R_IRQ_FIFO_BL3", 0xCB},
1194 {"R_IRQ_FIFO_BL4", 0xCC},
1195 {"R_IRQ_FIFO_BL5", 0xCD},
1196 {"R_IRQ_FIFO_BL6", 0xCE},
1197 {"R_IRQ_FIFO_BL7", 0xCF},
1199 #endif /* HFC_REGISTER_DEBUG */