2 * hfcmulti.c low level driver for hfc-4s/hfc-8s/hfc-e1 based cards
4 * Author Andreas Eversberg (jolly@eversberg.eu)
5 * ported to mqueue mechanism:
6 * Peter Sprenger (sprengermoving-bytes.de)
8 * inspired by existing hfc-pci driver:
9 * Copyright 1999 by Werner Cornelius (werner@isdn-development.de)
10 * Copyright 2008 by Karsten Keil (kkeil@suse.de)
11 * Copyright 2008 by Andreas Eversberg (jolly@eversberg.eu)
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2, or (at your option)
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
28 * Thanks to Cologne Chip AG for this great controller!
34 * By default (0), the card is automatically detected.
35 * Or use the following combinations:
36 * Bit 0-7 = 0x00001 = HFC-E1 (1 port)
37 * or Bit 0-7 = 0x00004 = HFC-4S (4 ports)
38 * or Bit 0-7 = 0x00008 = HFC-8S (8 ports)
39 * Bit 8 = 0x00100 = uLaw (instead of aLaw)
40 * Bit 9 = 0x00200 = Disable DTMF detect on all B-channels via hardware
42 * Bit 11 = 0x00800 = Force PCM bus into slave mode. (otherwhise auto)
43 * or Bit 12 = 0x01000 = Force PCM bus into master mode. (otherwhise auto)
45 * Bit 14 = 0x04000 = Use external ram (128K)
46 * Bit 15 = 0x08000 = Use external ram (512K)
47 * Bit 16 = 0x10000 = Use 64 timeslots instead of 32
48 * or Bit 17 = 0x20000 = Use 128 timeslots instead of anything else
50 * Bit 19 = 0x80000 = Send the Watchdog a Signal (Dual E1 with Watchdog)
51 * (all other bits are reserved and shall be 0)
52 * example: 0x20204 one HFC-4S with dtmf detection and 128 timeslots on PCM
55 * port: (optional or required for all ports on all installed cards)
56 * HFC-4S/HFC-8S only bits:
57 * Bit 0 = 0x001 = Use master clock for this S/T interface
58 * (ony once per chip).
59 * Bit 1 = 0x002 = transmitter line setup (non capacitive mode)
60 * Don't use this unless you know what you are doing!
61 * Bit 2 = 0x004 = Disable E-channel. (No E-channel processing)
62 * example: 0x0001,0x0000,0x0000,0x0000 one HFC-4S with master clock
63 * received from port 1
66 * Bit 0 = 0x0001 = interface: 0=copper, 1=optical
67 * Bit 1 = 0x0002 = reserved (later for 32 B-channels transparent mode)
68 * Bit 2 = 0x0004 = Report LOS
69 * Bit 3 = 0x0008 = Report AIS
70 * Bit 4 = 0x0010 = Report SLIP
71 * Bit 5 = 0x0020 = Report RDI
72 * Bit 8 = 0x0100 = Turn off CRC-4 Multiframe Mode, use double frame
74 * Bit 9 = 0x0200 = Force get clock from interface, even in NT mode.
75 * or Bit 10 = 0x0400 = Force put clock to interface, even in TE mode.
76 * Bit 11 = 0x0800 = Use direct RX clock for PCM sync rather than PLL.
78 * Bit 12-13 = 0xX000 = elastic jitter buffer (1-3), Set both bits to 0
80 * (all other bits are reserved and shall be 0)
83 * NOTE: only one debug value must be given for all cards
84 * enable debugging (see hfc_multi.h for debug options)
87 * NOTE: only one poll value must be given for all cards
88 * Give the number of samples for each fifo process.
89 * By default 128 is used. Decrease to reduce delay, increase to
90 * reduce cpu load. If unsure, don't mess with it!
91 * Valid is 8, 16, 32, 64, 128, 256.
94 * NOTE: only one pcm value must be given for every card.
95 * The PCM bus id tells the mISDNdsp module about the connected PCM bus.
96 * By default (0), the PCM bus id is 100 for the card that is PCM master.
97 * If multiple cards are PCM master (because they are not interconnected),
98 * each card with PCM master will have increasing PCM id.
99 * All PCM busses with the same ID are expected to be connected and have
100 * common time slots slots.
101 * Only one chip of the PCM bus must be master, the others slave.
102 * -1 means no support of PCM bus not even.
103 * Omit this value, if all cards are interconnected or none is connected.
104 * If unsure, don't give this parameter.
107 * NOTE: only one dslot value must be given for every card.
108 * Also this value must be given for non-E1 cards. If omitted, the E1
109 * card has D-channel on time slot 16, which is default.
110 * If 1..15 or 17..31, an alternate time slot is used for D-channel.
111 * In this case, the application must be able to handle this.
112 * If -1 is given, the D-channel is disabled and all 31 slots can be used
113 * for B-channel. (only for specific applications)
114 * If you don't know how to use it, you don't need it!
117 * NOTE: only one mode value must be given for every card.
118 * -> See hfc_multi.h for HFC_IO_MODE_* values
119 * By default, the IO mode is pci memory IO (MEMIO).
120 * Some cards require specific IO mode, so it cannot be changed.
121 * It may be useful to set IO mode to register io (REGIO) to solve
122 * PCI bridge problems.
123 * If unsure, don't give this parameter.
126 * NOTE: only one clockdelay_nt value must be given once for all cards.
127 * Give the value of the clock control register (A_ST_CLK_DLY)
128 * of the S/T interfaces in NT mode.
129 * This register is needed for the TBR3 certification, so don't change it.
132 * NOTE: only one clockdelay_te value must be given once
133 * Give the value of the clock control register (A_ST_CLK_DLY)
134 * of the S/T interfaces in TE mode.
135 * This register is needed for the TBR3 certification, so don't change it.
138 * NOTE: only one clock value must be given once
139 * Selects interface with clock source for mISDN and applications.
140 * Set to card number starting with 1. Set to -1 to disable.
141 * By default, the first card is used as clock source.
144 * NOTE: only one hwid value must be given once
145 * Enable special embedded devices with XHFC controllers.
149 * debug register access (never use this, it will flood your system log)
150 * #define HFC_REGISTER_DEBUG
153 #define HFC_MULTI_VERSION "2.03"
155 #include <linux/interrupt.h>
156 #include <linux/module.h>
157 #include <linux/slab.h>
158 #include <linux/pci.h>
159 #include <linux/delay.h>
160 #include <linux/mISDNhw.h>
161 #include <linux/mISDNdsp.h>
164 #define IRQCOUNT_DEBUG
168 #include "hfc_multi.h"
174 #define MAX_PORTS (8 * MAX_CARDS)
176 static LIST_HEAD(HFClist);
177 static spinlock_t HFClock; /* global hfc list lock */
179 static void ph_state_change(struct dchannel *);
181 static struct hfc_multi *syncmaster;
182 static int plxsd_master; /* if we have a master card (yet) */
183 static spinlock_t plx_lock; /* may not acquire other lock inside */
189 static int poll_timer = 6; /* default = 128 samples = 16ms */
190 /* number of POLL_TIMER interrupts for G2 timeout (ca 1s) */
191 static int nt_t1_count[] = { 3840, 1920, 960, 480, 240, 120, 60, 30 };
192 #define CLKDEL_TE 0x0f /* CLKDEL in TE mode */
193 #define CLKDEL_NT 0x6c /* CLKDEL in NT mode
194 (0x60 MUST be included!) */
196 #define DIP_4S 0x1 /* DIP Switches for Beronet 1S/2S/4S cards */
197 #define DIP_8S 0x2 /* DIP Switches for Beronet 8S+ cards */
198 #define DIP_E1 0x3 /* DIP Switches for Beronet E1 cards */
204 static uint type[MAX_CARDS];
205 static int pcm[MAX_CARDS];
206 static int dslot[MAX_CARDS];
207 static uint iomode[MAX_CARDS];
208 static uint port[MAX_PORTS];
213 static uint clockdelay_te = CLKDEL_TE;
214 static uint clockdelay_nt = CLKDEL_NT;
216 #define HWID_MINIP4 1
217 #define HWID_MINIP8 2
218 #define HWID_MINIP16 3
219 static uint hwid = HWID_NONE;
221 static int HFC_cnt, Port_cnt, PCM_cnt = 99;
223 MODULE_AUTHOR("Andreas Eversberg");
224 MODULE_LICENSE("GPL");
225 MODULE_VERSION(HFC_MULTI_VERSION);
226 module_param(debug, uint, S_IRUGO | S_IWUSR);
227 module_param(poll, uint, S_IRUGO | S_IWUSR);
228 module_param(clock, int, S_IRUGO | S_IWUSR);
229 module_param(timer, uint, S_IRUGO | S_IWUSR);
230 module_param(clockdelay_te, uint, S_IRUGO | S_IWUSR);
231 module_param(clockdelay_nt, uint, S_IRUGO | S_IWUSR);
232 module_param_array(type, uint, NULL, S_IRUGO | S_IWUSR);
233 module_param_array(pcm, int, NULL, S_IRUGO | S_IWUSR);
234 module_param_array(dslot, int, NULL, S_IRUGO | S_IWUSR);
235 module_param_array(iomode, uint, NULL, S_IRUGO | S_IWUSR);
236 module_param_array(port, uint, NULL, S_IRUGO | S_IWUSR);
237 module_param(hwid, uint, S_IRUGO | S_IWUSR); /* The hardware ID */
239 #ifdef HFC_REGISTER_DEBUG
240 #define HFC_outb(hc, reg, val) \
241 (hc->HFC_outb(hc, reg, val, __func__, __LINE__))
242 #define HFC_outb_nodebug(hc, reg, val) \
243 (hc->HFC_outb_nodebug(hc, reg, val, __func__, __LINE__))
244 #define HFC_inb(hc, reg) \
245 (hc->HFC_inb(hc, reg, __func__, __LINE__))
246 #define HFC_inb_nodebug(hc, reg) \
247 (hc->HFC_inb_nodebug(hc, reg, __func__, __LINE__))
248 #define HFC_inw(hc, reg) \
249 (hc->HFC_inw(hc, reg, __func__, __LINE__))
250 #define HFC_inw_nodebug(hc, reg) \
251 (hc->HFC_inw_nodebug(hc, reg, __func__, __LINE__))
252 #define HFC_wait(hc) \
253 (hc->HFC_wait(hc, __func__, __LINE__))
254 #define HFC_wait_nodebug(hc) \
255 (hc->HFC_wait_nodebug(hc, __func__, __LINE__))
257 #define HFC_outb(hc, reg, val) (hc->HFC_outb(hc, reg, val))
258 #define HFC_outb_nodebug(hc, reg, val) (hc->HFC_outb_nodebug(hc, reg, val))
259 #define HFC_inb(hc, reg) (hc->HFC_inb(hc, reg))
260 #define HFC_inb_nodebug(hc, reg) (hc->HFC_inb_nodebug(hc, reg))
261 #define HFC_inw(hc, reg) (hc->HFC_inw(hc, reg))
262 #define HFC_inw_nodebug(hc, reg) (hc->HFC_inw_nodebug(hc, reg))
263 #define HFC_wait(hc) (hc->HFC_wait(hc))
264 #define HFC_wait_nodebug(hc) (hc->HFC_wait_nodebug(hc))
267 #ifdef CONFIG_MISDN_HFCMULTI_8xx
268 #include "hfc_multi_8xx.h"
271 /* HFC_IO_MODE_PCIMEM */
273 #ifdef HFC_REGISTER_DEBUG
274 HFC_outb_pcimem(struct hfc_multi *hc, u_char reg, u_char val,
275 const char *function, int line)
277 HFC_outb_pcimem(struct hfc_multi *hc, u_char reg, u_char val)
280 writeb(val, hc->pci_membase + reg);
283 #ifdef HFC_REGISTER_DEBUG
284 HFC_inb_pcimem(struct hfc_multi *hc, u_char reg, const char *function, int line)
286 HFC_inb_pcimem(struct hfc_multi *hc, u_char reg)
289 return readb(hc->pci_membase + reg);
292 #ifdef HFC_REGISTER_DEBUG
293 HFC_inw_pcimem(struct hfc_multi *hc, u_char reg, const char *function, int line)
295 HFC_inw_pcimem(struct hfc_multi *hc, u_char reg)
298 return readw(hc->pci_membase + reg);
301 #ifdef HFC_REGISTER_DEBUG
302 HFC_wait_pcimem(struct hfc_multi *hc, const char *function, int line)
304 HFC_wait_pcimem(struct hfc_multi *hc)
307 while (readb(hc->pci_membase + R_STATUS) & V_BUSY)
311 /* HFC_IO_MODE_REGIO */
313 #ifdef HFC_REGISTER_DEBUG
314 HFC_outb_regio(struct hfc_multi *hc, u_char reg, u_char val,
315 const char *function, int line)
317 HFC_outb_regio(struct hfc_multi *hc, u_char reg, u_char val)
320 outb(reg, hc->pci_iobase + 4);
321 outb(val, hc->pci_iobase);
324 #ifdef HFC_REGISTER_DEBUG
325 HFC_inb_regio(struct hfc_multi *hc, u_char reg, const char *function, int line)
327 HFC_inb_regio(struct hfc_multi *hc, u_char reg)
330 outb(reg, hc->pci_iobase + 4);
331 return inb(hc->pci_iobase);
334 #ifdef HFC_REGISTER_DEBUG
335 HFC_inw_regio(struct hfc_multi *hc, u_char reg, const char *function, int line)
337 HFC_inw_regio(struct hfc_multi *hc, u_char reg)
340 outb(reg, hc->pci_iobase + 4);
341 return inw(hc->pci_iobase);
344 #ifdef HFC_REGISTER_DEBUG
345 HFC_wait_regio(struct hfc_multi *hc, const char *function, int line)
347 HFC_wait_regio(struct hfc_multi *hc)
350 outb(R_STATUS, hc->pci_iobase + 4);
351 while (inb(hc->pci_iobase) & V_BUSY)
355 #ifdef HFC_REGISTER_DEBUG
357 HFC_outb_debug(struct hfc_multi *hc, u_char reg, u_char val,
358 const char *function, int line)
360 char regname[256] = "", bits[9] = "xxxxxxxx";
364 while (hfc_register_names[++i].name) {
365 if (hfc_register_names[i].reg == reg)
366 strcat(regname, hfc_register_names[i].name);
368 if (regname[0] == '\0')
369 strcpy(regname, "register");
371 bits[7] = '0' + (!!(val & 1));
372 bits[6] = '0' + (!!(val & 2));
373 bits[5] = '0' + (!!(val & 4));
374 bits[4] = '0' + (!!(val & 8));
375 bits[3] = '0' + (!!(val & 16));
376 bits[2] = '0' + (!!(val & 32));
377 bits[1] = '0' + (!!(val & 64));
378 bits[0] = '0' + (!!(val & 128));
380 "HFC_outb(chip %d, %02x=%s, 0x%02x=%s); in %s() line %d\n",
381 hc->id, reg, regname, val, bits, function, line);
382 HFC_outb_nodebug(hc, reg, val);
385 HFC_inb_debug(struct hfc_multi *hc, u_char reg, const char *function, int line)
387 char regname[256] = "", bits[9] = "xxxxxxxx";
388 u_char val = HFC_inb_nodebug(hc, reg);
392 while (hfc_register_names[i++].name)
394 while (hfc_register_names[++i].name) {
395 if (hfc_register_names[i].reg == reg)
396 strcat(regname, hfc_register_names[i].name);
398 if (regname[0] == '\0')
399 strcpy(regname, "register");
401 bits[7] = '0' + (!!(val & 1));
402 bits[6] = '0' + (!!(val & 2));
403 bits[5] = '0' + (!!(val & 4));
404 bits[4] = '0' + (!!(val & 8));
405 bits[3] = '0' + (!!(val & 16));
406 bits[2] = '0' + (!!(val & 32));
407 bits[1] = '0' + (!!(val & 64));
408 bits[0] = '0' + (!!(val & 128));
410 "HFC_inb(chip %d, %02x=%s) = 0x%02x=%s; in %s() line %d\n",
411 hc->id, reg, regname, val, bits, function, line);
415 HFC_inw_debug(struct hfc_multi *hc, u_char reg, const char *function, int line)
417 char regname[256] = "";
418 u_short val = HFC_inw_nodebug(hc, reg);
422 while (hfc_register_names[i++].name)
424 while (hfc_register_names[++i].name) {
425 if (hfc_register_names[i].reg == reg)
426 strcat(regname, hfc_register_names[i].name);
428 if (regname[0] == '\0')
429 strcpy(regname, "register");
432 "HFC_inw(chip %d, %02x=%s) = 0x%04x; in %s() line %d\n",
433 hc->id, reg, regname, val, function, line);
437 HFC_wait_debug(struct hfc_multi *hc, const char *function, int line)
439 printk(KERN_DEBUG "HFC_wait(chip %d); in %s() line %d\n",
440 hc->id, function, line);
441 HFC_wait_nodebug(hc);
445 /* write fifo data (REGIO) */
447 write_fifo_regio(struct hfc_multi *hc, u_char *data, int len)
449 outb(A_FIFO_DATA0, (hc->pci_iobase) + 4);
451 outl(cpu_to_le32(*(u32 *)data), hc->pci_iobase);
456 outw(cpu_to_le16(*(u16 *)data), hc->pci_iobase);
461 outb(*data, hc->pci_iobase);
466 /* write fifo data (PCIMEM) */
468 write_fifo_pcimem(struct hfc_multi *hc, u_char *data, int len)
471 writel(cpu_to_le32(*(u32 *)data),
472 hc->pci_membase + A_FIFO_DATA0);
477 writew(cpu_to_le16(*(u16 *)data),
478 hc->pci_membase + A_FIFO_DATA0);
483 writeb(*data, hc->pci_membase + A_FIFO_DATA0);
489 /* read fifo data (REGIO) */
491 read_fifo_regio(struct hfc_multi *hc, u_char *data, int len)
493 outb(A_FIFO_DATA0, (hc->pci_iobase) + 4);
495 *(u32 *)data = le32_to_cpu(inl(hc->pci_iobase));
500 *(u16 *)data = le16_to_cpu(inw(hc->pci_iobase));
505 *data = inb(hc->pci_iobase);
511 /* read fifo data (PCIMEM) */
513 read_fifo_pcimem(struct hfc_multi *hc, u_char *data, int len)
517 le32_to_cpu(readl(hc->pci_membase + A_FIFO_DATA0));
523 le16_to_cpu(readw(hc->pci_membase + A_FIFO_DATA0));
528 *data = readb(hc->pci_membase + A_FIFO_DATA0);
535 enable_hwirq(struct hfc_multi *hc)
537 hc->hw.r_irq_ctrl |= V_GLOB_IRQ_EN;
538 HFC_outb(hc, R_IRQ_CTRL, hc->hw.r_irq_ctrl);
542 disable_hwirq(struct hfc_multi *hc)
544 hc->hw.r_irq_ctrl &= ~((u_char)V_GLOB_IRQ_EN);
545 HFC_outb(hc, R_IRQ_CTRL, hc->hw.r_irq_ctrl);
549 #define MAX_TDM_CHAN 32
553 enablepcibridge(struct hfc_multi *c)
555 HFC_outb(c, R_BRG_PCM_CFG, (0x0 << 6) | 0x3); /* was _io before */
559 disablepcibridge(struct hfc_multi *c)
561 HFC_outb(c, R_BRG_PCM_CFG, (0x0 << 6) | 0x2); /* was _io before */
565 readpcibridge(struct hfc_multi *hc, unsigned char address)
573 /* slow down a PCI read access by 1 PCI clock cycle */
574 HFC_outb(hc, R_CTRL, 0x4); /*was _io before*/
581 /* select local bridge port address by writing to CIP port */
582 /* data = HFC_inb(c, cipv); * was _io before */
583 outw(cipv, hc->pci_iobase + 4);
584 data = inb(hc->pci_iobase);
586 /* restore R_CTRL for normal PCI read cycle speed */
587 HFC_outb(hc, R_CTRL, 0x0); /* was _io before */
593 writepcibridge(struct hfc_multi *hc, unsigned char address, unsigned char data)
606 /* select local bridge port address by writing to CIP port */
607 outw(cipv, hc->pci_iobase + 4);
608 /* define a 32 bit dword with 4 identical bytes for write sequence */
609 datav = data | ((__u32) data << 8) | ((__u32) data << 16) |
610 ((__u32) data << 24);
613 * write this 32 bit dword to the bridge data port
614 * this will initiate a write sequence of up to 4 writes to the same
615 * address on the local bus interface the number of write accesses
616 * is undefined but >=1 and depends on the next PCI transaction
617 * during write sequence on the local bus
619 outl(datav, hc->pci_iobase);
623 cpld_set_reg(struct hfc_multi *hc, unsigned char reg)
625 /* Do data pin read low byte */
626 HFC_outb(hc, R_GPIO_OUT1, reg);
630 cpld_write_reg(struct hfc_multi *hc, unsigned char reg, unsigned char val)
632 cpld_set_reg(hc, reg);
635 writepcibridge(hc, 1, val);
636 disablepcibridge(hc);
642 cpld_read_reg(struct hfc_multi *hc, unsigned char reg)
644 unsigned char bytein;
646 cpld_set_reg(hc, reg);
648 /* Do data pin read low byte */
649 HFC_outb(hc, R_GPIO_OUT1, reg);
652 bytein = readpcibridge(hc, 1);
653 disablepcibridge(hc);
659 vpm_write_address(struct hfc_multi *hc, unsigned short addr)
661 cpld_write_reg(hc, 0, 0xff & addr);
662 cpld_write_reg(hc, 1, 0x01 & (addr >> 8));
665 inline unsigned short
666 vpm_read_address(struct hfc_multi *c)
669 unsigned short highbit;
671 addr = cpld_read_reg(c, 0);
672 highbit = cpld_read_reg(c, 1);
674 addr = addr | (highbit << 8);
680 vpm_in(struct hfc_multi *c, int which, unsigned short addr)
684 vpm_write_address(c, addr);
692 res = readpcibridge(c, 1);
701 vpm_out(struct hfc_multi *c, int which, unsigned short addr,
704 vpm_write_address(c, addr);
713 writepcibridge(c, 1, data);
721 regin = vpm_in(c, which, addr);
723 printk(KERN_DEBUG "Wrote 0x%x to register 0x%x but got back "
724 "0x%x\n", data, addr, regin);
731 vpm_init(struct hfc_multi *wc)
735 unsigned int i, x, y;
738 for (x = 0; x < NUM_EC; x++) {
741 ver = vpm_in(wc, x, 0x1a0);
742 printk(KERN_DEBUG "VPM: Chip %d: ver %02x\n", x, ver);
745 for (y = 0; y < 4; y++) {
746 vpm_out(wc, x, 0x1a8 + y, 0x00); /* GPIO out */
747 vpm_out(wc, x, 0x1ac + y, 0x00); /* GPIO dir */
748 vpm_out(wc, x, 0x1b0 + y, 0x00); /* GPIO sel */
751 /* Setup TDM path - sets fsync and tdm_clk as inputs */
752 reg = vpm_in(wc, x, 0x1a3); /* misc_con */
753 vpm_out(wc, x, 0x1a3, reg & ~2);
755 /* Setup Echo length (256 taps) */
756 vpm_out(wc, x, 0x022, 1);
757 vpm_out(wc, x, 0x023, 0xff);
759 /* Setup timeslots */
760 vpm_out(wc, x, 0x02f, 0x00);
761 mask = 0x02020202 << (x * 4);
763 /* Setup the tdm channel masks for all chips */
764 for (i = 0; i < 4; i++)
765 vpm_out(wc, x, 0x33 - i, (mask >> (i << 3)) & 0xff);
767 /* Setup convergence rate */
768 printk(KERN_DEBUG "VPM: A-law mode\n");
769 reg = 0x00 | 0x10 | 0x01;
770 vpm_out(wc, x, 0x20, reg);
771 printk(KERN_DEBUG "VPM reg 0x20 is %x\n", reg);
772 /*vpm_out(wc, x, 0x20, (0x00 | 0x08 | 0x20 | 0x10)); */
774 vpm_out(wc, x, 0x24, 0x02);
775 reg = vpm_in(wc, x, 0x24);
776 printk(KERN_DEBUG "NLP Thresh is set to %d (0x%x)\n", reg, reg);
778 /* Initialize echo cans */
779 for (i = 0; i < MAX_TDM_CHAN; i++) {
780 if (mask & (0x00000001 << i))
781 vpm_out(wc, x, i, 0x00);
785 * ARM arch at least disallows a udelay of
786 * more than 2ms... it gives a fake "__bad_udelay"
787 * reference at link-time.
788 * long delays in kernel code are pretty sucky anyway
789 * for now work around it using 5 x 2ms instead of 1 x 10ms
798 /* Put in bypass mode */
799 for (i = 0; i < MAX_TDM_CHAN; i++) {
800 if (mask & (0x00000001 << i))
801 vpm_out(wc, x, i, 0x01);
805 for (i = 0; i < MAX_TDM_CHAN; i++) {
806 if (mask & (0x00000001 << i))
807 vpm_out(wc, x, 0x78 + i, 0x01);
815 vpm_check(struct hfc_multi *hctmp)
819 gpi2 = HFC_inb(hctmp, R_GPI_IN2);
821 if ((gpi2 & 0x3) != 0x3)
822 printk(KERN_DEBUG "Got interrupt 0x%x from VPM!\n", gpi2);
828 * Interface to enable/disable the HW Echocan
830 * these functions are called within a spin_lock_irqsave on
831 * the channel instance lock, so we are not disturbed by irqs
833 * we can later easily change the interface to make other
834 * things configurable, for now we configure the taps
839 vpm_echocan_on(struct hfc_multi *hc, int ch, int taps)
841 unsigned int timeslot;
843 struct bchannel *bch = hc->chan[ch].bch;
848 if (hc->chan[ch].protocol != ISDN_P_B_RAW)
855 skb = _alloc_mISDN_skb(PH_CONTROL_IND, HFC_VOL_CHANGE_TX,
856 sizeof(int), &txadj, GFP_ATOMIC);
858 recv_Bchannel_skb(bch, skb);
861 timeslot = ((ch / 4) * 8) + ((ch % 4) * 4) + 1;
864 printk(KERN_NOTICE "vpm_echocan_on called taps [%d] on timeslot %d\n",
867 vpm_out(hc, unit, timeslot, 0x7e);
871 vpm_echocan_off(struct hfc_multi *hc, int ch)
873 unsigned int timeslot;
875 struct bchannel *bch = hc->chan[ch].bch;
881 if (hc->chan[ch].protocol != ISDN_P_B_RAW)
888 skb = _alloc_mISDN_skb(PH_CONTROL_IND, HFC_VOL_CHANGE_TX,
889 sizeof(int), &txadj, GFP_ATOMIC);
891 recv_Bchannel_skb(bch, skb);
894 timeslot = ((ch / 4) * 8) + ((ch % 4) * 4) + 1;
897 printk(KERN_NOTICE "vpm_echocan_off called on timeslot %d\n",
900 vpm_out(hc, unit, timeslot, 0x01);
905 * Speech Design resync feature
906 * NOTE: This is called sometimes outside interrupt handler.
907 * We must lock irqsave, so no other interrupt (other card) will occur!
908 * Also multiple interrupts may nest, so must lock each access (lists, card)!
911 hfcmulti_resync(struct hfc_multi *locked, struct hfc_multi *newmaster, int rm)
913 struct hfc_multi *hc, *next, *pcmmaster = NULL;
914 void __iomem *plx_acc_32;
918 spin_lock_irqsave(&HFClock, flags);
919 spin_lock(&plx_lock); /* must be locked inside other locks */
921 if (debug & DEBUG_HFCMULTI_PLXSD)
922 printk(KERN_DEBUG "%s: RESYNC(syncmaster=0x%p)\n",
923 __func__, syncmaster);
925 /* select new master */
927 if (debug & DEBUG_HFCMULTI_PLXSD)
928 printk(KERN_DEBUG "using provided controller\n");
930 list_for_each_entry_safe(hc, next, &HFClist, list) {
931 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
932 if (hc->syncronized) {
940 /* Disable sync of all cards */
941 list_for_each_entry_safe(hc, next, &HFClist, list) {
942 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
943 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
944 pv = readl(plx_acc_32);
945 pv &= ~PLX_SYNC_O_EN;
946 writel(pv, plx_acc_32);
947 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip)) {
949 if (hc->ctype == HFC_TYPE_E1) {
950 if (debug & DEBUG_HFCMULTI_PLXSD)
952 "Schedule SYNC_I\n");
953 hc->e1_resync |= 1; /* get SYNC_I */
961 if (debug & DEBUG_HFCMULTI_PLXSD)
962 printk(KERN_DEBUG "id=%d (0x%p) = syncronized with "
963 "interface.\n", hc->id, hc);
964 /* Enable new sync master */
965 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
966 pv = readl(plx_acc_32);
968 writel(pv, plx_acc_32);
969 /* switch to jatt PLL, if not disabled by RX_SYNC */
970 if (hc->ctype == HFC_TYPE_E1
971 && !test_bit(HFC_CHIP_RX_SYNC, &hc->chip)) {
972 if (debug & DEBUG_HFCMULTI_PLXSD)
973 printk(KERN_DEBUG "Schedule jatt PLL\n");
974 hc->e1_resync |= 2; /* switch to jatt */
979 if (debug & DEBUG_HFCMULTI_PLXSD)
981 "id=%d (0x%p) = PCM master syncronized "
982 "with QUARTZ\n", hc->id, hc);
983 if (hc->ctype == HFC_TYPE_E1) {
984 /* Use the crystal clock for the PCM
986 if (debug & DEBUG_HFCMULTI_PLXSD)
988 "Schedule QUARTZ for HFC-E1\n");
989 hc->e1_resync |= 4; /* switch quartz */
991 if (debug & DEBUG_HFCMULTI_PLXSD)
993 "QUARTZ is automatically "
994 "enabled by HFC-%dS\n", hc->ctype);
996 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
997 pv = readl(plx_acc_32);
999 writel(pv, plx_acc_32);
1002 printk(KERN_ERR "%s no pcm master, this MUST "
1003 "not happen!\n", __func__);
1005 syncmaster = newmaster;
1007 spin_unlock(&plx_lock);
1008 spin_unlock_irqrestore(&HFClock, flags);
1011 /* This must be called AND hc must be locked irqsave!!! */
1013 plxsd_checksync(struct hfc_multi *hc, int rm)
1015 if (hc->syncronized) {
1016 if (syncmaster == NULL) {
1017 if (debug & DEBUG_HFCMULTI_PLXSD)
1018 printk(KERN_DEBUG "%s: GOT sync on card %d"
1019 " (id=%d)\n", __func__, hc->id + 1,
1021 hfcmulti_resync(hc, hc, rm);
1024 if (syncmaster == hc) {
1025 if (debug & DEBUG_HFCMULTI_PLXSD)
1026 printk(KERN_DEBUG "%s: LOST sync on card %d"
1027 " (id=%d)\n", __func__, hc->id + 1,
1029 hfcmulti_resync(hc, NULL, rm);
1036 * free hardware resources used by driver
1039 release_io_hfcmulti(struct hfc_multi *hc)
1041 void __iomem *plx_acc_32;
1045 if (debug & DEBUG_HFCMULTI_INIT)
1046 printk(KERN_DEBUG "%s: entered\n", __func__);
1048 /* soft reset also masks all interrupts */
1049 hc->hw.r_cirm |= V_SRES;
1050 HFC_outb(hc, R_CIRM, hc->hw.r_cirm);
1052 hc->hw.r_cirm &= ~V_SRES;
1053 HFC_outb(hc, R_CIRM, hc->hw.r_cirm);
1054 udelay(1000); /* instead of 'wait' that may cause locking */
1056 /* release Speech Design card, if PLX was initialized */
1057 if (test_bit(HFC_CHIP_PLXSD, &hc->chip) && hc->plx_membase) {
1058 if (debug & DEBUG_HFCMULTI_PLXSD)
1059 printk(KERN_DEBUG "%s: release PLXSD card %d\n",
1060 __func__, hc->id + 1);
1061 spin_lock_irqsave(&plx_lock, plx_flags);
1062 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
1063 writel(PLX_GPIOC_INIT, plx_acc_32);
1064 pv = readl(plx_acc_32);
1065 /* Termination off */
1067 /* Disconnect the PCM */
1068 pv |= PLX_SLAVE_EN_N;
1069 pv &= ~PLX_MASTER_EN;
1070 pv &= ~PLX_SYNC_O_EN;
1071 /* Put the DSP in Reset */
1072 pv &= ~PLX_DSP_RES_N;
1073 writel(pv, plx_acc_32);
1074 if (debug & DEBUG_HFCMULTI_INIT)
1075 printk(KERN_DEBUG "%s: PCM off: PLX_GPIO=%x\n",
1077 spin_unlock_irqrestore(&plx_lock, plx_flags);
1080 /* disable memory mapped ports / io ports */
1081 test_and_clear_bit(HFC_CHIP_PLXSD, &hc->chip); /* prevent resync */
1083 pci_write_config_word(hc->pci_dev, PCI_COMMAND, 0);
1084 if (hc->pci_membase)
1085 iounmap(hc->pci_membase);
1086 if (hc->plx_membase)
1087 iounmap(hc->plx_membase);
1089 release_region(hc->pci_iobase, 8);
1090 if (hc->xhfc_membase)
1091 iounmap((void *)hc->xhfc_membase);
1094 pci_disable_device(hc->pci_dev);
1095 pci_set_drvdata(hc->pci_dev, NULL);
1097 if (debug & DEBUG_HFCMULTI_INIT)
1098 printk(KERN_DEBUG "%s: done\n", __func__);
1102 * function called to reset the HFC chip. A complete software reset of chip
1103 * and fifos is done. All configuration of the chip is done.
1107 init_chip(struct hfc_multi *hc)
1109 u_long flags, val, val2 = 0, rev;
1111 u_char r_conf_en, rval;
1112 void __iomem *plx_acc_32;
1114 u_long plx_flags, hfc_flags;
1116 struct hfc_multi *pos, *next, *plx_last_hc;
1118 spin_lock_irqsave(&hc->lock, flags);
1119 /* reset all registers */
1120 memset(&hc->hw, 0, sizeof(struct hfcm_hw));
1122 /* revision check */
1123 if (debug & DEBUG_HFCMULTI_INIT)
1124 printk(KERN_DEBUG "%s: entered\n", __func__);
1125 val = HFC_inb(hc, R_CHIP_ID);
1126 if ((val >> 4) != 0x8 && (val >> 4) != 0xc && (val >> 4) != 0xe &&
1127 (val >> 1) != 0x31) {
1128 printk(KERN_INFO "HFC_multi: unknown CHIP_ID:%x\n", (u_int)val);
1132 rev = HFC_inb(hc, R_CHIP_RV);
1134 "HFC_multi: detected HFC with chip ID=0x%lx revision=%ld%s\n",
1135 val, rev, (rev == 0 && (hc->ctype != HFC_TYPE_XHFC)) ?
1136 " (old FIFO handling)" : "");
1137 if (hc->ctype != HFC_TYPE_XHFC && rev == 0) {
1138 test_and_set_bit(HFC_CHIP_REVISION0, &hc->chip);
1140 "HFC_multi: NOTE: Your chip is revision 0, "
1141 "ask Cologne Chip for update. Newer chips "
1142 "have a better FIFO handling. Old chips "
1143 "still work but may have slightly lower "
1144 "HDLC transmit performance.\n");
1147 printk(KERN_WARNING "HFC_multi: WARNING: This driver doesn't "
1148 "consider chip revision = %ld. The chip / "
1149 "bridge may not work.\n", rev);
1152 /* set s-ram size */
1156 hc->DTMFbase = 0x1000;
1157 if (test_bit(HFC_CHIP_EXRAM_128, &hc->chip)) {
1158 if (debug & DEBUG_HFCMULTI_INIT)
1159 printk(KERN_DEBUG "%s: changing to 128K extenal RAM\n",
1161 hc->hw.r_ctrl |= V_EXT_RAM;
1162 hc->hw.r_ram_sz = 1;
1166 hc->DTMFbase = 0x2000;
1168 if (test_bit(HFC_CHIP_EXRAM_512, &hc->chip)) {
1169 if (debug & DEBUG_HFCMULTI_INIT)
1170 printk(KERN_DEBUG "%s: changing to 512K extenal RAM\n",
1172 hc->hw.r_ctrl |= V_EXT_RAM;
1173 hc->hw.r_ram_sz = 2;
1177 hc->DTMFbase = 0x2000;
1179 if (hc->ctype == HFC_TYPE_XHFC) {
1185 hc->max_trans = poll << 1;
1186 if (hc->max_trans > hc->Zlen)
1187 hc->max_trans = hc->Zlen;
1189 /* Speech Design PLX bridge */
1190 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
1191 if (debug & DEBUG_HFCMULTI_PLXSD)
1192 printk(KERN_DEBUG "%s: initializing PLXSD card %d\n",
1193 __func__, hc->id + 1);
1194 spin_lock_irqsave(&plx_lock, plx_flags);
1195 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
1196 writel(PLX_GPIOC_INIT, plx_acc_32);
1197 pv = readl(plx_acc_32);
1198 /* The first and the last cards are terminating the PCM bus */
1199 pv |= PLX_TERM_ON; /* hc is currently the last */
1200 /* Disconnect the PCM */
1201 pv |= PLX_SLAVE_EN_N;
1202 pv &= ~PLX_MASTER_EN;
1203 pv &= ~PLX_SYNC_O_EN;
1204 /* Put the DSP in Reset */
1205 pv &= ~PLX_DSP_RES_N;
1206 writel(pv, plx_acc_32);
1207 spin_unlock_irqrestore(&plx_lock, plx_flags);
1208 if (debug & DEBUG_HFCMULTI_INIT)
1209 printk(KERN_DEBUG "%s: slave/term: PLX_GPIO=%x\n",
1212 * If we are the 3rd PLXSD card or higher, we must turn
1213 * termination of last PLXSD card off.
1215 spin_lock_irqsave(&HFClock, hfc_flags);
1218 list_for_each_entry_safe(pos, next, &HFClist, list) {
1219 if (test_bit(HFC_CHIP_PLXSD, &pos->chip)) {
1225 if (plx_count >= 3) {
1226 if (debug & DEBUG_HFCMULTI_PLXSD)
1227 printk(KERN_DEBUG "%s: card %d is between, so "
1228 "we disable termination\n",
1229 __func__, plx_last_hc->id + 1);
1230 spin_lock_irqsave(&plx_lock, plx_flags);
1231 plx_acc_32 = plx_last_hc->plx_membase + PLX_GPIOC;
1232 pv = readl(plx_acc_32);
1234 writel(pv, plx_acc_32);
1235 spin_unlock_irqrestore(&plx_lock, plx_flags);
1236 if (debug & DEBUG_HFCMULTI_INIT)
1238 "%s: term off: PLX_GPIO=%x\n",
1241 spin_unlock_irqrestore(&HFClock, hfc_flags);
1242 hc->hw.r_pcm_md0 = V_F0_LEN; /* shift clock for DSP */
1245 if (test_bit(HFC_CHIP_EMBSD, &hc->chip))
1246 hc->hw.r_pcm_md0 = V_F0_LEN; /* shift clock for DSP */
1248 /* we only want the real Z2 read-pointer for revision > 0 */
1249 if (!test_bit(HFC_CHIP_REVISION0, &hc->chip))
1250 hc->hw.r_ram_sz |= V_FZ_MD;
1252 /* select pcm mode */
1253 if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) {
1254 if (debug & DEBUG_HFCMULTI_INIT)
1255 printk(KERN_DEBUG "%s: setting PCM into slave mode\n",
1258 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip) && !plxsd_master) {
1259 if (debug & DEBUG_HFCMULTI_INIT)
1260 printk(KERN_DEBUG "%s: setting PCM into master mode\n",
1262 hc->hw.r_pcm_md0 |= V_PCM_MD;
1264 if (debug & DEBUG_HFCMULTI_INIT)
1265 printk(KERN_DEBUG "%s: performing PCM auto detect\n",
1270 HFC_outb(hc, R_CTRL, hc->hw.r_ctrl);
1271 if (hc->ctype == HFC_TYPE_XHFC)
1272 HFC_outb(hc, 0x0C /* R_FIFO_THRES */,
1273 0x11 /* 16 Bytes TX/RX */);
1275 HFC_outb(hc, R_RAM_SZ, hc->hw.r_ram_sz);
1276 HFC_outb(hc, R_FIFO_MD, 0);
1277 if (hc->ctype == HFC_TYPE_XHFC)
1278 hc->hw.r_cirm = V_SRES | V_HFCRES | V_PCMRES | V_STRES;
1280 hc->hw.r_cirm = V_SRES | V_HFCRES | V_PCMRES | V_STRES
1282 HFC_outb(hc, R_CIRM, hc->hw.r_cirm);
1285 HFC_outb(hc, R_CIRM, hc->hw.r_cirm);
1287 if (hc->ctype != HFC_TYPE_XHFC)
1288 HFC_outb(hc, R_RAM_SZ, hc->hw.r_ram_sz);
1290 /* Speech Design PLX bridge pcm and sync mode */
1291 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
1292 spin_lock_irqsave(&plx_lock, plx_flags);
1293 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
1294 pv = readl(plx_acc_32);
1296 if (hc->hw.r_pcm_md0 & V_PCM_MD) {
1297 pv |= PLX_MASTER_EN | PLX_SLAVE_EN_N;
1298 pv |= PLX_SYNC_O_EN;
1299 if (debug & DEBUG_HFCMULTI_INIT)
1300 printk(KERN_DEBUG "%s: master: PLX_GPIO=%x\n",
1303 pv &= ~(PLX_MASTER_EN | PLX_SLAVE_EN_N);
1304 pv &= ~PLX_SYNC_O_EN;
1305 if (debug & DEBUG_HFCMULTI_INIT)
1306 printk(KERN_DEBUG "%s: slave: PLX_GPIO=%x\n",
1309 writel(pv, plx_acc_32);
1310 spin_unlock_irqrestore(&plx_lock, plx_flags);
1314 HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0x90);
1315 if (hc->slots == 32)
1316 HFC_outb(hc, R_PCM_MD1, 0x00);
1317 if (hc->slots == 64)
1318 HFC_outb(hc, R_PCM_MD1, 0x10);
1319 if (hc->slots == 128)
1320 HFC_outb(hc, R_PCM_MD1, 0x20);
1321 HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0xa0);
1322 if (test_bit(HFC_CHIP_PLXSD, &hc->chip))
1323 HFC_outb(hc, R_PCM_MD2, V_SYNC_SRC); /* sync via SYNC_I / O */
1324 else if (test_bit(HFC_CHIP_EMBSD, &hc->chip))
1325 HFC_outb(hc, R_PCM_MD2, 0x10); /* V_C2O_EN */
1327 HFC_outb(hc, R_PCM_MD2, 0x00); /* sync from interface */
1328 HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0x00);
1329 for (i = 0; i < 256; i++) {
1330 HFC_outb_nodebug(hc, R_SLOT, i);
1331 HFC_outb_nodebug(hc, A_SL_CFG, 0);
1332 if (hc->ctype != HFC_TYPE_XHFC)
1333 HFC_outb_nodebug(hc, A_CONF, 0);
1334 hc->slot_owner[i] = -1;
1337 /* set clock speed */
1338 if (test_bit(HFC_CHIP_CLOCK2, &hc->chip)) {
1339 if (debug & DEBUG_HFCMULTI_INIT)
1341 "%s: setting double clock\n", __func__);
1342 HFC_outb(hc, R_BRG_PCM_CFG, V_PCM_CLK);
1345 if (test_bit(HFC_CHIP_EMBSD, &hc->chip))
1346 HFC_outb(hc, 0x02 /* R_CLK_CFG */, 0x40 /* V_CLKO_OFF */);
1349 if (test_bit(HFC_CHIP_B410P, &hc->chip)) {
1350 printk(KERN_NOTICE "Setting GPIOs\n");
1351 HFC_outb(hc, R_GPIO_SEL, 0x30);
1352 HFC_outb(hc, R_GPIO_EN1, 0x3);
1354 printk(KERN_NOTICE "calling vpm_init\n");
1358 /* check if R_F0_CNT counts (8 kHz frame count) */
1359 val = HFC_inb(hc, R_F0_CNTL);
1360 val += HFC_inb(hc, R_F0_CNTH) << 8;
1361 if (debug & DEBUG_HFCMULTI_INIT)
1363 "HFC_multi F0_CNT %ld after reset\n", val);
1364 spin_unlock_irqrestore(&hc->lock, flags);
1365 set_current_state(TASK_UNINTERRUPTIBLE);
1366 schedule_timeout((HZ / 100) ? : 1); /* Timeout minimum 10ms */
1367 spin_lock_irqsave(&hc->lock, flags);
1368 val2 = HFC_inb(hc, R_F0_CNTL);
1369 val2 += HFC_inb(hc, R_F0_CNTH) << 8;
1370 if (debug & DEBUG_HFCMULTI_INIT)
1372 "HFC_multi F0_CNT %ld after 10 ms (1st try)\n",
1374 if (val2 >= val + 8) { /* 1 ms */
1375 /* it counts, so we keep the pcm mode */
1376 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip))
1377 printk(KERN_INFO "controller is PCM bus MASTER\n");
1379 if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip))
1380 printk(KERN_INFO "controller is PCM bus SLAVE\n");
1382 test_and_set_bit(HFC_CHIP_PCM_SLAVE, &hc->chip);
1383 printk(KERN_INFO "controller is PCM bus SLAVE "
1384 "(auto detected)\n");
1387 /* does not count */
1388 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip)) {
1390 printk(KERN_ERR "HFC_multi ERROR, getting no 125us "
1391 "pulse. Seems that controller fails.\n");
1395 if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) {
1396 printk(KERN_INFO "controller is PCM bus SLAVE "
1397 "(ignoring missing PCM clock)\n");
1399 /* only one pcm master */
1400 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)
1402 printk(KERN_ERR "HFC_multi ERROR, no clock "
1403 "on another Speech Design card found. "
1404 "Please be sure to connect PCM cable.\n");
1408 /* retry with master clock */
1409 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
1410 spin_lock_irqsave(&plx_lock, plx_flags);
1411 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
1412 pv = readl(plx_acc_32);
1413 pv |= PLX_MASTER_EN | PLX_SLAVE_EN_N;
1414 pv |= PLX_SYNC_O_EN;
1415 writel(pv, plx_acc_32);
1416 spin_unlock_irqrestore(&plx_lock, plx_flags);
1417 if (debug & DEBUG_HFCMULTI_INIT)
1418 printk(KERN_DEBUG "%s: master: "
1419 "PLX_GPIO=%x\n", __func__, pv);
1421 hc->hw.r_pcm_md0 |= V_PCM_MD;
1422 HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0x00);
1423 spin_unlock_irqrestore(&hc->lock, flags);
1424 set_current_state(TASK_UNINTERRUPTIBLE);
1425 schedule_timeout((HZ / 100) ?: 1); /* Timeout min. 10ms */
1426 spin_lock_irqsave(&hc->lock, flags);
1427 val2 = HFC_inb(hc, R_F0_CNTL);
1428 val2 += HFC_inb(hc, R_F0_CNTH) << 8;
1429 if (debug & DEBUG_HFCMULTI_INIT)
1430 printk(KERN_DEBUG "HFC_multi F0_CNT %ld after "
1431 "10 ms (2nd try)\n", val2);
1432 if (val2 >= val + 8) { /* 1 ms */
1433 test_and_set_bit(HFC_CHIP_PCM_MASTER,
1435 printk(KERN_INFO "controller is PCM bus MASTER "
1436 "(auto detected)\n");
1438 goto controller_fail;
1442 /* Release the DSP Reset */
1443 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
1444 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip))
1446 spin_lock_irqsave(&plx_lock, plx_flags);
1447 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
1448 pv = readl(plx_acc_32);
1449 pv |= PLX_DSP_RES_N;
1450 writel(pv, plx_acc_32);
1451 spin_unlock_irqrestore(&plx_lock, plx_flags);
1452 if (debug & DEBUG_HFCMULTI_INIT)
1453 printk(KERN_DEBUG "%s: reset off: PLX_GPIO=%x\n",
1459 printk(KERN_INFO "controller has given PCM BUS ID %d\n",
1462 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip)
1463 || test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
1464 PCM_cnt++; /* SD has proprietary bridging */
1467 printk(KERN_INFO "controller has PCM BUS ID %d "
1468 "(auto selected)\n", hc->pcm);
1472 HFC_outb(hc, R_TI_WD, poll_timer);
1473 hc->hw.r_irqmsk_misc |= V_TI_IRQMSK;
1475 /* set E1 state machine IRQ */
1476 if (hc->ctype == HFC_TYPE_E1)
1477 hc->hw.r_irqmsk_misc |= V_STA_IRQMSK;
1479 /* set DTMF detection */
1480 if (test_bit(HFC_CHIP_DTMF, &hc->chip)) {
1481 if (debug & DEBUG_HFCMULTI_INIT)
1482 printk(KERN_DEBUG "%s: enabling DTMF detection "
1483 "for all B-channel\n", __func__);
1484 hc->hw.r_dtmf = V_DTMF_EN | V_DTMF_STOP;
1485 if (test_bit(HFC_CHIP_ULAW, &hc->chip))
1486 hc->hw.r_dtmf |= V_ULAW_SEL;
1487 HFC_outb(hc, R_DTMF_N, 102 - 1);
1488 hc->hw.r_irqmsk_misc |= V_DTMF_IRQMSK;
1491 /* conference engine */
1492 if (test_bit(HFC_CHIP_ULAW, &hc->chip))
1493 r_conf_en = V_CONF_EN | V_ULAW;
1495 r_conf_en = V_CONF_EN;
1496 if (hc->ctype != HFC_TYPE_XHFC)
1497 HFC_outb(hc, R_CONF_EN, r_conf_en);
1501 case 1: /* HFC-E1 OEM */
1502 if (test_bit(HFC_CHIP_WATCHDOG, &hc->chip))
1503 HFC_outb(hc, R_GPIO_SEL, 0x32);
1505 HFC_outb(hc, R_GPIO_SEL, 0x30);
1507 HFC_outb(hc, R_GPIO_EN1, 0x0f);
1508 HFC_outb(hc, R_GPIO_OUT1, 0x00);
1510 HFC_outb(hc, R_GPIO_EN0, V_GPIO_EN2 | V_GPIO_EN3);
1513 case 2: /* HFC-4S OEM */
1515 HFC_outb(hc, R_GPIO_SEL, 0xf0);
1516 HFC_outb(hc, R_GPIO_EN1, 0xff);
1517 HFC_outb(hc, R_GPIO_OUT1, 0x00);
1521 if (test_bit(HFC_CHIP_EMBSD, &hc->chip)) {
1522 hc->hw.r_st_sync = 0x10; /* V_AUTO_SYNCI */
1523 HFC_outb(hc, R_ST_SYNC, hc->hw.r_st_sync);
1526 /* set master clock */
1527 if (hc->masterclk >= 0) {
1528 if (debug & DEBUG_HFCMULTI_INIT)
1529 printk(KERN_DEBUG "%s: setting ST master clock "
1530 "to port %d (0..%d)\n",
1531 __func__, hc->masterclk, hc->ports - 1);
1532 hc->hw.r_st_sync |= (hc->masterclk | V_AUTO_SYNC);
1533 HFC_outb(hc, R_ST_SYNC, hc->hw.r_st_sync);
1538 /* setting misc irq */
1539 HFC_outb(hc, R_IRQMSK_MISC, hc->hw.r_irqmsk_misc);
1540 if (debug & DEBUG_HFCMULTI_INIT)
1541 printk(KERN_DEBUG "r_irqmsk_misc.2: 0x%x\n",
1542 hc->hw.r_irqmsk_misc);
1544 /* RAM access test */
1545 HFC_outb(hc, R_RAM_ADDR0, 0);
1546 HFC_outb(hc, R_RAM_ADDR1, 0);
1547 HFC_outb(hc, R_RAM_ADDR2, 0);
1548 for (i = 0; i < 256; i++) {
1549 HFC_outb_nodebug(hc, R_RAM_ADDR0, i);
1550 HFC_outb_nodebug(hc, R_RAM_DATA, ((i * 3) & 0xff));
1552 for (i = 0; i < 256; i++) {
1553 HFC_outb_nodebug(hc, R_RAM_ADDR0, i);
1554 HFC_inb_nodebug(hc, R_RAM_DATA);
1555 rval = HFC_inb_nodebug(hc, R_INT_DATA);
1556 if (rval != ((i * 3) & 0xff)) {
1558 "addr:%x val:%x should:%x\n", i, rval,
1564 printk(KERN_DEBUG "aborting - %d RAM access errors\n", err);
1569 if (debug & DEBUG_HFCMULTI_INIT)
1570 printk(KERN_DEBUG "%s: done\n", __func__);
1572 spin_unlock_irqrestore(&hc->lock, flags);
1578 * control the watchdog
1581 hfcmulti_watchdog(struct hfc_multi *hc)
1585 if (hc->wdcount > 10) {
1587 hc->wdbyte = hc->wdbyte == V_GPIO_OUT2 ?
1588 V_GPIO_OUT3 : V_GPIO_OUT2;
1590 /* printk("Sending Watchdog Kill %x\n",hc->wdbyte); */
1591 HFC_outb(hc, R_GPIO_EN0, V_GPIO_EN2 | V_GPIO_EN3);
1592 HFC_outb(hc, R_GPIO_OUT0, hc->wdbyte);
1602 hfcmulti_leds(struct hfc_multi *hc)
1605 unsigned long leddw;
1606 int i, state, active, leds;
1607 struct dchannel *dch;
1610 hc->ledcount += poll;
1611 if (hc->ledcount > 4096) {
1612 hc->ledcount -= 4096;
1613 hc->ledstate = 0xAFFEAFFE;
1617 case 1: /* HFC-E1 OEM */
1618 /* 2 red blinking: NT mode deactivate
1619 * 2 red steady: TE mode deactivate
1620 * left green: L1 active
1621 * left red: frame sync, but no L1
1622 * todo right green: L2 active
1624 dch = hc->chan[hc->dslot].dch;
1625 if (test_bit(FLG_ACTIVE, &dch->Flags)) {
1631 if (dch->dev.D.protocol
1635 } else if (hc->ledcount >> 11) {
1645 leds = (led[0] | (led[1]<<2) | (led[2]<<1) | (led[3]<<3))^0xF;
1646 /* leds are inverted */
1647 if (leds != (int)hc->ledstate) {
1648 HFC_outb_nodebug(hc, R_GPIO_OUT1, leds);
1649 hc->ledstate = leds;
1653 case 2: /* HFC-4S OEM */
1654 /* red blinking = PH_DEACTIVATE NT Mode
1655 * red steady = PH_DEACTIVATE TE Mode
1656 * green steady = PH_ACTIVATE
1658 for (i = 0; i < 4; i++) {
1661 dch = hc->chan[(i << 2) | 2].dch;
1664 if (dch->dev.D.protocol == ISDN_P_NT_S0)
1670 if (state == active) {
1671 led[i] = 1; /* led green */
1673 if (dch->dev.D.protocol == ISDN_P_TE_S0)
1674 /* TE mode: led red */
1677 if (hc->ledcount >> 11)
1684 led[i] = 0; /* led off */
1686 if (test_bit(HFC_CHIP_B410P, &hc->chip)) {
1688 for (i = 0; i < 4; i++) {
1691 leds |= (0x2 << (i * 2));
1692 } else if (led[i] == 2) {
1694 leds |= (0x1 << (i * 2));
1697 if (leds != (int)hc->ledstate) {
1698 vpm_out(hc, 0, 0x1a8 + 3, leds);
1699 hc->ledstate = leds;
1702 leds = ((led[3] > 0) << 0) | ((led[1] > 0) << 1) |
1703 ((led[0] > 0) << 2) | ((led[2] > 0) << 3) |
1704 ((led[3] & 1) << 4) | ((led[1] & 1) << 5) |
1705 ((led[0] & 1) << 6) | ((led[2] & 1) << 7);
1706 if (leds != (int)hc->ledstate) {
1707 HFC_outb_nodebug(hc, R_GPIO_EN1, leds & 0x0F);
1708 HFC_outb_nodebug(hc, R_GPIO_OUT1, leds >> 4);
1709 hc->ledstate = leds;
1714 case 3: /* HFC 1S/2S Beronet */
1715 /* red blinking = PH_DEACTIVATE NT Mode
1716 * red steady = PH_DEACTIVATE TE Mode
1717 * green steady = PH_ACTIVATE
1719 for (i = 0; i < 2; i++) {
1722 dch = hc->chan[(i << 2) | 2].dch;
1725 if (dch->dev.D.protocol == ISDN_P_NT_S0)
1731 if (state == active) {
1732 led[i] = 1; /* led green */
1734 if (dch->dev.D.protocol == ISDN_P_TE_S0)
1735 /* TE mode: led red */
1738 if (hc->ledcount >> 11)
1745 led[i] = 0; /* led off */
1749 leds = (led[0] > 0) | ((led[1] > 0) << 1) | ((led[0]&1) << 2)
1750 | ((led[1]&1) << 3);
1751 if (leds != (int)hc->ledstate) {
1752 HFC_outb_nodebug(hc, R_GPIO_EN1,
1753 ((led[0] > 0) << 2) | ((led[1] > 0) << 3));
1754 HFC_outb_nodebug(hc, R_GPIO_OUT1,
1755 ((led[0] & 1) << 2) | ((led[1] & 1) << 3));
1756 hc->ledstate = leds;
1759 case 8: /* HFC 8S+ Beronet */
1762 for (i = 0; i < 8; i++) {
1765 dch = hc->chan[(i << 2) | 2].dch;
1768 if (dch->dev.D.protocol == ISDN_P_NT_S0)
1774 if (state == active) {
1777 if (hc->ledcount >> 11)
1784 leddw = lled << 24 | lled << 16 | lled << 8 | lled;
1785 if (leddw != hc->ledstate) {
1786 /* HFC_outb(hc, R_BRG_PCM_CFG, 1);
1787 HFC_outb(c, R_BRG_PCM_CFG, (0x0 << 6) | 0x3); */
1788 /* was _io before */
1789 HFC_outb_nodebug(hc, R_BRG_PCM_CFG, 1 | V_PCM_CLK);
1790 outw(0x4000, hc->pci_iobase + 4);
1791 outl(leddw, hc->pci_iobase);
1792 HFC_outb_nodebug(hc, R_BRG_PCM_CFG, V_PCM_CLK);
1793 hc->ledstate = leddw;
1799 * read dtmf coefficients
1803 hfcmulti_dtmf(struct hfc_multi *hc)
1808 struct bchannel *bch = NULL;
1813 struct sk_buff *skb;
1814 struct mISDNhead *hh;
1816 if (debug & DEBUG_HFCMULTI_DTMF)
1817 printk(KERN_DEBUG "%s: dtmf detection irq\n", __func__);
1818 for (ch = 0; ch <= 31; ch++) {
1819 /* only process enabled B-channels */
1820 bch = hc->chan[ch].bch;
1823 if (!hc->created[hc->chan[ch].port])
1825 if (!test_bit(FLG_TRANSPARENT, &bch->Flags))
1827 if (debug & DEBUG_HFCMULTI_DTMF)
1828 printk(KERN_DEBUG "%s: dtmf channel %d:",
1830 coeff = &(hc->chan[ch].coeff[hc->chan[ch].coeff_count * 16]);
1832 for (co = 0; co < 8; co++) {
1833 /* read W(n-1) coefficient */
1834 addr = hc->DTMFbase + ((co << 7) | (ch << 2));
1835 HFC_outb_nodebug(hc, R_RAM_ADDR0, addr);
1836 HFC_outb_nodebug(hc, R_RAM_ADDR1, addr >> 8);
1837 HFC_outb_nodebug(hc, R_RAM_ADDR2, (addr >> 16)
1839 w_float = HFC_inb_nodebug(hc, R_RAM_DATA);
1840 w_float |= (HFC_inb_nodebug(hc, R_RAM_DATA) << 8);
1841 if (debug & DEBUG_HFCMULTI_DTMF)
1842 printk(" %04x", w_float);
1844 /* decode float (see chip doc) */
1845 mantissa = w_float & 0x0fff;
1846 if (w_float & 0x8000)
1847 mantissa |= 0xfffff000;
1848 exponent = (w_float >> 12) & 0x7;
1851 mantissa <<= (exponent - 1);
1854 /* store coefficient */
1855 coeff[co << 1] = mantissa;
1857 /* read W(n) coefficient */
1858 w_float = HFC_inb_nodebug(hc, R_RAM_DATA);
1859 w_float |= (HFC_inb_nodebug(hc, R_RAM_DATA) << 8);
1860 if (debug & DEBUG_HFCMULTI_DTMF)
1861 printk(" %04x", w_float);
1863 /* decode float (see chip doc) */
1864 mantissa = w_float & 0x0fff;
1865 if (w_float & 0x8000)
1866 mantissa |= 0xfffff000;
1867 exponent = (w_float >> 12) & 0x7;
1870 mantissa <<= (exponent - 1);
1873 /* store coefficient */
1874 coeff[(co << 1) | 1] = mantissa;
1876 if (debug & DEBUG_HFCMULTI_DTMF)
1877 printk(" DTMF ready %08x %08x %08x %08x "
1878 "%08x %08x %08x %08x\n",
1879 coeff[0], coeff[1], coeff[2], coeff[3],
1880 coeff[4], coeff[5], coeff[6], coeff[7]);
1881 hc->chan[ch].coeff_count++;
1882 if (hc->chan[ch].coeff_count == 8) {
1883 hc->chan[ch].coeff_count = 0;
1884 skb = mI_alloc_skb(512, GFP_ATOMIC);
1886 printk(KERN_DEBUG "%s: No memory for skb\n",
1890 hh = mISDN_HEAD_P(skb);
1891 hh->prim = PH_CONTROL_IND;
1892 hh->id = DTMF_HFC_COEF;
1893 memcpy(skb_put(skb, 512), hc->chan[ch].coeff, 512);
1894 recv_Bchannel_skb(bch, skb);
1898 /* restart DTMF processing */
1901 HFC_outb_nodebug(hc, R_DTMF, hc->hw.r_dtmf | V_RST_DTMF);
1906 * fill fifo as much as possible
1910 hfcmulti_tx(struct hfc_multi *hc, int ch)
1912 int i, ii, temp, len = 0;
1913 int Zspace, z1, z2; /* must be int for calculation */
1916 int *txpending, slot_tx;
1917 struct bchannel *bch;
1918 struct dchannel *dch;
1919 struct sk_buff **sp = NULL;
1922 bch = hc->chan[ch].bch;
1923 dch = hc->chan[ch].dch;
1924 if ((!dch) && (!bch))
1927 txpending = &hc->chan[ch].txpending;
1928 slot_tx = hc->chan[ch].slot_tx;
1930 if (!test_bit(FLG_ACTIVE, &dch->Flags))
1933 idxp = &dch->tx_idx;
1935 if (!test_bit(FLG_ACTIVE, &bch->Flags))
1938 idxp = &bch->tx_idx;
1943 if ((!len) && *txpending != 1)
1944 return; /* no data */
1946 if (test_bit(HFC_CHIP_B410P, &hc->chip) &&
1947 (hc->chan[ch].protocol == ISDN_P_B_RAW) &&
1948 (hc->chan[ch].slot_rx < 0) &&
1949 (hc->chan[ch].slot_tx < 0))
1950 HFC_outb_nodebug(hc, R_FIFO, 0x20 | (ch << 1));
1952 HFC_outb_nodebug(hc, R_FIFO, ch << 1);
1953 HFC_wait_nodebug(hc);
1955 if (*txpending == 2) {
1957 HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_RES_F);
1958 HFC_wait_nodebug(hc);
1959 HFC_outb(hc, A_SUBCH_CFG, 0);
1963 if (dch || test_bit(FLG_HDLC, &bch->Flags)) {
1964 f1 = HFC_inb_nodebug(hc, A_F1);
1965 f2 = HFC_inb_nodebug(hc, A_F2);
1966 while (f2 != (temp = HFC_inb_nodebug(hc, A_F2))) {
1967 if (debug & DEBUG_HFCMULTI_FIFO)
1969 "%s(card %d): reread f2 because %d!=%d\n",
1970 __func__, hc->id + 1, temp, f2);
1971 f2 = temp; /* repeat until F2 is equal */
1973 Fspace = f2 - f1 - 1;
1977 * Old FIFO handling doesn't give us the current Z2 read
1978 * pointer, so we cannot send the next frame before the fifo
1979 * is empty. It makes no difference except for a slightly
1980 * lower performance.
1982 if (test_bit(HFC_CHIP_REVISION0, &hc->chip)) {
1988 /* one frame only for ST D-channels, to allow resending */
1989 if (hc->ctype != HFC_TYPE_E1 && dch) {
1993 /* F-counter full condition */
1997 z1 = HFC_inw_nodebug(hc, A_Z1) - hc->Zmin;
1998 z2 = HFC_inw_nodebug(hc, A_Z2) - hc->Zmin;
1999 while (z2 != (temp = (HFC_inw_nodebug(hc, A_Z2) - hc->Zmin))) {
2000 if (debug & DEBUG_HFCMULTI_FIFO)
2001 printk(KERN_DEBUG "%s(card %d): reread z2 because "
2002 "%d!=%d\n", __func__, hc->id + 1, temp, z2);
2003 z2 = temp; /* repeat unti Z2 is equal */
2005 hc->chan[ch].Zfill = z1 - z2;
2006 if (hc->chan[ch].Zfill < 0)
2007 hc->chan[ch].Zfill += hc->Zlen;
2011 Zspace -= 4; /* keep not too full, so pointers will not overrun */
2012 /* fill transparent data only to maxinum transparent load (minus 4) */
2013 if (bch && test_bit(FLG_TRANSPARENT, &bch->Flags))
2014 Zspace = Zspace - hc->Zlen + hc->max_trans;
2015 if (Zspace <= 0) /* no space of 4 bytes */
2020 if (z1 == z2) { /* empty */
2021 /* if done with FIFO audio data during PCM connection */
2022 if (bch && (!test_bit(FLG_HDLC, &bch->Flags)) &&
2023 *txpending && slot_tx >= 0) {
2024 if (debug & DEBUG_HFCMULTI_MODE)
2026 "%s: reconnecting PCM due to no "
2027 "more FIFO data: channel %d "
2029 __func__, ch, slot_tx);
2031 if (hc->ctype == HFC_TYPE_XHFC)
2032 HFC_outb(hc, A_CON_HDLC, 0xc0
2033 | 0x07 << 2 | V_HDLC_TRP | V_IFF);
2034 /* Enable FIFO, no interrupt */
2036 HFC_outb(hc, A_CON_HDLC, 0xc0 | 0x00 |
2037 V_HDLC_TRP | V_IFF);
2038 HFC_outb_nodebug(hc, R_FIFO, ch << 1 | 1);
2039 HFC_wait_nodebug(hc);
2040 if (hc->ctype == HFC_TYPE_XHFC)
2041 HFC_outb(hc, A_CON_HDLC, 0xc0
2042 | 0x07 << 2 | V_HDLC_TRP | V_IFF);
2043 /* Enable FIFO, no interrupt */
2045 HFC_outb(hc, A_CON_HDLC, 0xc0 | 0x00 |
2046 V_HDLC_TRP | V_IFF);
2047 HFC_outb_nodebug(hc, R_FIFO, ch << 1);
2048 HFC_wait_nodebug(hc);
2052 return; /* no data */
2055 /* "fill fifo if empty" feature */
2056 if (bch && test_bit(FLG_FILLEMPTY, &bch->Flags)
2057 && !test_bit(FLG_HDLC, &bch->Flags) && z2 == z1) {
2058 if (debug & DEBUG_HFCMULTI_FILL)
2059 printk(KERN_DEBUG "%s: buffer empty, so we have "
2060 "underrun\n", __func__);
2061 /* fill buffer, to prevent future underrun */
2062 hc->write_fifo(hc, hc->silence_data, poll >> 1);
2063 Zspace -= (poll >> 1);
2066 /* if audio data and connected slot */
2067 if (bch && (!test_bit(FLG_HDLC, &bch->Flags)) && (!*txpending)
2069 if (debug & DEBUG_HFCMULTI_MODE)
2070 printk(KERN_DEBUG "%s: disconnecting PCM due to "
2071 "FIFO data: channel %d slot_tx %d\n",
2072 __func__, ch, slot_tx);
2073 /* disconnect slot */
2074 if (hc->ctype == HFC_TYPE_XHFC)
2075 HFC_outb(hc, A_CON_HDLC, 0x80
2076 | 0x07 << 2 | V_HDLC_TRP | V_IFF);
2077 /* Enable FIFO, no interrupt */
2079 HFC_outb(hc, A_CON_HDLC, 0x80 | 0x00 |
2080 V_HDLC_TRP | V_IFF);
2081 HFC_outb_nodebug(hc, R_FIFO, ch << 1 | 1);
2082 HFC_wait_nodebug(hc);
2083 if (hc->ctype == HFC_TYPE_XHFC)
2084 HFC_outb(hc, A_CON_HDLC, 0x80
2085 | 0x07 << 2 | V_HDLC_TRP | V_IFF);
2086 /* Enable FIFO, no interrupt */
2088 HFC_outb(hc, A_CON_HDLC, 0x80 | 0x00 |
2089 V_HDLC_TRP | V_IFF);
2090 HFC_outb_nodebug(hc, R_FIFO, ch << 1);
2091 HFC_wait_nodebug(hc);
2096 hc->activity[hc->chan[ch].port] = 1;
2098 /* fill fifo to what we have left */
2100 if (dch || test_bit(FLG_HDLC, &bch->Flags))
2105 d = (*sp)->data + i;
2106 if (ii - i > Zspace)
2108 if (debug & DEBUG_HFCMULTI_FIFO)
2109 printk(KERN_DEBUG "%s(card %d): fifo(%d) has %d bytes space "
2110 "left (z1=%04x, z2=%04x) sending %d of %d bytes %s\n",
2111 __func__, hc->id + 1, ch, Zspace, z1, z2, ii-i, len-i,
2112 temp ? "HDLC" : "TRANS");
2114 /* Have to prep the audio data */
2115 hc->write_fifo(hc, d, ii - i);
2116 hc->chan[ch].Zfill += ii - i;
2119 /* if not all data has been written */
2121 /* NOTE: fifo is started by the calling function */
2125 /* if all data has been written, terminate frame */
2126 if (dch || test_bit(FLG_HDLC, &bch->Flags)) {
2127 /* increment f-counter */
2128 HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_INC_F);
2129 HFC_wait_nodebug(hc);
2132 /* send confirm, since get_net_bframe will not do it with trans */
2133 if (bch && test_bit(FLG_TRANSPARENT, &bch->Flags))
2136 /* check for next frame */
2138 if (bch && get_next_bframe(bch)) { /* hdlc is confirmed here */
2142 if (dch && get_next_dframe(dch)) {
2148 * now we have no more data, so in case of transparent,
2149 * we set the last byte in fifo to 'silence' in case we will get
2150 * no more data at all. this prevents sending an undefined value.
2152 if (bch && test_bit(FLG_TRANSPARENT, &bch->Flags))
2153 HFC_outb_nodebug(hc, A_FIFO_DATA0_NOINC, hc->silence);
2157 /* NOTE: only called if E1 card is in active state */
2159 hfcmulti_rx(struct hfc_multi *hc, int ch)
2162 int Zsize, z1, z2 = 0; /* = 0, to make GCC happy */
2163 int f1 = 0, f2 = 0; /* = 0, to make GCC happy */
2165 struct bchannel *bch;
2166 struct dchannel *dch;
2167 struct sk_buff *skb, **sp = NULL;
2170 bch = hc->chan[ch].bch;
2171 dch = hc->chan[ch].dch;
2172 if ((!dch) && (!bch))
2175 if (!test_bit(FLG_ACTIVE, &dch->Flags))
2178 maxlen = dch->maxlen;
2180 if (!test_bit(FLG_ACTIVE, &bch->Flags))
2183 maxlen = bch->maxlen;
2186 /* on first AND before getting next valid frame, R_FIFO must be written
2188 if (test_bit(HFC_CHIP_B410P, &hc->chip) &&
2189 (hc->chan[ch].protocol == ISDN_P_B_RAW) &&
2190 (hc->chan[ch].slot_rx < 0) &&
2191 (hc->chan[ch].slot_tx < 0))
2192 HFC_outb_nodebug(hc, R_FIFO, 0x20 | (ch << 1) | 1);
2194 HFC_outb_nodebug(hc, R_FIFO, (ch << 1) | 1);
2195 HFC_wait_nodebug(hc);
2197 /* ignore if rx is off BUT change fifo (above) to start pending TX */
2198 if (hc->chan[ch].rx_off)
2201 if (dch || test_bit(FLG_HDLC, &bch->Flags)) {
2202 f1 = HFC_inb_nodebug(hc, A_F1);
2203 while (f1 != (temp = HFC_inb_nodebug(hc, A_F1))) {
2204 if (debug & DEBUG_HFCMULTI_FIFO)
2206 "%s(card %d): reread f1 because %d!=%d\n",
2207 __func__, hc->id + 1, temp, f1);
2208 f1 = temp; /* repeat until F1 is equal */
2210 f2 = HFC_inb_nodebug(hc, A_F2);
2212 z1 = HFC_inw_nodebug(hc, A_Z1) - hc->Zmin;
2213 while (z1 != (temp = (HFC_inw_nodebug(hc, A_Z1) - hc->Zmin))) {
2214 if (debug & DEBUG_HFCMULTI_FIFO)
2215 printk(KERN_DEBUG "%s(card %d): reread z2 because "
2216 "%d!=%d\n", __func__, hc->id + 1, temp, z2);
2217 z1 = temp; /* repeat until Z1 is equal */
2219 z2 = HFC_inw_nodebug(hc, A_Z2) - hc->Zmin;
2221 if ((dch || test_bit(FLG_HDLC, &bch->Flags)) && f1 != f2)
2222 /* complete hdlc frame */
2226 /* if buffer is empty */
2231 *sp = mI_alloc_skb(maxlen + 3, GFP_ATOMIC);
2233 printk(KERN_DEBUG "%s: No mem for rx_skb\n",
2239 hc->activity[hc->chan[ch].port] = 1;
2241 /* empty fifo with what we have */
2242 if (dch || test_bit(FLG_HDLC, &bch->Flags)) {
2243 if (debug & DEBUG_HFCMULTI_FIFO)
2244 printk(KERN_DEBUG "%s(card %d): fifo(%d) reading %d "
2245 "bytes (z1=%04x, z2=%04x) HDLC %s (f1=%d, f2=%d) "
2246 "got=%d (again %d)\n", __func__, hc->id + 1, ch,
2247 Zsize, z1, z2, (f1 == f2) ? "fragment" : "COMPLETE",
2248 f1, f2, Zsize + (*sp)->len, again);
2250 if ((Zsize + (*sp)->len) > (maxlen + 3)) {
2251 if (debug & DEBUG_HFCMULTI_FIFO)
2253 "%s(card %d): hdlc-frame too large.\n",
2254 __func__, hc->id + 1);
2256 HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_RES_F);
2257 HFC_wait_nodebug(hc);
2261 hc->read_fifo(hc, skb_put(*sp, Zsize), Zsize);
2264 /* increment Z2,F2-counter */
2265 HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_INC_F);
2266 HFC_wait_nodebug(hc);
2268 if ((*sp)->len < 4) {
2269 if (debug & DEBUG_HFCMULTI_FIFO)
2271 "%s(card %d): Frame below minimum "
2272 "size\n", __func__, hc->id + 1);
2276 /* there is at least one complete frame, check crc */
2277 if ((*sp)->data[(*sp)->len - 1]) {
2278 if (debug & DEBUG_HFCMULTI_CRC)
2280 "%s: CRC-error\n", __func__);
2284 skb_trim(*sp, (*sp)->len - 3);
2285 if ((*sp)->len < MISDN_COPY_SIZE) {
2287 *sp = mI_alloc_skb(skb->len, GFP_ATOMIC);
2289 memcpy(skb_put(*sp, skb->len),
2290 skb->data, skb->len);
2293 printk(KERN_DEBUG "%s: No mem\n",
2301 if (debug & DEBUG_HFCMULTI_FIFO) {
2302 printk(KERN_DEBUG "%s(card %d):",
2303 __func__, hc->id + 1);
2305 while (temp < (*sp)->len)
2306 printk(" %02x", (*sp)->data[temp++]);
2312 recv_Bchannel(bch, MISDN_ID_ANY);
2317 /* there is an incomplete frame */
2320 if (Zsize > skb_tailroom(*sp))
2321 Zsize = skb_tailroom(*sp);
2322 hc->read_fifo(hc, skb_put(*sp, Zsize), Zsize);
2323 if (((*sp)->len) < MISDN_COPY_SIZE) {
2325 *sp = mI_alloc_skb(skb->len, GFP_ATOMIC);
2327 memcpy(skb_put(*sp, skb->len),
2328 skb->data, skb->len);
2331 printk(KERN_DEBUG "%s: No mem\n", __func__);
2338 if (debug & DEBUG_HFCMULTI_FIFO)
2340 "%s(card %d): fifo(%d) reading %d bytes "
2341 "(z1=%04x, z2=%04x) TRANS\n",
2342 __func__, hc->id + 1, ch, Zsize, z1, z2);
2343 /* only bch is transparent */
2344 recv_Bchannel(bch, hc->chan[ch].Zfill);
2354 signal_state_up(struct dchannel *dch, int info, char *msg)
2356 struct sk_buff *skb;
2357 int id, data = info;
2359 if (debug & DEBUG_HFCMULTI_STATE)
2360 printk(KERN_DEBUG "%s: %s\n", __func__, msg);
2362 id = TEI_SAPI | (GROUP_TEI << 8); /* manager address */
2364 skb = _alloc_mISDN_skb(MPH_INFORMATION_IND, id, sizeof(data), &data,
2368 recv_Dchannel_skb(dch, skb);
2372 handle_timer_irq(struct hfc_multi *hc)
2375 struct dchannel *dch;
2378 /* process queued resync jobs */
2379 if (hc->e1_resync) {
2380 /* lock, so e1_resync gets not changed */
2381 spin_lock_irqsave(&HFClock, flags);
2382 if (hc->e1_resync & 1) {
2383 if (debug & DEBUG_HFCMULTI_PLXSD)
2384 printk(KERN_DEBUG "Enable SYNC_I\n");
2385 HFC_outb(hc, R_SYNC_CTRL, V_EXT_CLK_SYNC);
2386 /* disable JATT, if RX_SYNC is set */
2387 if (test_bit(HFC_CHIP_RX_SYNC, &hc->chip))
2388 HFC_outb(hc, R_SYNC_OUT, V_SYNC_E1_RX);
2390 if (hc->e1_resync & 2) {
2391 if (debug & DEBUG_HFCMULTI_PLXSD)
2392 printk(KERN_DEBUG "Enable jatt PLL\n");
2393 HFC_outb(hc, R_SYNC_CTRL, V_SYNC_OFFS);
2395 if (hc->e1_resync & 4) {
2396 if (debug & DEBUG_HFCMULTI_PLXSD)
2398 "Enable QUARTZ for HFC-E1\n");
2399 /* set jatt to quartz */
2400 HFC_outb(hc, R_SYNC_CTRL, V_EXT_CLK_SYNC
2402 /* switch to JATT, in case it is not already */
2403 HFC_outb(hc, R_SYNC_OUT, 0);
2406 spin_unlock_irqrestore(&HFClock, flags);
2409 if (hc->ctype != HFC_TYPE_E1 || hc->e1_state == 1)
2410 for (ch = 0; ch <= 31; ch++) {
2411 if (hc->created[hc->chan[ch].port]) {
2412 hfcmulti_tx(hc, ch);
2413 /* fifo is started when switching to rx-fifo */
2414 hfcmulti_rx(hc, ch);
2415 if (hc->chan[ch].dch &&
2416 hc->chan[ch].nt_timer > -1) {
2417 dch = hc->chan[ch].dch;
2418 if (!(--hc->chan[ch].nt_timer)) {
2422 DEBUG_HFCMULTI_STATE)
2432 if (hc->ctype == HFC_TYPE_E1 && hc->created[0]) {
2433 dch = hc->chan[hc->dslot].dch;
2434 if (test_bit(HFC_CFG_REPORT_LOS, &hc->chan[hc->dslot].cfg)) {
2436 temp = HFC_inb_nodebug(hc, R_SYNC_STA) & V_SIG_LOS;
2437 if (!temp && hc->chan[hc->dslot].los)
2438 signal_state_up(dch, L1_SIGNAL_LOS_ON,
2440 if (temp && !hc->chan[hc->dslot].los)
2441 signal_state_up(dch, L1_SIGNAL_LOS_OFF,
2443 hc->chan[hc->dslot].los = temp;
2445 if (test_bit(HFC_CFG_REPORT_AIS, &hc->chan[hc->dslot].cfg)) {
2447 temp = HFC_inb_nodebug(hc, R_SYNC_STA) & V_AIS;
2448 if (!temp && hc->chan[hc->dslot].ais)
2449 signal_state_up(dch, L1_SIGNAL_AIS_ON,
2451 if (temp && !hc->chan[hc->dslot].ais)
2452 signal_state_up(dch, L1_SIGNAL_AIS_OFF,
2454 hc->chan[hc->dslot].ais = temp;
2456 if (test_bit(HFC_CFG_REPORT_SLIP, &hc->chan[hc->dslot].cfg)) {
2458 temp = HFC_inb_nodebug(hc, R_SLIP) & V_FOSLIP_RX;
2459 if (!temp && hc->chan[hc->dslot].slip_rx)
2460 signal_state_up(dch, L1_SIGNAL_SLIP_RX,
2461 " bit SLIP detected RX");
2462 hc->chan[hc->dslot].slip_rx = temp;
2463 temp = HFC_inb_nodebug(hc, R_SLIP) & V_FOSLIP_TX;
2464 if (!temp && hc->chan[hc->dslot].slip_tx)
2465 signal_state_up(dch, L1_SIGNAL_SLIP_TX,
2466 " bit SLIP detected TX");
2467 hc->chan[hc->dslot].slip_tx = temp;
2469 if (test_bit(HFC_CFG_REPORT_RDI, &hc->chan[hc->dslot].cfg)) {
2471 temp = HFC_inb_nodebug(hc, R_RX_SL0_0) & V_A;
2472 if (!temp && hc->chan[hc->dslot].rdi)
2473 signal_state_up(dch, L1_SIGNAL_RDI_ON,
2475 if (temp && !hc->chan[hc->dslot].rdi)
2476 signal_state_up(dch, L1_SIGNAL_RDI_OFF,
2478 hc->chan[hc->dslot].rdi = temp;
2480 temp = HFC_inb_nodebug(hc, R_JATT_DIR);
2481 switch (hc->chan[hc->dslot].sync) {
2483 if ((temp & 0x60) == 0x60) {
2484 if (debug & DEBUG_HFCMULTI_SYNC)
2486 "%s: (id=%d) E1 now "
2489 HFC_outb(hc, R_RX_OFF,
2490 hc->chan[hc->dslot].jitter | V_RX_INIT);
2491 HFC_outb(hc, R_TX_OFF,
2492 hc->chan[hc->dslot].jitter | V_RX_INIT);
2493 hc->chan[hc->dslot].sync = 1;
2494 goto check_framesync;
2498 if ((temp & 0x60) != 0x60) {
2499 if (debug & DEBUG_HFCMULTI_SYNC)
2502 "lost clock sync\n",
2504 hc->chan[hc->dslot].sync = 0;
2508 temp = HFC_inb_nodebug(hc, R_SYNC_STA);
2510 if (debug & DEBUG_HFCMULTI_SYNC)
2513 "now in frame sync\n",
2515 hc->chan[hc->dslot].sync = 2;
2519 if ((temp & 0x60) != 0x60) {
2520 if (debug & DEBUG_HFCMULTI_SYNC)
2522 "%s: (id=%d) E1 lost "
2523 "clock & frame sync\n",
2525 hc->chan[hc->dslot].sync = 0;
2528 temp = HFC_inb_nodebug(hc, R_SYNC_STA);
2530 if (debug & DEBUG_HFCMULTI_SYNC)
2533 "lost frame sync\n",
2535 hc->chan[hc->dslot].sync = 1;
2541 if (test_bit(HFC_CHIP_WATCHDOG, &hc->chip))
2542 hfcmulti_watchdog(hc);
2549 ph_state_irq(struct hfc_multi *hc, u_char r_irq_statech)
2551 struct dchannel *dch;
2554 u_char st_status, temp;
2557 for (ch = 0; ch <= 31; ch++) {
2558 if (hc->chan[ch].dch) {
2559 dch = hc->chan[ch].dch;
2560 if (r_irq_statech & 1) {
2561 HFC_outb_nodebug(hc, R_ST_SEL,
2563 /* undocumented: delay after R_ST_SEL */
2565 /* undocumented: status changes during read */
2566 st_status = HFC_inb_nodebug(hc, A_ST_RD_STATE);
2567 while (st_status != (temp =
2568 HFC_inb_nodebug(hc, A_ST_RD_STATE))) {
2569 if (debug & DEBUG_HFCMULTI_STATE)
2570 printk(KERN_DEBUG "%s: reread "
2571 "STATE because %d!=%d\n",
2574 st_status = temp; /* repeat */
2577 /* Speech Design TE-sync indication */
2578 if (test_bit(HFC_CHIP_PLXSD, &hc->chip) &&
2579 dch->dev.D.protocol == ISDN_P_TE_S0) {
2580 if (st_status & V_FR_SYNC_ST)
2582 (1 << hc->chan[ch].port);
2585 ~(1 << hc->chan[ch].port);
2587 dch->state = st_status & 0x0f;
2588 if (dch->dev.D.protocol == ISDN_P_NT_S0)
2592 if (dch->state == active) {
2593 HFC_outb_nodebug(hc, R_FIFO,
2595 HFC_wait_nodebug(hc);
2596 HFC_outb_nodebug(hc,
2597 R_INC_RES_FIFO, V_RES_F);
2598 HFC_wait_nodebug(hc);
2601 schedule_event(dch, FLG_PHCHANGE);
2602 if (debug & DEBUG_HFCMULTI_STATE)
2604 "%s: S/T newstate %x port %d\n",
2605 __func__, dch->state,
2608 r_irq_statech >>= 1;
2611 if (test_bit(HFC_CHIP_PLXSD, &hc->chip))
2612 plxsd_checksync(hc, 0);
2616 fifo_irq(struct hfc_multi *hc, int block)
2619 struct dchannel *dch;
2620 struct bchannel *bch;
2621 u_char r_irq_fifo_bl;
2623 r_irq_fifo_bl = HFC_inb_nodebug(hc, R_IRQ_FIFO_BL0 + block);
2626 ch = (block << 2) + (j >> 1);
2627 dch = hc->chan[ch].dch;
2628 bch = hc->chan[ch].bch;
2629 if (((!dch) && (!bch)) || (!hc->created[hc->chan[ch].port])) {
2633 if (dch && (r_irq_fifo_bl & (1 << j)) &&
2634 test_bit(FLG_ACTIVE, &dch->Flags)) {
2635 hfcmulti_tx(hc, ch);
2637 HFC_outb_nodebug(hc, R_FIFO, 0);
2638 HFC_wait_nodebug(hc);
2640 if (bch && (r_irq_fifo_bl & (1 << j)) &&
2641 test_bit(FLG_ACTIVE, &bch->Flags)) {
2642 hfcmulti_tx(hc, ch);
2644 HFC_outb_nodebug(hc, R_FIFO, 0);
2645 HFC_wait_nodebug(hc);
2648 if (dch && (r_irq_fifo_bl & (1 << j)) &&
2649 test_bit(FLG_ACTIVE, &dch->Flags)) {
2650 hfcmulti_rx(hc, ch);
2652 if (bch && (r_irq_fifo_bl & (1 << j)) &&
2653 test_bit(FLG_ACTIVE, &bch->Flags)) {
2654 hfcmulti_rx(hc, ch);
2664 hfcmulti_interrupt(int intno, void *dev_id)
2666 #ifdef IRQCOUNT_DEBUG
2667 static int iq1 = 0, iq2 = 0, iq3 = 0, iq4 = 0,
2668 iq5 = 0, iq6 = 0, iqcnt = 0;
2670 struct hfc_multi *hc = dev_id;
2671 struct dchannel *dch;
2672 u_char r_irq_statech, status, r_irq_misc, r_irq_oview;
2674 void __iomem *plx_acc;
2676 u_char e1_syncsta, temp;
2680 printk(KERN_ERR "HFC-multi: Spurious interrupt!\n");
2684 spin_lock(&hc->lock);
2688 printk(KERN_ERR "irq for card %d during irq from "
2689 "card %d, this is no bug.\n", hc->id + 1, irqsem);
2690 irqsem = hc->id + 1;
2692 #ifdef CONFIG_MISDN_HFCMULTI_8xx
2693 if (hc->immap->im_cpm.cp_pbdat & hc->pb_irqmsk)
2696 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
2697 spin_lock_irqsave(&plx_lock, flags);
2698 plx_acc = hc->plx_membase + PLX_INTCSR;
2699 wval = readw(plx_acc);
2700 spin_unlock_irqrestore(&plx_lock, flags);
2701 if (!(wval & PLX_INTCSR_LINTI1_STATUS))
2705 status = HFC_inb_nodebug(hc, R_STATUS);
2706 r_irq_statech = HFC_inb_nodebug(hc, R_IRQ_STATECH);
2707 #ifdef IRQCOUNT_DEBUG
2710 if (status & V_DTMF_STA)
2712 if (status & V_LOST_STA)
2714 if (status & V_EXT_IRQSTA)
2716 if (status & V_MISC_IRQSTA)
2718 if (status & V_FR_IRQSTA)
2720 if (iqcnt++ > 5000) {
2721 printk(KERN_ERR "iq1:%x iq2:%x iq3:%x iq4:%x iq5:%x iq6:%x\n",
2722 iq1, iq2, iq3, iq4, iq5, iq6);
2727 if (!r_irq_statech &&
2728 !(status & (V_DTMF_STA | V_LOST_STA | V_EXT_IRQSTA |
2729 V_MISC_IRQSTA | V_FR_IRQSTA))) {
2730 /* irq is not for us */
2734 if (r_irq_statech) {
2735 if (hc->ctype != HFC_TYPE_E1)
2736 ph_state_irq(hc, r_irq_statech);
2738 if (status & V_EXT_IRQSTA)
2739 ; /* external IRQ */
2740 if (status & V_LOST_STA) {
2742 HFC_outb(hc, R_INC_RES_FIFO, V_RES_LOST); /* clear irq! */
2744 if (status & V_MISC_IRQSTA) {
2746 r_irq_misc = HFC_inb_nodebug(hc, R_IRQ_MISC);
2747 r_irq_misc &= hc->hw.r_irqmsk_misc; /* ignore disabled irqs */
2748 if (r_irq_misc & V_STA_IRQ) {
2749 if (hc->ctype == HFC_TYPE_E1) {
2751 dch = hc->chan[hc->dslot].dch;
2752 e1_syncsta = HFC_inb_nodebug(hc, R_SYNC_STA);
2753 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)
2754 && hc->e1_getclock) {
2755 if (e1_syncsta & V_FR_SYNC_E1)
2756 hc->syncronized = 1;
2758 hc->syncronized = 0;
2760 /* undocumented: status changes during read */
2761 dch->state = HFC_inb_nodebug(hc, R_E1_RD_STA);
2762 while (dch->state != (temp =
2763 HFC_inb_nodebug(hc, R_E1_RD_STA))) {
2764 if (debug & DEBUG_HFCMULTI_STATE)
2765 printk(KERN_DEBUG "%s: reread "
2766 "STATE because %d!=%d\n",
2769 dch->state = temp; /* repeat */
2771 dch->state = HFC_inb_nodebug(hc, R_E1_RD_STA)
2773 schedule_event(dch, FLG_PHCHANGE);
2774 if (debug & DEBUG_HFCMULTI_STATE)
2776 "%s: E1 (id=%d) newstate %x\n",
2777 __func__, hc->id, dch->state);
2778 if (test_bit(HFC_CHIP_PLXSD, &hc->chip))
2779 plxsd_checksync(hc, 0);
2782 if (r_irq_misc & V_TI_IRQ) {
2784 mISDN_clock_update(hc->iclock, poll, NULL);
2785 handle_timer_irq(hc);
2788 if (r_irq_misc & V_DTMF_IRQ)
2791 if (r_irq_misc & V_IRQ_PROC) {
2792 static int irq_proc_cnt;
2793 if (!irq_proc_cnt++)
2794 printk(KERN_DEBUG "%s: got V_IRQ_PROC -"
2795 " this should not happen\n", __func__);
2799 if (status & V_FR_IRQSTA) {
2801 r_irq_oview = HFC_inb_nodebug(hc, R_IRQ_OVIEW);
2802 for (i = 0; i < 8; i++) {
2803 if (r_irq_oview & (1 << i))
2811 spin_unlock(&hc->lock);
2818 spin_unlock(&hc->lock);
2824 * timer callback for D-chan busy resolution. Currently no function
2828 hfcmulti_dbusy_timer(struct hfc_multi *hc)
2834 * activate/deactivate hardware for selected channels and mode
2836 * configure B-channel with the given protocol
2837 * ch eqals to the HFC-channel (0-31)
2838 * ch is the number of channel (0-4,4-7,8-11,12-15,16-19,20-23,24-27,28-31
2839 * for S/T, 1-31 for E1)
2840 * the hdlc interrupts will be set/unset
2843 mode_hfcmulti(struct hfc_multi *hc, int ch, int protocol, int slot_tx,
2844 int bank_tx, int slot_rx, int bank_rx)
2846 int flow_tx = 0, flow_rx = 0, routing = 0;
2847 int oslot_tx, oslot_rx;
2850 if (ch < 0 || ch > 31)
2852 oslot_tx = hc->chan[ch].slot_tx;
2853 oslot_rx = hc->chan[ch].slot_rx;
2854 conf = hc->chan[ch].conf;
2856 if (debug & DEBUG_HFCMULTI_MODE)
2858 "%s: card %d channel %d protocol %x slot old=%d new=%d "
2859 "bank new=%d (TX) slot old=%d new=%d bank new=%d (RX)\n",
2860 __func__, hc->id, ch, protocol, oslot_tx, slot_tx,
2861 bank_tx, oslot_rx, slot_rx, bank_rx);
2863 if (oslot_tx >= 0 && slot_tx != oslot_tx) {
2864 /* remove from slot */
2865 if (debug & DEBUG_HFCMULTI_MODE)
2866 printk(KERN_DEBUG "%s: remove from slot %d (TX)\n",
2867 __func__, oslot_tx);
2868 if (hc->slot_owner[oslot_tx << 1] == ch) {
2869 HFC_outb(hc, R_SLOT, oslot_tx << 1);
2870 HFC_outb(hc, A_SL_CFG, 0);
2871 if (hc->ctype != HFC_TYPE_XHFC)
2872 HFC_outb(hc, A_CONF, 0);
2873 hc->slot_owner[oslot_tx << 1] = -1;
2875 if (debug & DEBUG_HFCMULTI_MODE)
2877 "%s: we are not owner of this tx slot "
2878 "anymore, channel %d is.\n",
2879 __func__, hc->slot_owner[oslot_tx << 1]);
2883 if (oslot_rx >= 0 && slot_rx != oslot_rx) {
2884 /* remove from slot */
2885 if (debug & DEBUG_HFCMULTI_MODE)
2887 "%s: remove from slot %d (RX)\n",
2888 __func__, oslot_rx);
2889 if (hc->slot_owner[(oslot_rx << 1) | 1] == ch) {
2890 HFC_outb(hc, R_SLOT, (oslot_rx << 1) | V_SL_DIR);
2891 HFC_outb(hc, A_SL_CFG, 0);
2892 hc->slot_owner[(oslot_rx << 1) | 1] = -1;
2894 if (debug & DEBUG_HFCMULTI_MODE)
2896 "%s: we are not owner of this rx slot "
2897 "anymore, channel %d is.\n",
2899 hc->slot_owner[(oslot_rx << 1) | 1]);
2904 flow_tx = 0x80; /* FIFO->ST */
2905 /* disable pcm slot */
2906 hc->chan[ch].slot_tx = -1;
2907 hc->chan[ch].bank_tx = 0;
2910 if (hc->chan[ch].txpending)
2911 flow_tx = 0x80; /* FIFO->ST */
2913 flow_tx = 0xc0; /* PCM->ST */
2915 routing = bank_tx ? 0xc0 : 0x80;
2916 if (conf >= 0 || bank_tx > 1)
2917 routing = 0x40; /* loop */
2918 if (debug & DEBUG_HFCMULTI_MODE)
2919 printk(KERN_DEBUG "%s: put channel %d to slot %d bank"
2920 " %d flow %02x routing %02x conf %d (TX)\n",
2921 __func__, ch, slot_tx, bank_tx,
2922 flow_tx, routing, conf);
2923 HFC_outb(hc, R_SLOT, slot_tx << 1);
2924 HFC_outb(hc, A_SL_CFG, (ch << 1) | routing);
2925 if (hc->ctype != HFC_TYPE_XHFC)
2926 HFC_outb(hc, A_CONF,
2927 (conf < 0) ? 0 : (conf | V_CONF_SL));
2928 hc->slot_owner[slot_tx << 1] = ch;
2929 hc->chan[ch].slot_tx = slot_tx;
2930 hc->chan[ch].bank_tx = bank_tx;
2933 /* disable pcm slot */
2934 flow_rx = 0x80; /* ST->FIFO */
2935 hc->chan[ch].slot_rx = -1;
2936 hc->chan[ch].bank_rx = 0;
2939 if (hc->chan[ch].txpending)
2940 flow_rx = 0x80; /* ST->FIFO */
2942 flow_rx = 0xc0; /* ST->(FIFO,PCM) */
2944 routing = bank_rx ? 0x80 : 0xc0; /* reversed */
2945 if (conf >= 0 || bank_rx > 1)
2946 routing = 0x40; /* loop */
2947 if (debug & DEBUG_HFCMULTI_MODE)
2948 printk(KERN_DEBUG "%s: put channel %d to slot %d bank"
2949 " %d flow %02x routing %02x conf %d (RX)\n",
2950 __func__, ch, slot_rx, bank_rx,
2951 flow_rx, routing, conf);
2952 HFC_outb(hc, R_SLOT, (slot_rx << 1) | V_SL_DIR);
2953 HFC_outb(hc, A_SL_CFG, (ch << 1) | V_CH_DIR | routing);
2954 hc->slot_owner[(slot_rx << 1) | 1] = ch;
2955 hc->chan[ch].slot_rx = slot_rx;
2956 hc->chan[ch].bank_rx = bank_rx;
2961 /* disable TX fifo */
2962 HFC_outb(hc, R_FIFO, ch << 1);
2964 HFC_outb(hc, A_CON_HDLC, flow_tx | 0x00 | V_IFF);
2965 HFC_outb(hc, A_SUBCH_CFG, 0);
2966 HFC_outb(hc, A_IRQ_MSK, 0);
2967 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
2969 /* disable RX fifo */
2970 HFC_outb(hc, R_FIFO, (ch << 1) | 1);
2972 HFC_outb(hc, A_CON_HDLC, flow_rx | 0x00);
2973 HFC_outb(hc, A_SUBCH_CFG, 0);
2974 HFC_outb(hc, A_IRQ_MSK, 0);
2975 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
2977 if (hc->chan[ch].bch && hc->ctype != HFC_TYPE_E1) {
2978 hc->hw.a_st_ctrl0[hc->chan[ch].port] &=
2979 ((ch & 0x3) == 0) ? ~V_B1_EN : ~V_B2_EN;
2980 HFC_outb(hc, R_ST_SEL, hc->chan[ch].port);
2981 /* undocumented: delay after R_ST_SEL */
2983 HFC_outb(hc, A_ST_CTRL0,
2984 hc->hw.a_st_ctrl0[hc->chan[ch].port]);
2986 if (hc->chan[ch].bch) {
2987 test_and_clear_bit(FLG_HDLC, &hc->chan[ch].bch->Flags);
2988 test_and_clear_bit(FLG_TRANSPARENT,
2989 &hc->chan[ch].bch->Flags);
2992 case (ISDN_P_B_RAW): /* B-channel */
2994 if (test_bit(HFC_CHIP_B410P, &hc->chip) &&
2995 (hc->chan[ch].slot_rx < 0) &&
2996 (hc->chan[ch].slot_tx < 0)) {
2999 "Setting B-channel %d to echo cancelable "
3000 "state on PCM slot %d\n", ch,
3001 ((ch / 4) * 8) + ((ch % 4) * 4) + 1);
3003 "Enabling pass through for channel\n");
3004 vpm_out(hc, ch, ((ch / 4) * 8) +
3005 ((ch % 4) * 4) + 1, 0x01);
3008 HFC_outb(hc, R_FIFO, (ch << 1));
3010 HFC_outb(hc, A_CON_HDLC, 0xc0 | V_HDLC_TRP | V_IFF);
3011 HFC_outb(hc, R_SLOT, (((ch / 4) * 8) +
3012 ((ch % 4) * 4) + 1) << 1);
3013 HFC_outb(hc, A_SL_CFG, 0x80 | (ch << 1));
3016 HFC_outb(hc, R_FIFO, 0x20 | (ch << 1) | 1);
3018 HFC_outb(hc, A_CON_HDLC, 0x20 | V_HDLC_TRP | V_IFF);
3019 HFC_outb(hc, A_SUBCH_CFG, 0);
3020 HFC_outb(hc, A_IRQ_MSK, 0);
3021 if (hc->chan[ch].protocol != protocol) {
3022 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
3025 HFC_outb(hc, R_SLOT, ((((ch / 4) * 8) +
3026 ((ch % 4) * 4) + 1) << 1) | 1);
3027 HFC_outb(hc, A_SL_CFG, 0x80 | 0x20 | (ch << 1) | 1);
3031 HFC_outb(hc, R_FIFO, (ch << 1) | 1);
3033 HFC_outb(hc, A_CON_HDLC, 0xc0 | V_HDLC_TRP | V_IFF);
3034 HFC_outb(hc, R_SLOT, ((((ch / 4) * 8) +
3035 ((ch % 4) * 4)) << 1) | 1);
3036 HFC_outb(hc, A_SL_CFG, 0x80 | 0x40 | (ch << 1) | 1);
3039 HFC_outb(hc, R_FIFO, 0x20 | (ch << 1));
3041 HFC_outb(hc, A_CON_HDLC, 0x20 | V_HDLC_TRP | V_IFF);
3042 HFC_outb(hc, A_SUBCH_CFG, 0);
3043 HFC_outb(hc, A_IRQ_MSK, 0);
3044 if (hc->chan[ch].protocol != protocol) {
3045 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
3049 HFC_outb_nodebug(hc, A_FIFO_DATA0_NOINC, hc->silence);
3050 HFC_outb(hc, R_SLOT, (((ch / 4) * 8) +
3051 ((ch % 4) * 4)) << 1);
3052 HFC_outb(hc, A_SL_CFG, 0x80 | 0x20 | (ch << 1));
3054 /* enable TX fifo */
3055 HFC_outb(hc, R_FIFO, ch << 1);
3057 if (hc->ctype == HFC_TYPE_XHFC)
3058 HFC_outb(hc, A_CON_HDLC, flow_tx | 0x07 << 2 |
3059 V_HDLC_TRP | V_IFF);
3060 /* Enable FIFO, no interrupt */
3062 HFC_outb(hc, A_CON_HDLC, flow_tx | 0x00 |
3063 V_HDLC_TRP | V_IFF);
3064 HFC_outb(hc, A_SUBCH_CFG, 0);
3065 HFC_outb(hc, A_IRQ_MSK, 0);
3066 if (hc->chan[ch].protocol != protocol) {
3067 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
3071 HFC_outb_nodebug(hc, A_FIFO_DATA0_NOINC, hc->silence);
3072 /* enable RX fifo */
3073 HFC_outb(hc, R_FIFO, (ch << 1) | 1);
3075 if (hc->ctype == HFC_TYPE_XHFC)
3076 HFC_outb(hc, A_CON_HDLC, flow_rx | 0x07 << 2 |
3078 /* Enable FIFO, no interrupt*/
3080 HFC_outb(hc, A_CON_HDLC, flow_rx | 0x00 |
3082 HFC_outb(hc, A_SUBCH_CFG, 0);
3083 HFC_outb(hc, A_IRQ_MSK, 0);
3084 if (hc->chan[ch].protocol != protocol) {
3085 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
3089 if (hc->ctype != HFC_TYPE_E1) {
3090 hc->hw.a_st_ctrl0[hc->chan[ch].port] |=
3091 ((ch & 0x3) == 0) ? V_B1_EN : V_B2_EN;
3092 HFC_outb(hc, R_ST_SEL, hc->chan[ch].port);
3093 /* undocumented: delay after R_ST_SEL */
3095 HFC_outb(hc, A_ST_CTRL0,
3096 hc->hw.a_st_ctrl0[hc->chan[ch].port]);
3098 if (hc->chan[ch].bch)
3099 test_and_set_bit(FLG_TRANSPARENT,
3100 &hc->chan[ch].bch->Flags);
3102 case (ISDN_P_B_HDLC): /* B-channel */
3103 case (ISDN_P_TE_S0): /* D-channel */
3104 case (ISDN_P_NT_S0):
3105 case (ISDN_P_TE_E1):
3106 case (ISDN_P_NT_E1):
3107 /* enable TX fifo */
3108 HFC_outb(hc, R_FIFO, ch << 1);
3110 if (hc->ctype == HFC_TYPE_E1 || hc->chan[ch].bch) {
3111 /* E1 or B-channel */
3112 HFC_outb(hc, A_CON_HDLC, flow_tx | 0x04);
3113 HFC_outb(hc, A_SUBCH_CFG, 0);
3115 /* D-Channel without HDLC fill flags */
3116 HFC_outb(hc, A_CON_HDLC, flow_tx | 0x04 | V_IFF);
3117 HFC_outb(hc, A_SUBCH_CFG, 2);
3119 HFC_outb(hc, A_IRQ_MSK, V_IRQ);
3120 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
3122 /* enable RX fifo */
3123 HFC_outb(hc, R_FIFO, (ch << 1) | 1);
3125 HFC_outb(hc, A_CON_HDLC, flow_rx | 0x04);
3126 if (hc->ctype == HFC_TYPE_E1 || hc->chan[ch].bch)
3127 HFC_outb(hc, A_SUBCH_CFG, 0); /* full 8 bits */
3129 HFC_outb(hc, A_SUBCH_CFG, 2); /* 2 bits dchannel */
3130 HFC_outb(hc, A_IRQ_MSK, V_IRQ);
3131 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
3133 if (hc->chan[ch].bch) {
3134 test_and_set_bit(FLG_HDLC, &hc->chan[ch].bch->Flags);
3135 if (hc->ctype != HFC_TYPE_E1) {
3136 hc->hw.a_st_ctrl0[hc->chan[ch].port] |=
3137 ((ch & 0x3) == 0) ? V_B1_EN : V_B2_EN;
3138 HFC_outb(hc, R_ST_SEL, hc->chan[ch].port);
3139 /* undocumented: delay after R_ST_SEL */
3141 HFC_outb(hc, A_ST_CTRL0,
3142 hc->hw.a_st_ctrl0[hc->chan[ch].port]);
3147 printk(KERN_DEBUG "%s: protocol not known %x\n",
3148 __func__, protocol);
3149 hc->chan[ch].protocol = ISDN_P_NONE;
3150 return -ENOPROTOOPT;
3152 hc->chan[ch].protocol = protocol;
3158 * connect/disconnect PCM
3162 hfcmulti_pcm(struct hfc_multi *hc, int ch, int slot_tx, int bank_tx,
3163 int slot_rx, int bank_rx)
3165 if (slot_tx < 0 || slot_rx < 0 || bank_tx < 0 || bank_rx < 0) {
3167 mode_hfcmulti(hc, ch, hc->chan[ch].protocol, -1, 0, -1, 0);
3172 mode_hfcmulti(hc, ch, hc->chan[ch].protocol, slot_tx, bank_tx,
3177 * set/disable conference
3181 hfcmulti_conf(struct hfc_multi *hc, int ch, int num)
3183 if (num >= 0 && num <= 7)
3184 hc->chan[ch].conf = num;
3186 hc->chan[ch].conf = -1;
3187 mode_hfcmulti(hc, ch, hc->chan[ch].protocol, hc->chan[ch].slot_tx,
3188 hc->chan[ch].bank_tx, hc->chan[ch].slot_rx,
3189 hc->chan[ch].bank_rx);
3194 * set/disable sample loop
3197 /* NOTE: this function is experimental and therefore disabled */
3200 * Layer 1 callback function
3203 hfcm_l1callback(struct dchannel *dch, u_int cmd)
3205 struct hfc_multi *hc = dch->hw;
3213 /* start activation */
3214 spin_lock_irqsave(&hc->lock, flags);
3215 if (hc->ctype == HFC_TYPE_E1) {
3216 if (debug & DEBUG_HFCMULTI_MSG)
3218 "%s: HW_RESET_REQ no BRI\n",
3221 HFC_outb(hc, R_ST_SEL, hc->chan[dch->slot].port);
3222 /* undocumented: delay after R_ST_SEL */
3224 HFC_outb(hc, A_ST_WR_STATE, V_ST_LD_STA | 3); /* F3 */
3225 udelay(6); /* wait at least 5,21us */
3226 HFC_outb(hc, A_ST_WR_STATE, 3);
3227 HFC_outb(hc, A_ST_WR_STATE, 3 | (V_ST_ACT * 3));
3230 spin_unlock_irqrestore(&hc->lock, flags);
3231 l1_event(dch->l1, HW_POWERUP_IND);
3234 /* start deactivation */
3235 spin_lock_irqsave(&hc->lock, flags);
3236 if (hc->ctype == HFC_TYPE_E1) {
3237 if (debug & DEBUG_HFCMULTI_MSG)
3239 "%s: HW_DEACT_REQ no BRI\n",
3242 HFC_outb(hc, R_ST_SEL, hc->chan[dch->slot].port);
3243 /* undocumented: delay after R_ST_SEL */
3245 HFC_outb(hc, A_ST_WR_STATE, V_ST_ACT * 2);
3247 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
3249 ~(1 << hc->chan[dch->slot].port);
3250 plxsd_checksync(hc, 0);
3253 skb_queue_purge(&dch->squeue);
3255 dev_kfree_skb(dch->tx_skb);
3260 dev_kfree_skb(dch->rx_skb);
3263 test_and_clear_bit(FLG_TX_BUSY, &dch->Flags);
3264 if (test_and_clear_bit(FLG_BUSY_TIMER, &dch->Flags))
3265 del_timer(&dch->timer);
3266 spin_unlock_irqrestore(&hc->lock, flags);
3268 case HW_POWERUP_REQ:
3269 spin_lock_irqsave(&hc->lock, flags);
3270 if (hc->ctype == HFC_TYPE_E1) {
3271 if (debug & DEBUG_HFCMULTI_MSG)
3273 "%s: HW_POWERUP_REQ no BRI\n",
3276 HFC_outb(hc, R_ST_SEL, hc->chan[dch->slot].port);
3277 /* undocumented: delay after R_ST_SEL */
3279 HFC_outb(hc, A_ST_WR_STATE, 3 | 0x10); /* activate */
3280 udelay(6); /* wait at least 5,21us */
3281 HFC_outb(hc, A_ST_WR_STATE, 3); /* activate */
3283 spin_unlock_irqrestore(&hc->lock, flags);
3285 case PH_ACTIVATE_IND:
3286 test_and_set_bit(FLG_ACTIVE, &dch->Flags);
3287 _queue_data(&dch->dev.D, cmd, MISDN_ID_ANY, 0, NULL,
3290 case PH_DEACTIVATE_IND:
3291 test_and_clear_bit(FLG_ACTIVE, &dch->Flags);
3292 _queue_data(&dch->dev.D, cmd, MISDN_ID_ANY, 0, NULL,
3296 if (dch->debug & DEBUG_HW)
3297 printk(KERN_DEBUG "%s: unknown command %x\n",
3305 * Layer2 -> Layer 1 Transfer
3309 handle_dmsg(struct mISDNchannel *ch, struct sk_buff *skb)
3311 struct mISDNdevice *dev = container_of(ch, struct mISDNdevice, D);
3312 struct dchannel *dch = container_of(dev, struct dchannel, dev);
3313 struct hfc_multi *hc = dch->hw;
3314 struct mISDNhead *hh = mISDN_HEAD_P(skb);
3323 spin_lock_irqsave(&hc->lock, flags);
3324 ret = dchannel_senddata(dch, skb);
3325 if (ret > 0) { /* direct TX */
3326 id = hh->id; /* skb can be freed */
3327 hfcmulti_tx(hc, dch->slot);
3330 HFC_outb(hc, R_FIFO, 0);
3332 spin_unlock_irqrestore(&hc->lock, flags);
3333 queue_ch_frame(ch, PH_DATA_CNF, id, NULL);
3335 spin_unlock_irqrestore(&hc->lock, flags);
3337 case PH_ACTIVATE_REQ:
3338 if (dch->dev.D.protocol != ISDN_P_TE_S0) {
3339 spin_lock_irqsave(&hc->lock, flags);
3341 if (debug & DEBUG_HFCMULTI_MSG)
3343 "%s: PH_ACTIVATE port %d (0..%d)\n",
3344 __func__, hc->chan[dch->slot].port,
3346 /* start activation */
3347 if (hc->ctype == HFC_TYPE_E1) {
3348 ph_state_change(dch);
3349 if (debug & DEBUG_HFCMULTI_STATE)
3351 "%s: E1 report state %x \n",
3352 __func__, dch->state);
3354 HFC_outb(hc, R_ST_SEL,
3355 hc->chan[dch->slot].port);
3356 /* undocumented: delay after R_ST_SEL */
3358 HFC_outb(hc, A_ST_WR_STATE, V_ST_LD_STA | 1);
3360 udelay(6); /* wait at least 5,21us */
3361 HFC_outb(hc, A_ST_WR_STATE, 1);
3362 HFC_outb(hc, A_ST_WR_STATE, 1 |
3363 (V_ST_ACT * 3)); /* activate */
3366 spin_unlock_irqrestore(&hc->lock, flags);
3368 ret = l1_event(dch->l1, hh->prim);
3370 case PH_DEACTIVATE_REQ:
3371 test_and_clear_bit(FLG_L2_ACTIVATED, &dch->Flags);
3372 if (dch->dev.D.protocol != ISDN_P_TE_S0) {
3373 spin_lock_irqsave(&hc->lock, flags);
3374 if (debug & DEBUG_HFCMULTI_MSG)
3376 "%s: PH_DEACTIVATE port %d (0..%d)\n",
3377 __func__, hc->chan[dch->slot].port,
3379 /* start deactivation */
3380 if (hc->ctype == HFC_TYPE_E1) {
3381 if (debug & DEBUG_HFCMULTI_MSG)
3383 "%s: PH_DEACTIVATE no BRI\n",
3386 HFC_outb(hc, R_ST_SEL,
3387 hc->chan[dch->slot].port);
3388 /* undocumented: delay after R_ST_SEL */
3390 HFC_outb(hc, A_ST_WR_STATE, V_ST_ACT * 2);
3394 skb_queue_purge(&dch->squeue);
3396 dev_kfree_skb(dch->tx_skb);
3401 dev_kfree_skb(dch->rx_skb);
3404 test_and_clear_bit(FLG_TX_BUSY, &dch->Flags);
3405 if (test_and_clear_bit(FLG_BUSY_TIMER, &dch->Flags))
3406 del_timer(&dch->timer);
3408 if (test_and_clear_bit(FLG_L1_BUSY, &dch->Flags))
3409 dchannel_sched_event(&hc->dch, D_CLEARBUSY);
3412 spin_unlock_irqrestore(&hc->lock, flags);
3414 ret = l1_event(dch->l1, hh->prim);
3423 deactivate_bchannel(struct bchannel *bch)
3425 struct hfc_multi *hc = bch->hw;
3428 spin_lock_irqsave(&hc->lock, flags);
3429 mISDN_clear_bchannel(bch);
3430 hc->chan[bch->slot].coeff_count = 0;
3431 hc->chan[bch->slot].rx_off = 0;
3432 hc->chan[bch->slot].conf = -1;
3433 mode_hfcmulti(hc, bch->slot, ISDN_P_NONE, -1, 0, -1, 0);
3434 spin_unlock_irqrestore(&hc->lock, flags);
3438 handle_bmsg(struct mISDNchannel *ch, struct sk_buff *skb)
3440 struct bchannel *bch = container_of(ch, struct bchannel, ch);
3441 struct hfc_multi *hc = bch->hw;
3443 struct mISDNhead *hh = mISDN_HEAD_P(skb);
3451 spin_lock_irqsave(&hc->lock, flags);
3452 ret = bchannel_senddata(bch, skb);
3453 if (ret > 0) { /* direct TX */
3454 id = hh->id; /* skb can be freed */
3455 hfcmulti_tx(hc, bch->slot);
3458 HFC_outb_nodebug(hc, R_FIFO, 0);
3459 HFC_wait_nodebug(hc);
3460 if (!test_bit(FLG_TRANSPARENT, &bch->Flags)) {
3461 spin_unlock_irqrestore(&hc->lock, flags);
3462 queue_ch_frame(ch, PH_DATA_CNF, id, NULL);
3464 spin_unlock_irqrestore(&hc->lock, flags);
3466 spin_unlock_irqrestore(&hc->lock, flags);
3468 case PH_ACTIVATE_REQ:
3469 if (debug & DEBUG_HFCMULTI_MSG)
3470 printk(KERN_DEBUG "%s: PH_ACTIVATE ch %d (0..32)\n",
3471 __func__, bch->slot);
3472 spin_lock_irqsave(&hc->lock, flags);
3473 /* activate B-channel if not already activated */
3474 if (!test_and_set_bit(FLG_ACTIVE, &bch->Flags)) {
3475 hc->chan[bch->slot].txpending = 0;
3476 ret = mode_hfcmulti(hc, bch->slot,
3478 hc->chan[bch->slot].slot_tx,
3479 hc->chan[bch->slot].bank_tx,
3480 hc->chan[bch->slot].slot_rx,
3481 hc->chan[bch->slot].bank_rx);
3483 if (ch->protocol == ISDN_P_B_RAW && !hc->dtmf
3484 && test_bit(HFC_CHIP_DTMF, &hc->chip)) {
3487 if (debug & DEBUG_HFCMULTI_DTMF)
3489 "%s: start dtmf decoder\n",
3491 HFC_outb(hc, R_DTMF, hc->hw.r_dtmf |
3497 spin_unlock_irqrestore(&hc->lock, flags);
3499 _queue_data(ch, PH_ACTIVATE_IND, MISDN_ID_ANY, 0, NULL,
3502 case PH_CONTROL_REQ:
3503 spin_lock_irqsave(&hc->lock, flags);
3505 case HFC_SPL_LOOP_ON: /* set sample loop */
3506 if (debug & DEBUG_HFCMULTI_MSG)
3508 "%s: HFC_SPL_LOOP_ON (len = %d)\n",
3509 __func__, skb->len);
3512 case HFC_SPL_LOOP_OFF: /* set silence */
3513 if (debug & DEBUG_HFCMULTI_MSG)
3514 printk(KERN_DEBUG "%s: HFC_SPL_LOOP_OFF\n",
3520 "%s: unknown PH_CONTROL_REQ info %x\n",
3524 spin_unlock_irqrestore(&hc->lock, flags);
3526 case PH_DEACTIVATE_REQ:
3527 deactivate_bchannel(bch); /* locked there */
3528 _queue_data(ch, PH_DEACTIVATE_IND, MISDN_ID_ANY, 0, NULL,
3539 * bchannel control function
3542 channel_bctrl(struct bchannel *bch, struct mISDN_ctrl_req *cq)
3545 struct dsp_features *features =
3546 (struct dsp_features *)(*((u_long *)&cq->p1));
3547 struct hfc_multi *hc = bch->hw;
3555 case MISDN_CTRL_GETOP:
3556 cq->op = MISDN_CTRL_HFC_OP | MISDN_CTRL_HW_FEATURES_OP
3557 | MISDN_CTRL_RX_OFF | MISDN_CTRL_FILL_EMPTY;
3559 case MISDN_CTRL_RX_OFF: /* turn off / on rx stream */
3560 hc->chan[bch->slot].rx_off = !!cq->p1;
3561 if (!hc->chan[bch->slot].rx_off) {
3562 /* reset fifo on rx on */
3563 HFC_outb_nodebug(hc, R_FIFO, (bch->slot << 1) | 1);
3564 HFC_wait_nodebug(hc);
3565 HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_RES_F);
3566 HFC_wait_nodebug(hc);
3568 if (debug & DEBUG_HFCMULTI_MSG)
3569 printk(KERN_DEBUG "%s: RX_OFF request (nr=%d off=%d)\n",
3570 __func__, bch->nr, hc->chan[bch->slot].rx_off);
3572 case MISDN_CTRL_FILL_EMPTY: /* fill fifo, if empty */
3573 test_and_set_bit(FLG_FILLEMPTY, &bch->Flags);
3574 if (debug & DEBUG_HFCMULTI_MSG)
3575 printk(KERN_DEBUG "%s: FILL_EMPTY request (nr=%d "
3576 "off=%d)\n", __func__, bch->nr, !!cq->p1);
3578 case MISDN_CTRL_HW_FEATURES: /* fill features structure */
3579 if (debug & DEBUG_HFCMULTI_MSG)
3580 printk(KERN_DEBUG "%s: HW_FEATURE request\n",
3582 /* create confirm */
3583 features->hfc_id = hc->id;
3584 if (test_bit(HFC_CHIP_DTMF, &hc->chip))
3585 features->hfc_dtmf = 1;
3586 if (test_bit(HFC_CHIP_CONF, &hc->chip))
3587 features->hfc_conf = 1;
3588 features->hfc_loops = 0;
3589 if (test_bit(HFC_CHIP_B410P, &hc->chip)) {
3590 features->hfc_echocanhw = 1;
3592 features->pcm_id = hc->pcm;
3593 features->pcm_slots = hc->slots;
3594 features->pcm_banks = 2;
3597 case MISDN_CTRL_HFC_PCM_CONN: /* connect to pcm timeslot (0..N) */
3598 slot_tx = cq->p1 & 0xff;
3599 bank_tx = cq->p1 >> 8;
3600 slot_rx = cq->p2 & 0xff;
3601 bank_rx = cq->p2 >> 8;
3602 if (debug & DEBUG_HFCMULTI_MSG)
3604 "%s: HFC_PCM_CONN slot %d bank %d (TX) "
3605 "slot %d bank %d (RX)\n",
3606 __func__, slot_tx, bank_tx,
3608 if (slot_tx < hc->slots && bank_tx <= 2 &&
3609 slot_rx < hc->slots && bank_rx <= 2)
3610 hfcmulti_pcm(hc, bch->slot,
3611 slot_tx, bank_tx, slot_rx, bank_rx);
3614 "%s: HFC_PCM_CONN slot %d bank %d (TX) "
3615 "slot %d bank %d (RX) out of range\n",
3616 __func__, slot_tx, bank_tx,
3621 case MISDN_CTRL_HFC_PCM_DISC: /* release interface from pcm timeslot */
3622 if (debug & DEBUG_HFCMULTI_MSG)
3623 printk(KERN_DEBUG "%s: HFC_PCM_DISC\n",
3625 hfcmulti_pcm(hc, bch->slot, -1, 0, -1, 0);
3627 case MISDN_CTRL_HFC_CONF_JOIN: /* join conference (0..7) */
3628 num = cq->p1 & 0xff;
3629 if (debug & DEBUG_HFCMULTI_MSG)
3630 printk(KERN_DEBUG "%s: HFC_CONF_JOIN conf %d\n",
3633 hfcmulti_conf(hc, bch->slot, num);
3636 "%s: HW_CONF_JOIN conf %d out of range\n",
3641 case MISDN_CTRL_HFC_CONF_SPLIT: /* split conference */
3642 if (debug & DEBUG_HFCMULTI_MSG)
3643 printk(KERN_DEBUG "%s: HFC_CONF_SPLIT\n", __func__);
3644 hfcmulti_conf(hc, bch->slot, -1);
3646 case MISDN_CTRL_HFC_ECHOCAN_ON:
3647 if (debug & DEBUG_HFCMULTI_MSG)
3648 printk(KERN_DEBUG "%s: HFC_ECHOCAN_ON\n", __func__);
3649 if (test_bit(HFC_CHIP_B410P, &hc->chip))
3650 vpm_echocan_on(hc, bch->slot, cq->p1);
3655 case MISDN_CTRL_HFC_ECHOCAN_OFF:
3656 if (debug & DEBUG_HFCMULTI_MSG)
3657 printk(KERN_DEBUG "%s: HFC_ECHOCAN_OFF\n",
3659 if (test_bit(HFC_CHIP_B410P, &hc->chip))
3660 vpm_echocan_off(hc, bch->slot);
3665 printk(KERN_WARNING "%s: unknown Op %x\n",
3674 hfcm_bctrl(struct mISDNchannel *ch, u_int cmd, void *arg)
3676 struct bchannel *bch = container_of(ch, struct bchannel, ch);
3677 struct hfc_multi *hc = bch->hw;
3681 if (bch->debug & DEBUG_HW)
3682 printk(KERN_DEBUG "%s: cmd:%x %p\n",
3683 __func__, cmd, arg);
3686 test_and_clear_bit(FLG_OPEN, &bch->Flags);
3687 if (test_bit(FLG_ACTIVE, &bch->Flags))
3688 deactivate_bchannel(bch); /* locked there */
3689 ch->protocol = ISDN_P_NONE;
3691 module_put(THIS_MODULE);
3694 case CONTROL_CHANNEL:
3695 spin_lock_irqsave(&hc->lock, flags);
3696 err = channel_bctrl(bch, arg);
3697 spin_unlock_irqrestore(&hc->lock, flags);
3700 printk(KERN_WARNING "%s: unknown prim(%x)\n",
3707 * handle D-channel events
3709 * handle state change event
3712 ph_state_change(struct dchannel *dch)
3714 struct hfc_multi *hc;
3718 printk(KERN_WARNING "%s: ERROR given dch is NULL\n", __func__);
3724 if (hc->ctype == HFC_TYPE_E1) {
3725 if (dch->dev.D.protocol == ISDN_P_TE_E1) {
3726 if (debug & DEBUG_HFCMULTI_STATE)
3728 "%s: E1 TE (id=%d) newstate %x\n",
3729 __func__, hc->id, dch->state);
3731 if (debug & DEBUG_HFCMULTI_STATE)
3733 "%s: E1 NT (id=%d) newstate %x\n",
3734 __func__, hc->id, dch->state);
3736 switch (dch->state) {
3738 if (hc->e1_state != 1) {
3739 for (i = 1; i <= 31; i++) {
3740 /* reset fifos on e1 activation */
3741 HFC_outb_nodebug(hc, R_FIFO,
3743 HFC_wait_nodebug(hc);
3744 HFC_outb_nodebug(hc, R_INC_RES_FIFO,
3746 HFC_wait_nodebug(hc);
3749 test_and_set_bit(FLG_ACTIVE, &dch->Flags);
3750 _queue_data(&dch->dev.D, PH_ACTIVATE_IND,
3751 MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
3755 if (hc->e1_state != 1)
3757 test_and_clear_bit(FLG_ACTIVE, &dch->Flags);
3758 _queue_data(&dch->dev.D, PH_DEACTIVATE_IND,
3759 MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
3761 hc->e1_state = dch->state;
3763 if (dch->dev.D.protocol == ISDN_P_TE_S0) {
3764 if (debug & DEBUG_HFCMULTI_STATE)
3766 "%s: S/T TE newstate %x\n",
3767 __func__, dch->state);
3768 switch (dch->state) {
3770 l1_event(dch->l1, HW_RESET_IND);
3773 l1_event(dch->l1, HW_DEACT_IND);
3777 l1_event(dch->l1, ANYSIGNAL);
3780 l1_event(dch->l1, INFO2);
3783 l1_event(dch->l1, INFO4_P8);
3787 if (debug & DEBUG_HFCMULTI_STATE)
3788 printk(KERN_DEBUG "%s: S/T NT newstate %x\n",
3789 __func__, dch->state);
3790 switch (dch->state) {
3792 if (hc->chan[ch].nt_timer == 0) {
3793 hc->chan[ch].nt_timer = -1;
3794 HFC_outb(hc, R_ST_SEL,
3796 /* undocumented: delay after R_ST_SEL */
3798 HFC_outb(hc, A_ST_WR_STATE, 4 |
3799 V_ST_LD_STA); /* G4 */
3800 udelay(6); /* wait at least 5,21us */
3801 HFC_outb(hc, A_ST_WR_STATE, 4);
3804 /* one extra count for the next event */
3805 hc->chan[ch].nt_timer =
3806 nt_t1_count[poll_timer] + 1;
3807 HFC_outb(hc, R_ST_SEL,
3809 /* undocumented: delay after R_ST_SEL */
3811 /* allow G2 -> G3 transition */
3812 HFC_outb(hc, A_ST_WR_STATE, 2 |
3817 hc->chan[ch].nt_timer = -1;
3818 test_and_clear_bit(FLG_ACTIVE, &dch->Flags);
3819 _queue_data(&dch->dev.D, PH_DEACTIVATE_IND,
3820 MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
3823 hc->chan[ch].nt_timer = -1;
3826 hc->chan[ch].nt_timer = -1;
3827 test_and_set_bit(FLG_ACTIVE, &dch->Flags);
3828 _queue_data(&dch->dev.D, PH_ACTIVATE_IND,
3829 MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
3837 * called for card mode init message
3841 hfcmulti_initmode(struct dchannel *dch)
3843 struct hfc_multi *hc = dch->hw;
3844 u_char a_st_wr_state, r_e1_wr_sta;
3847 if (debug & DEBUG_HFCMULTI_INIT)
3848 printk(KERN_DEBUG "%s: entered\n", __func__);
3850 if (hc->ctype == HFC_TYPE_E1) {
3851 hc->chan[hc->dslot].slot_tx = -1;
3852 hc->chan[hc->dslot].slot_rx = -1;
3853 hc->chan[hc->dslot].conf = -1;
3855 mode_hfcmulti(hc, hc->dslot, dch->dev.D.protocol,
3857 dch->timer.function = (void *) hfcmulti_dbusy_timer;
3858 dch->timer.data = (long) dch;
3859 init_timer(&dch->timer);
3861 for (i = 1; i <= 31; i++) {
3864 hc->chan[i].slot_tx = -1;
3865 hc->chan[i].slot_rx = -1;
3866 hc->chan[i].conf = -1;
3867 mode_hfcmulti(hc, i, ISDN_P_NONE, -1, 0, -1, 0);
3870 if (test_bit(HFC_CFG_REPORT_LOS, &hc->chan[hc->dslot].cfg)) {
3871 HFC_outb(hc, R_LOS0, 255); /* 2 ms */
3872 HFC_outb(hc, R_LOS1, 255); /* 512 ms */
3874 if (test_bit(HFC_CFG_OPTICAL, &hc->chan[hc->dslot].cfg)) {
3875 HFC_outb(hc, R_RX0, 0);
3876 hc->hw.r_tx0 = 0 | V_OUT_EN;
3878 HFC_outb(hc, R_RX0, 1);
3879 hc->hw.r_tx0 = 1 | V_OUT_EN;
3881 hc->hw.r_tx1 = V_ATX | V_NTRI;
3882 HFC_outb(hc, R_TX0, hc->hw.r_tx0);
3883 HFC_outb(hc, R_TX1, hc->hw.r_tx1);
3884 HFC_outb(hc, R_TX_FR0, 0x00);
3885 HFC_outb(hc, R_TX_FR1, 0xf8);
3887 if (test_bit(HFC_CFG_CRC4, &hc->chan[hc->dslot].cfg))
3888 HFC_outb(hc, R_TX_FR2, V_TX_MF | V_TX_E | V_NEG_E);
3890 HFC_outb(hc, R_RX_FR0, V_AUTO_RESYNC | V_AUTO_RECO | 0);
3892 if (test_bit(HFC_CFG_CRC4, &hc->chan[hc->dslot].cfg))
3893 HFC_outb(hc, R_RX_FR1, V_RX_MF | V_RX_MF_SYNC);
3895 if (dch->dev.D.protocol == ISDN_P_NT_E1) {
3896 if (debug & DEBUG_HFCMULTI_INIT)
3897 printk(KERN_DEBUG "%s: E1 port is NT-mode\n",
3899 r_e1_wr_sta = 0; /* G0 */
3900 hc->e1_getclock = 0;
3902 if (debug & DEBUG_HFCMULTI_INIT)
3903 printk(KERN_DEBUG "%s: E1 port is TE-mode\n",
3905 r_e1_wr_sta = 0; /* F0 */
3906 hc->e1_getclock = 1;
3908 if (test_bit(HFC_CHIP_RX_SYNC, &hc->chip))
3909 HFC_outb(hc, R_SYNC_OUT, V_SYNC_E1_RX);
3911 HFC_outb(hc, R_SYNC_OUT, 0);
3912 if (test_bit(HFC_CHIP_E1CLOCK_GET, &hc->chip))
3913 hc->e1_getclock = 1;
3914 if (test_bit(HFC_CHIP_E1CLOCK_PUT, &hc->chip))
3915 hc->e1_getclock = 0;
3916 if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) {
3917 /* SLAVE (clock master) */
3918 if (debug & DEBUG_HFCMULTI_INIT)
3920 "%s: E1 port is clock master "
3921 "(clock from PCM)\n", __func__);
3922 HFC_outb(hc, R_SYNC_CTRL, V_EXT_CLK_SYNC | V_PCM_SYNC);
3924 if (hc->e1_getclock) {
3925 /* MASTER (clock slave) */
3926 if (debug & DEBUG_HFCMULTI_INIT)
3928 "%s: E1 port is clock slave "
3929 "(clock to PCM)\n", __func__);
3930 HFC_outb(hc, R_SYNC_CTRL, V_SYNC_OFFS);
3932 /* MASTER (clock master) */
3933 if (debug & DEBUG_HFCMULTI_INIT)
3934 printk(KERN_DEBUG "%s: E1 port is "
3936 "(clock from QUARTZ)\n",
3938 HFC_outb(hc, R_SYNC_CTRL, V_EXT_CLK_SYNC |
3939 V_PCM_SYNC | V_JATT_OFF);
3940 HFC_outb(hc, R_SYNC_OUT, 0);
3943 HFC_outb(hc, R_JATT_ATT, 0x9c); /* undoc register */
3944 HFC_outb(hc, R_PWM_MD, V_PWM0_MD);
3945 HFC_outb(hc, R_PWM0, 0x50);
3946 HFC_outb(hc, R_PWM1, 0xff);
3947 /* state machine setup */
3948 HFC_outb(hc, R_E1_WR_STA, r_e1_wr_sta | V_E1_LD_STA);
3949 udelay(6); /* wait at least 5,21us */
3950 HFC_outb(hc, R_E1_WR_STA, r_e1_wr_sta);
3951 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
3952 hc->syncronized = 0;
3953 plxsd_checksync(hc, 0);
3957 hc->chan[i].slot_tx = -1;
3958 hc->chan[i].slot_rx = -1;
3959 hc->chan[i].conf = -1;
3960 mode_hfcmulti(hc, i, dch->dev.D.protocol, -1, 0, -1, 0);
3961 dch->timer.function = (void *)hfcmulti_dbusy_timer;
3962 dch->timer.data = (long) dch;
3963 init_timer(&dch->timer);
3964 hc->chan[i - 2].slot_tx = -1;
3965 hc->chan[i - 2].slot_rx = -1;
3966 hc->chan[i - 2].conf = -1;
3967 mode_hfcmulti(hc, i - 2, ISDN_P_NONE, -1, 0, -1, 0);
3968 hc->chan[i - 1].slot_tx = -1;
3969 hc->chan[i - 1].slot_rx = -1;
3970 hc->chan[i - 1].conf = -1;
3971 mode_hfcmulti(hc, i - 1, ISDN_P_NONE, -1, 0, -1, 0);
3973 pt = hc->chan[i].port;
3974 /* select interface */
3975 HFC_outb(hc, R_ST_SEL, pt);
3976 /* undocumented: delay after R_ST_SEL */
3978 if (dch->dev.D.protocol == ISDN_P_NT_S0) {
3979 if (debug & DEBUG_HFCMULTI_INIT)
3981 "%s: ST port %d is NT-mode\n",
3984 HFC_outb(hc, A_ST_CLK_DLY, clockdelay_nt);
3985 a_st_wr_state = 1; /* G1 */
3986 hc->hw.a_st_ctrl0[pt] = V_ST_MD;
3988 if (debug & DEBUG_HFCMULTI_INIT)
3990 "%s: ST port %d is TE-mode\n",
3993 HFC_outb(hc, A_ST_CLK_DLY, clockdelay_te);
3994 a_st_wr_state = 2; /* F2 */
3995 hc->hw.a_st_ctrl0[pt] = 0;
3997 if (!test_bit(HFC_CFG_NONCAP_TX, &hc->chan[i].cfg))
3998 hc->hw.a_st_ctrl0[pt] |= V_TX_LI;
3999 if (hc->ctype == HFC_TYPE_XHFC) {
4000 hc->hw.a_st_ctrl0[pt] |= 0x40 /* V_ST_PU_CTRL */;
4001 HFC_outb(hc, 0x35 /* A_ST_CTRL3 */,
4002 0x7c << 1 /* V_ST_PULSE */);
4005 HFC_outb(hc, A_ST_CTRL0, hc->hw.a_st_ctrl0[pt]);
4006 /* disable E-channel */
4007 if ((dch->dev.D.protocol == ISDN_P_NT_S0) ||
4008 test_bit(HFC_CFG_DIS_ECHANNEL, &hc->chan[i].cfg))
4009 HFC_outb(hc, A_ST_CTRL1, V_E_IGNO);
4011 HFC_outb(hc, A_ST_CTRL1, 0);
4012 /* enable B-channel receive */
4013 HFC_outb(hc, A_ST_CTRL2, V_B1_RX_EN | V_B2_RX_EN);
4014 /* state machine setup */
4015 HFC_outb(hc, A_ST_WR_STATE, a_st_wr_state | V_ST_LD_STA);
4016 udelay(6); /* wait at least 5,21us */
4017 HFC_outb(hc, A_ST_WR_STATE, a_st_wr_state);
4018 hc->hw.r_sci_msk |= 1 << pt;
4019 /* state machine interrupts */
4020 HFC_outb(hc, R_SCI_MSK, hc->hw.r_sci_msk);
4021 /* unset sync on port */
4022 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
4024 ~(1 << hc->chan[dch->slot].port);
4025 plxsd_checksync(hc, 0);
4028 if (debug & DEBUG_HFCMULTI_INIT)
4029 printk("%s: done\n", __func__);
4034 open_dchannel(struct hfc_multi *hc, struct dchannel *dch,
4035 struct channel_req *rq)
4040 if (debug & DEBUG_HW_OPEN)
4041 printk(KERN_DEBUG "%s: dev(%d) open from %p\n", __func__,
4042 dch->dev.id, __builtin_return_address(0));
4043 if (rq->protocol == ISDN_P_NONE)
4045 if ((dch->dev.D.protocol != ISDN_P_NONE) &&
4046 (dch->dev.D.protocol != rq->protocol)) {
4047 if (debug & DEBUG_HFCMULTI_MODE)
4048 printk(KERN_DEBUG "%s: change protocol %x to %x\n",
4049 __func__, dch->dev.D.protocol, rq->protocol);
4051 if ((dch->dev.D.protocol == ISDN_P_TE_S0) &&
4052 (rq->protocol != ISDN_P_TE_S0))
4053 l1_event(dch->l1, CLOSE_CHANNEL);
4054 if (dch->dev.D.protocol != rq->protocol) {
4055 if (rq->protocol == ISDN_P_TE_S0) {
4056 err = create_l1(dch, hfcm_l1callback);
4060 dch->dev.D.protocol = rq->protocol;
4061 spin_lock_irqsave(&hc->lock, flags);
4062 hfcmulti_initmode(dch);
4063 spin_unlock_irqrestore(&hc->lock, flags);
4065 if (test_bit(FLG_ACTIVE, &dch->Flags))
4066 _queue_data(&dch->dev.D, PH_ACTIVATE_IND, MISDN_ID_ANY,
4067 0, NULL, GFP_KERNEL);
4068 rq->ch = &dch->dev.D;
4069 if (!try_module_get(THIS_MODULE))
4070 printk(KERN_WARNING "%s:cannot get module\n", __func__);
4075 open_bchannel(struct hfc_multi *hc, struct dchannel *dch,
4076 struct channel_req *rq)
4078 struct bchannel *bch;
4081 if (!test_channelmap(rq->adr.channel, dch->dev.channelmap))
4083 if (rq->protocol == ISDN_P_NONE)
4085 if (hc->ctype == HFC_TYPE_E1)
4086 ch = rq->adr.channel;
4088 ch = (rq->adr.channel - 1) + (dch->slot - 2);
4089 bch = hc->chan[ch].bch;
4091 printk(KERN_ERR "%s:internal error ch %d has no bch\n",
4095 if (test_and_set_bit(FLG_OPEN, &bch->Flags))
4096 return -EBUSY; /* b-channel can be only open once */
4097 test_and_clear_bit(FLG_FILLEMPTY, &bch->Flags);
4098 bch->ch.protocol = rq->protocol;
4099 hc->chan[ch].rx_off = 0;
4101 if (!try_module_get(THIS_MODULE))
4102 printk(KERN_WARNING "%s:cannot get module\n", __func__);
4107 * device control function
4110 channel_dctrl(struct dchannel *dch, struct mISDN_ctrl_req *cq)
4112 struct hfc_multi *hc = dch->hw;
4114 int wd_mode, wd_cnt;
4117 case MISDN_CTRL_GETOP:
4118 cq->op = MISDN_CTRL_HFC_OP;
4120 case MISDN_CTRL_HFC_WD_INIT: /* init the watchdog */
4121 wd_cnt = cq->p1 & 0xf;
4122 wd_mode = !!(cq->p1 >> 4);
4123 if (debug & DEBUG_HFCMULTI_MSG)
4124 printk(KERN_DEBUG "%s: MISDN_CTRL_HFC_WD_INIT mode %s"
4125 ", counter 0x%x\n", __func__,
4126 wd_mode ? "AUTO" : "MANUAL", wd_cnt);
4127 /* set the watchdog timer */
4128 HFC_outb(hc, R_TI_WD, poll_timer | (wd_cnt << 4));
4129 hc->hw.r_bert_wd_md = (wd_mode ? V_AUTO_WD_RES : 0);
4130 if (hc->ctype == HFC_TYPE_XHFC)
4131 hc->hw.r_bert_wd_md |= 0x40 /* V_WD_EN */;
4132 /* init the watchdog register and reset the counter */
4133 HFC_outb(hc, R_BERT_WD_MD, hc->hw.r_bert_wd_md | V_WD_RES);
4134 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
4135 /* enable the watchdog output for Speech-Design */
4136 HFC_outb(hc, R_GPIO_SEL, V_GPIO_SEL7);
4137 HFC_outb(hc, R_GPIO_EN1, V_GPIO_EN15);
4138 HFC_outb(hc, R_GPIO_OUT1, 0);
4139 HFC_outb(hc, R_GPIO_OUT1, V_GPIO_OUT15);
4142 case MISDN_CTRL_HFC_WD_RESET: /* reset the watchdog counter */
4143 if (debug & DEBUG_HFCMULTI_MSG)
4144 printk(KERN_DEBUG "%s: MISDN_CTRL_HFC_WD_RESET\n",
4146 HFC_outb(hc, R_BERT_WD_MD, hc->hw.r_bert_wd_md | V_WD_RES);
4149 printk(KERN_WARNING "%s: unknown Op %x\n",
4158 hfcm_dctrl(struct mISDNchannel *ch, u_int cmd, void *arg)
4160 struct mISDNdevice *dev = container_of(ch, struct mISDNdevice, D);
4161 struct dchannel *dch = container_of(dev, struct dchannel, dev);
4162 struct hfc_multi *hc = dch->hw;
4163 struct channel_req *rq;
4167 if (dch->debug & DEBUG_HW)
4168 printk(KERN_DEBUG "%s: cmd:%x %p\n",
4169 __func__, cmd, arg);
4173 switch (rq->protocol) {
4176 if (hc->ctype == HFC_TYPE_E1) {
4180 err = open_dchannel(hc, dch, rq); /* locked there */
4184 if (hc->ctype != HFC_TYPE_E1) {
4188 err = open_dchannel(hc, dch, rq); /* locked there */
4191 spin_lock_irqsave(&hc->lock, flags);
4192 err = open_bchannel(hc, dch, rq);
4193 spin_unlock_irqrestore(&hc->lock, flags);
4197 if (debug & DEBUG_HW_OPEN)
4198 printk(KERN_DEBUG "%s: dev(%d) close from %p\n",
4199 __func__, dch->dev.id,
4200 __builtin_return_address(0));
4201 module_put(THIS_MODULE);
4203 case CONTROL_CHANNEL:
4204 spin_lock_irqsave(&hc->lock, flags);
4205 err = channel_dctrl(dch, arg);
4206 spin_unlock_irqrestore(&hc->lock, flags);
4209 if (dch->debug & DEBUG_HW)
4210 printk(KERN_DEBUG "%s: unknown command %x\n",
4218 clockctl(void *priv, int enable)
4220 struct hfc_multi *hc = priv;
4222 hc->iclock_on = enable;
4227 * initialize the card
4231 * start timer irq, wait some time and check if we have interrupts.
4232 * if not, reset chip and try again.
4235 init_card(struct hfc_multi *hc)
4239 void __iomem *plx_acc;
4242 if (debug & DEBUG_HFCMULTI_INIT)
4243 printk(KERN_DEBUG "%s: entered\n", __func__);
4245 spin_lock_irqsave(&hc->lock, flags);
4246 /* set interrupts but leave global interrupt disabled */
4247 hc->hw.r_irq_ctrl = V_FIFO_IRQ;
4249 spin_unlock_irqrestore(&hc->lock, flags);
4251 if (request_irq(hc->irq, hfcmulti_interrupt, IRQF_SHARED,
4253 printk(KERN_WARNING "mISDN: Could not get interrupt %d.\n",
4259 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
4260 spin_lock_irqsave(&plx_lock, plx_flags);
4261 plx_acc = hc->plx_membase + PLX_INTCSR;
4262 writew((PLX_INTCSR_PCIINT_ENABLE | PLX_INTCSR_LINTI1_ENABLE),
4263 plx_acc); /* enable PCI & LINT1 irq */
4264 spin_unlock_irqrestore(&plx_lock, plx_flags);
4267 if (debug & DEBUG_HFCMULTI_INIT)
4268 printk(KERN_DEBUG "%s: IRQ %d count %d\n",
4269 __func__, hc->irq, hc->irqcnt);
4270 err = init_chip(hc);
4274 * Finally enable IRQ output
4275 * this is only allowed, if an IRQ routine is already
4276 * established for this HFC, so don't do that earlier
4278 spin_lock_irqsave(&hc->lock, flags);
4280 spin_unlock_irqrestore(&hc->lock, flags);
4281 /* printk(KERN_DEBUG "no master irq set!!!\n"); */
4282 set_current_state(TASK_UNINTERRUPTIBLE);
4283 schedule_timeout((100 * HZ) / 1000); /* Timeout 100ms */
4284 /* turn IRQ off until chip is completely initialized */
4285 spin_lock_irqsave(&hc->lock, flags);
4287 spin_unlock_irqrestore(&hc->lock, flags);
4288 if (debug & DEBUG_HFCMULTI_INIT)
4289 printk(KERN_DEBUG "%s: IRQ %d count %d\n",
4290 __func__, hc->irq, hc->irqcnt);
4292 if (debug & DEBUG_HFCMULTI_INIT)
4293 printk(KERN_DEBUG "%s: done\n", __func__);
4297 if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) {
4298 printk(KERN_INFO "ignoring missing interrupts\n");
4302 printk(KERN_ERR "HFC PCI: IRQ(%d) getting no interrupts during init.\n",
4308 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
4309 spin_lock_irqsave(&plx_lock, plx_flags);
4310 plx_acc = hc->plx_membase + PLX_INTCSR;
4311 writew(0x00, plx_acc); /*disable IRQs*/
4312 spin_unlock_irqrestore(&plx_lock, plx_flags);
4315 if (debug & DEBUG_HFCMULTI_INIT)
4316 printk(KERN_DEBUG "%s: free irq %d\n", __func__, hc->irq);
4318 free_irq(hc->irq, hc);
4322 if (debug & DEBUG_HFCMULTI_INIT)
4323 printk(KERN_DEBUG "%s: done (err=%d)\n", __func__, err);
4328 * find pci device and set it up
4332 setup_pci(struct hfc_multi *hc, struct pci_dev *pdev,
4333 const struct pci_device_id *ent)
4335 struct hm_map *m = (struct hm_map *)ent->driver_data;
4338 "HFC-multi: card manufacturer: '%s' card name: '%s' clock: %s\n",
4339 m->vendor_name, m->card_name, m->clock2 ? "double" : "normal");
4343 test_and_set_bit(HFC_CHIP_CLOCK2, &hc->chip);
4345 if (ent->device == 0xB410) {
4346 test_and_set_bit(HFC_CHIP_B410P, &hc->chip);
4347 test_and_set_bit(HFC_CHIP_PCM_MASTER, &hc->chip);
4348 test_and_clear_bit(HFC_CHIP_PCM_SLAVE, &hc->chip);
4352 if (hc->pci_dev->irq <= 0) {
4353 printk(KERN_WARNING "HFC-multi: No IRQ for PCI card found.\n");
4356 if (pci_enable_device(hc->pci_dev)) {
4357 printk(KERN_WARNING "HFC-multi: Error enabling PCI card.\n");
4361 hc->ledstate = 0xAFFEAFFE;
4362 hc->opticalsupport = m->opticalsupport;
4365 hc->pci_membase = NULL;
4366 hc->plx_membase = NULL;
4368 /* set memory access methods */
4369 if (m->io_mode) /* use mode from card config */
4370 hc->io_mode = m->io_mode;
4371 switch (hc->io_mode) {
4372 case HFC_IO_MODE_PLXSD:
4373 test_and_set_bit(HFC_CHIP_PLXSD, &hc->chip);
4374 hc->slots = 128; /* required */
4375 hc->HFC_outb = HFC_outb_pcimem;
4376 hc->HFC_inb = HFC_inb_pcimem;
4377 hc->HFC_inw = HFC_inw_pcimem;
4378 hc->HFC_wait = HFC_wait_pcimem;
4379 hc->read_fifo = read_fifo_pcimem;
4380 hc->write_fifo = write_fifo_pcimem;
4381 hc->plx_origmembase = hc->pci_dev->resource[0].start;
4382 /* MEMBASE 1 is PLX PCI Bridge */
4384 if (!hc->plx_origmembase) {
4386 "HFC-multi: No IO-Memory for PCI PLX bridge found\n");
4387 pci_disable_device(hc->pci_dev);
4391 hc->plx_membase = ioremap(hc->plx_origmembase, 0x80);
4392 if (!hc->plx_membase) {
4394 "HFC-multi: failed to remap plx address space. "
4395 "(internal error)\n");
4396 pci_disable_device(hc->pci_dev);
4400 "HFC-multi: plx_membase:%#lx plx_origmembase:%#lx\n",
4401 (u_long)hc->plx_membase, hc->plx_origmembase);
4403 hc->pci_origmembase = hc->pci_dev->resource[2].start;
4404 /* MEMBASE 1 is PLX PCI Bridge */
4405 if (!hc->pci_origmembase) {
4407 "HFC-multi: No IO-Memory for PCI card found\n");
4408 pci_disable_device(hc->pci_dev);
4412 hc->pci_membase = ioremap(hc->pci_origmembase, 0x400);
4413 if (!hc->pci_membase) {
4414 printk(KERN_WARNING "HFC-multi: failed to remap io "
4415 "address space. (internal error)\n");
4416 pci_disable_device(hc->pci_dev);
4421 "card %d: defined at MEMBASE %#lx (%#lx) IRQ %d HZ %d "
4423 hc->id, (u_long)hc->pci_membase, hc->pci_origmembase,
4424 hc->pci_dev->irq, HZ, hc->leds);
4425 pci_write_config_word(hc->pci_dev, PCI_COMMAND, PCI_ENA_MEMIO);
4427 case HFC_IO_MODE_PCIMEM:
4428 hc->HFC_outb = HFC_outb_pcimem;
4429 hc->HFC_inb = HFC_inb_pcimem;
4430 hc->HFC_inw = HFC_inw_pcimem;
4431 hc->HFC_wait = HFC_wait_pcimem;
4432 hc->read_fifo = read_fifo_pcimem;
4433 hc->write_fifo = write_fifo_pcimem;
4434 hc->pci_origmembase = hc->pci_dev->resource[1].start;
4435 if (!hc->pci_origmembase) {
4437 "HFC-multi: No IO-Memory for PCI card found\n");
4438 pci_disable_device(hc->pci_dev);
4442 hc->pci_membase = ioremap(hc->pci_origmembase, 256);
4443 if (!hc->pci_membase) {
4445 "HFC-multi: failed to remap io address space. "
4446 "(internal error)\n");
4447 pci_disable_device(hc->pci_dev);
4450 printk(KERN_INFO "card %d: defined at MEMBASE %#lx (%#lx) IRQ "
4451 "%d HZ %d leds-type %d\n", hc->id, (u_long)hc->pci_membase,
4452 hc->pci_origmembase, hc->pci_dev->irq, HZ, hc->leds);
4453 pci_write_config_word(hc->pci_dev, PCI_COMMAND, PCI_ENA_MEMIO);
4455 case HFC_IO_MODE_REGIO:
4456 hc->HFC_outb = HFC_outb_regio;
4457 hc->HFC_inb = HFC_inb_regio;
4458 hc->HFC_inw = HFC_inw_regio;
4459 hc->HFC_wait = HFC_wait_regio;
4460 hc->read_fifo = read_fifo_regio;
4461 hc->write_fifo = write_fifo_regio;
4462 hc->pci_iobase = (u_int) hc->pci_dev->resource[0].start;
4463 if (!hc->pci_iobase) {
4465 "HFC-multi: No IO for PCI card found\n");
4466 pci_disable_device(hc->pci_dev);
4470 if (!request_region(hc->pci_iobase, 8, "hfcmulti")) {
4471 printk(KERN_WARNING "HFC-multi: failed to request "
4472 "address space at 0x%08lx (internal error)\n",
4474 pci_disable_device(hc->pci_dev);
4479 "%s %s: defined at IOBASE %#x IRQ %d HZ %d leds-type %d\n",
4480 m->vendor_name, m->card_name, (u_int) hc->pci_iobase,
4481 hc->pci_dev->irq, HZ, hc->leds);
4482 pci_write_config_word(hc->pci_dev, PCI_COMMAND, PCI_ENA_REGIO);
4485 printk(KERN_WARNING "HFC-multi: Invalid IO mode.\n");
4486 pci_disable_device(hc->pci_dev);
4490 pci_set_drvdata(hc->pci_dev, hc);
4492 /* At this point the needed PCI config is done */
4493 /* fifos are still not enabled */
4503 release_port(struct hfc_multi *hc, struct dchannel *dch)
4507 struct bchannel *pb;
4510 pt = hc->chan[ci].port;
4512 if (debug & DEBUG_HFCMULTI_INIT)
4513 printk(KERN_DEBUG "%s: entered for port %d\n",
4516 if (pt >= hc->ports) {
4517 printk(KERN_WARNING "%s: ERROR port out of range (%d).\n",
4522 if (debug & DEBUG_HFCMULTI_INIT)
4523 printk(KERN_DEBUG "%s: releasing port=%d\n",
4526 if (dch->dev.D.protocol == ISDN_P_TE_S0)
4527 l1_event(dch->l1, CLOSE_CHANNEL);
4529 hc->chan[ci].dch = NULL;
4531 if (hc->created[pt]) {
4532 hc->created[pt] = 0;
4533 mISDN_unregister_device(&dch->dev);
4536 spin_lock_irqsave(&hc->lock, flags);
4538 if (dch->timer.function) {
4539 del_timer(&dch->timer);
4540 dch->timer.function = NULL;
4543 if (hc->ctype == HFC_TYPE_E1) { /* E1 */
4545 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
4546 hc->syncronized = 0;
4547 plxsd_checksync(hc, 1);
4550 for (i = 0; i <= 31; i++) {
4551 if (hc->chan[i].bch) {
4552 if (debug & DEBUG_HFCMULTI_INIT)
4554 "%s: free port %d channel %d\n",
4555 __func__, hc->chan[i].port + 1, i);
4556 pb = hc->chan[i].bch;
4557 hc->chan[i].bch = NULL;
4558 spin_unlock_irqrestore(&hc->lock, flags);
4559 mISDN_freebchannel(pb);
4561 kfree(hc->chan[i].coeff);
4562 spin_lock_irqsave(&hc->lock, flags);
4567 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
4569 ~(1 << hc->chan[ci].port);
4570 plxsd_checksync(hc, 1);
4573 if (hc->chan[ci - 2].bch) {
4574 if (debug & DEBUG_HFCMULTI_INIT)
4576 "%s: free port %d channel %d\n",
4577 __func__, hc->chan[ci - 2].port + 1,
4579 pb = hc->chan[ci - 2].bch;
4580 hc->chan[ci - 2].bch = NULL;
4581 spin_unlock_irqrestore(&hc->lock, flags);
4582 mISDN_freebchannel(pb);
4584 kfree(hc->chan[ci - 2].coeff);
4585 spin_lock_irqsave(&hc->lock, flags);
4587 if (hc->chan[ci - 1].bch) {
4588 if (debug & DEBUG_HFCMULTI_INIT)
4590 "%s: free port %d channel %d\n",
4591 __func__, hc->chan[ci - 1].port + 1,
4593 pb = hc->chan[ci - 1].bch;
4594 hc->chan[ci - 1].bch = NULL;
4595 spin_unlock_irqrestore(&hc->lock, flags);
4596 mISDN_freebchannel(pb);
4598 kfree(hc->chan[ci - 1].coeff);
4599 spin_lock_irqsave(&hc->lock, flags);
4603 spin_unlock_irqrestore(&hc->lock, flags);
4605 if (debug & DEBUG_HFCMULTI_INIT)
4606 printk(KERN_DEBUG "%s: free port %d channel D\n", __func__, pt);
4607 mISDN_freedchannel(dch);
4610 if (debug & DEBUG_HFCMULTI_INIT)
4611 printk(KERN_DEBUG "%s: done!\n", __func__);
4615 release_card(struct hfc_multi *hc)
4620 if (debug & DEBUG_HFCMULTI_INIT)
4621 printk(KERN_DEBUG "%s: release card (%d) entered\n",
4624 /* unregister clock source */
4626 mISDN_unregister_clock(hc->iclock);
4629 spin_lock_irqsave(&hc->lock, flags);
4631 spin_unlock_irqrestore(&hc->lock, flags);
4638 /* disable D-channels & B-channels */
4639 if (debug & DEBUG_HFCMULTI_INIT)
4640 printk(KERN_DEBUG "%s: disable all channels (d and b)\n",
4642 for (ch = 0; ch <= 31; ch++) {
4643 if (hc->chan[ch].dch)
4644 release_port(hc, hc->chan[ch].dch);
4647 /* release hardware & irq */
4649 if (debug & DEBUG_HFCMULTI_INIT)
4650 printk(KERN_DEBUG "%s: free irq %d\n",
4652 free_irq(hc->irq, hc);
4656 release_io_hfcmulti(hc);
4658 if (debug & DEBUG_HFCMULTI_INIT)
4659 printk(KERN_DEBUG "%s: remove instance from list\n",
4661 list_del(&hc->list);
4663 if (debug & DEBUG_HFCMULTI_INIT)
4664 printk(KERN_DEBUG "%s: delete instance\n", __func__);
4665 if (hc == syncmaster)
4668 if (debug & DEBUG_HFCMULTI_INIT)
4669 printk(KERN_DEBUG "%s: card successfully removed\n",
4674 init_e1_port(struct hfc_multi *hc, struct hm_map *m)
4676 struct dchannel *dch;
4677 struct bchannel *bch;
4679 char name[MISDN_MAX_IDLEN];
4681 dch = kzalloc(sizeof(struct dchannel), GFP_KERNEL);
4685 mISDN_initdchannel(dch, MAX_DFRAME_LEN_L1, ph_state_change);
4687 dch->dev.Dprotocols = (1 << ISDN_P_TE_E1) | (1 << ISDN_P_NT_E1);
4688 dch->dev.Bprotocols = (1 << (ISDN_P_B_RAW & ISDN_P_B_MASK)) |
4689 (1 << (ISDN_P_B_HDLC & ISDN_P_B_MASK));
4690 dch->dev.D.send = handle_dmsg;
4691 dch->dev.D.ctrl = hfcm_dctrl;
4692 dch->dev.nrbchan = (hc->dslot) ? 30 : 31;
4693 dch->slot = hc->dslot;
4694 hc->chan[hc->dslot].dch = dch;
4695 hc->chan[hc->dslot].port = 0;
4696 hc->chan[hc->dslot].nt_timer = -1;
4697 for (ch = 1; ch <= 31; ch++) {
4698 if (ch == hc->dslot) /* skip dchannel */
4700 bch = kzalloc(sizeof(struct bchannel), GFP_KERNEL);
4702 printk(KERN_ERR "%s: no memory for bchannel\n",
4707 hc->chan[ch].coeff = kzalloc(512, GFP_KERNEL);
4708 if (!hc->chan[ch].coeff) {
4709 printk(KERN_ERR "%s: no memory for coeffs\n",
4718 mISDN_initbchannel(bch, MAX_DATA_MEM);
4720 bch->ch.send = handle_bmsg;
4721 bch->ch.ctrl = hfcm_bctrl;
4723 list_add(&bch->ch.list, &dch->dev.bchannels);
4724 hc->chan[ch].bch = bch;
4725 hc->chan[ch].port = 0;
4726 set_channelmap(bch->nr, dch->dev.channelmap);
4728 /* set optical line type */
4729 if (port[Port_cnt] & 0x001) {
4730 if (!m->opticalsupport) {
4732 "This board has no optical "
4735 if (debug & DEBUG_HFCMULTI_INIT)
4737 "%s: PORT set optical "
4738 "interfacs: card(%d) "
4742 test_and_set_bit(HFC_CFG_OPTICAL,
4743 &hc->chan[hc->dslot].cfg);
4746 /* set LOS report */
4747 if (port[Port_cnt] & 0x004) {
4748 if (debug & DEBUG_HFCMULTI_INIT)
4749 printk(KERN_DEBUG "%s: PORT set "
4750 "LOS report: card(%d) port(%d)\n",
4751 __func__, HFC_cnt + 1, 1);
4752 test_and_set_bit(HFC_CFG_REPORT_LOS,
4753 &hc->chan[hc->dslot].cfg);
4755 /* set AIS report */
4756 if (port[Port_cnt] & 0x008) {
4757 if (debug & DEBUG_HFCMULTI_INIT)
4758 printk(KERN_DEBUG "%s: PORT set "
4759 "AIS report: card(%d) port(%d)\n",
4760 __func__, HFC_cnt + 1, 1);
4761 test_and_set_bit(HFC_CFG_REPORT_AIS,
4762 &hc->chan[hc->dslot].cfg);
4764 /* set SLIP report */
4765 if (port[Port_cnt] & 0x010) {
4766 if (debug & DEBUG_HFCMULTI_INIT)
4768 "%s: PORT set SLIP report: "
4769 "card(%d) port(%d)\n",
4770 __func__, HFC_cnt + 1, 1);
4771 test_and_set_bit(HFC_CFG_REPORT_SLIP,
4772 &hc->chan[hc->dslot].cfg);
4774 /* set RDI report */
4775 if (port[Port_cnt] & 0x020) {
4776 if (debug & DEBUG_HFCMULTI_INIT)
4778 "%s: PORT set RDI report: "
4779 "card(%d) port(%d)\n",
4780 __func__, HFC_cnt + 1, 1);
4781 test_and_set_bit(HFC_CFG_REPORT_RDI,
4782 &hc->chan[hc->dslot].cfg);
4784 /* set CRC-4 Mode */
4785 if (!(port[Port_cnt] & 0x100)) {
4786 if (debug & DEBUG_HFCMULTI_INIT)
4787 printk(KERN_DEBUG "%s: PORT turn on CRC4 report:"
4788 " card(%d) port(%d)\n",
4789 __func__, HFC_cnt + 1, 1);
4790 test_and_set_bit(HFC_CFG_CRC4,
4791 &hc->chan[hc->dslot].cfg);
4793 if (debug & DEBUG_HFCMULTI_INIT)
4794 printk(KERN_DEBUG "%s: PORT turn off CRC4"
4795 " report: card(%d) port(%d)\n",
4796 __func__, HFC_cnt + 1, 1);
4798 /* set forced clock */
4799 if (port[Port_cnt] & 0x0200) {
4800 if (debug & DEBUG_HFCMULTI_INIT)
4801 printk(KERN_DEBUG "%s: PORT force getting clock from "
4802 "E1: card(%d) port(%d)\n",
4803 __func__, HFC_cnt + 1, 1);
4804 test_and_set_bit(HFC_CHIP_E1CLOCK_GET, &hc->chip);
4806 if (port[Port_cnt] & 0x0400) {
4807 if (debug & DEBUG_HFCMULTI_INIT)
4808 printk(KERN_DEBUG "%s: PORT force putting clock to "
4809 "E1: card(%d) port(%d)\n",
4810 __func__, HFC_cnt + 1, 1);
4811 test_and_set_bit(HFC_CHIP_E1CLOCK_PUT, &hc->chip);
4814 if (port[Port_cnt] & 0x0800) {
4815 if (debug & DEBUG_HFCMULTI_INIT)
4816 printk(KERN_DEBUG "%s: PORT disable JATT PLL on "
4817 "E1: card(%d) port(%d)\n",
4818 __func__, HFC_cnt + 1, 1);
4819 test_and_set_bit(HFC_CHIP_RX_SYNC, &hc->chip);
4821 /* set elastic jitter buffer */
4822 if (port[Port_cnt] & 0x3000) {
4823 hc->chan[hc->dslot].jitter = (port[Port_cnt]>>12) & 0x3;
4824 if (debug & DEBUG_HFCMULTI_INIT)
4826 "%s: PORT set elastic "
4827 "buffer to %d: card(%d) port(%d)\n",
4828 __func__, hc->chan[hc->dslot].jitter,
4831 hc->chan[hc->dslot].jitter = 2; /* default */
4832 snprintf(name, MISDN_MAX_IDLEN - 1, "hfc-e1.%d", HFC_cnt + 1);
4833 ret = mISDN_register_device(&dch->dev, &hc->pci_dev->dev, name);
4839 release_port(hc, dch);
4844 init_multi_port(struct hfc_multi *hc, int pt)
4846 struct dchannel *dch;
4847 struct bchannel *bch;
4849 char name[MISDN_MAX_IDLEN];
4851 dch = kzalloc(sizeof(struct dchannel), GFP_KERNEL);
4855 mISDN_initdchannel(dch, MAX_DFRAME_LEN_L1, ph_state_change);
4857 dch->dev.Dprotocols = (1 << ISDN_P_TE_S0) | (1 << ISDN_P_NT_S0);
4858 dch->dev.Bprotocols = (1 << (ISDN_P_B_RAW & ISDN_P_B_MASK)) |
4859 (1 << (ISDN_P_B_HDLC & ISDN_P_B_MASK));
4860 dch->dev.D.send = handle_dmsg;
4861 dch->dev.D.ctrl = hfcm_dctrl;
4862 dch->dev.nrbchan = 2;
4865 hc->chan[i + 2].dch = dch;
4866 hc->chan[i + 2].port = pt;
4867 hc->chan[i + 2].nt_timer = -1;
4868 for (ch = 0; ch < dch->dev.nrbchan; ch++) {
4869 bch = kzalloc(sizeof(struct bchannel), GFP_KERNEL);
4871 printk(KERN_ERR "%s: no memory for bchannel\n",
4876 hc->chan[i + ch].coeff = kzalloc(512, GFP_KERNEL);
4877 if (!hc->chan[i + ch].coeff) {
4878 printk(KERN_ERR "%s: no memory for coeffs\n",
4887 mISDN_initbchannel(bch, MAX_DATA_MEM);
4889 bch->ch.send = handle_bmsg;
4890 bch->ch.ctrl = hfcm_bctrl;
4891 bch->ch.nr = ch + 1;
4892 list_add(&bch->ch.list, &dch->dev.bchannels);
4893 hc->chan[i + ch].bch = bch;
4894 hc->chan[i + ch].port = pt;
4895 set_channelmap(bch->nr, dch->dev.channelmap);
4897 /* set master clock */
4898 if (port[Port_cnt] & 0x001) {
4899 if (debug & DEBUG_HFCMULTI_INIT)
4901 "%s: PROTOCOL set master clock: "
4902 "card(%d) port(%d)\n",
4903 __func__, HFC_cnt + 1, pt + 1);
4904 if (dch->dev.D.protocol != ISDN_P_TE_S0) {
4905 printk(KERN_ERR "Error: Master clock "
4906 "for port(%d) of card(%d) is only"
4907 " possible with TE-mode\n",
4908 pt + 1, HFC_cnt + 1);
4912 if (hc->masterclk >= 0) {
4913 printk(KERN_ERR "Error: Master clock "
4914 "for port(%d) of card(%d) already "
4915 "defined for port(%d)\n",
4916 pt + 1, HFC_cnt + 1, hc->masterclk + 1);
4922 /* set transmitter line to non capacitive */
4923 if (port[Port_cnt] & 0x002) {
4924 if (debug & DEBUG_HFCMULTI_INIT)
4926 "%s: PROTOCOL set non capacitive "
4927 "transmitter: card(%d) port(%d)\n",
4928 __func__, HFC_cnt + 1, pt + 1);
4929 test_and_set_bit(HFC_CFG_NONCAP_TX,
4930 &hc->chan[i + 2].cfg);
4932 /* disable E-channel */
4933 if (port[Port_cnt] & 0x004) {
4934 if (debug & DEBUG_HFCMULTI_INIT)
4936 "%s: PROTOCOL disable E-channel: "
4937 "card(%d) port(%d)\n",
4938 __func__, HFC_cnt + 1, pt + 1);
4939 test_and_set_bit(HFC_CFG_DIS_ECHANNEL,
4940 &hc->chan[i + 2].cfg);
4942 if (hc->ctype == HFC_TYPE_XHFC) {
4943 snprintf(name, MISDN_MAX_IDLEN - 1, "xhfc.%d-%d",
4944 HFC_cnt + 1, pt + 1);
4945 ret = mISDN_register_device(&dch->dev, NULL, name);
4947 snprintf(name, MISDN_MAX_IDLEN - 1, "hfc-%ds.%d-%d",
4948 hc->ctype, HFC_cnt + 1, pt + 1);
4949 ret = mISDN_register_device(&dch->dev, &hc->pci_dev->dev, name);
4953 hc->created[pt] = 1;
4956 release_port(hc, dch);
4961 hfcmulti_init(struct hm_map *m, struct pci_dev *pdev,
4962 const struct pci_device_id *ent)
4966 struct hfc_multi *hc;
4968 u_char dips = 0, pmj = 0; /* dip settings, port mode Jumpers */
4971 if (HFC_cnt >= MAX_CARDS) {
4972 printk(KERN_ERR "too many cards (max=%d).\n",
4976 if ((type[HFC_cnt] & 0xff) && (type[HFC_cnt] & 0xff) != m->type) {
4977 printk(KERN_WARNING "HFC-MULTI: Card '%s:%s' type %d found but "
4978 "type[%d] %d was supplied as module parameter\n",
4979 m->vendor_name, m->card_name, m->type, HFC_cnt,
4980 type[HFC_cnt] & 0xff);
4981 printk(KERN_WARNING "HFC-MULTI: Load module without parameters "
4982 "first, to see cards and their types.");
4985 if (debug & DEBUG_HFCMULTI_INIT)
4986 printk(KERN_DEBUG "%s: Registering %s:%s chip type %d (0x%x)\n",
4987 __func__, m->vendor_name, m->card_name, m->type,
4990 /* allocate card+fifo structure */
4991 hc = kzalloc(sizeof(struct hfc_multi), GFP_KERNEL);
4993 printk(KERN_ERR "No kmem for HFC-Multi card\n");
4996 spin_lock_init(&hc->lock);
4998 hc->ctype = m->type;
4999 hc->ports = m->ports;
5001 hc->pcm = pcm[HFC_cnt];
5002 hc->io_mode = iomode[HFC_cnt];
5003 if (dslot[HFC_cnt] < 0 && hc->ctype == HFC_TYPE_E1) {
5005 printk(KERN_INFO "HFC-E1 card has disabled D-channel, but "
5008 if (dslot[HFC_cnt] > 0 && dslot[HFC_cnt] < 32
5009 && hc->ctype == HFC_TYPE_E1) {
5010 hc->dslot = dslot[HFC_cnt];
5011 printk(KERN_INFO "HFC-E1 card has alternating D-channel on "
5012 "time slot %d\n", dslot[HFC_cnt]);
5016 /* set chip specific features */
5018 if (type[HFC_cnt] & 0x100) {
5019 test_and_set_bit(HFC_CHIP_ULAW, &hc->chip);
5020 hc->silence = 0xff; /* ulaw silence */
5022 hc->silence = 0x2a; /* alaw silence */
5023 if ((poll >> 1) > sizeof(hc->silence_data)) {
5024 printk(KERN_ERR "HFCMULTI error: silence_data too small, "
5028 for (i = 0; i < (poll >> 1); i++)
5029 hc->silence_data[i] = hc->silence;
5031 if (hc->ctype != HFC_TYPE_XHFC) {
5032 if (!(type[HFC_cnt] & 0x200))
5033 test_and_set_bit(HFC_CHIP_DTMF, &hc->chip);
5034 test_and_set_bit(HFC_CHIP_CONF, &hc->chip);
5037 if (type[HFC_cnt] & 0x800)
5038 test_and_set_bit(HFC_CHIP_PCM_SLAVE, &hc->chip);
5039 if (type[HFC_cnt] & 0x1000) {
5040 test_and_set_bit(HFC_CHIP_PCM_MASTER, &hc->chip);
5041 test_and_clear_bit(HFC_CHIP_PCM_SLAVE, &hc->chip);
5043 if (type[HFC_cnt] & 0x4000)
5044 test_and_set_bit(HFC_CHIP_EXRAM_128, &hc->chip);
5045 if (type[HFC_cnt] & 0x8000)
5046 test_and_set_bit(HFC_CHIP_EXRAM_512, &hc->chip);
5048 if (type[HFC_cnt] & 0x10000)
5050 if (type[HFC_cnt] & 0x20000)
5052 if (type[HFC_cnt] & 0x80000) {
5053 test_and_set_bit(HFC_CHIP_WATCHDOG, &hc->chip);
5055 hc->wdbyte = V_GPIO_OUT2;
5056 printk(KERN_NOTICE "Watchdog enabled\n");
5060 /* setup pci, hc->slots may change due to PLXSD */
5061 ret_err = setup_pci(hc, pdev, ent);
5063 #ifdef CONFIG_MISDN_HFCMULTI_8xx
5064 ret_err = setup_embedded(hc, m);
5067 printk(KERN_WARNING "Embedded IO Mode not selected\n");
5072 if (hc == syncmaster)
5078 hc->HFC_outb_nodebug = hc->HFC_outb;
5079 hc->HFC_inb_nodebug = hc->HFC_inb;
5080 hc->HFC_inw_nodebug = hc->HFC_inw;
5081 hc->HFC_wait_nodebug = hc->HFC_wait;
5082 #ifdef HFC_REGISTER_DEBUG
5083 hc->HFC_outb = HFC_outb_debug;
5084 hc->HFC_inb = HFC_inb_debug;
5085 hc->HFC_inw = HFC_inw_debug;
5086 hc->HFC_wait = HFC_wait_debug;
5088 /* create channels */
5089 for (pt = 0; pt < hc->ports; pt++) {
5090 if (Port_cnt >= MAX_PORTS) {
5091 printk(KERN_ERR "too many ports (max=%d).\n",
5096 if (hc->ctype == HFC_TYPE_E1)
5097 ret_err = init_e1_port(hc, m);
5099 ret_err = init_multi_port(hc, pt);
5100 if (debug & DEBUG_HFCMULTI_INIT)
5102 "%s: Registering D-channel, card(%d) port(%d)"
5104 __func__, HFC_cnt + 1, pt, ret_err);
5107 while (pt) { /* release already registered ports */
5109 release_port(hc, hc->chan[(pt << 2) + 2].dch);
5117 switch (m->dip_type) {
5120 * Get DIP setting for beroNet 1S/2S/4S cards
5121 * DIP Setting: (collect GPIO 13/14/15 (R_GPIO_IN1) +
5122 * GPI 19/23 (R_GPI_IN2))
5124 dips = ((~HFC_inb(hc, R_GPIO_IN1) & 0xE0) >> 5) |
5125 ((~HFC_inb(hc, R_GPI_IN2) & 0x80) >> 3) |
5126 (~HFC_inb(hc, R_GPI_IN2) & 0x08);
5128 /* Port mode (TE/NT) jumpers */
5129 pmj = ((HFC_inb(hc, R_GPI_IN3) >> 4) & 0xf);
5131 if (test_bit(HFC_CHIP_B410P, &hc->chip))
5134 printk(KERN_INFO "%s: %s DIPs(0x%x) jumpers(0x%x)\n",
5135 m->vendor_name, m->card_name, dips, pmj);
5139 * Get DIP Setting for beroNet 8S0+ cards
5140 * Enable PCI auxbridge function
5142 HFC_outb(hc, R_BRG_PCM_CFG, 1 | V_PCM_CLK);
5143 /* prepare access to auxport */
5144 outw(0x4000, hc->pci_iobase + 4);
5146 * some dummy reads are required to
5147 * read valid DIP switch data
5149 dips = inb(hc->pci_iobase);
5150 dips = inb(hc->pci_iobase);
5151 dips = inb(hc->pci_iobase);
5152 dips = ~inb(hc->pci_iobase) & 0x3F;
5153 outw(0x0, hc->pci_iobase + 4);
5154 /* disable PCI auxbridge function */
5155 HFC_outb(hc, R_BRG_PCM_CFG, V_PCM_CLK);
5156 printk(KERN_INFO "%s: %s DIPs(0x%x)\n",
5157 m->vendor_name, m->card_name, dips);
5161 * get DIP Setting for beroNet E1 cards
5162 * DIP Setting: collect GPI 4/5/6/7 (R_GPI_IN0)
5164 dips = (~HFC_inb(hc, R_GPI_IN0) & 0xF0) >> 4;
5165 printk(KERN_INFO "%s: %s DIPs(0x%x)\n",
5166 m->vendor_name, m->card_name, dips);
5171 spin_lock_irqsave(&HFClock, flags);
5172 list_add_tail(&hc->list, &HFClist);
5173 spin_unlock_irqrestore(&HFClock, flags);
5175 /* use as clock source */
5176 if (clock == HFC_cnt + 1)
5177 hc->iclock = mISDN_register_clock("HFCMulti", 0, clockctl, hc);
5179 /* initialize hardware */
5180 hc->irq = (m->irq) ? : hc->pci_dev->irq;
5181 ret_err = init_card(hc);
5183 printk(KERN_ERR "init card returns %d\n", ret_err);
5188 /* start IRQ and return */
5189 spin_lock_irqsave(&hc->lock, flags);
5191 spin_unlock_irqrestore(&hc->lock, flags);
5195 release_io_hfcmulti(hc);
5196 if (hc == syncmaster)
5202 static void __devexit hfc_remove_pci(struct pci_dev *pdev)
5204 struct hfc_multi *card = pci_get_drvdata(pdev);
5208 printk(KERN_INFO "removing hfc_multi card vendor:%x "
5209 "device:%x subvendor:%x subdevice:%x\n",
5210 pdev->vendor, pdev->device,
5211 pdev->subsystem_vendor, pdev->subsystem_device);
5214 spin_lock_irqsave(&HFClock, flags);
5216 spin_unlock_irqrestore(&HFClock, flags);
5219 printk(KERN_DEBUG "%s: drvdata already removed\n",
5224 #define VENDOR_CCD "Cologne Chip AG"
5225 #define VENDOR_BN "beroNet GmbH"
5226 #define VENDOR_DIG "Digium Inc."
5227 #define VENDOR_JH "Junghanns.NET GmbH"
5228 #define VENDOR_PRIM "PrimuX"
5230 static const struct hm_map hfcm_map[] = {
5231 /*0*/ {VENDOR_BN, "HFC-1S Card (mini PCI)", 4, 1, 1, 3, 0, DIP_4S, 0, 0},
5232 /*1*/ {VENDOR_BN, "HFC-2S Card", 4, 2, 1, 3, 0, DIP_4S, 0, 0},
5233 /*2*/ {VENDOR_BN, "HFC-2S Card (mini PCI)", 4, 2, 1, 3, 0, DIP_4S, 0, 0},
5234 /*3*/ {VENDOR_BN, "HFC-4S Card", 4, 4, 1, 2, 0, DIP_4S, 0, 0},
5235 /*4*/ {VENDOR_BN, "HFC-4S Card (mini PCI)", 4, 4, 1, 2, 0, 0, 0, 0},
5236 /*5*/ {VENDOR_CCD, "HFC-4S Eval (old)", 4, 4, 0, 0, 0, 0, 0, 0},
5237 /*6*/ {VENDOR_CCD, "HFC-4S IOB4ST", 4, 4, 1, 2, 0, DIP_4S, 0, 0},
5238 /*7*/ {VENDOR_CCD, "HFC-4S", 4, 4, 1, 2, 0, 0, 0, 0},
5239 /*8*/ {VENDOR_DIG, "HFC-4S Card", 4, 4, 0, 2, 0, 0, HFC_IO_MODE_REGIO, 0},
5240 /*9*/ {VENDOR_CCD, "HFC-4S Swyx 4xS0 SX2 QuadBri", 4, 4, 1, 2, 0, 0, 0, 0},
5241 /*10*/ {VENDOR_JH, "HFC-4S (junghanns 2.0)", 4, 4, 1, 2, 0, 0, 0, 0},
5242 /*11*/ {VENDOR_PRIM, "HFC-2S Primux Card", 4, 2, 0, 0, 0, 0, 0, 0},
5244 /*12*/ {VENDOR_BN, "HFC-8S Card", 8, 8, 1, 0, 0, 0, 0, 0},
5245 /*13*/ {VENDOR_BN, "HFC-8S Card (+)", 8, 8, 1, 8, 0, DIP_8S,
5246 HFC_IO_MODE_REGIO, 0},
5247 /*14*/ {VENDOR_CCD, "HFC-8S Eval (old)", 8, 8, 0, 0, 0, 0, 0, 0},
5248 /*15*/ {VENDOR_CCD, "HFC-8S IOB4ST Recording", 8, 8, 1, 0, 0, 0, 0, 0},
5250 /*16*/ {VENDOR_CCD, "HFC-8S IOB8ST", 8, 8, 1, 0, 0, 0, 0, 0},
5251 /*17*/ {VENDOR_CCD, "HFC-8S", 8, 8, 1, 0, 0, 0, 0, 0},
5252 /*18*/ {VENDOR_CCD, "HFC-8S", 8, 8, 1, 0, 0, 0, 0, 0},
5254 /*19*/ {VENDOR_BN, "HFC-E1 Card", 1, 1, 0, 1, 0, DIP_E1, 0, 0},
5255 /*20*/ {VENDOR_BN, "HFC-E1 Card (mini PCI)", 1, 1, 0, 1, 0, 0, 0, 0},
5256 /*21*/ {VENDOR_BN, "HFC-E1+ Card (Dual)", 1, 1, 0, 1, 0, DIP_E1, 0, 0},
5257 /*22*/ {VENDOR_BN, "HFC-E1 Card (Dual)", 1, 1, 0, 1, 0, DIP_E1, 0, 0},
5259 /*23*/ {VENDOR_CCD, "HFC-E1 Eval (old)", 1, 1, 0, 0, 0, 0, 0, 0},
5260 /*24*/ {VENDOR_CCD, "HFC-E1 IOB1E1", 1, 1, 0, 1, 0, 0, 0, 0},
5261 /*25*/ {VENDOR_CCD, "HFC-E1", 1, 1, 0, 1, 0, 0, 0, 0},
5263 /*26*/ {VENDOR_CCD, "HFC-4S Speech Design", 4, 4, 0, 0, 0, 0,
5264 HFC_IO_MODE_PLXSD, 0},
5265 /*27*/ {VENDOR_CCD, "HFC-E1 Speech Design", 1, 1, 0, 0, 0, 0,
5266 HFC_IO_MODE_PLXSD, 0},
5267 /*28*/ {VENDOR_CCD, "HFC-4S OpenVox", 4, 4, 1, 0, 0, 0, 0, 0},
5268 /*29*/ {VENDOR_CCD, "HFC-2S OpenVox", 4, 2, 1, 0, 0, 0, 0, 0},
5269 /*30*/ {VENDOR_CCD, "HFC-8S OpenVox", 8, 8, 1, 0, 0, 0, 0, 0},
5270 /*31*/ {VENDOR_CCD, "XHFC-4S Speech Design", 5, 4, 0, 0, 0, 0,
5271 HFC_IO_MODE_EMBSD, XHFC_IRQ},
5272 /*32*/ {VENDOR_JH, "HFC-8S (junghanns)", 8, 8, 1, 0, 0, 0, 0, 0},
5273 /*33*/ {VENDOR_BN, "HFC-2S Beronet Card PCIe", 4, 2, 1, 3, 0, DIP_4S, 0, 0},
5274 /*34*/ {VENDOR_BN, "HFC-4S Beronet Card PCIe", 4, 4, 1, 2, 0, DIP_4S, 0, 0},
5278 #define H(x) ((unsigned long)&hfcm_map[x])
5279 static struct pci_device_id hfmultipci_ids[] __devinitdata = {
5281 /* Cards with HFC-4S Chip */
5282 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5283 PCI_SUBDEVICE_ID_CCD_BN1SM, 0, 0, H(0)}, /* BN1S mini PCI */
5284 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5285 PCI_SUBDEVICE_ID_CCD_BN2S, 0, 0, H(1)}, /* BN2S */
5286 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5287 PCI_SUBDEVICE_ID_CCD_BN2SM, 0, 0, H(2)}, /* BN2S mini PCI */
5288 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5289 PCI_SUBDEVICE_ID_CCD_BN4S, 0, 0, H(3)}, /* BN4S */
5290 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5291 PCI_SUBDEVICE_ID_CCD_BN4SM, 0, 0, H(4)}, /* BN4S mini PCI */
5292 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5293 PCI_DEVICE_ID_CCD_HFC4S, 0, 0, H(5)}, /* Old Eval */
5294 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5295 PCI_SUBDEVICE_ID_CCD_IOB4ST, 0, 0, H(6)}, /* IOB4ST */
5296 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5297 PCI_SUBDEVICE_ID_CCD_HFC4S, 0, 0, H(7)}, /* 4S */
5298 { PCI_VENDOR_ID_DIGIUM, PCI_DEVICE_ID_DIGIUM_HFC4S,
5299 PCI_VENDOR_ID_DIGIUM, PCI_DEVICE_ID_DIGIUM_HFC4S, 0, 0, H(8)},
5300 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5301 PCI_SUBDEVICE_ID_CCD_SWYX4S, 0, 0, H(9)}, /* 4S Swyx */
5302 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5303 PCI_SUBDEVICE_ID_CCD_JH4S20, 0, 0, H(10)},
5304 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5305 PCI_SUBDEVICE_ID_CCD_PMX2S, 0, 0, H(11)}, /* Primux */
5306 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5307 PCI_SUBDEVICE_ID_CCD_OV4S, 0, 0, H(28)}, /* OpenVox 4 */
5308 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5309 PCI_SUBDEVICE_ID_CCD_OV2S, 0, 0, H(29)}, /* OpenVox 2 */
5310 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5311 0xb761, 0, 0, H(33)}, /* BN2S PCIe */
5312 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5313 0xb762, 0, 0, H(34)}, /* BN4S PCIe */
5315 /* Cards with HFC-8S Chip */
5316 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5317 PCI_SUBDEVICE_ID_CCD_BN8S, 0, 0, H(12)}, /* BN8S */
5318 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5319 PCI_SUBDEVICE_ID_CCD_BN8SP, 0, 0, H(13)}, /* BN8S+ */
5320 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5321 PCI_DEVICE_ID_CCD_HFC8S, 0, 0, H(14)}, /* old Eval */
5322 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5323 PCI_SUBDEVICE_ID_CCD_IOB8STR, 0, 0, H(15)}, /* IOB8ST Recording */
5324 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5325 PCI_SUBDEVICE_ID_CCD_IOB8ST, 0, 0, H(16)}, /* IOB8ST */
5326 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5327 PCI_SUBDEVICE_ID_CCD_IOB8ST_1, 0, 0, H(17)}, /* IOB8ST */
5328 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5329 PCI_SUBDEVICE_ID_CCD_HFC8S, 0, 0, H(18)}, /* 8S */
5330 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5331 PCI_SUBDEVICE_ID_CCD_OV8S, 0, 0, H(30)}, /* OpenVox 8 */
5332 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5333 PCI_SUBDEVICE_ID_CCD_JH8S, 0, 0, H(32)}, /* Junganns 8S */
5336 /* Cards with HFC-E1 Chip */
5337 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5338 PCI_SUBDEVICE_ID_CCD_BNE1, 0, 0, H(19)}, /* BNE1 */
5339 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5340 PCI_SUBDEVICE_ID_CCD_BNE1M, 0, 0, H(20)}, /* BNE1 mini PCI */
5341 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5342 PCI_SUBDEVICE_ID_CCD_BNE1DP, 0, 0, H(21)}, /* BNE1 + (Dual) */
5343 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5344 PCI_SUBDEVICE_ID_CCD_BNE1D, 0, 0, H(22)}, /* BNE1 (Dual) */
5346 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5347 PCI_DEVICE_ID_CCD_HFCE1, 0, 0, H(23)}, /* Old Eval */
5348 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5349 PCI_SUBDEVICE_ID_CCD_IOB1E1, 0, 0, H(24)}, /* IOB1E1 */
5350 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5351 PCI_SUBDEVICE_ID_CCD_HFCE1, 0, 0, H(25)}, /* E1 */
5353 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, PCI_VENDOR_ID_CCD,
5354 PCI_SUBDEVICE_ID_CCD_SPD4S, 0, 0, H(26)}, /* PLX PCI Bridge */
5355 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, PCI_VENDOR_ID_CCD,
5356 PCI_SUBDEVICE_ID_CCD_SPDE1, 0, 0, H(27)}, /* PLX PCI Bridge */
5358 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5359 PCI_SUBDEVICE_ID_CCD_JHSE1, 0, 0, H(25)}, /* Junghanns E1 */
5361 { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_HFC4S), 0 },
5362 { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_HFC8S), 0 },
5363 { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_HFCE1), 0 },
5368 MODULE_DEVICE_TABLE(pci, hfmultipci_ids);
5371 hfcmulti_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
5373 struct hm_map *m = (struct hm_map *)ent->driver_data;
5376 if (m == NULL && ent->vendor == PCI_VENDOR_ID_CCD && (
5377 ent->device == PCI_DEVICE_ID_CCD_HFC4S ||
5378 ent->device == PCI_DEVICE_ID_CCD_HFC8S ||
5379 ent->device == PCI_DEVICE_ID_CCD_HFCE1)) {
5381 "Unknown HFC multiport controller (vendor:%04x device:%04x "
5382 "subvendor:%04x subdevice:%04x)\n", pdev->vendor,
5383 pdev->device, pdev->subsystem_vendor,
5384 pdev->subsystem_device);
5386 "Please contact the driver maintainer for support.\n");
5389 ret = hfcmulti_init(m, pdev, ent);
5393 printk(KERN_INFO "%d devices registered\n", HFC_cnt);
5397 static struct pci_driver hfcmultipci_driver = {
5398 .name = "hfc_multi",
5399 .probe = hfcmulti_probe,
5400 .remove = __devexit_p(hfc_remove_pci),
5401 .id_table = hfmultipci_ids,
5405 HFCmulti_cleanup(void)
5407 struct hfc_multi *card, *next;
5409 /* get rid of all devices of this driver */
5410 list_for_each_entry_safe(card, next, &HFClist, list)
5412 pci_unregister_driver(&hfcmultipci_driver);
5422 printk(KERN_INFO "mISDN: HFC-multi driver %s\n", HFC_MULTI_VERSION);
5425 printk(KERN_DEBUG "%s: IRQ_DEBUG IS ENABLED!\n", __func__);
5428 spin_lock_init(&HFClock);
5429 spin_lock_init(&plx_lock);
5431 if (debug & DEBUG_HFCMULTI_INIT)
5432 printk(KERN_DEBUG "%s: init entered\n", __func__);
5459 "%s: Wrong poll value (%d).\n", __func__, poll);
5468 /* Register the embedded devices.
5469 * This should be done before the PCI cards registration */
5487 for (i = 0; i < xhfc; ++i) {
5488 err = hfcmulti_init(&m, NULL, NULL);
5490 printk(KERN_ERR "error registering embedded driver: "
5495 printk(KERN_INFO "%d devices registered\n", HFC_cnt);
5498 /* Register the PCI cards */
5499 err = pci_register_driver(&hfcmultipci_driver);
5501 printk(KERN_ERR "error registering pci driver: %x\n", err);
5509 module_init(HFCmulti_init);
5510 module_exit(HFCmulti_cleanup);