3 * hfcpci.c low level driver for CCD's hfc-pci based cards
5 * Author Werner Cornelius (werner@isdn4linux.de)
6 * based on existing driver for CCD hfc ISA cards
7 * type approval valid for HFC-S PCI A based card
9 * Copyright 1999 by Werner Cornelius (werner@isdn-development.de)
10 * Copyright 2008 by Karsten Keil <kkeil@novell.com>
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2, or (at your option)
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
29 * NOTE: only one poll value must be given for all cards
30 * See hfc_pci.h for debug flags.
33 * NOTE: only one poll value must be given for all cards
34 * Give the number of samples for each fifo process.
35 * By default 128 is used. Decrease to reduce delay, increase to
36 * reduce cpu load. If unsure, don't mess with it!
37 * A value of 128 will use controller's interrupt. Other values will
38 * use kernel timer, because the controller will not allow lower values
40 * Also note that the value depends on the kernel timer frequency.
41 * If kernel uses a frequency of 1000 Hz, steps of 8 samples are possible.
42 * If the kernel uses 100 Hz, steps of 80 samples are possible.
43 * If the kernel uses 300 Hz, steps of about 26 samples are possible.
47 #include <linux/module.h>
48 #include <linux/pci.h>
49 #include <linux/delay.h>
50 #include <linux/mISDNhw.h>
51 #include <linux/slab.h>
55 static const char *hfcpci_revision = "2.0";
59 static uint poll, tics;
60 static struct timer_list hfc_tl;
61 static unsigned long hfc_jiffies;
63 MODULE_AUTHOR("Karsten Keil");
64 MODULE_LICENSE("GPL");
65 module_param(debug, uint, S_IRUGO | S_IWUSR);
66 module_param(poll, uint, S_IRUGO | S_IWUSR);
101 unsigned char int_m1;
102 unsigned char int_m2;
104 unsigned char sctrl_r;
105 unsigned char sctrl_e;
107 unsigned char fifo_en;
108 unsigned char bswapped;
109 unsigned char protocol;
111 unsigned char __iomem *pci_io; /* start of PCI IO memory */
112 dma_addr_t dmahandle;
113 void *fifos; /* FIFO memory */
114 int last_bfifo_cnt[2];
115 /* marker saving last b-fifo frame count */
116 struct timer_list timer;
119 #define HFC_CFG_MASTER 1
120 #define HFC_CFG_SLAVE 2
121 #define HFC_CFG_PCM 3
122 #define HFC_CFG_2HFC 4
123 #define HFC_CFG_SLAVEHFC 5
124 #define HFC_CFG_NEG_F0 6
125 #define HFC_CFG_SW_DD_DU 7
127 #define FLG_HFC_TIMER_T1 16
128 #define FLG_HFC_TIMER_T3 17
130 #define NT_T1_COUNT 1120 /* number of 3.125ms interrupts (3.5s) */
131 #define NT_T3_COUNT 31 /* number of 3.125ms interrupts (97 ms) */
132 #define CLKDEL_TE 0x0e /* CLKDEL in TE mode */
133 #define CLKDEL_NT 0x6c /* CLKDEL in NT mode */
143 struct pci_dev *pdev;
145 spinlock_t lock; /* card lock */
147 struct bchannel bch[2];
150 /* Interface functions */
152 enable_hwirq(struct hfc_pci *hc)
154 hc->hw.int_m2 |= HFCPCI_IRQ_ENABLE;
155 Write_hfc(hc, HFCPCI_INT_M2, hc->hw.int_m2);
159 disable_hwirq(struct hfc_pci *hc)
161 hc->hw.int_m2 &= ~((u_char)HFCPCI_IRQ_ENABLE);
162 Write_hfc(hc, HFCPCI_INT_M2, hc->hw.int_m2);
166 * free hardware resources used by driver
169 release_io_hfcpci(struct hfc_pci *hc)
171 /* disable memory mapped ports + busmaster */
172 pci_write_config_word(hc->pdev, PCI_COMMAND, 0);
173 del_timer(&hc->hw.timer);
174 pci_free_consistent(hc->pdev, 0x8000, hc->hw.fifos, hc->hw.dmahandle);
175 iounmap(hc->hw.pci_io);
179 * set mode (NT or TE)
182 hfcpci_setmode(struct hfc_pci *hc)
184 if (hc->hw.protocol == ISDN_P_NT_S0) {
185 hc->hw.clkdel = CLKDEL_NT; /* ST-Bit delay for NT-Mode */
186 hc->hw.sctrl |= SCTRL_MODE_NT; /* NT-MODE */
187 hc->hw.states = 1; /* G1 */
189 hc->hw.clkdel = CLKDEL_TE; /* ST-Bit delay for TE-Mode */
190 hc->hw.sctrl &= ~SCTRL_MODE_NT; /* TE-MODE */
191 hc->hw.states = 2; /* F2 */
193 Write_hfc(hc, HFCPCI_CLKDEL, hc->hw.clkdel);
194 Write_hfc(hc, HFCPCI_STATES, HFCPCI_LOAD_STATE | hc->hw.states);
196 Write_hfc(hc, HFCPCI_STATES, hc->hw.states | 0x40); /* Deactivate */
197 Write_hfc(hc, HFCPCI_SCTRL, hc->hw.sctrl);
201 * function called to reset the HFC PCI chip. A complete software reset of chip
205 reset_hfcpci(struct hfc_pci *hc)
210 printk(KERN_DEBUG "reset_hfcpci: entered\n");
211 val = Read_hfc(hc, HFCPCI_CHIP_ID);
212 printk(KERN_INFO "HFC_PCI: resetting HFC ChipId(%x)\n", val);
213 /* enable memory mapped ports, disable busmaster */
214 pci_write_config_word(hc->pdev, PCI_COMMAND, PCI_ENA_MEMIO);
216 /* enable memory ports + busmaster */
217 pci_write_config_word(hc->pdev, PCI_COMMAND,
218 PCI_ENA_MEMIO + PCI_ENA_MASTER);
219 val = Read_hfc(hc, HFCPCI_STATUS);
220 printk(KERN_DEBUG "HFC-PCI status(%x) before reset\n", val);
221 hc->hw.cirm = HFCPCI_RESET; /* Reset On */
222 Write_hfc(hc, HFCPCI_CIRM, hc->hw.cirm);
223 set_current_state(TASK_UNINTERRUPTIBLE);
224 mdelay(10); /* Timeout 10ms */
225 hc->hw.cirm = 0; /* Reset Off */
226 Write_hfc(hc, HFCPCI_CIRM, hc->hw.cirm);
227 val = Read_hfc(hc, HFCPCI_STATUS);
228 printk(KERN_DEBUG "HFC-PCI status(%x) after reset\n", val);
229 while (cnt < 50000) { /* max 50000 us */
232 val = Read_hfc(hc, HFCPCI_STATUS);
236 printk(KERN_DEBUG "HFC-PCI status(%x) after %dus\n", val, cnt);
238 hc->hw.fifo_en = 0x30; /* only D fifos enabled */
240 hc->hw.bswapped = 0; /* no exchange */
241 hc->hw.ctmt = HFCPCI_TIM3_125 | HFCPCI_AUTO_TIMER;
242 hc->hw.trm = HFCPCI_BTRANS_THRESMASK; /* no echo connect , threshold */
243 hc->hw.sctrl = 0x40; /* set tx_lo mode, error in datasheet ! */
245 hc->hw.sctrl_e = HFCPCI_AUTO_AWAKE; /* S/T Auto awake */
247 if (test_bit(HFC_CFG_MASTER, &hc->cfg))
248 hc->hw.mst_m |= HFCPCI_MASTER; /* HFC Master Mode */
249 if (test_bit(HFC_CFG_NEG_F0, &hc->cfg))
250 hc->hw.mst_m |= HFCPCI_F0_NEGATIV;
251 Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
252 Write_hfc(hc, HFCPCI_TRM, hc->hw.trm);
253 Write_hfc(hc, HFCPCI_SCTRL_E, hc->hw.sctrl_e);
254 Write_hfc(hc, HFCPCI_CTMT, hc->hw.ctmt);
256 hc->hw.int_m1 = HFCPCI_INTS_DTRANS | HFCPCI_INTS_DREC |
257 HFCPCI_INTS_L1STATE | HFCPCI_INTS_TIMER;
258 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
260 /* Clear already pending ints */
261 val = Read_hfc(hc, HFCPCI_INT_S1);
266 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
267 Write_hfc(hc, HFCPCI_SCTRL_R, hc->hw.sctrl_r);
270 * Init GCI/IOM2 in master mode
271 * Slots 0 and 1 are set for B-chan 1 and 2
272 * D- and monitor/CI channel are not enabled
273 * STIO1 is used as output for data, B1+B2 from ST->IOM+HFC
274 * STIO2 is used as data input, B1+B2 from IOM->ST
275 * ST B-channel send disabled -> continuous 1s
276 * The IOM slots are always enabled
278 if (test_bit(HFC_CFG_PCM, &hc->cfg)) {
279 /* set data flow directions: connect B1,B2: HFC to/from PCM */
282 hc->hw.conn = 0x36; /* set data flow directions */
283 if (test_bit(HFC_CFG_SW_DD_DU, &hc->cfg)) {
284 Write_hfc(hc, HFCPCI_B1_SSL, 0xC0);
285 Write_hfc(hc, HFCPCI_B2_SSL, 0xC1);
286 Write_hfc(hc, HFCPCI_B1_RSL, 0xC0);
287 Write_hfc(hc, HFCPCI_B2_RSL, 0xC1);
289 Write_hfc(hc, HFCPCI_B1_SSL, 0x80);
290 Write_hfc(hc, HFCPCI_B2_SSL, 0x81);
291 Write_hfc(hc, HFCPCI_B1_RSL, 0x80);
292 Write_hfc(hc, HFCPCI_B2_RSL, 0x81);
295 Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
296 val = Read_hfc(hc, HFCPCI_INT_S2);
300 * Timer function called when kernel timer expires
303 hfcpci_Timer(struct hfc_pci *hc)
305 hc->hw.timer.expires = jiffies + 75;
308 * WriteReg(hc, HFCD_DATA, HFCD_CTMT, hc->hw.ctmt | 0x80);
309 * add_timer(&hc->hw.timer);
315 * select a b-channel entry matching and active
317 static struct bchannel *
318 Sel_BCS(struct hfc_pci *hc, int channel)
320 if (test_bit(FLG_ACTIVE, &hc->bch[0].Flags) &&
321 (hc->bch[0].nr & channel))
323 else if (test_bit(FLG_ACTIVE, &hc->bch[1].Flags) &&
324 (hc->bch[1].nr & channel))
331 * clear the desired B-channel rx fifo
334 hfcpci_clear_fifo_rx(struct hfc_pci *hc, int fifo)
340 bzr = &((union fifo_area *)(hc->hw.fifos))->b_chans.rxbz_b2;
341 fifo_state = hc->hw.fifo_en & HFCPCI_FIFOEN_B2RX;
343 bzr = &((union fifo_area *)(hc->hw.fifos))->b_chans.rxbz_b1;
344 fifo_state = hc->hw.fifo_en & HFCPCI_FIFOEN_B1RX;
347 hc->hw.fifo_en ^= fifo_state;
348 Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
349 hc->hw.last_bfifo_cnt[fifo] = 0;
350 bzr->f1 = MAX_B_FRAMES;
351 bzr->f2 = bzr->f1; /* init F pointers to remain constant */
352 bzr->za[MAX_B_FRAMES].z1 = cpu_to_le16(B_FIFO_SIZE + B_SUB_VAL - 1);
353 bzr->za[MAX_B_FRAMES].z2 = cpu_to_le16(
354 le16_to_cpu(bzr->za[MAX_B_FRAMES].z1));
356 hc->hw.fifo_en |= fifo_state;
357 Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
361 * clear the desired B-channel tx fifo
363 static void hfcpci_clear_fifo_tx(struct hfc_pci *hc, int fifo)
369 bzt = &((union fifo_area *)(hc->hw.fifos))->b_chans.txbz_b2;
370 fifo_state = hc->hw.fifo_en & HFCPCI_FIFOEN_B2TX;
372 bzt = &((union fifo_area *)(hc->hw.fifos))->b_chans.txbz_b1;
373 fifo_state = hc->hw.fifo_en & HFCPCI_FIFOEN_B1TX;
376 hc->hw.fifo_en ^= fifo_state;
377 Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
378 if (hc->bch[fifo].debug & DEBUG_HW_BCHANNEL)
379 printk(KERN_DEBUG "hfcpci_clear_fifo_tx%d f1(%x) f2(%x) "
380 "z1(%x) z2(%x) state(%x)\n",
381 fifo, bzt->f1, bzt->f2,
382 le16_to_cpu(bzt->za[MAX_B_FRAMES].z1),
383 le16_to_cpu(bzt->za[MAX_B_FRAMES].z2),
385 bzt->f2 = MAX_B_FRAMES;
386 bzt->f1 = bzt->f2; /* init F pointers to remain constant */
387 bzt->za[MAX_B_FRAMES].z1 = cpu_to_le16(B_FIFO_SIZE + B_SUB_VAL - 1);
388 bzt->za[MAX_B_FRAMES].z2 = cpu_to_le16(B_FIFO_SIZE + B_SUB_VAL - 2);
390 hc->hw.fifo_en |= fifo_state;
391 Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
392 if (hc->bch[fifo].debug & DEBUG_HW_BCHANNEL)
394 "hfcpci_clear_fifo_tx%d f1(%x) f2(%x) z1(%x) z2(%x)\n",
395 fifo, bzt->f1, bzt->f2,
396 le16_to_cpu(bzt->za[MAX_B_FRAMES].z1),
397 le16_to_cpu(bzt->za[MAX_B_FRAMES].z2));
401 * read a complete B-frame out of the buffer
404 hfcpci_empty_bfifo(struct bchannel *bch, struct bzfifo *bz,
405 u_char *bdata, int count)
407 u_char *ptr, *ptr1, new_f2;
411 if ((bch->debug & DEBUG_HW_BCHANNEL) && !(bch->debug & DEBUG_HW_BFIFO))
412 printk(KERN_DEBUG "hfcpci_empty_fifo\n");
413 zp = &bz->za[bz->f2]; /* point to Z-Regs */
414 new_z2 = le16_to_cpu(zp->z2) + count; /* new position in fifo */
415 if (new_z2 >= (B_FIFO_SIZE + B_SUB_VAL))
416 new_z2 -= B_FIFO_SIZE; /* buffer wrap */
417 new_f2 = (bz->f2 + 1) & MAX_B_FRAMES;
418 if ((count > MAX_DATA_SIZE + 3) || (count < 4) ||
419 (*(bdata + (le16_to_cpu(zp->z1) - B_SUB_VAL)))) {
420 if (bch->debug & DEBUG_HW)
421 printk(KERN_DEBUG "hfcpci_empty_fifo: incoming packet "
422 "invalid length %d or crc\n", count);
423 #ifdef ERROR_STATISTIC
426 bz->za[new_f2].z2 = cpu_to_le16(new_z2);
427 bz->f2 = new_f2; /* next buffer */
429 bch->rx_skb = mI_alloc_skb(count - 3, GFP_ATOMIC);
431 printk(KERN_WARNING "HFCPCI: receive out of memory\n");
435 ptr = skb_put(bch->rx_skb, count);
437 if (le16_to_cpu(zp->z2) + count <= B_FIFO_SIZE + B_SUB_VAL)
438 maxlen = count; /* complete transfer */
440 maxlen = B_FIFO_SIZE + B_SUB_VAL -
441 le16_to_cpu(zp->z2); /* maximum */
443 ptr1 = bdata + (le16_to_cpu(zp->z2) - B_SUB_VAL);
445 memcpy(ptr, ptr1, maxlen); /* copy data */
448 if (count) { /* rest remaining */
450 ptr1 = bdata; /* start of buffer */
451 memcpy(ptr, ptr1, count); /* rest */
453 bz->za[new_f2].z2 = cpu_to_le16(new_z2);
454 bz->f2 = new_f2; /* next buffer */
455 recv_Bchannel(bch, MISDN_ID_ANY);
460 * D-channel receive procedure
463 receive_dmsg(struct hfc_pci *hc)
465 struct dchannel *dch = &hc->dch;
473 df = &((union fifo_area *)(hc->hw.fifos))->d_chan.d_rx;
474 while (((df->f1 & D_FREG_MASK) != (df->f2 & D_FREG_MASK)) && count--) {
475 zp = &df->za[df->f2 & D_FREG_MASK];
476 rcnt = le16_to_cpu(zp->z1) - le16_to_cpu(zp->z2);
480 if (dch->debug & DEBUG_HW_DCHANNEL)
482 "hfcpci recd f1(%d) f2(%d) z1(%x) z2(%x) cnt(%d)\n",
488 if ((rcnt > MAX_DFRAME_LEN + 3) || (rcnt < 4) ||
489 (df->data[le16_to_cpu(zp->z1)])) {
490 if (dch->debug & DEBUG_HW)
492 "empty_fifo hfcpci paket inv. len "
495 df->data[le16_to_cpu(zp->z1)]);
496 #ifdef ERROR_STATISTIC
499 df->f2 = ((df->f2 + 1) & MAX_D_FRAMES) |
500 (MAX_D_FRAMES + 1); /* next buffer */
501 df->za[df->f2 & D_FREG_MASK].z2 =
502 cpu_to_le16((le16_to_cpu(zp->z2) + rcnt) &
505 dch->rx_skb = mI_alloc_skb(rcnt - 3, GFP_ATOMIC);
508 "HFC-PCI: D receive out of memory\n");
513 ptr = skb_put(dch->rx_skb, rcnt);
515 if (le16_to_cpu(zp->z2) + rcnt <= D_FIFO_SIZE)
516 maxlen = rcnt; /* complete transfer */
518 maxlen = D_FIFO_SIZE - le16_to_cpu(zp->z2);
521 ptr1 = df->data + le16_to_cpu(zp->z2);
523 memcpy(ptr, ptr1, maxlen); /* copy data */
526 if (rcnt) { /* rest remaining */
528 ptr1 = df->data; /* start of buffer */
529 memcpy(ptr, ptr1, rcnt); /* rest */
531 df->f2 = ((df->f2 + 1) & MAX_D_FRAMES) |
532 (MAX_D_FRAMES + 1); /* next buffer */
533 df->za[df->f2 & D_FREG_MASK].z2 = cpu_to_le16((
534 le16_to_cpu(zp->z2) + total) & (D_FIFO_SIZE - 1));
542 * check for transparent receive data and read max one 'poll' size if avail
545 hfcpci_empty_fifo_trans(struct bchannel *bch, struct bzfifo *rxbz,
546 struct bzfifo *txbz, u_char *bdata)
548 __le16 *z1r, *z2r, *z1t, *z2t;
549 int new_z2, fcnt_rx, fcnt_tx, maxlen;
552 z1r = &rxbz->za[MAX_B_FRAMES].z1; /* pointer to z reg */
554 z1t = &txbz->za[MAX_B_FRAMES].z1;
557 fcnt_rx = le16_to_cpu(*z1r) - le16_to_cpu(*z2r);
559 return; /* no data avail */
562 fcnt_rx += B_FIFO_SIZE; /* bytes actually buffered */
563 new_z2 = le16_to_cpu(*z2r) + fcnt_rx; /* new position in fifo */
564 if (new_z2 >= (B_FIFO_SIZE + B_SUB_VAL))
565 new_z2 -= B_FIFO_SIZE; /* buffer wrap */
567 if (fcnt_rx > MAX_DATA_SIZE) { /* flush, if oversized */
568 *z2r = cpu_to_le16(new_z2); /* new position */
572 fcnt_tx = le16_to_cpu(*z2t) - le16_to_cpu(*z1t);
574 fcnt_tx += B_FIFO_SIZE;
575 /* fcnt_tx contains available bytes in tx-fifo */
576 fcnt_tx = B_FIFO_SIZE - fcnt_tx;
577 /* remaining bytes to send (bytes in tx-fifo) */
579 bch->rx_skb = mI_alloc_skb(fcnt_rx, GFP_ATOMIC);
581 ptr = skb_put(bch->rx_skb, fcnt_rx);
582 if (le16_to_cpu(*z2r) + fcnt_rx <= B_FIFO_SIZE + B_SUB_VAL)
583 maxlen = fcnt_rx; /* complete transfer */
585 maxlen = B_FIFO_SIZE + B_SUB_VAL - le16_to_cpu(*z2r);
588 ptr1 = bdata + (le16_to_cpu(*z2r) - B_SUB_VAL);
590 memcpy(ptr, ptr1, maxlen); /* copy data */
593 if (fcnt_rx) { /* rest remaining */
595 ptr1 = bdata; /* start of buffer */
596 memcpy(ptr, ptr1, fcnt_rx); /* rest */
598 recv_Bchannel(bch, fcnt_tx); /* bch, id */
600 printk(KERN_WARNING "HFCPCI: receive out of memory\n");
602 *z2r = cpu_to_le16(new_z2); /* new position */
606 * B-channel main receive routine
609 main_rec_hfcpci(struct bchannel *bch)
611 struct hfc_pci *hc = bch->hw;
613 int receive = 0, count = 5;
614 struct bzfifo *txbz, *rxbz;
618 if ((bch->nr & 2) && (!hc->hw.bswapped)) {
619 rxbz = &((union fifo_area *)(hc->hw.fifos))->b_chans.rxbz_b2;
620 txbz = &((union fifo_area *)(hc->hw.fifos))->b_chans.txbz_b2;
621 bdata = ((union fifo_area *)(hc->hw.fifos))->b_chans.rxdat_b2;
624 rxbz = &((union fifo_area *)(hc->hw.fifos))->b_chans.rxbz_b1;
625 txbz = &((union fifo_area *)(hc->hw.fifos))->b_chans.txbz_b1;
626 bdata = ((union fifo_area *)(hc->hw.fifos))->b_chans.rxdat_b1;
631 if (rxbz->f1 != rxbz->f2) {
632 if (bch->debug & DEBUG_HW_BCHANNEL)
633 printk(KERN_DEBUG "hfcpci rec ch(%x) f1(%d) f2(%d)\n",
634 bch->nr, rxbz->f1, rxbz->f2);
635 zp = &rxbz->za[rxbz->f2];
637 rcnt = le16_to_cpu(zp->z1) - le16_to_cpu(zp->z2);
641 if (bch->debug & DEBUG_HW_BCHANNEL)
643 "hfcpci rec ch(%x) z1(%x) z2(%x) cnt(%d)\n",
644 bch->nr, le16_to_cpu(zp->z1),
645 le16_to_cpu(zp->z2), rcnt);
646 hfcpci_empty_bfifo(bch, rxbz, bdata, rcnt);
647 rcnt = rxbz->f1 - rxbz->f2;
649 rcnt += MAX_B_FRAMES + 1;
650 if (hc->hw.last_bfifo_cnt[real_fifo] > rcnt + 1) {
652 hfcpci_clear_fifo_rx(hc, real_fifo);
654 hc->hw.last_bfifo_cnt[real_fifo] = rcnt;
659 } else if (test_bit(FLG_TRANSPARENT, &bch->Flags)) {
660 hfcpci_empty_fifo_trans(bch, rxbz, txbz, bdata);
664 if (count && receive)
670 * D-channel send routine
673 hfcpci_fill_dfifo(struct hfc_pci *hc)
675 struct dchannel *dch = &hc->dch;
677 int count, new_z1, maxlen;
679 u_char *src, *dst, new_f1;
681 if ((dch->debug & DEBUG_HW_DCHANNEL) && !(dch->debug & DEBUG_HW_DFIFO))
682 printk(KERN_DEBUG "%s\n", __func__);
686 count = dch->tx_skb->len - dch->tx_idx;
689 df = &((union fifo_area *) (hc->hw.fifos))->d_chan.d_tx;
691 if (dch->debug & DEBUG_HW_DFIFO)
692 printk(KERN_DEBUG "%s:f1(%d) f2(%d) z1(f1)(%x)\n", __func__,
694 le16_to_cpu(df->za[df->f1 & D_FREG_MASK].z1));
695 fcnt = df->f1 - df->f2; /* frame count actually buffered */
697 fcnt += (MAX_D_FRAMES + 1); /* if wrap around */
698 if (fcnt > (MAX_D_FRAMES - 1)) {
699 if (dch->debug & DEBUG_HW_DCHANNEL)
701 "hfcpci_fill_Dfifo more as 14 frames\n");
702 #ifdef ERROR_STATISTIC
707 /* now determine free bytes in FIFO buffer */
708 maxlen = le16_to_cpu(df->za[df->f2 & D_FREG_MASK].z2) -
709 le16_to_cpu(df->za[df->f1 & D_FREG_MASK].z1) - 1;
711 maxlen += D_FIFO_SIZE; /* count now contains available bytes */
713 if (dch->debug & DEBUG_HW_DCHANNEL)
714 printk(KERN_DEBUG "hfcpci_fill_Dfifo count(%d/%d)\n",
716 if (count > maxlen) {
717 if (dch->debug & DEBUG_HW_DCHANNEL)
718 printk(KERN_DEBUG "hfcpci_fill_Dfifo no fifo mem\n");
721 new_z1 = (le16_to_cpu(df->za[df->f1 & D_FREG_MASK].z1) + count) &
723 new_f1 = ((df->f1 + 1) & D_FREG_MASK) | (D_FREG_MASK + 1);
724 src = dch->tx_skb->data + dch->tx_idx; /* source pointer */
725 dst = df->data + le16_to_cpu(df->za[df->f1 & D_FREG_MASK].z1);
726 maxlen = D_FIFO_SIZE - le16_to_cpu(df->za[df->f1 & D_FREG_MASK].z1);
729 maxlen = count; /* limit size */
730 memcpy(dst, src, maxlen); /* first copy */
732 count -= maxlen; /* remaining bytes */
734 dst = df->data; /* start of buffer */
735 src += maxlen; /* new position */
736 memcpy(dst, src, count);
738 df->za[new_f1 & D_FREG_MASK].z1 = cpu_to_le16(new_z1);
739 /* for next buffer */
740 df->za[df->f1 & D_FREG_MASK].z1 = cpu_to_le16(new_z1);
741 /* new pos actual buffer */
742 df->f1 = new_f1; /* next frame */
743 dch->tx_idx = dch->tx_skb->len;
747 * B-channel send routine
750 hfcpci_fill_fifo(struct bchannel *bch)
752 struct hfc_pci *hc = bch->hw;
757 u_char new_f1, *src, *dst;
760 if ((bch->debug & DEBUG_HW_BCHANNEL) && !(bch->debug & DEBUG_HW_BFIFO))
761 printk(KERN_DEBUG "%s\n", __func__);
762 if ((!bch->tx_skb) || bch->tx_skb->len <= 0)
764 count = bch->tx_skb->len - bch->tx_idx;
765 if ((bch->nr & 2) && (!hc->hw.bswapped)) {
766 bz = &((union fifo_area *)(hc->hw.fifos))->b_chans.txbz_b2;
767 bdata = ((union fifo_area *)(hc->hw.fifos))->b_chans.txdat_b2;
769 bz = &((union fifo_area *)(hc->hw.fifos))->b_chans.txbz_b1;
770 bdata = ((union fifo_area *)(hc->hw.fifos))->b_chans.txdat_b1;
773 if (test_bit(FLG_TRANSPARENT, &bch->Flags)) {
774 z1t = &bz->za[MAX_B_FRAMES].z1;
776 if (bch->debug & DEBUG_HW_BCHANNEL)
777 printk(KERN_DEBUG "hfcpci_fill_fifo_trans ch(%x) "
778 "cnt(%d) z1(%x) z2(%x)\n", bch->nr, count,
779 le16_to_cpu(*z1t), le16_to_cpu(*z2t));
780 fcnt = le16_to_cpu(*z2t) - le16_to_cpu(*z1t);
783 /* fcnt contains available bytes in fifo */
784 fcnt = B_FIFO_SIZE - fcnt;
785 /* remaining bytes to send (bytes in fifo) */
787 /* "fill fifo if empty" feature */
788 if (test_bit(FLG_FILLEMPTY, &bch->Flags) && !fcnt) {
789 /* printk(KERN_DEBUG "%s: buffer empty, so we have "
790 "underrun\n", __func__); */
791 /* fill buffer, to prevent future underrun */
792 count = HFCPCI_FILLEMPTY;
793 new_z1 = le16_to_cpu(*z1t) + count;
794 /* new buffer Position */
795 if (new_z1 >= (B_FIFO_SIZE + B_SUB_VAL))
796 new_z1 -= B_FIFO_SIZE; /* buffer wrap */
797 dst = bdata + (le16_to_cpu(*z1t) - B_SUB_VAL);
798 maxlen = (B_FIFO_SIZE + B_SUB_VAL) - le16_to_cpu(*z1t);
800 if (bch->debug & DEBUG_HW_BFIFO)
801 printk(KERN_DEBUG "hfcpci_FFt fillempty "
802 "fcnt(%d) maxl(%d) nz1(%x) dst(%p)\n",
803 fcnt, maxlen, new_z1, dst);
806 maxlen = count; /* limit size */
807 memset(dst, 0x2a, maxlen); /* first copy */
808 count -= maxlen; /* remaining bytes */
810 dst = bdata; /* start of buffer */
811 memset(dst, 0x2a, count);
813 *z1t = cpu_to_le16(new_z1); /* now send data */
817 count = bch->tx_skb->len - bch->tx_idx;
818 /* maximum fill shall be poll*2 */
819 if (count > (poll << 1) - fcnt)
820 count = (poll << 1) - fcnt;
823 /* data is suitable for fifo */
824 new_z1 = le16_to_cpu(*z1t) + count;
825 /* new buffer Position */
826 if (new_z1 >= (B_FIFO_SIZE + B_SUB_VAL))
827 new_z1 -= B_FIFO_SIZE; /* buffer wrap */
828 src = bch->tx_skb->data + bch->tx_idx;
830 dst = bdata + (le16_to_cpu(*z1t) - B_SUB_VAL);
831 maxlen = (B_FIFO_SIZE + B_SUB_VAL) - le16_to_cpu(*z1t);
833 if (bch->debug & DEBUG_HW_BFIFO)
834 printk(KERN_DEBUG "hfcpci_FFt fcnt(%d) "
835 "maxl(%d) nz1(%x) dst(%p)\n",
836 fcnt, maxlen, new_z1, dst);
838 bch->tx_idx += count;
840 maxlen = count; /* limit size */
841 memcpy(dst, src, maxlen); /* first copy */
842 count -= maxlen; /* remaining bytes */
844 dst = bdata; /* start of buffer */
845 src += maxlen; /* new position */
846 memcpy(dst, src, count);
848 *z1t = cpu_to_le16(new_z1); /* now send data */
849 if (bch->tx_idx < bch->tx_skb->len)
851 /* send confirm, on trans, free on hdlc. */
852 if (test_bit(FLG_TRANSPARENT, &bch->Flags))
854 dev_kfree_skb(bch->tx_skb);
855 if (get_next_bframe(bch))
859 if (bch->debug & DEBUG_HW_BCHANNEL)
861 "%s: ch(%x) f1(%d) f2(%d) z1(f1)(%x)\n",
862 __func__, bch->nr, bz->f1, bz->f2,
864 fcnt = bz->f1 - bz->f2; /* frame count actually buffered */
866 fcnt += (MAX_B_FRAMES + 1); /* if wrap around */
867 if (fcnt > (MAX_B_FRAMES - 1)) {
868 if (bch->debug & DEBUG_HW_BCHANNEL)
870 "hfcpci_fill_Bfifo more as 14 frames\n");
873 /* now determine free bytes in FIFO buffer */
874 maxlen = le16_to_cpu(bz->za[bz->f2].z2) -
875 le16_to_cpu(bz->za[bz->f1].z1) - 1;
877 maxlen += B_FIFO_SIZE; /* count now contains available bytes */
879 if (bch->debug & DEBUG_HW_BCHANNEL)
880 printk(KERN_DEBUG "hfcpci_fill_fifo ch(%x) count(%d/%d)\n",
881 bch->nr, count, maxlen);
883 if (maxlen < count) {
884 if (bch->debug & DEBUG_HW_BCHANNEL)
885 printk(KERN_DEBUG "hfcpci_fill_fifo no fifo mem\n");
888 new_z1 = le16_to_cpu(bz->za[bz->f1].z1) + count;
889 /* new buffer Position */
890 if (new_z1 >= (B_FIFO_SIZE + B_SUB_VAL))
891 new_z1 -= B_FIFO_SIZE; /* buffer wrap */
893 new_f1 = ((bz->f1 + 1) & MAX_B_FRAMES);
894 src = bch->tx_skb->data + bch->tx_idx; /* source pointer */
895 dst = bdata + (le16_to_cpu(bz->za[bz->f1].z1) - B_SUB_VAL);
896 maxlen = (B_FIFO_SIZE + B_SUB_VAL) - le16_to_cpu(bz->za[bz->f1].z1);
899 maxlen = count; /* limit size */
900 memcpy(dst, src, maxlen); /* first copy */
902 count -= maxlen; /* remaining bytes */
904 dst = bdata; /* start of buffer */
905 src += maxlen; /* new position */
906 memcpy(dst, src, count);
908 bz->za[new_f1].z1 = cpu_to_le16(new_z1); /* for next buffer */
909 bz->f1 = new_f1; /* next frame */
910 dev_kfree_skb(bch->tx_skb);
911 get_next_bframe(bch);
917 * handle L1 state changes TE
921 ph_state_te(struct dchannel *dch)
924 printk(KERN_DEBUG "%s: TE newstate %x\n",
925 __func__, dch->state);
926 switch (dch->state) {
928 l1_event(dch->l1, HW_RESET_IND);
931 l1_event(dch->l1, HW_DEACT_IND);
935 l1_event(dch->l1, ANYSIGNAL);
938 l1_event(dch->l1, INFO2);
941 l1_event(dch->l1, INFO4_P8);
947 * handle L1 state changes NT
951 handle_nt_timer3(struct dchannel *dch) {
952 struct hfc_pci *hc = dch->hw;
954 test_and_clear_bit(FLG_HFC_TIMER_T3, &dch->Flags);
955 hc->hw.int_m1 &= ~HFCPCI_INTS_TIMER;
956 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
958 test_and_set_bit(FLG_ACTIVE, &dch->Flags);
959 if (test_bit(HFC_CFG_MASTER, &hc->cfg))
960 hc->hw.mst_m |= HFCPCI_MASTER;
961 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
962 _queue_data(&dch->dev.D, PH_ACTIVATE_IND,
963 MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
967 ph_state_nt(struct dchannel *dch)
969 struct hfc_pci *hc = dch->hw;
972 printk(KERN_DEBUG "%s: NT newstate %x\n",
973 __func__, dch->state);
974 switch (dch->state) {
976 if (hc->hw.nt_timer < 0) {
978 test_and_clear_bit(FLG_HFC_TIMER_T3, &dch->Flags);
979 test_and_clear_bit(FLG_HFC_TIMER_T1, &dch->Flags);
980 hc->hw.int_m1 &= ~HFCPCI_INTS_TIMER;
981 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
982 /* Clear already pending ints */
983 (void) Read_hfc(hc, HFCPCI_INT_S1);
984 Write_hfc(hc, HFCPCI_STATES, 4 | HFCPCI_LOAD_STATE);
986 Write_hfc(hc, HFCPCI_STATES, 4);
988 } else if (hc->hw.nt_timer == 0) {
989 hc->hw.int_m1 |= HFCPCI_INTS_TIMER;
990 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
991 hc->hw.nt_timer = NT_T1_COUNT;
992 hc->hw.ctmt &= ~HFCPCI_AUTO_TIMER;
993 hc->hw.ctmt |= HFCPCI_TIM3_125;
994 Write_hfc(hc, HFCPCI_CTMT, hc->hw.ctmt |
996 test_and_clear_bit(FLG_HFC_TIMER_T3, &dch->Flags);
997 test_and_set_bit(FLG_HFC_TIMER_T1, &dch->Flags);
998 /* allow G2 -> G3 transition */
999 Write_hfc(hc, HFCPCI_STATES, 2 | HFCPCI_NT_G2_G3);
1001 Write_hfc(hc, HFCPCI_STATES, 2 | HFCPCI_NT_G2_G3);
1005 hc->hw.nt_timer = 0;
1006 test_and_clear_bit(FLG_HFC_TIMER_T3, &dch->Flags);
1007 test_and_clear_bit(FLG_HFC_TIMER_T1, &dch->Flags);
1008 hc->hw.int_m1 &= ~HFCPCI_INTS_TIMER;
1009 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
1010 test_and_clear_bit(FLG_ACTIVE, &dch->Flags);
1011 hc->hw.mst_m &= ~HFCPCI_MASTER;
1012 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
1013 test_and_clear_bit(FLG_L2_ACTIVATED, &dch->Flags);
1014 _queue_data(&dch->dev.D, PH_DEACTIVATE_IND,
1015 MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
1018 hc->hw.nt_timer = 0;
1019 test_and_clear_bit(FLG_HFC_TIMER_T3, &dch->Flags);
1020 test_and_clear_bit(FLG_HFC_TIMER_T1, &dch->Flags);
1021 hc->hw.int_m1 &= ~HFCPCI_INTS_TIMER;
1022 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
1025 if (!test_and_set_bit(FLG_HFC_TIMER_T3, &dch->Flags)) {
1026 if (!test_and_clear_bit(FLG_L2_ACTIVATED,
1028 handle_nt_timer3(dch);
1031 test_and_clear_bit(FLG_HFC_TIMER_T1, &dch->Flags);
1032 hc->hw.int_m1 |= HFCPCI_INTS_TIMER;
1033 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
1034 hc->hw.nt_timer = NT_T3_COUNT;
1035 hc->hw.ctmt &= ~HFCPCI_AUTO_TIMER;
1036 hc->hw.ctmt |= HFCPCI_TIM3_125;
1037 Write_hfc(hc, HFCPCI_CTMT, hc->hw.ctmt |
1045 ph_state(struct dchannel *dch)
1047 struct hfc_pci *hc = dch->hw;
1049 if (hc->hw.protocol == ISDN_P_NT_S0) {
1050 if (test_bit(FLG_HFC_TIMER_T3, &dch->Flags) &&
1051 hc->hw.nt_timer < 0)
1052 handle_nt_timer3(dch);
1060 * Layer 1 callback function
1063 hfc_l1callback(struct dchannel *dch, u_int cmd)
1065 struct hfc_pci *hc = dch->hw;
1070 if (test_bit(HFC_CFG_MASTER, &hc->cfg))
1071 hc->hw.mst_m |= HFCPCI_MASTER;
1072 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
1075 Write_hfc(hc, HFCPCI_STATES, HFCPCI_LOAD_STATE | 3);
1078 Write_hfc(hc, HFCPCI_STATES, 3); /* HFC ST 2 */
1079 if (test_bit(HFC_CFG_MASTER, &hc->cfg))
1080 hc->hw.mst_m |= HFCPCI_MASTER;
1081 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
1082 Write_hfc(hc, HFCPCI_STATES, HFCPCI_ACTIVATE |
1084 l1_event(dch->l1, HW_POWERUP_IND);
1087 hc->hw.mst_m &= ~HFCPCI_MASTER;
1088 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
1089 skb_queue_purge(&dch->squeue);
1091 dev_kfree_skb(dch->tx_skb);
1096 dev_kfree_skb(dch->rx_skb);
1099 test_and_clear_bit(FLG_TX_BUSY, &dch->Flags);
1100 if (test_and_clear_bit(FLG_BUSY_TIMER, &dch->Flags))
1101 del_timer(&dch->timer);
1103 case HW_POWERUP_REQ:
1104 Write_hfc(hc, HFCPCI_STATES, HFCPCI_DO_ACTION);
1106 case PH_ACTIVATE_IND:
1107 test_and_set_bit(FLG_ACTIVE, &dch->Flags);
1108 _queue_data(&dch->dev.D, cmd, MISDN_ID_ANY, 0, NULL,
1111 case PH_DEACTIVATE_IND:
1112 test_and_clear_bit(FLG_ACTIVE, &dch->Flags);
1113 _queue_data(&dch->dev.D, cmd, MISDN_ID_ANY, 0, NULL,
1117 if (dch->debug & DEBUG_HW)
1118 printk(KERN_DEBUG "%s: unknown command %x\n",
1129 tx_birq(struct bchannel *bch)
1131 if (bch->tx_skb && bch->tx_idx < bch->tx_skb->len)
1132 hfcpci_fill_fifo(bch);
1135 dev_kfree_skb(bch->tx_skb);
1136 if (get_next_bframe(bch))
1137 hfcpci_fill_fifo(bch);
1142 tx_dirq(struct dchannel *dch)
1144 if (dch->tx_skb && dch->tx_idx < dch->tx_skb->len)
1145 hfcpci_fill_dfifo(dch->hw);
1148 dev_kfree_skb(dch->tx_skb);
1149 if (get_next_dframe(dch))
1150 hfcpci_fill_dfifo(dch->hw);
1155 hfcpci_int(int intno, void *dev_id)
1157 struct hfc_pci *hc = dev_id;
1159 struct bchannel *bch;
1162 spin_lock(&hc->lock);
1163 if (!(hc->hw.int_m2 & 0x08)) {
1164 spin_unlock(&hc->lock);
1165 return IRQ_NONE; /* not initialised */
1167 stat = Read_hfc(hc, HFCPCI_STATUS);
1168 if (HFCPCI_ANYINT & stat) {
1169 val = Read_hfc(hc, HFCPCI_INT_S1);
1170 if (hc->dch.debug & DEBUG_HW_DCHANNEL)
1172 "HFC-PCI: stat(%02x) s1(%02x)\n", stat, val);
1175 spin_unlock(&hc->lock);
1180 if (hc->dch.debug & DEBUG_HW_DCHANNEL)
1181 printk(KERN_DEBUG "HFC-PCI irq %x\n", val);
1182 val &= hc->hw.int_m1;
1183 if (val & 0x40) { /* state machine irq */
1184 exval = Read_hfc(hc, HFCPCI_STATES) & 0xf;
1185 if (hc->dch.debug & DEBUG_HW_DCHANNEL)
1186 printk(KERN_DEBUG "ph_state chg %d->%d\n",
1187 hc->dch.state, exval);
1188 hc->dch.state = exval;
1189 schedule_event(&hc->dch, FLG_PHCHANGE);
1192 if (val & 0x80) { /* timer irq */
1193 if (hc->hw.protocol == ISDN_P_NT_S0) {
1194 if ((--hc->hw.nt_timer) < 0)
1195 schedule_event(&hc->dch, FLG_PHCHANGE);
1198 Write_hfc(hc, HFCPCI_CTMT, hc->hw.ctmt | HFCPCI_CLTIMER);
1200 if (val & 0x08) { /* B1 rx */
1201 bch = Sel_BCS(hc, hc->hw.bswapped ? 2 : 1);
1203 main_rec_hfcpci(bch);
1204 else if (hc->dch.debug)
1205 printk(KERN_DEBUG "hfcpci spurious 0x08 IRQ\n");
1207 if (val & 0x10) { /* B2 rx */
1208 bch = Sel_BCS(hc, 2);
1210 main_rec_hfcpci(bch);
1211 else if (hc->dch.debug)
1212 printk(KERN_DEBUG "hfcpci spurious 0x10 IRQ\n");
1214 if (val & 0x01) { /* B1 tx */
1215 bch = Sel_BCS(hc, hc->hw.bswapped ? 2 : 1);
1218 else if (hc->dch.debug)
1219 printk(KERN_DEBUG "hfcpci spurious 0x01 IRQ\n");
1221 if (val & 0x02) { /* B2 tx */
1222 bch = Sel_BCS(hc, 2);
1225 else if (hc->dch.debug)
1226 printk(KERN_DEBUG "hfcpci spurious 0x02 IRQ\n");
1228 if (val & 0x20) /* D rx */
1230 if (val & 0x04) { /* D tx */
1231 if (test_and_clear_bit(FLG_BUSY_TIMER, &hc->dch.Flags))
1232 del_timer(&hc->dch.timer);
1235 spin_unlock(&hc->lock);
1240 * timer callback for D-chan busy resolution. Currently no function
1243 hfcpci_dbusy_timer(struct hfc_pci *hc)
1248 * activate/deactivate hardware for selected channels and mode
1251 mode_hfcpci(struct bchannel *bch, int bc, int protocol)
1253 struct hfc_pci *hc = bch->hw;
1255 u_char rx_slot = 0, tx_slot = 0, pcm_mode;
1257 if (bch->debug & DEBUG_HW_BCHANNEL)
1259 "HFCPCI bchannel protocol %x-->%x ch %x-->%x\n",
1260 bch->state, protocol, bch->nr, bc);
1263 pcm_mode = (bc>>24) & 0xff;
1264 if (pcm_mode) { /* PCM SLOT USE */
1265 if (!test_bit(HFC_CFG_PCM, &hc->cfg))
1267 "%s: pcm channel id without HFC_CFG_PCM\n",
1269 rx_slot = (bc>>8) & 0xff;
1270 tx_slot = (bc>>16) & 0xff;
1272 } else if (test_bit(HFC_CFG_PCM, &hc->cfg) && (protocol > ISDN_P_NONE))
1273 printk(KERN_WARNING "%s: no pcm channel id but HFC_CFG_PCM\n",
1275 if (hc->chanlimit > 1) {
1276 hc->hw.bswapped = 0; /* B1 and B2 normal mode */
1277 hc->hw.sctrl_e &= ~0x80;
1280 if (protocol != ISDN_P_NONE) {
1281 hc->hw.bswapped = 1; /* B1 and B2 exchanged */
1282 hc->hw.sctrl_e |= 0x80;
1284 hc->hw.bswapped = 0; /* B1 and B2 normal mode */
1285 hc->hw.sctrl_e &= ~0x80;
1289 hc->hw.bswapped = 0; /* B1 and B2 normal mode */
1290 hc->hw.sctrl_e &= ~0x80;
1294 case (-1): /* used for init */
1298 if (bch->state == ISDN_P_NONE)
1301 hc->hw.sctrl &= ~SCTRL_B2_ENA;
1302 hc->hw.sctrl_r &= ~SCTRL_B2_ENA;
1304 hc->hw.sctrl &= ~SCTRL_B1_ENA;
1305 hc->hw.sctrl_r &= ~SCTRL_B1_ENA;
1308 hc->hw.fifo_en &= ~HFCPCI_FIFOEN_B2;
1309 hc->hw.int_m1 &= ~(HFCPCI_INTS_B2TRANS +
1312 hc->hw.fifo_en &= ~HFCPCI_FIFOEN_B1;
1313 hc->hw.int_m1 &= ~(HFCPCI_INTS_B1TRANS +
1316 #ifdef REVERSE_BITORDER
1318 hc->hw.cirm &= 0x7f;
1320 hc->hw.cirm &= 0xbf;
1322 bch->state = ISDN_P_NONE;
1324 test_and_clear_bit(FLG_HDLC, &bch->Flags);
1325 test_and_clear_bit(FLG_TRANSPARENT, &bch->Flags);
1327 case (ISDN_P_B_RAW):
1328 bch->state = protocol;
1330 hfcpci_clear_fifo_rx(hc, (fifo2 & 2) ? 1 : 0);
1331 hfcpci_clear_fifo_tx(hc, (fifo2 & 2) ? 1 : 0);
1333 hc->hw.sctrl |= SCTRL_B2_ENA;
1334 hc->hw.sctrl_r |= SCTRL_B2_ENA;
1335 #ifdef REVERSE_BITORDER
1336 hc->hw.cirm |= 0x80;
1339 hc->hw.sctrl |= SCTRL_B1_ENA;
1340 hc->hw.sctrl_r |= SCTRL_B1_ENA;
1341 #ifdef REVERSE_BITORDER
1342 hc->hw.cirm |= 0x40;
1346 hc->hw.fifo_en |= HFCPCI_FIFOEN_B2;
1348 hc->hw.int_m1 |= (HFCPCI_INTS_B2TRANS +
1351 hc->hw.conn &= ~0x18;
1353 hc->hw.fifo_en |= HFCPCI_FIFOEN_B1;
1355 hc->hw.int_m1 |= (HFCPCI_INTS_B1TRANS +
1358 hc->hw.conn &= ~0x03;
1360 test_and_set_bit(FLG_TRANSPARENT, &bch->Flags);
1362 case (ISDN_P_B_HDLC):
1363 bch->state = protocol;
1365 hfcpci_clear_fifo_rx(hc, (fifo2 & 2) ? 1 : 0);
1366 hfcpci_clear_fifo_tx(hc, (fifo2 & 2) ? 1 : 0);
1368 hc->hw.sctrl |= SCTRL_B2_ENA;
1369 hc->hw.sctrl_r |= SCTRL_B2_ENA;
1371 hc->hw.sctrl |= SCTRL_B1_ENA;
1372 hc->hw.sctrl_r |= SCTRL_B1_ENA;
1375 hc->hw.last_bfifo_cnt[1] = 0;
1376 hc->hw.fifo_en |= HFCPCI_FIFOEN_B2;
1377 hc->hw.int_m1 |= (HFCPCI_INTS_B2TRANS +
1380 hc->hw.conn &= ~0x18;
1382 hc->hw.last_bfifo_cnt[0] = 0;
1383 hc->hw.fifo_en |= HFCPCI_FIFOEN_B1;
1384 hc->hw.int_m1 |= (HFCPCI_INTS_B1TRANS +
1387 hc->hw.conn &= ~0x03;
1389 test_and_set_bit(FLG_HDLC, &bch->Flags);
1392 printk(KERN_DEBUG "prot not known %x\n", protocol);
1393 return -ENOPROTOOPT;
1395 if (test_bit(HFC_CFG_PCM, &hc->cfg)) {
1396 if ((protocol == ISDN_P_NONE) ||
1397 (protocol == -1)) { /* init case */
1401 if (test_bit(HFC_CFG_SW_DD_DU, &hc->cfg)) {
1410 hc->hw.conn &= 0xc7;
1411 hc->hw.conn |= 0x08;
1412 printk(KERN_DEBUG "%s: Write_hfc: B2_SSL 0x%x\n",
1414 printk(KERN_DEBUG "%s: Write_hfc: B2_RSL 0x%x\n",
1416 Write_hfc(hc, HFCPCI_B2_SSL, tx_slot);
1417 Write_hfc(hc, HFCPCI_B2_RSL, rx_slot);
1419 hc->hw.conn &= 0xf8;
1420 hc->hw.conn |= 0x01;
1421 printk(KERN_DEBUG "%s: Write_hfc: B1_SSL 0x%x\n",
1423 printk(KERN_DEBUG "%s: Write_hfc: B1_RSL 0x%x\n",
1425 Write_hfc(hc, HFCPCI_B1_SSL, tx_slot);
1426 Write_hfc(hc, HFCPCI_B1_RSL, rx_slot);
1429 Write_hfc(hc, HFCPCI_SCTRL_E, hc->hw.sctrl_e);
1430 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
1431 Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
1432 Write_hfc(hc, HFCPCI_SCTRL, hc->hw.sctrl);
1433 Write_hfc(hc, HFCPCI_SCTRL_R, hc->hw.sctrl_r);
1434 Write_hfc(hc, HFCPCI_CTMT, hc->hw.ctmt);
1435 Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
1436 #ifdef REVERSE_BITORDER
1437 Write_hfc(hc, HFCPCI_CIRM, hc->hw.cirm);
1443 set_hfcpci_rxtest(struct bchannel *bch, int protocol, int chan)
1445 struct hfc_pci *hc = bch->hw;
1447 if (bch->debug & DEBUG_HW_BCHANNEL)
1449 "HFCPCI bchannel test rx protocol %x-->%x ch %x-->%x\n",
1450 bch->state, protocol, bch->nr, chan);
1451 if (bch->nr != chan) {
1453 "HFCPCI rxtest wrong channel parameter %x/%x\n",
1458 case (ISDN_P_B_RAW):
1459 bch->state = protocol;
1460 hfcpci_clear_fifo_rx(hc, (chan & 2) ? 1 : 0);
1462 hc->hw.sctrl_r |= SCTRL_B2_ENA;
1463 hc->hw.fifo_en |= HFCPCI_FIFOEN_B2RX;
1465 hc->hw.int_m1 |= HFCPCI_INTS_B2REC;
1467 hc->hw.conn &= ~0x18;
1468 #ifdef REVERSE_BITORDER
1469 hc->hw.cirm |= 0x80;
1472 hc->hw.sctrl_r |= SCTRL_B1_ENA;
1473 hc->hw.fifo_en |= HFCPCI_FIFOEN_B1RX;
1475 hc->hw.int_m1 |= HFCPCI_INTS_B1REC;
1477 hc->hw.conn &= ~0x03;
1478 #ifdef REVERSE_BITORDER
1479 hc->hw.cirm |= 0x40;
1483 case (ISDN_P_B_HDLC):
1484 bch->state = protocol;
1485 hfcpci_clear_fifo_rx(hc, (chan & 2) ? 1 : 0);
1487 hc->hw.sctrl_r |= SCTRL_B2_ENA;
1488 hc->hw.last_bfifo_cnt[1] = 0;
1489 hc->hw.fifo_en |= HFCPCI_FIFOEN_B2RX;
1490 hc->hw.int_m1 |= HFCPCI_INTS_B2REC;
1492 hc->hw.conn &= ~0x18;
1494 hc->hw.sctrl_r |= SCTRL_B1_ENA;
1495 hc->hw.last_bfifo_cnt[0] = 0;
1496 hc->hw.fifo_en |= HFCPCI_FIFOEN_B1RX;
1497 hc->hw.int_m1 |= HFCPCI_INTS_B1REC;
1499 hc->hw.conn &= ~0x03;
1503 printk(KERN_DEBUG "prot not known %x\n", protocol);
1504 return -ENOPROTOOPT;
1506 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
1507 Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
1508 Write_hfc(hc, HFCPCI_SCTRL_R, hc->hw.sctrl_r);
1509 Write_hfc(hc, HFCPCI_CTMT, hc->hw.ctmt);
1510 Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
1511 #ifdef REVERSE_BITORDER
1512 Write_hfc(hc, HFCPCI_CIRM, hc->hw.cirm);
1518 deactivate_bchannel(struct bchannel *bch)
1520 struct hfc_pci *hc = bch->hw;
1523 spin_lock_irqsave(&hc->lock, flags);
1524 mISDN_clear_bchannel(bch);
1525 mode_hfcpci(bch, bch->nr, ISDN_P_NONE);
1526 spin_unlock_irqrestore(&hc->lock, flags);
1530 * Layer 1 B-channel hardware access
1533 channel_bctrl(struct bchannel *bch, struct mISDN_ctrl_req *cq)
1538 case MISDN_CTRL_GETOP:
1539 cq->op = MISDN_CTRL_FILL_EMPTY;
1541 case MISDN_CTRL_FILL_EMPTY: /* fill fifo, if empty */
1542 test_and_set_bit(FLG_FILLEMPTY, &bch->Flags);
1543 if (debug & DEBUG_HW_OPEN)
1544 printk(KERN_DEBUG "%s: FILL_EMPTY request (nr=%d "
1545 "off=%d)\n", __func__, bch->nr, !!cq->p1);
1548 printk(KERN_WARNING "%s: unknown Op %x\n", __func__, cq->op);
1555 hfc_bctrl(struct mISDNchannel *ch, u_int cmd, void *arg)
1557 struct bchannel *bch = container_of(ch, struct bchannel, ch);
1558 struct hfc_pci *hc = bch->hw;
1562 if (bch->debug & DEBUG_HW)
1563 printk(KERN_DEBUG "%s: cmd:%x %p\n", __func__, cmd, arg);
1566 spin_lock_irqsave(&hc->lock, flags);
1567 ret = set_hfcpci_rxtest(bch, ISDN_P_B_RAW, (int)(long)arg);
1568 spin_unlock_irqrestore(&hc->lock, flags);
1570 case HW_TESTRX_HDLC:
1571 spin_lock_irqsave(&hc->lock, flags);
1572 ret = set_hfcpci_rxtest(bch, ISDN_P_B_HDLC, (int)(long)arg);
1573 spin_unlock_irqrestore(&hc->lock, flags);
1576 spin_lock_irqsave(&hc->lock, flags);
1577 mode_hfcpci(bch, bch->nr, ISDN_P_NONE);
1578 spin_unlock_irqrestore(&hc->lock, flags);
1582 test_and_clear_bit(FLG_OPEN, &bch->Flags);
1583 if (test_bit(FLG_ACTIVE, &bch->Flags))
1584 deactivate_bchannel(bch);
1585 ch->protocol = ISDN_P_NONE;
1587 module_put(THIS_MODULE);
1590 case CONTROL_CHANNEL:
1591 ret = channel_bctrl(bch, arg);
1594 printk(KERN_WARNING "%s: unknown prim(%x)\n",
1601 * Layer2 -> Layer 1 Dchannel data
1604 hfcpci_l2l1D(struct mISDNchannel *ch, struct sk_buff *skb)
1606 struct mISDNdevice *dev = container_of(ch, struct mISDNdevice, D);
1607 struct dchannel *dch = container_of(dev, struct dchannel, dev);
1608 struct hfc_pci *hc = dch->hw;
1610 struct mISDNhead *hh = mISDN_HEAD_P(skb);
1616 spin_lock_irqsave(&hc->lock, flags);
1617 ret = dchannel_senddata(dch, skb);
1618 if (ret > 0) { /* direct TX */
1619 id = hh->id; /* skb can be freed */
1620 hfcpci_fill_dfifo(dch->hw);
1622 spin_unlock_irqrestore(&hc->lock, flags);
1623 queue_ch_frame(ch, PH_DATA_CNF, id, NULL);
1625 spin_unlock_irqrestore(&hc->lock, flags);
1627 case PH_ACTIVATE_REQ:
1628 spin_lock_irqsave(&hc->lock, flags);
1629 if (hc->hw.protocol == ISDN_P_NT_S0) {
1631 if (test_bit(HFC_CFG_MASTER, &hc->cfg))
1632 hc->hw.mst_m |= HFCPCI_MASTER;
1633 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
1634 if (test_bit(FLG_ACTIVE, &dch->Flags)) {
1635 spin_unlock_irqrestore(&hc->lock, flags);
1636 _queue_data(&dch->dev.D, PH_ACTIVATE_IND,
1637 MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
1640 test_and_set_bit(FLG_L2_ACTIVATED, &dch->Flags);
1641 Write_hfc(hc, HFCPCI_STATES, HFCPCI_ACTIVATE |
1642 HFCPCI_DO_ACTION | 1);
1644 ret = l1_event(dch->l1, hh->prim);
1645 spin_unlock_irqrestore(&hc->lock, flags);
1647 case PH_DEACTIVATE_REQ:
1648 test_and_clear_bit(FLG_L2_ACTIVATED, &dch->Flags);
1649 spin_lock_irqsave(&hc->lock, flags);
1650 if (hc->hw.protocol == ISDN_P_NT_S0) {
1651 /* prepare deactivation */
1652 Write_hfc(hc, HFCPCI_STATES, 0x40);
1653 skb_queue_purge(&dch->squeue);
1655 dev_kfree_skb(dch->tx_skb);
1660 dev_kfree_skb(dch->rx_skb);
1663 test_and_clear_bit(FLG_TX_BUSY, &dch->Flags);
1664 if (test_and_clear_bit(FLG_BUSY_TIMER, &dch->Flags))
1665 del_timer(&dch->timer);
1667 if (test_and_clear_bit(FLG_L1_BUSY, &dch->Flags))
1668 dchannel_sched_event(&hc->dch, D_CLEARBUSY);
1670 hc->hw.mst_m &= ~HFCPCI_MASTER;
1671 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
1674 ret = l1_event(dch->l1, hh->prim);
1676 spin_unlock_irqrestore(&hc->lock, flags);
1685 * Layer2 -> Layer 1 Bchannel data
1688 hfcpci_l2l1B(struct mISDNchannel *ch, struct sk_buff *skb)
1690 struct bchannel *bch = container_of(ch, struct bchannel, ch);
1691 struct hfc_pci *hc = bch->hw;
1693 struct mISDNhead *hh = mISDN_HEAD_P(skb);
1699 spin_lock_irqsave(&hc->lock, flags);
1700 ret = bchannel_senddata(bch, skb);
1701 if (ret > 0) { /* direct TX */
1702 id = hh->id; /* skb can be freed */
1703 hfcpci_fill_fifo(bch);
1705 spin_unlock_irqrestore(&hc->lock, flags);
1706 if (!test_bit(FLG_TRANSPARENT, &bch->Flags))
1707 queue_ch_frame(ch, PH_DATA_CNF, id, NULL);
1709 spin_unlock_irqrestore(&hc->lock, flags);
1711 case PH_ACTIVATE_REQ:
1712 spin_lock_irqsave(&hc->lock, flags);
1713 if (!test_and_set_bit(FLG_ACTIVE, &bch->Flags))
1714 ret = mode_hfcpci(bch, bch->nr, ch->protocol);
1717 spin_unlock_irqrestore(&hc->lock, flags);
1719 _queue_data(ch, PH_ACTIVATE_IND, MISDN_ID_ANY, 0,
1722 case PH_DEACTIVATE_REQ:
1723 deactivate_bchannel(bch);
1724 _queue_data(ch, PH_DEACTIVATE_IND, MISDN_ID_ANY, 0,
1735 * called for card init message
1739 inithfcpci(struct hfc_pci *hc)
1741 printk(KERN_DEBUG "inithfcpci: entered\n");
1742 hc->dch.timer.function = (void *) hfcpci_dbusy_timer;
1743 hc->dch.timer.data = (long) &hc->dch;
1744 init_timer(&hc->dch.timer);
1746 mode_hfcpci(&hc->bch[0], 1, -1);
1747 mode_hfcpci(&hc->bch[1], 2, -1);
1752 init_card(struct hfc_pci *hc)
1757 printk(KERN_DEBUG "init_card: entered\n");
1760 spin_lock_irqsave(&hc->lock, flags);
1762 spin_unlock_irqrestore(&hc->lock, flags);
1763 if (request_irq(hc->irq, hfcpci_int, IRQF_SHARED, "HFC PCI", hc)) {
1765 "mISDN: couldn't get interrupt %d\n", hc->irq);
1768 spin_lock_irqsave(&hc->lock, flags);
1773 * Finally enable IRQ output
1774 * this is only allowed, if an IRQ routine is already
1775 * established for this HFC, so don't do that earlier
1778 spin_unlock_irqrestore(&hc->lock, flags);
1780 current->state = TASK_UNINTERRUPTIBLE;
1781 schedule_timeout((80*HZ)/1000);
1782 printk(KERN_INFO "HFC PCI: IRQ %d count %d\n",
1783 hc->irq, hc->irqcnt);
1784 /* now switch timer interrupt off */
1785 spin_lock_irqsave(&hc->lock, flags);
1786 hc->hw.int_m1 &= ~HFCPCI_INTS_TIMER;
1787 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
1788 /* reinit mode reg */
1789 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
1792 "HFC PCI: IRQ(%d) getting no interrupts "
1793 "during init %d\n", hc->irq, 4 - cnt);
1801 spin_unlock_irqrestore(&hc->lock, flags);
1807 spin_unlock_irqrestore(&hc->lock, flags);
1808 free_irq(hc->irq, hc);
1813 channel_ctrl(struct hfc_pci *hc, struct mISDN_ctrl_req *cq)
1819 case MISDN_CTRL_GETOP:
1820 cq->op = MISDN_CTRL_LOOP | MISDN_CTRL_CONNECT |
1821 MISDN_CTRL_DISCONNECT;
1823 case MISDN_CTRL_LOOP:
1824 /* channel 0 disabled loop */
1825 if (cq->channel < 0 || cq->channel > 2) {
1829 if (cq->channel & 1) {
1830 if (test_bit(HFC_CFG_SW_DD_DU, &hc->cfg))
1834 printk(KERN_DEBUG "%s: Write_hfc: B1_SSL/RSL 0x%x\n",
1836 Write_hfc(hc, HFCPCI_B1_SSL, slot);
1837 Write_hfc(hc, HFCPCI_B1_RSL, slot);
1838 hc->hw.conn = (hc->hw.conn & ~7) | 6;
1839 Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
1841 if (cq->channel & 2) {
1842 if (test_bit(HFC_CFG_SW_DD_DU, &hc->cfg))
1846 printk(KERN_DEBUG "%s: Write_hfc: B2_SSL/RSL 0x%x\n",
1848 Write_hfc(hc, HFCPCI_B2_SSL, slot);
1849 Write_hfc(hc, HFCPCI_B2_RSL, slot);
1850 hc->hw.conn = (hc->hw.conn & ~0x38) | 0x30;
1851 Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
1853 if (cq->channel & 3)
1854 hc->hw.trm |= 0x80; /* enable IOM-loop */
1856 hc->hw.conn = (hc->hw.conn & ~0x3f) | 0x09;
1857 Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
1858 hc->hw.trm &= 0x7f; /* disable IOM-loop */
1860 Write_hfc(hc, HFCPCI_TRM, hc->hw.trm);
1862 case MISDN_CTRL_CONNECT:
1863 if (cq->channel == cq->p1) {
1867 if (cq->channel < 1 || cq->channel > 2 ||
1868 cq->p1 < 1 || cq->p1 > 2) {
1872 if (test_bit(HFC_CFG_SW_DD_DU, &hc->cfg))
1876 printk(KERN_DEBUG "%s: Write_hfc: B1_SSL/RSL 0x%x\n",
1878 Write_hfc(hc, HFCPCI_B1_SSL, slot);
1879 Write_hfc(hc, HFCPCI_B2_RSL, slot);
1880 if (test_bit(HFC_CFG_SW_DD_DU, &hc->cfg))
1884 printk(KERN_DEBUG "%s: Write_hfc: B2_SSL/RSL 0x%x\n",
1886 Write_hfc(hc, HFCPCI_B2_SSL, slot);
1887 Write_hfc(hc, HFCPCI_B1_RSL, slot);
1888 hc->hw.conn = (hc->hw.conn & ~0x3f) | 0x36;
1889 Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
1891 Write_hfc(hc, HFCPCI_TRM, hc->hw.trm);
1893 case MISDN_CTRL_DISCONNECT:
1894 hc->hw.conn = (hc->hw.conn & ~0x3f) | 0x09;
1895 Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
1896 hc->hw.trm &= 0x7f; /* disable IOM-loop */
1899 printk(KERN_WARNING "%s: unknown Op %x\n",
1908 open_dchannel(struct hfc_pci *hc, struct mISDNchannel *ch,
1909 struct channel_req *rq)
1913 if (debug & DEBUG_HW_OPEN)
1914 printk(KERN_DEBUG "%s: dev(%d) open from %p\n", __func__,
1915 hc->dch.dev.id, __builtin_return_address(0));
1916 if (rq->protocol == ISDN_P_NONE)
1918 if (rq->adr.channel == 1) {
1919 /* TODO: E-Channel */
1922 if (!hc->initdone) {
1923 if (rq->protocol == ISDN_P_TE_S0) {
1924 err = create_l1(&hc->dch, hfc_l1callback);
1928 hc->hw.protocol = rq->protocol;
1929 ch->protocol = rq->protocol;
1930 err = init_card(hc);
1934 if (rq->protocol != ch->protocol) {
1935 if (hc->hw.protocol == ISDN_P_TE_S0)
1936 l1_event(hc->dch.l1, CLOSE_CHANNEL);
1937 if (rq->protocol == ISDN_P_TE_S0) {
1938 err = create_l1(&hc->dch, hfc_l1callback);
1942 hc->hw.protocol = rq->protocol;
1943 ch->protocol = rq->protocol;
1948 if (((ch->protocol == ISDN_P_NT_S0) && (hc->dch.state == 3)) ||
1949 ((ch->protocol == ISDN_P_TE_S0) && (hc->dch.state == 7))) {
1950 _queue_data(ch, PH_ACTIVATE_IND, MISDN_ID_ANY,
1951 0, NULL, GFP_KERNEL);
1954 if (!try_module_get(THIS_MODULE))
1955 printk(KERN_WARNING "%s:cannot get module\n", __func__);
1960 open_bchannel(struct hfc_pci *hc, struct channel_req *rq)
1962 struct bchannel *bch;
1964 if (rq->adr.channel > 2)
1966 if (rq->protocol == ISDN_P_NONE)
1968 bch = &hc->bch[rq->adr.channel - 1];
1969 if (test_and_set_bit(FLG_OPEN, &bch->Flags))
1970 return -EBUSY; /* b-channel can be only open once */
1971 test_and_clear_bit(FLG_FILLEMPTY, &bch->Flags);
1972 bch->ch.protocol = rq->protocol;
1973 rq->ch = &bch->ch; /* TODO: E-channel */
1974 if (!try_module_get(THIS_MODULE))
1975 printk(KERN_WARNING "%s:cannot get module\n", __func__);
1980 * device control function
1983 hfc_dctrl(struct mISDNchannel *ch, u_int cmd, void *arg)
1985 struct mISDNdevice *dev = container_of(ch, struct mISDNdevice, D);
1986 struct dchannel *dch = container_of(dev, struct dchannel, dev);
1987 struct hfc_pci *hc = dch->hw;
1988 struct channel_req *rq;
1991 if (dch->debug & DEBUG_HW)
1992 printk(KERN_DEBUG "%s: cmd:%x %p\n",
1993 __func__, cmd, arg);
1997 if ((rq->protocol == ISDN_P_TE_S0) ||
1998 (rq->protocol == ISDN_P_NT_S0))
1999 err = open_dchannel(hc, ch, rq);
2001 err = open_bchannel(hc, rq);
2004 if (debug & DEBUG_HW_OPEN)
2005 printk(KERN_DEBUG "%s: dev(%d) close from %p\n",
2006 __func__, hc->dch.dev.id,
2007 __builtin_return_address(0));
2008 module_put(THIS_MODULE);
2010 case CONTROL_CHANNEL:
2011 err = channel_ctrl(hc, arg);
2014 if (dch->debug & DEBUG_HW)
2015 printk(KERN_DEBUG "%s: unknown command %x\n",
2023 setup_hw(struct hfc_pci *hc)
2027 printk(KERN_INFO "mISDN: HFC-PCI driver %s\n", hfcpci_revision);
2030 pci_set_master(hc->pdev);
2032 printk(KERN_WARNING "HFC-PCI: No IRQ for PCI card found\n");
2036 (char __iomem *)(unsigned long)hc->pdev->resource[1].start;
2038 if (!hc->hw.pci_io) {
2039 printk(KERN_WARNING "HFC-PCI: No IO-Mem for PCI card found\n");
2042 /* Allocate memory for FIFOS */
2043 /* the memory needs to be on a 32k boundary within the first 4G */
2044 pci_set_dma_mask(hc->pdev, 0xFFFF8000);
2045 buffer = pci_alloc_consistent(hc->pdev, 0x8000, &hc->hw.dmahandle);
2046 /* We silently assume the address is okay if nonzero */
2049 "HFC-PCI: Error allocating memory for FIFO!\n");
2052 hc->hw.fifos = buffer;
2053 pci_write_config_dword(hc->pdev, 0x80, hc->hw.dmahandle);
2054 hc->hw.pci_io = ioremap((ulong) hc->hw.pci_io, 256);
2056 "HFC-PCI: defined at mem %#lx fifo %#lx(%#lx) IRQ %d HZ %d\n",
2057 (u_long) hc->hw.pci_io, (u_long) hc->hw.fifos,
2058 (u_long) hc->hw.dmahandle, hc->irq, HZ);
2059 /* enable memory mapped ports, disable busmaster */
2060 pci_write_config_word(hc->pdev, PCI_COMMAND, PCI_ENA_MEMIO);
2064 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
2065 /* At this point the needed PCI config is done */
2066 /* fifos are still not enabled */
2067 hc->hw.timer.function = (void *) hfcpci_Timer;
2068 hc->hw.timer.data = (long) hc;
2069 init_timer(&hc->hw.timer);
2070 /* default PCM master */
2071 test_and_set_bit(HFC_CFG_MASTER, &hc->cfg);
2076 release_card(struct hfc_pci *hc) {
2079 spin_lock_irqsave(&hc->lock, flags);
2080 hc->hw.int_m2 = 0; /* interrupt output off ! */
2082 mode_hfcpci(&hc->bch[0], 1, ISDN_P_NONE);
2083 mode_hfcpci(&hc->bch[1], 2, ISDN_P_NONE);
2084 if (hc->dch.timer.function != NULL) {
2085 del_timer(&hc->dch.timer);
2086 hc->dch.timer.function = NULL;
2088 spin_unlock_irqrestore(&hc->lock, flags);
2089 if (hc->hw.protocol == ISDN_P_TE_S0)
2090 l1_event(hc->dch.l1, CLOSE_CHANNEL);
2092 free_irq(hc->irq, hc);
2093 release_io_hfcpci(hc); /* must release after free_irq! */
2094 mISDN_unregister_device(&hc->dch.dev);
2095 mISDN_freebchannel(&hc->bch[1]);
2096 mISDN_freebchannel(&hc->bch[0]);
2097 mISDN_freedchannel(&hc->dch);
2098 pci_set_drvdata(hc->pdev, NULL);
2103 setup_card(struct hfc_pci *card)
2107 char name[MISDN_MAX_IDLEN];
2109 card->dch.debug = debug;
2110 spin_lock_init(&card->lock);
2111 mISDN_initdchannel(&card->dch, MAX_DFRAME_LEN_L1, ph_state);
2112 card->dch.hw = card;
2113 card->dch.dev.Dprotocols = (1 << ISDN_P_TE_S0) | (1 << ISDN_P_NT_S0);
2114 card->dch.dev.Bprotocols = (1 << (ISDN_P_B_RAW & ISDN_P_B_MASK)) |
2115 (1 << (ISDN_P_B_HDLC & ISDN_P_B_MASK));
2116 card->dch.dev.D.send = hfcpci_l2l1D;
2117 card->dch.dev.D.ctrl = hfc_dctrl;
2118 card->dch.dev.nrbchan = 2;
2119 for (i = 0; i < 2; i++) {
2120 card->bch[i].nr = i + 1;
2121 set_channelmap(i + 1, card->dch.dev.channelmap);
2122 card->bch[i].debug = debug;
2123 mISDN_initbchannel(&card->bch[i], MAX_DATA_MEM);
2124 card->bch[i].hw = card;
2125 card->bch[i].ch.send = hfcpci_l2l1B;
2126 card->bch[i].ch.ctrl = hfc_bctrl;
2127 card->bch[i].ch.nr = i + 1;
2128 list_add(&card->bch[i].ch.list, &card->dch.dev.bchannels);
2130 err = setup_hw(card);
2133 snprintf(name, MISDN_MAX_IDLEN - 1, "hfc-pci.%d", HFC_cnt + 1);
2134 err = mISDN_register_device(&card->dch.dev, &card->pdev->dev, name);
2138 printk(KERN_INFO "HFC %d cards installed\n", HFC_cnt);
2141 mISDN_freebchannel(&card->bch[1]);
2142 mISDN_freebchannel(&card->bch[0]);
2143 mISDN_freedchannel(&card->dch);
2148 /* private data in the PCI devices list */
2155 static const struct _hfc_map hfc_map[] =
2157 {HFC_CCD_2BD0, 0, "CCD/Billion/Asuscom 2BD0"},
2158 {HFC_CCD_B000, 0, "Billion B000"},
2159 {HFC_CCD_B006, 0, "Billion B006"},
2160 {HFC_CCD_B007, 0, "Billion B007"},
2161 {HFC_CCD_B008, 0, "Billion B008"},
2162 {HFC_CCD_B009, 0, "Billion B009"},
2163 {HFC_CCD_B00A, 0, "Billion B00A"},
2164 {HFC_CCD_B00B, 0, "Billion B00B"},
2165 {HFC_CCD_B00C, 0, "Billion B00C"},
2166 {HFC_CCD_B100, 0, "Seyeon B100"},
2167 {HFC_CCD_B700, 0, "Primux II S0 B700"},
2168 {HFC_CCD_B701, 0, "Primux II S0 NT B701"},
2169 {HFC_ABOCOM_2BD1, 0, "Abocom/Magitek 2BD1"},
2170 {HFC_ASUS_0675, 0, "Asuscom/Askey 675"},
2171 {HFC_BERKOM_TCONCEPT, 0, "German telekom T-Concept"},
2172 {HFC_BERKOM_A1T, 0, "German telekom A1T"},
2173 {HFC_ANIGMA_MC145575, 0, "Motorola MC145575"},
2174 {HFC_ZOLTRIX_2BD0, 0, "Zoltrix 2BD0"},
2175 {HFC_DIGI_DF_M_IOM2_E, 0,
2176 "Digi International DataFire Micro V IOM2 (Europe)"},
2177 {HFC_DIGI_DF_M_E, 0,
2178 "Digi International DataFire Micro V (Europe)"},
2179 {HFC_DIGI_DF_M_IOM2_A, 0,
2180 "Digi International DataFire Micro V IOM2 (North America)"},
2181 {HFC_DIGI_DF_M_A, 0,
2182 "Digi International DataFire Micro V (North America)"},
2183 {HFC_SITECOM_DC105V2, 0, "Sitecom Connectivity DC-105 ISDN TA"},
2187 static struct pci_device_id hfc_ids[] =
2189 { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_2BD0),
2190 (unsigned long) &hfc_map[0] },
2191 { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_B000),
2192 (unsigned long) &hfc_map[1] },
2193 { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_B006),
2194 (unsigned long) &hfc_map[2] },
2195 { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_B007),
2196 (unsigned long) &hfc_map[3] },
2197 { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_B008),
2198 (unsigned long) &hfc_map[4] },
2199 { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_B009),
2200 (unsigned long) &hfc_map[5] },
2201 { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_B00A),
2202 (unsigned long) &hfc_map[6] },
2203 { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_B00B),
2204 (unsigned long) &hfc_map[7] },
2205 { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_B00C),
2206 (unsigned long) &hfc_map[8] },
2207 { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_B100),
2208 (unsigned long) &hfc_map[9] },
2209 { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_B700),
2210 (unsigned long) &hfc_map[10] },
2211 { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_B701),
2212 (unsigned long) &hfc_map[11] },
2213 { PCI_VDEVICE(ABOCOM, PCI_DEVICE_ID_ABOCOM_2BD1),
2214 (unsigned long) &hfc_map[12] },
2215 { PCI_VDEVICE(ASUSTEK, PCI_DEVICE_ID_ASUSTEK_0675),
2216 (unsigned long) &hfc_map[13] },
2217 { PCI_VDEVICE(BERKOM, PCI_DEVICE_ID_BERKOM_T_CONCEPT),
2218 (unsigned long) &hfc_map[14] },
2219 { PCI_VDEVICE(BERKOM, PCI_DEVICE_ID_BERKOM_A1T),
2220 (unsigned long) &hfc_map[15] },
2221 { PCI_VDEVICE(ANIGMA, PCI_DEVICE_ID_ANIGMA_MC145575),
2222 (unsigned long) &hfc_map[16] },
2223 { PCI_VDEVICE(ZOLTRIX, PCI_DEVICE_ID_ZOLTRIX_2BD0),
2224 (unsigned long) &hfc_map[17] },
2225 { PCI_VDEVICE(DIGI, PCI_DEVICE_ID_DIGI_DF_M_IOM2_E),
2226 (unsigned long) &hfc_map[18] },
2227 { PCI_VDEVICE(DIGI, PCI_DEVICE_ID_DIGI_DF_M_E),
2228 (unsigned long) &hfc_map[19] },
2229 { PCI_VDEVICE(DIGI, PCI_DEVICE_ID_DIGI_DF_M_IOM2_A),
2230 (unsigned long) &hfc_map[20] },
2231 { PCI_VDEVICE(DIGI, PCI_DEVICE_ID_DIGI_DF_M_A),
2232 (unsigned long) &hfc_map[21] },
2233 { PCI_VDEVICE(SITECOM, PCI_DEVICE_ID_SITECOM_DC105V2),
2234 (unsigned long) &hfc_map[22] },
2238 static int __devinit
2239 hfc_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
2242 struct hfc_pci *card;
2243 struct _hfc_map *m = (struct _hfc_map *)ent->driver_data;
2245 card = kzalloc(sizeof(struct hfc_pci), GFP_ATOMIC);
2247 printk(KERN_ERR "No kmem for HFC card\n");
2251 card->subtype = m->subtype;
2252 err = pci_enable_device(pdev);
2258 printk(KERN_INFO "mISDN_hfcpci: found adapter %s at %s\n",
2259 m->name, pci_name(pdev));
2261 card->irq = pdev->irq;
2262 pci_set_drvdata(pdev, card);
2263 err = setup_card(card);
2265 pci_set_drvdata(pdev, NULL);
2269 static void __devexit
2270 hfc_remove_pci(struct pci_dev *pdev)
2272 struct hfc_pci *card = pci_get_drvdata(pdev);
2278 printk(KERN_DEBUG "%s: drvdata already removed\n",
2283 static struct pci_driver hfc_driver = {
2286 .remove = __devexit_p(hfc_remove_pci),
2287 .id_table = hfc_ids,
2291 _hfcpci_softirq(struct device *dev, void *arg)
2293 struct hfc_pci *hc = dev_get_drvdata(dev);
2294 struct bchannel *bch;
2298 if (hc->hw.int_m2 & HFCPCI_IRQ_ENABLE) {
2299 spin_lock(&hc->lock);
2300 bch = Sel_BCS(hc, hc->hw.bswapped ? 2 : 1);
2301 if (bch && bch->state == ISDN_P_B_RAW) { /* B1 rx&tx */
2302 main_rec_hfcpci(bch);
2305 bch = Sel_BCS(hc, hc->hw.bswapped ? 1 : 2);
2306 if (bch && bch->state == ISDN_P_B_RAW) { /* B2 rx&tx */
2307 main_rec_hfcpci(bch);
2310 spin_unlock(&hc->lock);
2316 hfcpci_softirq(void *arg)
2318 (void) driver_for_each_device(&hfc_driver.driver, NULL, arg,
2321 /* if next event would be in the past ... */
2322 if ((s32)(hfc_jiffies + tics - jiffies) <= 0)
2323 hfc_jiffies = jiffies + 1;
2325 hfc_jiffies += tics;
2326 hfc_tl.expires = hfc_jiffies;
2336 poll = HFCPCI_BTRANS_THRESHOLD;
2338 if (poll != HFCPCI_BTRANS_THRESHOLD) {
2339 tics = (poll * HZ) / 8000;
2342 poll = (tics * 8000) / HZ;
2343 if (poll > 256 || poll < 8) {
2344 printk(KERN_ERR "%s: Wrong poll value %d not in range "
2345 "of 8..256.\n", __func__, poll);
2350 if (poll != HFCPCI_BTRANS_THRESHOLD) {
2351 printk(KERN_INFO "%s: Using alternative poll value of %d\n",
2353 hfc_tl.function = (void *)hfcpci_softirq;
2355 init_timer(&hfc_tl);
2356 hfc_tl.expires = jiffies + tics;
2357 hfc_jiffies = hfc_tl.expires;
2360 tics = 0; /* indicate the use of controller's timer */
2362 err = pci_register_driver(&hfc_driver);
2364 if (timer_pending(&hfc_tl))
2374 if (timer_pending(&hfc_tl))
2377 pci_unregister_driver(&hfc_driver);
2380 module_init(HFC_init);
2381 module_exit(HFC_cleanup);
2383 MODULE_DEVICE_TABLE(pci, hfc_ids);