4 * Author Karsten Keil <keil@isdn4linux.de>
6 * Copyright 2009 by Karsten Keil <keil@isdn4linux.de>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 #include <linux/interrupt.h>
24 #include <linux/module.h>
25 #include <linux/pci.h>
26 #include <linux/delay.h>
27 #include <linux/mISDNhw.h>
28 #include <linux/slab.h>
32 #include <linux/isdn/hdlc.h>
34 #define NETJET_REV "2.0"
62 struct isdnhdlc_vars hsend;
63 struct isdnhdlc_vars hrecv;
68 #define TX_INIT 0x0001
69 #define TX_IDLE 0x0002
71 #define TX_UNDERRUN 0x0100
72 #define RX_OVERRUN 0x0100
77 struct list_head list;
79 char name[MISDN_MAX_IDLEN];
87 spinlock_t lock; /* lock HW */
89 struct tiger_dma send;
90 struct tiger_dma recv;
91 struct tiger_ch bc[2];
100 static LIST_HEAD(Cards);
101 static DEFINE_RWLOCK(card_lock); /* protect Cards */
106 _set_debug(struct tiger_hw *card)
108 card->isac.dch.debug = debug;
109 card->bc[0].bch.debug = debug;
110 card->bc[1].bch.debug = debug;
114 set_debug(const char *val, struct kernel_param *kp)
117 struct tiger_hw *card;
119 ret = param_set_uint(val, kp);
121 read_lock(&card_lock);
122 list_for_each_entry(card, &Cards, list)
124 read_unlock(&card_lock);
129 MODULE_AUTHOR("Karsten Keil");
130 MODULE_LICENSE("GPL v2");
131 MODULE_VERSION(NETJET_REV);
132 module_param_call(debug, set_debug, param_get_uint, &debug, S_IRUGO | S_IWUSR);
133 MODULE_PARM_DESC(debug, "Netjet debug mask");
136 nj_disable_hwirq(struct tiger_hw *card)
138 outb(0, card->base + NJ_IRQMASK0);
139 outb(0, card->base + NJ_IRQMASK1);
144 ReadISAC_nj(void *p, u8 offset)
146 struct tiger_hw *card = p;
150 card->auxd |= (offset >> 4) & 3;
151 outb(card->auxd, card->base + NJ_AUXDATA);
152 ret = inb(card->base + NJ_ISAC_OFF + ((offset & 0x0f) << 2));
157 WriteISAC_nj(void *p, u8 offset, u8 value)
159 struct tiger_hw *card = p;
162 card->auxd |= (offset >> 4) & 3;
163 outb(card->auxd, card->base + NJ_AUXDATA);
164 outb(value, card->base + NJ_ISAC_OFF + ((offset & 0x0f) << 2));
168 ReadFiFoISAC_nj(void *p, u8 offset, u8 *data, int size)
170 struct tiger_hw *card = p;
173 outb(card->auxd, card->base + NJ_AUXDATA);
174 insb(card->base + NJ_ISAC_OFF, data, size);
178 WriteFiFoISAC_nj(void *p, u8 offset, u8 *data, int size)
180 struct tiger_hw *card = p;
183 outb(card->auxd, card->base + NJ_AUXDATA);
184 outsb(card->base + NJ_ISAC_OFF, data, size);
188 fill_mem(struct tiger_ch *bc, u32 idx, u32 cnt, u32 fill)
190 struct tiger_hw *card = bc->bch.hw;
191 u32 mask = 0xff, val;
193 pr_debug("%s: B%1d fill %02x len %d idx %d/%d\n", card->name,
194 bc->bch.nr, fill, cnt, idx, card->send.idx);
195 if (bc->bch.nr & 2) {
201 val = card->send.start[idx];
204 card->send.start[idx++] = val;
205 if (idx >= card->send.size)
211 mode_tiger(struct tiger_ch *bc, u32 protocol)
213 struct tiger_hw *card = bc->bch.hw;
215 pr_debug("%s: B%1d protocol %x-->%x\n", card->name,
216 bc->bch.nr, bc->bch.state, protocol);
219 if (bc->bch.state == ISDN_P_NONE)
221 fill_mem(bc, 0, card->send.size, 0xff);
222 bc->bch.state = protocol;
223 /* only stop dma and interrupts if both channels NULL */
224 if ((card->bc[0].bch.state == ISDN_P_NONE) &&
225 (card->bc[1].bch.state == ISDN_P_NONE)) {
227 outb(card->dmactrl, card->base + NJ_DMACTRL);
228 outb(0, card->base + NJ_IRQMASK0);
230 test_and_clear_bit(FLG_HDLC, &bc->bch.Flags);
231 test_and_clear_bit(FLG_TRANSPARENT, &bc->bch.Flags);
237 test_and_set_bit(FLG_TRANSPARENT, &bc->bch.Flags);
238 bc->bch.state = protocol;
240 bc->free = card->send.size / 2;
242 bc->txstate = TX_INIT | TX_IDLE;
244 if (!card->dmactrl) {
246 outb(card->dmactrl, card->base + NJ_DMACTRL);
247 outb(0x0f, card->base + NJ_IRQMASK0);
251 test_and_set_bit(FLG_HDLC, &bc->bch.Flags);
252 bc->bch.state = protocol;
254 bc->free = card->send.size / 2;
256 bc->txstate = TX_INIT | TX_IDLE;
257 isdnhdlc_rcv_init(&bc->hrecv, 0);
258 isdnhdlc_out_init(&bc->hsend, 0);
260 if (!card->dmactrl) {
262 outb(card->dmactrl, card->base + NJ_DMACTRL);
263 outb(0x0f, card->base + NJ_IRQMASK0);
267 pr_info("%s: %s protocol %x not handled\n", card->name,
271 card->send.dmacur = inl(card->base + NJ_DMA_READ_ADR);
272 card->recv.dmacur = inl(card->base + NJ_DMA_WRITE_ADR);
273 card->send.idx = (card->send.dmacur - card->send.dmastart) >> 2;
274 card->recv.idx = (card->recv.dmacur - card->recv.dmastart) >> 2;
275 pr_debug("%s: %s ctrl %x irq %02x/%02x idx %d/%d\n",
276 card->name, __func__,
277 inb(card->base + NJ_DMACTRL),
278 inb(card->base + NJ_IRQMASK0),
279 inb(card->base + NJ_IRQSTAT0),
286 nj_reset(struct tiger_hw *card)
288 outb(0xff, card->base + NJ_CTRL); /* Reset On */
291 /* now edge triggered for TJ320 GE 13/07/00 */
292 /* see comment in IRQ function */
293 if (card->typ == NETJET_S_TJ320) /* TJ320 */
294 card->ctrlreg = 0x40; /* Reset Off and status read clear */
296 card->ctrlreg = 0x00; /* Reset Off and status read clear */
297 outb(card->ctrlreg, card->base + NJ_CTRL);
300 /* configure AUX pins (all output except ISAC IRQ pin) */
303 outb(~NJ_ISACIRQ, card->base + NJ_AUXCTRL);
304 outb(NJ_ISACIRQ, card->base + NJ_IRQMASK1);
305 outb(card->auxd, card->base + NJ_AUXDATA);
309 inittiger(struct tiger_hw *card)
313 card->dma_p = pci_alloc_consistent(card->pdev, NJ_DMA_SIZE,
316 pr_info("%s: No DMA memory\n", card->name);
319 if ((u64)card->dma > 0xffffffff) {
320 pr_info("%s: DMA outside 32 bit\n", card->name);
323 for (i = 0; i < 2; i++) {
324 card->bc[i].hsbuf = kmalloc(NJ_DMA_TXSIZE, GFP_ATOMIC);
325 if (!card->bc[i].hsbuf) {
326 pr_info("%s: no B%d send buffer\n", card->name, i + 1);
329 card->bc[i].hrbuf = kmalloc(NJ_DMA_RXSIZE, GFP_ATOMIC);
330 if (!card->bc[i].hrbuf) {
331 pr_info("%s: no B%d recv buffer\n", card->name, i + 1);
335 memset(card->dma_p, 0xff, NJ_DMA_SIZE);
337 card->send.start = card->dma_p;
338 card->send.dmastart = (u32)card->dma;
339 card->send.dmaend = card->send.dmastart +
340 (4 * (NJ_DMA_TXSIZE - 1));
341 card->send.dmairq = card->send.dmastart +
342 (4 * ((NJ_DMA_TXSIZE / 2) - 1));
343 card->send.size = NJ_DMA_TXSIZE;
345 if (debug & DEBUG_HW)
346 pr_notice("%s: send buffer phy %#x - %#x - %#x virt %p"
347 " size %zu u32\n", card->name,
348 card->send.dmastart, card->send.dmairq,
349 card->send.dmaend, card->send.start, card->send.size);
351 outl(card->send.dmastart, card->base + NJ_DMA_READ_START);
352 outl(card->send.dmairq, card->base + NJ_DMA_READ_IRQ);
353 outl(card->send.dmaend, card->base + NJ_DMA_READ_END);
355 card->recv.start = card->dma_p + (NJ_DMA_SIZE / 2);
356 card->recv.dmastart = (u32)card->dma + (NJ_DMA_SIZE / 2);
357 card->recv.dmaend = card->recv.dmastart +
358 (4 * (NJ_DMA_RXSIZE - 1));
359 card->recv.dmairq = card->recv.dmastart +
360 (4 * ((NJ_DMA_RXSIZE / 2) - 1));
361 card->recv.size = NJ_DMA_RXSIZE;
363 if (debug & DEBUG_HW)
364 pr_notice("%s: recv buffer phy %#x - %#x - %#x virt %p"
365 " size %zu u32\n", card->name,
366 card->recv.dmastart, card->recv.dmairq,
367 card->recv.dmaend, card->recv.start, card->recv.size);
369 outl(card->recv.dmastart, card->base + NJ_DMA_WRITE_START);
370 outl(card->recv.dmairq, card->base + NJ_DMA_WRITE_IRQ);
371 outl(card->recv.dmaend, card->base + NJ_DMA_WRITE_END);
376 read_dma(struct tiger_ch *bc, u32 idx, int cnt)
378 struct tiger_hw *card = bc->bch.hw;
383 if (bc->lastrx == idx) {
384 bc->rxstate |= RX_OVERRUN;
385 pr_info("%s: B%1d overrun at idx %d\n", card->name,
389 if (test_bit(FLG_RX_OFF, &bc->bch.Flags)) {
390 bc->bch.dropcnt += cnt;
393 stat = bchannel_get_rxbuf(&bc->bch, cnt);
394 /* only transparent use the count here, HDLC overun is detected later */
395 if (stat == ENOMEM) {
396 pr_warning("%s.B%d: No memory for %d bytes\n",
397 card->name, bc->bch.nr, cnt);
400 if (test_bit(FLG_TRANSPARENT, &bc->bch.Flags))
401 p = skb_put(bc->bch.rx_skb, cnt);
405 for (i = 0; i < cnt; i++) {
406 val = card->recv.start[idx++];
409 if (idx >= card->recv.size)
414 if (test_bit(FLG_TRANSPARENT, &bc->bch.Flags)) {
415 recv_Bchannel(&bc->bch, 0, false);
421 stat = isdnhdlc_decode(&bc->hrecv, pn, cnt, &i,
422 bc->bch.rx_skb->data, bc->bch.maxlen);
423 if (stat > 0) { /* valid frame received */
424 p = skb_put(bc->bch.rx_skb, stat);
425 if (debug & DEBUG_HW_BFIFO) {
426 snprintf(card->log, LOG_SIZE,
427 "B%1d-recv %s %d ", bc->bch.nr,
429 print_hex_dump_bytes(card->log,
430 DUMP_PREFIX_OFFSET, p,
433 recv_Bchannel(&bc->bch, 0, false);
434 stat = bchannel_get_rxbuf(&bc->bch, bc->bch.maxlen);
436 pr_warning("%s.B%d: No memory for %d bytes\n",
437 card->name, bc->bch.nr, cnt);
440 } else if (stat == -HDLC_CRC_ERROR) {
441 pr_info("%s: B%1d receive frame CRC error\n",
442 card->name, bc->bch.nr);
443 } else if (stat == -HDLC_FRAMING_ERROR) {
444 pr_info("%s: B%1d receive framing error\n",
445 card->name, bc->bch.nr);
446 } else if (stat == -HDLC_LENGTH_ERROR) {
447 pr_info("%s: B%1d receive frame too long (> %d)\n",
448 card->name, bc->bch.nr, bc->bch.maxlen);
456 recv_tiger(struct tiger_hw *card, u8 irq_stat)
459 int cnt = card->recv.size / 2;
461 /* Note receive is via the WRITE DMA channel */
462 card->last_is0 &= ~NJ_IRQM0_WR_MASK;
463 card->last_is0 |= (irq_stat & NJ_IRQM0_WR_MASK);
465 if (irq_stat & NJ_IRQM0_WR_END)
468 idx = card->recv.size - 1;
470 if (test_bit(FLG_ACTIVE, &card->bc[0].bch.Flags))
471 read_dma(&card->bc[0], idx, cnt);
472 if (test_bit(FLG_ACTIVE, &card->bc[1].bch.Flags))
473 read_dma(&card->bc[1], idx, cnt);
476 /* sync with current DMA address at start or after exception */
478 resync(struct tiger_ch *bc, struct tiger_hw *card)
480 card->send.dmacur = inl(card->base | NJ_DMA_READ_ADR);
481 card->send.idx = (card->send.dmacur - card->send.dmastart) >> 2;
482 if (bc->free > card->send.size / 2)
483 bc->free = card->send.size / 2;
484 /* currently we simple sync to the next complete free area
485 * this hast the advantage that we have always maximum time to
488 if (card->send.idx < ((card->send.size / 2) - 1))
489 bc->idx = (card->recv.size / 2) - 1;
491 bc->idx = card->recv.size - 1;
492 bc->txstate = TX_RUN;
493 pr_debug("%s: %s B%1d free %d idx %d/%d\n", card->name,
494 __func__, bc->bch.nr, bc->free, bc->idx, card->send.idx);
497 static int bc_next_frame(struct tiger_ch *);
500 fill_hdlc_flag(struct tiger_ch *bc)
502 struct tiger_hw *card = bc->bch.hw;
509 pr_debug("%s: %s B%1d %d state %x idx %d/%d\n", card->name,
510 __func__, bc->bch.nr, bc->free, bc->txstate,
511 bc->idx, card->send.idx);
512 if (bc->txstate & (TX_IDLE | TX_INIT | TX_UNDERRUN))
514 count = isdnhdlc_encode(&bc->hsend, NULL, 0, &i,
515 bc->hsbuf, bc->free);
516 pr_debug("%s: B%1d hdlc encoded %d flags\n", card->name,
520 m = (bc->bch.nr & 1) ? 0xffffff00 : 0xffff00ff;
521 for (i = 0; i < count; i++) {
522 if (bc->idx >= card->send.size)
524 v = card->send.start[bc->idx];
526 v |= (bc->bch.nr & 1) ? (u32)(p[i]) : ((u32)(p[i])) << 8;
527 card->send.start[bc->idx++] = v;
529 if (debug & DEBUG_HW_BFIFO) {
530 snprintf(card->log, LOG_SIZE, "B%1d-send %s %d ",
531 bc->bch.nr, card->name, count);
532 print_hex_dump_bytes(card->log, DUMP_PREFIX_OFFSET, p, count);
537 fill_dma(struct tiger_ch *bc)
539 struct tiger_hw *card = bc->bch.hw;
540 int count, i, fillempty = 0;
546 if (!bc->bch.tx_skb) {
547 if (!test_bit(FLG_TX_EMPTY, &bc->bch.Flags))
550 count = card->send.size >> 1;
553 count = bc->bch.tx_skb->len - bc->bch.tx_idx;
556 pr_debug("%s: %s B%1d %d/%d/%d/%d state %x idx %d/%d\n",
557 card->name, __func__, bc->bch.nr, count, bc->free,
558 bc->bch.tx_idx, bc->bch.tx_skb->len, bc->txstate,
559 bc->idx, card->send.idx);
560 p = bc->bch.tx_skb->data + bc->bch.tx_idx;
562 if (bc->txstate & (TX_IDLE | TX_INIT | TX_UNDERRUN))
564 if (test_bit(FLG_HDLC, &bc->bch.Flags) && !fillempty) {
565 count = isdnhdlc_encode(&bc->hsend, p, count, &i,
566 bc->hsbuf, bc->free);
567 pr_debug("%s: B%1d hdlc encoded %d in %d\n", card->name,
568 bc->bch.nr, i, count);
573 if (count > bc->free)
576 bc->bch.tx_idx += count;
579 m = (bc->bch.nr & 1) ? 0xffffff00 : 0xffff00ff;
582 if (!(bc->bch.nr & 1))
584 for (i = 0; i < count; i++) {
585 if (bc->idx >= card->send.size)
587 v = card->send.start[bc->idx];
590 card->send.start[bc->idx++] = v;
593 for (i = 0; i < count; i++) {
594 if (bc->idx >= card->send.size)
596 v = card->send.start[bc->idx];
599 v |= (bc->bch.nr & 1) ? n : n << 8;
600 card->send.start[bc->idx++] = v;
603 if (debug & DEBUG_HW_BFIFO) {
604 snprintf(card->log, LOG_SIZE, "B%1d-send %s %d ",
605 bc->bch.nr, card->name, count);
606 print_hex_dump_bytes(card->log, DUMP_PREFIX_OFFSET, p, count);
614 bc_next_frame(struct tiger_ch *bc)
618 if (bc->bch.tx_skb && bc->bch.tx_idx < bc->bch.tx_skb->len) {
622 dev_kfree_skb(bc->bch.tx_skb);
623 if (get_next_bframe(&bc->bch)) {
625 test_and_clear_bit(FLG_TX_EMPTY, &bc->bch.Flags);
626 } else if (test_bit(FLG_TX_EMPTY, &bc->bch.Flags)) {
628 } else if (test_bit(FLG_FILLEMPTY, &bc->bch.Flags)) {
629 test_and_set_bit(FLG_TX_EMPTY, &bc->bch.Flags);
639 send_tiger_bc(struct tiger_hw *card, struct tiger_ch *bc)
643 bc->free += card->send.size / 2;
644 if (bc->free >= card->send.size) {
645 if (!(bc->txstate & (TX_UNDERRUN | TX_INIT))) {
646 pr_info("%s: B%1d TX underrun state %x\n", card->name,
647 bc->bch.nr, bc->txstate);
648 bc->txstate |= TX_UNDERRUN;
650 bc->free = card->send.size;
652 ret = bc_next_frame(bc);
654 if (test_bit(FLG_HDLC, &bc->bch.Flags)) {
658 pr_debug("%s: B%1d TX no data free %d idx %d/%d\n", card->name,
659 bc->bch.nr, bc->free, bc->idx, card->send.idx);
660 if (!(bc->txstate & (TX_IDLE | TX_INIT))) {
661 fill_mem(bc, bc->idx, bc->free, 0xff);
662 if (bc->free == card->send.size)
663 bc->txstate |= TX_IDLE;
669 send_tiger(struct tiger_hw *card, u8 irq_stat)
673 /* Note send is via the READ DMA channel */
674 if ((irq_stat & card->last_is0) & NJ_IRQM0_RD_MASK) {
675 pr_info("%s: tiger warn write double dma %x/%x\n",
676 card->name, irq_stat, card->last_is0);
679 card->last_is0 &= ~NJ_IRQM0_RD_MASK;
680 card->last_is0 |= (irq_stat & NJ_IRQM0_RD_MASK);
682 for (i = 0; i < 2; i++) {
683 if (test_bit(FLG_ACTIVE, &card->bc[i].bch.Flags))
684 send_tiger_bc(card, &card->bc[i]);
689 nj_irq(int intno, void *dev_id)
691 struct tiger_hw *card = dev_id;
692 u8 val, s1val, s0val;
694 spin_lock(&card->lock);
695 s0val = inb(card->base | NJ_IRQSTAT0);
696 s1val = inb(card->base | NJ_IRQSTAT1);
697 if ((s1val & NJ_ISACIRQ) && (s0val == 0)) {
699 spin_unlock(&card->lock);
702 pr_debug("%s: IRQSTAT0 %02x IRQSTAT1 %02x\n", card->name, s0val, s1val);
704 if (!(s1val & NJ_ISACIRQ)) {
705 val = ReadISAC_nj(card, ISAC_ISTA);
707 mISDNisac_irq(&card->isac, val);
712 outb(s0val, card->base | NJ_IRQSTAT0);
716 /* set bits in sval to indicate which page is free */
717 card->recv.dmacur = inl(card->base | NJ_DMA_WRITE_ADR);
718 card->recv.idx = (card->recv.dmacur - card->recv.dmastart) >> 2;
719 if (card->recv.dmacur < card->recv.dmairq)
720 s0val = 0x08; /* the 2nd write area is free */
722 s0val = 0x04; /* the 1st write area is free */
724 card->send.dmacur = inl(card->base | NJ_DMA_READ_ADR);
725 card->send.idx = (card->send.dmacur - card->send.dmastart) >> 2;
726 if (card->send.dmacur < card->send.dmairq)
727 s0val |= 0x02; /* the 2nd read area is free */
729 s0val |= 0x01; /* the 1st read area is free */
731 pr_debug("%s: DMA Status %02x/%02x/%02x %d/%d\n", card->name,
732 s1val, s0val, card->last_is0,
733 card->recv.idx, card->send.idx);
734 /* test if we have a DMA interrupt */
735 if (s0val != card->last_is0) {
736 if ((s0val & NJ_IRQM0_RD_MASK) !=
737 (card->last_is0 & NJ_IRQM0_RD_MASK))
738 /* got a write dma int */
739 send_tiger(card, s0val);
740 if ((s0val & NJ_IRQM0_WR_MASK) !=
741 (card->last_is0 & NJ_IRQM0_WR_MASK))
742 /* got a read dma int */
743 recv_tiger(card, s0val);
746 spin_unlock(&card->lock);
751 nj_l2l1B(struct mISDNchannel *ch, struct sk_buff *skb)
754 struct bchannel *bch = container_of(ch, struct bchannel, ch);
755 struct tiger_ch *bc = container_of(bch, struct tiger_ch, bch);
756 struct tiger_hw *card = bch->hw;
757 struct mISDNhead *hh = mISDN_HEAD_P(skb);
762 spin_lock_irqsave(&card->lock, flags);
763 ret = bchannel_senddata(bch, skb);
764 if (ret > 0) { /* direct TX */
768 spin_unlock_irqrestore(&card->lock, flags);
770 case PH_ACTIVATE_REQ:
771 spin_lock_irqsave(&card->lock, flags);
772 if (!test_and_set_bit(FLG_ACTIVE, &bch->Flags))
773 ret = mode_tiger(bc, ch->protocol);
776 spin_unlock_irqrestore(&card->lock, flags);
778 _queue_data(ch, PH_ACTIVATE_IND, MISDN_ID_ANY, 0,
781 case PH_DEACTIVATE_REQ:
782 spin_lock_irqsave(&card->lock, flags);
783 mISDN_clear_bchannel(bch);
784 mode_tiger(bc, ISDN_P_NONE);
785 spin_unlock_irqrestore(&card->lock, flags);
786 _queue_data(ch, PH_DEACTIVATE_IND, MISDN_ID_ANY, 0,
797 channel_bctrl(struct tiger_ch *bc, struct mISDN_ctrl_req *cq)
799 return mISDN_ctrl_bchannel(&bc->bch, cq);
803 nj_bctrl(struct mISDNchannel *ch, u32 cmd, void *arg)
805 struct bchannel *bch = container_of(ch, struct bchannel, ch);
806 struct tiger_ch *bc = container_of(bch, struct tiger_ch, bch);
807 struct tiger_hw *card = bch->hw;
811 pr_debug("%s: %s cmd:%x %p\n", card->name, __func__, cmd, arg);
814 test_and_clear_bit(FLG_OPEN, &bch->Flags);
815 cancel_work_sync(&bch->workq);
816 spin_lock_irqsave(&card->lock, flags);
817 mISDN_clear_bchannel(bch);
818 mode_tiger(bc, ISDN_P_NONE);
819 spin_unlock_irqrestore(&card->lock, flags);
820 ch->protocol = ISDN_P_NONE;
822 module_put(THIS_MODULE);
825 case CONTROL_CHANNEL:
826 ret = channel_bctrl(bc, arg);
829 pr_info("%s: %s unknown prim(%x)\n", card->name, __func__, cmd);
835 channel_ctrl(struct tiger_hw *card, struct mISDN_ctrl_req *cq)
840 case MISDN_CTRL_GETOP:
841 cq->op = MISDN_CTRL_LOOP | MISDN_CTRL_L1_TIMER3;
843 case MISDN_CTRL_LOOP:
844 /* cq->channel: 0 disable, 1 B1 loop 2 B2 loop, 3 both */
845 if (cq->channel < 0 || cq->channel > 3) {
849 ret = card->isac.ctrl(&card->isac, HW_TESTLOOP, cq->channel);
851 case MISDN_CTRL_L1_TIMER3:
852 ret = card->isac.ctrl(&card->isac, HW_TIMER3_VALUE, cq->p1);
855 pr_info("%s: %s unknown Op %x\n", card->name, __func__, cq->op);
863 open_bchannel(struct tiger_hw *card, struct channel_req *rq)
865 struct bchannel *bch;
867 if (rq->adr.channel == 0 || rq->adr.channel > 2)
869 if (rq->protocol == ISDN_P_NONE)
871 bch = &card->bc[rq->adr.channel - 1].bch;
872 if (test_and_set_bit(FLG_OPEN, &bch->Flags))
873 return -EBUSY; /* b-channel can be only open once */
874 test_and_clear_bit(FLG_FILLEMPTY, &bch->Flags);
875 bch->ch.protocol = rq->protocol;
881 * device control function
884 nj_dctrl(struct mISDNchannel *ch, u32 cmd, void *arg)
886 struct mISDNdevice *dev = container_of(ch, struct mISDNdevice, D);
887 struct dchannel *dch = container_of(dev, struct dchannel, dev);
888 struct tiger_hw *card = dch->hw;
889 struct channel_req *rq;
892 pr_debug("%s: %s cmd:%x %p\n", card->name, __func__, cmd, arg);
896 if (rq->protocol == ISDN_P_TE_S0)
897 err = card->isac.open(&card->isac, rq);
899 err = open_bchannel(card, rq);
902 if (!try_module_get(THIS_MODULE))
903 pr_info("%s: cannot get module\n", card->name);
906 pr_debug("%s: dev(%d) close from %p\n", card->name, dch->dev.id,
907 __builtin_return_address(0));
908 module_put(THIS_MODULE);
910 case CONTROL_CHANNEL:
911 err = channel_ctrl(card, arg);
914 pr_debug("%s: %s unknown command %x\n",
915 card->name, __func__, cmd);
922 nj_init_card(struct tiger_hw *card)
927 spin_lock_irqsave(&card->lock, flags);
928 nj_disable_hwirq(card);
929 spin_unlock_irqrestore(&card->lock, flags);
931 card->irq = card->pdev->irq;
932 if (request_irq(card->irq, nj_irq, IRQF_SHARED, card->name, card)) {
933 pr_info("%s: couldn't get interrupt %d\n",
934 card->name, card->irq);
939 spin_lock_irqsave(&card->lock, flags);
941 ret = card->isac.init(&card->isac);
944 ret = inittiger(card);
947 mode_tiger(&card->bc[0], ISDN_P_NONE);
948 mode_tiger(&card->bc[1], ISDN_P_NONE);
950 spin_unlock_irqrestore(&card->lock, flags);
956 nj_release(struct tiger_hw *card)
962 spin_lock_irqsave(&card->lock, flags);
963 nj_disable_hwirq(card);
964 mode_tiger(&card->bc[0], ISDN_P_NONE);
965 mode_tiger(&card->bc[1], ISDN_P_NONE);
966 card->isac.release(&card->isac);
967 spin_unlock_irqrestore(&card->lock, flags);
968 release_region(card->base, card->base_s);
972 free_irq(card->irq, card);
973 if (card->isac.dch.dev.dev.class)
974 mISDN_unregister_device(&card->isac.dch.dev);
976 for (i = 0; i < 2; i++) {
977 mISDN_freebchannel(&card->bc[i].bch);
978 kfree(card->bc[i].hsbuf);
979 kfree(card->bc[i].hrbuf);
982 pci_free_consistent(card->pdev, NJ_DMA_SIZE,
983 card->dma_p, card->dma);
984 write_lock_irqsave(&card_lock, flags);
985 list_del(&card->list);
986 write_unlock_irqrestore(&card_lock, flags);
987 pci_clear_master(card->pdev);
988 pci_disable_device(card->pdev);
989 pci_set_drvdata(card->pdev, NULL);
995 nj_setup(struct tiger_hw *card)
997 card->base = pci_resource_start(card->pdev, 0);
998 card->base_s = pci_resource_len(card->pdev, 0);
999 if (!request_region(card->base, card->base_s, card->name)) {
1000 pr_info("%s: NETjet config port %#x-%#x already in use\n",
1001 card->name, card->base,
1002 (u32)(card->base + card->base_s - 1));
1006 ASSIGN_FUNC(nj, ISAC, card->isac);
1011 static int __devinit
1012 setup_instance(struct tiger_hw *card)
1017 snprintf(card->name, MISDN_MAX_IDLEN - 1, "netjet.%d", nj_cnt + 1);
1018 write_lock_irqsave(&card_lock, flags);
1019 list_add_tail(&card->list, &Cards);
1020 write_unlock_irqrestore(&card_lock, flags);
1023 card->isac.name = card->name;
1024 spin_lock_init(&card->lock);
1025 card->isac.hwlock = &card->lock;
1026 mISDNisac_init(&card->isac, card);
1028 card->isac.dch.dev.Bprotocols = (1 << (ISDN_P_B_RAW & ISDN_P_B_MASK)) |
1029 (1 << (ISDN_P_B_HDLC & ISDN_P_B_MASK));
1030 card->isac.dch.dev.D.ctrl = nj_dctrl;
1031 for (i = 0; i < 2; i++) {
1032 card->bc[i].bch.nr = i + 1;
1033 set_channelmap(i + 1, card->isac.dch.dev.channelmap);
1034 mISDN_initbchannel(&card->bc[i].bch, MAX_DATA_MEM,
1035 NJ_DMA_RXSIZE >> 1);
1036 card->bc[i].bch.hw = card;
1037 card->bc[i].bch.ch.send = nj_l2l1B;
1038 card->bc[i].bch.ch.ctrl = nj_bctrl;
1039 card->bc[i].bch.ch.nr = i + 1;
1040 list_add(&card->bc[i].bch.ch.list,
1041 &card->isac.dch.dev.bchannels);
1042 card->bc[i].bch.hw = card;
1044 err = nj_setup(card);
1047 err = mISDN_register_device(&card->isac.dch.dev, &card->pdev->dev,
1051 err = nj_init_card(card);
1054 pr_notice("Netjet %d cards installed\n", nj_cnt);
1062 static int __devinit
1063 nj_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1067 struct tiger_hw *card;
1069 if (pdev->subsystem_vendor == 0x8086 &&
1070 pdev->subsystem_device == 0x0003) {
1071 pr_notice("Netjet: Digium X100P/X101P not handled\n");
1075 if (pdev->subsystem_vendor == 0x55 &&
1076 pdev->subsystem_device == 0x02) {
1077 pr_notice("Netjet: Enter!Now not handled yet\n");
1081 if (pdev->subsystem_vendor == 0xb100 &&
1082 pdev->subsystem_device == 0x0003) {
1083 pr_notice("Netjet: Digium TDM400P not handled yet\n");
1087 card = kzalloc(sizeof(struct tiger_hw), GFP_ATOMIC);
1089 pr_info("No kmem for Netjet\n");
1095 err = pci_enable_device(pdev);
1101 printk(KERN_INFO "nj_probe(mISDN): found adapter at %s\n",
1104 pci_set_master(pdev);
1106 /* the TJ300 and TJ320 must be detected, the IRQ handling is different
1107 * unfortunately the chips use the same device ID, but the TJ320 has
1108 * the bit20 in status PCI cfg register set
1110 pci_read_config_dword(pdev, 0x04, &cfg);
1111 if (cfg & 0x00100000)
1112 card->typ = NETJET_S_TJ320;
1114 card->typ = NETJET_S_TJ300;
1116 card->base = pci_resource_start(pdev, 0);
1117 card->irq = pdev->irq;
1118 pci_set_drvdata(pdev, card);
1119 err = setup_instance(card);
1121 pci_set_drvdata(pdev, NULL);
1127 static void __devexit nj_remove(struct pci_dev *pdev)
1129 struct tiger_hw *card = pci_get_drvdata(pdev);
1134 pr_info("%s drvdata already removed\n", __func__);
1137 /* We cannot select cards with PCI_SUB... IDs, since here are cards with
1138 * SUB IDs set to PCI_ANY_ID, so we need to match all and reject
1139 * known other cards which not work with this driver - see probe function */
1140 static struct pci_device_id nj_pci_ids[] __devinitdata = {
1141 { PCI_VENDOR_ID_TIGERJET, PCI_DEVICE_ID_TIGERJET_300,
1142 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1145 MODULE_DEVICE_TABLE(pci, nj_pci_ids);
1147 static struct pci_driver nj_driver = {
1150 .remove = __devexit_p(nj_remove),
1151 .id_table = nj_pci_ids,
1154 static int __init nj_init(void)
1158 pr_notice("Netjet PCI driver Rev. %s\n", NETJET_REV);
1159 err = pci_register_driver(&nj_driver);
1163 static void __exit nj_cleanup(void)
1165 pci_unregister_driver(&nj_driver);
1168 module_init(nj_init);
1169 module_exit(nj_cleanup);