2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
10 * Avi Kivity <avi@qumranet.com>
11 * Yaniv Kamay <yaniv@qumranet.com>
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
20 #include <linux/module.h>
21 #include <linux/kernel.h>
23 #include <linux/highmem.h>
24 #include <linux/profile.h>
25 #include <linux/sched.h>
29 #include "segment_descriptor.h"
31 MODULE_AUTHOR("Qumranet");
32 MODULE_LICENSE("GPL");
34 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
35 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
37 static struct page *vmx_io_bitmap_a;
38 static struct page *vmx_io_bitmap_b;
46 static struct vmcs_descriptor {
52 #define VMX_SEGMENT_FIELD(seg) \
53 [VCPU_SREG_##seg] = { \
54 .selector = GUEST_##seg##_SELECTOR, \
55 .base = GUEST_##seg##_BASE, \
56 .limit = GUEST_##seg##_LIMIT, \
57 .ar_bytes = GUEST_##seg##_AR_BYTES, \
60 static struct kvm_vmx_segment_field {
65 } kvm_vmx_segment_fields[] = {
66 VMX_SEGMENT_FIELD(CS),
67 VMX_SEGMENT_FIELD(DS),
68 VMX_SEGMENT_FIELD(ES),
69 VMX_SEGMENT_FIELD(FS),
70 VMX_SEGMENT_FIELD(GS),
71 VMX_SEGMENT_FIELD(SS),
72 VMX_SEGMENT_FIELD(TR),
73 VMX_SEGMENT_FIELD(LDTR),
77 * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
78 * away by decrementing the array size.
80 static const u32 vmx_msr_index[] = {
82 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, MSR_KERNEL_GS_BASE,
84 MSR_EFER, MSR_K6_STAR,
86 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
89 static unsigned msr_offset_kernel_gs_base;
90 #define NR_64BIT_MSRS 4
92 * avoid save/load MSR_SYSCALL_MASK and MSR_LSTAR by std vt
93 * mechanism (cpu bug AA24)
97 #define NR_64BIT_MSRS 0
101 static inline int is_page_fault(u32 intr_info)
103 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
104 INTR_INFO_VALID_MASK)) ==
105 (INTR_TYPE_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
108 static inline int is_no_device(u32 intr_info)
110 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
111 INTR_INFO_VALID_MASK)) ==
112 (INTR_TYPE_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
115 static inline int is_external_interrupt(u32 intr_info)
117 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
118 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
121 static struct vmx_msr_entry *find_msr_entry(struct kvm_vcpu *vcpu, u32 msr)
125 for (i = 0; i < vcpu->nmsrs; ++i)
126 if (vcpu->guest_msrs[i].index == msr)
127 return &vcpu->guest_msrs[i];
131 static void vmcs_clear(struct vmcs *vmcs)
133 u64 phys_addr = __pa(vmcs);
136 asm volatile (ASM_VMX_VMCLEAR_RAX "; setna %0"
137 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
140 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
144 static void __vcpu_clear(void *arg)
146 struct kvm_vcpu *vcpu = arg;
147 int cpu = raw_smp_processor_id();
149 if (vcpu->cpu == cpu)
150 vmcs_clear(vcpu->vmcs);
151 if (per_cpu(current_vmcs, cpu) == vcpu->vmcs)
152 per_cpu(current_vmcs, cpu) = NULL;
155 static void vcpu_clear(struct kvm_vcpu *vcpu)
157 if (vcpu->cpu != raw_smp_processor_id() && vcpu->cpu != -1)
158 smp_call_function_single(vcpu->cpu, __vcpu_clear, vcpu, 0, 1);
164 static unsigned long vmcs_readl(unsigned long field)
168 asm volatile (ASM_VMX_VMREAD_RDX_RAX
169 : "=a"(value) : "d"(field) : "cc");
173 static u16 vmcs_read16(unsigned long field)
175 return vmcs_readl(field);
178 static u32 vmcs_read32(unsigned long field)
180 return vmcs_readl(field);
183 static u64 vmcs_read64(unsigned long field)
186 return vmcs_readl(field);
188 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
192 static noinline void vmwrite_error(unsigned long field, unsigned long value)
194 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
195 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
199 static void vmcs_writel(unsigned long field, unsigned long value)
203 asm volatile (ASM_VMX_VMWRITE_RAX_RDX "; setna %0"
204 : "=q"(error) : "a"(value), "d"(field) : "cc" );
206 vmwrite_error(field, value);
209 static void vmcs_write16(unsigned long field, u16 value)
211 vmcs_writel(field, value);
214 static void vmcs_write32(unsigned long field, u32 value)
216 vmcs_writel(field, value);
219 static void vmcs_write64(unsigned long field, u64 value)
222 vmcs_writel(field, value);
224 vmcs_writel(field, value);
226 vmcs_writel(field+1, value >> 32);
230 static void vmcs_clear_bits(unsigned long field, u32 mask)
232 vmcs_writel(field, vmcs_readl(field) & ~mask);
235 static void vmcs_set_bits(unsigned long field, u32 mask)
237 vmcs_writel(field, vmcs_readl(field) | mask);
241 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
242 * vcpu mutex is already taken.
244 static void vmx_vcpu_load(struct kvm_vcpu *vcpu)
246 u64 phys_addr = __pa(vcpu->vmcs);
251 if (vcpu->cpu != cpu)
254 if (per_cpu(current_vmcs, cpu) != vcpu->vmcs) {
257 per_cpu(current_vmcs, cpu) = vcpu->vmcs;
258 asm volatile (ASM_VMX_VMPTRLD_RAX "; setna %0"
259 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
262 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
263 vcpu->vmcs, phys_addr);
266 if (vcpu->cpu != cpu) {
267 struct descriptor_table dt;
268 unsigned long sysenter_esp;
272 * Linux uses per-cpu TSS and GDT, so set these when switching
275 vmcs_writel(HOST_TR_BASE, read_tr_base()); /* 22.2.4 */
277 vmcs_writel(HOST_GDTR_BASE, dt.base); /* 22.2.4 */
279 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
280 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
284 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
286 kvm_put_guest_fpu(vcpu);
290 static void vmx_vcpu_decache(struct kvm_vcpu *vcpu)
295 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
297 return vmcs_readl(GUEST_RFLAGS);
300 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
302 vmcs_writel(GUEST_RFLAGS, rflags);
305 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
308 u32 interruptibility;
310 rip = vmcs_readl(GUEST_RIP);
311 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
312 vmcs_writel(GUEST_RIP, rip);
315 * We emulated an instruction, so temporary interrupt blocking
316 * should be removed, if set.
318 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
319 if (interruptibility & 3)
320 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
321 interruptibility & ~3);
322 vcpu->interrupt_window_open = 1;
325 static void vmx_inject_gp(struct kvm_vcpu *vcpu, unsigned error_code)
327 printk(KERN_DEBUG "inject_general_protection: rip 0x%lx\n",
328 vmcs_readl(GUEST_RIP));
329 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
330 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
332 INTR_TYPE_EXCEPTION |
333 INTR_INFO_DELIEVER_CODE_MASK |
334 INTR_INFO_VALID_MASK);
338 * Set up the vmcs to automatically save and restore system
339 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
340 * mode, as fiddling with msrs is very expensive.
342 static void setup_msrs(struct kvm_vcpu *vcpu)
344 int nr_skip, nr_good_msrs;
346 if (is_long_mode(vcpu))
347 nr_skip = NR_BAD_MSRS;
349 nr_skip = NR_64BIT_MSRS;
350 nr_good_msrs = vcpu->nmsrs - nr_skip;
353 * MSR_K6_STAR is only needed on long mode guests, and only
354 * if efer.sce is enabled.
356 if (find_msr_entry(vcpu, MSR_K6_STAR)) {
359 if (is_long_mode(vcpu) && (vcpu->shadow_efer & EFER_SCE))
364 vmcs_writel(VM_ENTRY_MSR_LOAD_ADDR,
365 virt_to_phys(vcpu->guest_msrs + nr_skip));
366 vmcs_writel(VM_EXIT_MSR_STORE_ADDR,
367 virt_to_phys(vcpu->guest_msrs + nr_skip));
368 vmcs_writel(VM_EXIT_MSR_LOAD_ADDR,
369 virt_to_phys(vcpu->host_msrs + nr_skip));
370 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, nr_good_msrs); /* 22.2.2 */
371 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, nr_good_msrs); /* 22.2.2 */
372 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, nr_good_msrs); /* 22.2.2 */
376 * reads and returns guest's timestamp counter "register"
377 * guest_tsc = host_tsc + tsc_offset -- 21.3
379 static u64 guest_read_tsc(void)
381 u64 host_tsc, tsc_offset;
384 tsc_offset = vmcs_read64(TSC_OFFSET);
385 return host_tsc + tsc_offset;
389 * writes 'guest_tsc' into guest's timestamp counter "register"
390 * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
392 static void guest_write_tsc(u64 guest_tsc)
397 vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
400 static void reload_tss(void)
402 #ifndef CONFIG_X86_64
405 * VT restores TR but not its size. Useless.
407 struct descriptor_table gdt;
408 struct segment_descriptor *descs;
411 descs = (void *)gdt.base;
412 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
418 * Reads an msr value (of 'msr_index') into 'pdata'.
419 * Returns 0 on success, non-0 otherwise.
420 * Assumes vcpu_load() was already called.
422 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
425 struct vmx_msr_entry *msr;
428 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
435 data = vmcs_readl(GUEST_FS_BASE);
438 data = vmcs_readl(GUEST_GS_BASE);
441 return kvm_get_msr_common(vcpu, msr_index, pdata);
443 case MSR_IA32_TIME_STAMP_COUNTER:
444 data = guest_read_tsc();
446 case MSR_IA32_SYSENTER_CS:
447 data = vmcs_read32(GUEST_SYSENTER_CS);
449 case MSR_IA32_SYSENTER_EIP:
450 data = vmcs_readl(GUEST_SYSENTER_EIP);
452 case MSR_IA32_SYSENTER_ESP:
453 data = vmcs_readl(GUEST_SYSENTER_ESP);
456 msr = find_msr_entry(vcpu, msr_index);
461 return kvm_get_msr_common(vcpu, msr_index, pdata);
469 * Writes msr value into into the appropriate "register".
470 * Returns 0 on success, non-0 otherwise.
471 * Assumes vcpu_load() was already called.
473 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
475 struct vmx_msr_entry *msr;
479 return kvm_set_msr_common(vcpu, msr_index, data);
481 vmcs_writel(GUEST_FS_BASE, data);
484 vmcs_writel(GUEST_GS_BASE, data);
487 case MSR_SYSCALL_MASK:
488 msr = find_msr_entry(vcpu, msr_index);
491 load_msrs(vcpu->guest_msrs, NR_BAD_MSRS);
494 case MSR_IA32_SYSENTER_CS:
495 vmcs_write32(GUEST_SYSENTER_CS, data);
497 case MSR_IA32_SYSENTER_EIP:
498 vmcs_writel(GUEST_SYSENTER_EIP, data);
500 case MSR_IA32_SYSENTER_ESP:
501 vmcs_writel(GUEST_SYSENTER_ESP, data);
503 case MSR_IA32_TIME_STAMP_COUNTER:
504 guest_write_tsc(data);
507 msr = find_msr_entry(vcpu, msr_index);
512 return kvm_set_msr_common(vcpu, msr_index, data);
521 * Sync the rsp and rip registers into the vcpu structure. This allows
522 * registers to be accessed by indexing vcpu->regs.
524 static void vcpu_load_rsp_rip(struct kvm_vcpu *vcpu)
526 vcpu->regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
527 vcpu->rip = vmcs_readl(GUEST_RIP);
531 * Syncs rsp and rip back into the vmcs. Should be called after possible
534 static void vcpu_put_rsp_rip(struct kvm_vcpu *vcpu)
536 vmcs_writel(GUEST_RSP, vcpu->regs[VCPU_REGS_RSP]);
537 vmcs_writel(GUEST_RIP, vcpu->rip);
540 static int set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg)
542 unsigned long dr7 = 0x400;
543 u32 exception_bitmap;
546 exception_bitmap = vmcs_read32(EXCEPTION_BITMAP);
547 old_singlestep = vcpu->guest_debug.singlestep;
549 vcpu->guest_debug.enabled = dbg->enabled;
550 if (vcpu->guest_debug.enabled) {
553 dr7 |= 0x200; /* exact */
554 for (i = 0; i < 4; ++i) {
555 if (!dbg->breakpoints[i].enabled)
557 vcpu->guest_debug.bp[i] = dbg->breakpoints[i].address;
558 dr7 |= 2 << (i*2); /* global enable */
559 dr7 |= 0 << (i*4+16); /* execution breakpoint */
562 exception_bitmap |= (1u << 1); /* Trap debug exceptions */
564 vcpu->guest_debug.singlestep = dbg->singlestep;
566 exception_bitmap &= ~(1u << 1); /* Ignore debug exceptions */
567 vcpu->guest_debug.singlestep = 0;
570 if (old_singlestep && !vcpu->guest_debug.singlestep) {
573 flags = vmcs_readl(GUEST_RFLAGS);
574 flags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
575 vmcs_writel(GUEST_RFLAGS, flags);
578 vmcs_write32(EXCEPTION_BITMAP, exception_bitmap);
579 vmcs_writel(GUEST_DR7, dr7);
584 static __init int cpu_has_kvm_support(void)
586 unsigned long ecx = cpuid_ecx(1);
587 return test_bit(5, &ecx); /* CPUID.1:ECX.VMX[bit 5] -> VT */
590 static __init int vmx_disabled_by_bios(void)
594 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
595 return (msr & 5) == 1; /* locked but not enabled */
598 static void hardware_enable(void *garbage)
600 int cpu = raw_smp_processor_id();
601 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
604 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
606 /* enable and lock */
607 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | 5);
608 write_cr4(read_cr4() | CR4_VMXE); /* FIXME: not cpu hotplug safe */
609 asm volatile (ASM_VMX_VMXON_RAX : : "a"(&phys_addr), "m"(phys_addr)
613 static void hardware_disable(void *garbage)
615 asm volatile (ASM_VMX_VMXOFF : : : "cc");
618 static __init void setup_vmcs_descriptor(void)
620 u32 vmx_msr_low, vmx_msr_high;
622 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
623 vmcs_descriptor.size = vmx_msr_high & 0x1fff;
624 vmcs_descriptor.order = get_order(vmcs_descriptor.size);
625 vmcs_descriptor.revision_id = vmx_msr_low;
628 static struct vmcs *alloc_vmcs_cpu(int cpu)
630 int node = cpu_to_node(cpu);
634 pages = alloc_pages_node(node, GFP_KERNEL, vmcs_descriptor.order);
637 vmcs = page_address(pages);
638 memset(vmcs, 0, vmcs_descriptor.size);
639 vmcs->revision_id = vmcs_descriptor.revision_id; /* vmcs revision id */
643 static struct vmcs *alloc_vmcs(void)
645 return alloc_vmcs_cpu(raw_smp_processor_id());
648 static void free_vmcs(struct vmcs *vmcs)
650 free_pages((unsigned long)vmcs, vmcs_descriptor.order);
653 static void free_kvm_area(void)
657 for_each_online_cpu(cpu)
658 free_vmcs(per_cpu(vmxarea, cpu));
661 extern struct vmcs *alloc_vmcs_cpu(int cpu);
663 static __init int alloc_kvm_area(void)
667 for_each_online_cpu(cpu) {
670 vmcs = alloc_vmcs_cpu(cpu);
676 per_cpu(vmxarea, cpu) = vmcs;
681 static __init int hardware_setup(void)
683 setup_vmcs_descriptor();
684 return alloc_kvm_area();
687 static __exit void hardware_unsetup(void)
692 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
694 if (vcpu->rmode.active)
695 vmcs_write32(EXCEPTION_BITMAP, ~0);
697 vmcs_write32(EXCEPTION_BITMAP, 1 << PF_VECTOR);
700 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
702 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
704 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
705 vmcs_write16(sf->selector, save->selector);
706 vmcs_writel(sf->base, save->base);
707 vmcs_write32(sf->limit, save->limit);
708 vmcs_write32(sf->ar_bytes, save->ar);
710 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
712 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
716 static void enter_pmode(struct kvm_vcpu *vcpu)
720 vcpu->rmode.active = 0;
722 vmcs_writel(GUEST_TR_BASE, vcpu->rmode.tr.base);
723 vmcs_write32(GUEST_TR_LIMIT, vcpu->rmode.tr.limit);
724 vmcs_write32(GUEST_TR_AR_BYTES, vcpu->rmode.tr.ar);
726 flags = vmcs_readl(GUEST_RFLAGS);
727 flags &= ~(IOPL_MASK | X86_EFLAGS_VM);
728 flags |= (vcpu->rmode.save_iopl << IOPL_SHIFT);
729 vmcs_writel(GUEST_RFLAGS, flags);
731 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~CR4_VME_MASK) |
732 (vmcs_readl(CR4_READ_SHADOW) & CR4_VME_MASK));
734 update_exception_bitmap(vcpu);
736 fix_pmode_dataseg(VCPU_SREG_ES, &vcpu->rmode.es);
737 fix_pmode_dataseg(VCPU_SREG_DS, &vcpu->rmode.ds);
738 fix_pmode_dataseg(VCPU_SREG_GS, &vcpu->rmode.gs);
739 fix_pmode_dataseg(VCPU_SREG_FS, &vcpu->rmode.fs);
741 vmcs_write16(GUEST_SS_SELECTOR, 0);
742 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
744 vmcs_write16(GUEST_CS_SELECTOR,
745 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
746 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
749 static int rmode_tss_base(struct kvm* kvm)
751 gfn_t base_gfn = kvm->memslots[0].base_gfn + kvm->memslots[0].npages - 3;
752 return base_gfn << PAGE_SHIFT;
755 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
757 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
759 save->selector = vmcs_read16(sf->selector);
760 save->base = vmcs_readl(sf->base);
761 save->limit = vmcs_read32(sf->limit);
762 save->ar = vmcs_read32(sf->ar_bytes);
763 vmcs_write16(sf->selector, vmcs_readl(sf->base) >> 4);
764 vmcs_write32(sf->limit, 0xffff);
765 vmcs_write32(sf->ar_bytes, 0xf3);
768 static void enter_rmode(struct kvm_vcpu *vcpu)
772 vcpu->rmode.active = 1;
774 vcpu->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
775 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
777 vcpu->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
778 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
780 vcpu->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
781 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
783 flags = vmcs_readl(GUEST_RFLAGS);
784 vcpu->rmode.save_iopl = (flags & IOPL_MASK) >> IOPL_SHIFT;
786 flags |= IOPL_MASK | X86_EFLAGS_VM;
788 vmcs_writel(GUEST_RFLAGS, flags);
789 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | CR4_VME_MASK);
790 update_exception_bitmap(vcpu);
792 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
793 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
794 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
796 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
797 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
798 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
799 vmcs_writel(GUEST_CS_BASE, 0xf0000);
800 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
802 fix_rmode_seg(VCPU_SREG_ES, &vcpu->rmode.es);
803 fix_rmode_seg(VCPU_SREG_DS, &vcpu->rmode.ds);
804 fix_rmode_seg(VCPU_SREG_GS, &vcpu->rmode.gs);
805 fix_rmode_seg(VCPU_SREG_FS, &vcpu->rmode.fs);
810 static void enter_lmode(struct kvm_vcpu *vcpu)
814 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
815 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
816 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
818 vmcs_write32(GUEST_TR_AR_BYTES,
819 (guest_tr_ar & ~AR_TYPE_MASK)
820 | AR_TYPE_BUSY_64_TSS);
823 vcpu->shadow_efer |= EFER_LMA;
825 find_msr_entry(vcpu, MSR_EFER)->data |= EFER_LMA | EFER_LME;
826 vmcs_write32(VM_ENTRY_CONTROLS,
827 vmcs_read32(VM_ENTRY_CONTROLS)
828 | VM_ENTRY_CONTROLS_IA32E_MASK);
831 static void exit_lmode(struct kvm_vcpu *vcpu)
833 vcpu->shadow_efer &= ~EFER_LMA;
835 vmcs_write32(VM_ENTRY_CONTROLS,
836 vmcs_read32(VM_ENTRY_CONTROLS)
837 & ~VM_ENTRY_CONTROLS_IA32E_MASK);
842 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
844 vcpu->cr4 &= KVM_GUEST_CR4_MASK;
845 vcpu->cr4 |= vmcs_readl(GUEST_CR4) & ~KVM_GUEST_CR4_MASK;
848 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
850 if (vcpu->rmode.active && (cr0 & CR0_PE_MASK))
853 if (!vcpu->rmode.active && !(cr0 & CR0_PE_MASK))
857 if (vcpu->shadow_efer & EFER_LME) {
858 if (!is_paging(vcpu) && (cr0 & CR0_PG_MASK))
860 if (is_paging(vcpu) && !(cr0 & CR0_PG_MASK))
865 if (!(cr0 & CR0_TS_MASK)) {
866 vcpu->fpu_active = 1;
867 vmcs_clear_bits(EXCEPTION_BITMAP, CR0_TS_MASK);
870 vmcs_writel(CR0_READ_SHADOW, cr0);
871 vmcs_writel(GUEST_CR0,
872 (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON);
876 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
878 vmcs_writel(GUEST_CR3, cr3);
880 if (!(vcpu->cr0 & CR0_TS_MASK)) {
881 vcpu->fpu_active = 0;
882 vmcs_set_bits(GUEST_CR0, CR0_TS_MASK);
883 vmcs_set_bits(EXCEPTION_BITMAP, 1 << NM_VECTOR);
887 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
889 vmcs_writel(CR4_READ_SHADOW, cr4);
890 vmcs_writel(GUEST_CR4, cr4 | (vcpu->rmode.active ?
891 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON));
897 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
899 struct vmx_msr_entry *msr = find_msr_entry(vcpu, MSR_EFER);
901 vcpu->shadow_efer = efer;
902 if (efer & EFER_LMA) {
903 vmcs_write32(VM_ENTRY_CONTROLS,
904 vmcs_read32(VM_ENTRY_CONTROLS) |
905 VM_ENTRY_CONTROLS_IA32E_MASK);
909 vmcs_write32(VM_ENTRY_CONTROLS,
910 vmcs_read32(VM_ENTRY_CONTROLS) &
911 ~VM_ENTRY_CONTROLS_IA32E_MASK);
913 msr->data = efer & ~EFER_LME;
920 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
922 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
924 return vmcs_readl(sf->base);
927 static void vmx_get_segment(struct kvm_vcpu *vcpu,
928 struct kvm_segment *var, int seg)
930 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
933 var->base = vmcs_readl(sf->base);
934 var->limit = vmcs_read32(sf->limit);
935 var->selector = vmcs_read16(sf->selector);
936 ar = vmcs_read32(sf->ar_bytes);
937 if (ar & AR_UNUSABLE_MASK)
940 var->s = (ar >> 4) & 1;
941 var->dpl = (ar >> 5) & 3;
942 var->present = (ar >> 7) & 1;
943 var->avl = (ar >> 12) & 1;
944 var->l = (ar >> 13) & 1;
945 var->db = (ar >> 14) & 1;
946 var->g = (ar >> 15) & 1;
947 var->unusable = (ar >> 16) & 1;
950 static void vmx_set_segment(struct kvm_vcpu *vcpu,
951 struct kvm_segment *var, int seg)
953 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
956 vmcs_writel(sf->base, var->base);
957 vmcs_write32(sf->limit, var->limit);
958 vmcs_write16(sf->selector, var->selector);
959 if (vcpu->rmode.active && var->s) {
961 * Hack real-mode segments into vm86 compatibility.
963 if (var->base == 0xffff0000 && var->selector == 0xf000)
964 vmcs_writel(sf->base, 0xf0000);
966 } else if (var->unusable)
970 ar |= (var->s & 1) << 4;
971 ar |= (var->dpl & 3) << 5;
972 ar |= (var->present & 1) << 7;
973 ar |= (var->avl & 1) << 12;
974 ar |= (var->l & 1) << 13;
975 ar |= (var->db & 1) << 14;
976 ar |= (var->g & 1) << 15;
978 if (ar == 0) /* a 0 value means unusable */
979 ar = AR_UNUSABLE_MASK;
980 vmcs_write32(sf->ar_bytes, ar);
983 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
985 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
987 *db = (ar >> 14) & 1;
991 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
993 dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
994 dt->base = vmcs_readl(GUEST_IDTR_BASE);
997 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
999 vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
1000 vmcs_writel(GUEST_IDTR_BASE, dt->base);
1003 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1005 dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
1006 dt->base = vmcs_readl(GUEST_GDTR_BASE);
1009 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1011 vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
1012 vmcs_writel(GUEST_GDTR_BASE, dt->base);
1015 static int init_rmode_tss(struct kvm* kvm)
1017 struct page *p1, *p2, *p3;
1018 gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
1021 p1 = gfn_to_page(kvm, fn++);
1022 p2 = gfn_to_page(kvm, fn++);
1023 p3 = gfn_to_page(kvm, fn);
1025 if (!p1 || !p2 || !p3) {
1026 kvm_printf(kvm,"%s: gfn_to_page failed\n", __FUNCTION__);
1030 page = kmap_atomic(p1, KM_USER0);
1031 memset(page, 0, PAGE_SIZE);
1032 *(u16*)(page + 0x66) = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
1033 kunmap_atomic(page, KM_USER0);
1035 page = kmap_atomic(p2, KM_USER0);
1036 memset(page, 0, PAGE_SIZE);
1037 kunmap_atomic(page, KM_USER0);
1039 page = kmap_atomic(p3, KM_USER0);
1040 memset(page, 0, PAGE_SIZE);
1041 *(page + RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1) = ~0;
1042 kunmap_atomic(page, KM_USER0);
1047 static void vmcs_write32_fixedbits(u32 msr, u32 vmcs_field, u32 val)
1049 u32 msr_high, msr_low;
1051 rdmsr(msr, msr_low, msr_high);
1055 vmcs_write32(vmcs_field, val);
1058 static void seg_setup(int seg)
1060 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1062 vmcs_write16(sf->selector, 0);
1063 vmcs_writel(sf->base, 0);
1064 vmcs_write32(sf->limit, 0xffff);
1065 vmcs_write32(sf->ar_bytes, 0x93);
1069 * Sets up the vmcs for emulated real mode.
1071 static int vmx_vcpu_setup(struct kvm_vcpu *vcpu)
1073 u32 host_sysenter_cs;
1076 struct descriptor_table dt;
1079 extern asmlinkage void kvm_vmx_return(void);
1081 if (!init_rmode_tss(vcpu->kvm)) {
1086 memset(vcpu->regs, 0, sizeof(vcpu->regs));
1087 vcpu->regs[VCPU_REGS_RDX] = get_rdx_init_val();
1089 vcpu->apic_base = 0xfee00000 |
1090 /*for vcpu 0*/ MSR_IA32_APICBASE_BSP |
1091 MSR_IA32_APICBASE_ENABLE;
1096 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
1097 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
1099 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
1100 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
1101 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1102 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1104 seg_setup(VCPU_SREG_DS);
1105 seg_setup(VCPU_SREG_ES);
1106 seg_setup(VCPU_SREG_FS);
1107 seg_setup(VCPU_SREG_GS);
1108 seg_setup(VCPU_SREG_SS);
1110 vmcs_write16(GUEST_TR_SELECTOR, 0);
1111 vmcs_writel(GUEST_TR_BASE, 0);
1112 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
1113 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1115 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
1116 vmcs_writel(GUEST_LDTR_BASE, 0);
1117 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
1118 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
1120 vmcs_write32(GUEST_SYSENTER_CS, 0);
1121 vmcs_writel(GUEST_SYSENTER_ESP, 0);
1122 vmcs_writel(GUEST_SYSENTER_EIP, 0);
1124 vmcs_writel(GUEST_RFLAGS, 0x02);
1125 vmcs_writel(GUEST_RIP, 0xfff0);
1126 vmcs_writel(GUEST_RSP, 0);
1128 //todo: dr0 = dr1 = dr2 = dr3 = 0; dr6 = 0xffff0ff0
1129 vmcs_writel(GUEST_DR7, 0x400);
1131 vmcs_writel(GUEST_GDTR_BASE, 0);
1132 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
1134 vmcs_writel(GUEST_IDTR_BASE, 0);
1135 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
1137 vmcs_write32(GUEST_ACTIVITY_STATE, 0);
1138 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
1139 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
1142 vmcs_write64(IO_BITMAP_A, page_to_phys(vmx_io_bitmap_a));
1143 vmcs_write64(IO_BITMAP_B, page_to_phys(vmx_io_bitmap_b));
1147 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
1149 /* Special registers */
1150 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
1153 vmcs_write32_fixedbits(MSR_IA32_VMX_PINBASED_CTLS,
1154 PIN_BASED_VM_EXEC_CONTROL,
1155 PIN_BASED_EXT_INTR_MASK /* 20.6.1 */
1156 | PIN_BASED_NMI_EXITING /* 20.6.1 */
1158 vmcs_write32_fixedbits(MSR_IA32_VMX_PROCBASED_CTLS,
1159 CPU_BASED_VM_EXEC_CONTROL,
1160 CPU_BASED_HLT_EXITING /* 20.6.2 */
1161 | CPU_BASED_CR8_LOAD_EXITING /* 20.6.2 */
1162 | CPU_BASED_CR8_STORE_EXITING /* 20.6.2 */
1163 | CPU_BASED_ACTIVATE_IO_BITMAP /* 20.6.2 */
1164 | CPU_BASED_MOV_DR_EXITING
1165 | CPU_BASED_USE_TSC_OFFSETING /* 21.3 */
1168 vmcs_write32(EXCEPTION_BITMAP, 1 << PF_VECTOR);
1169 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
1170 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
1171 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
1173 vmcs_writel(HOST_CR0, read_cr0()); /* 22.2.3 */
1174 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
1175 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
1177 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
1178 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
1179 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
1180 vmcs_write16(HOST_FS_SELECTOR, read_fs()); /* 22.2.4 */
1181 vmcs_write16(HOST_GS_SELECTOR, read_gs()); /* 22.2.4 */
1182 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
1183 #ifdef CONFIG_X86_64
1184 rdmsrl(MSR_FS_BASE, a);
1185 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
1186 rdmsrl(MSR_GS_BASE, a);
1187 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
1189 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
1190 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
1193 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
1196 vmcs_writel(HOST_IDTR_BASE, dt.base); /* 22.2.4 */
1199 vmcs_writel(HOST_RIP, (unsigned long)kvm_vmx_return); /* 22.2.5 */
1201 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
1202 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
1203 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
1204 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
1205 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
1206 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
1208 for (i = 0; i < NR_VMX_MSR; ++i) {
1209 u32 index = vmx_msr_index[i];
1210 u32 data_low, data_high;
1212 int j = vcpu->nmsrs;
1214 if (rdmsr_safe(index, &data_low, &data_high) < 0)
1216 if (wrmsr_safe(index, data_low, data_high) < 0)
1218 data = data_low | ((u64)data_high << 32);
1219 vcpu->host_msrs[j].index = index;
1220 vcpu->host_msrs[j].reserved = 0;
1221 vcpu->host_msrs[j].data = data;
1222 vcpu->guest_msrs[j] = vcpu->host_msrs[j];
1223 #ifdef CONFIG_X86_64
1224 if (index == MSR_KERNEL_GS_BASE)
1225 msr_offset_kernel_gs_base = j;
1232 vmcs_write32_fixedbits(MSR_IA32_VMX_EXIT_CTLS, VM_EXIT_CONTROLS,
1233 (HOST_IS_64 << 9)); /* 22.2,1, 20.7.1 */
1235 /* 22.2.1, 20.8.1 */
1236 vmcs_write32_fixedbits(MSR_IA32_VMX_ENTRY_CTLS,
1237 VM_ENTRY_CONTROLS, 0);
1238 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
1240 #ifdef CONFIG_X86_64
1241 vmcs_writel(VIRTUAL_APIC_PAGE_ADDR, 0);
1242 vmcs_writel(TPR_THRESHOLD, 0);
1245 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
1246 vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK);
1248 vcpu->cr0 = 0x60000010;
1249 vmx_set_cr0(vcpu, vcpu->cr0); // enter rmode
1250 vmx_set_cr4(vcpu, 0);
1251 #ifdef CONFIG_X86_64
1252 vmx_set_efer(vcpu, 0);
1261 static void inject_rmode_irq(struct kvm_vcpu *vcpu, int irq)
1266 unsigned long flags;
1267 unsigned long ss_base = vmcs_readl(GUEST_SS_BASE);
1268 u16 sp = vmcs_readl(GUEST_RSP);
1269 u32 ss_limit = vmcs_read32(GUEST_SS_LIMIT);
1271 if (sp > ss_limit || sp < 6 ) {
1272 vcpu_printf(vcpu, "%s: #SS, rsp 0x%lx ss 0x%lx limit 0x%x\n",
1274 vmcs_readl(GUEST_RSP),
1275 vmcs_readl(GUEST_SS_BASE),
1276 vmcs_read32(GUEST_SS_LIMIT));
1280 if (kvm_read_guest(vcpu, irq * sizeof(ent), sizeof(ent), &ent) !=
1282 vcpu_printf(vcpu, "%s: read guest err\n", __FUNCTION__);
1286 flags = vmcs_readl(GUEST_RFLAGS);
1287 cs = vmcs_readl(GUEST_CS_BASE) >> 4;
1288 ip = vmcs_readl(GUEST_RIP);
1291 if (kvm_write_guest(vcpu, ss_base + sp - 2, 2, &flags) != 2 ||
1292 kvm_write_guest(vcpu, ss_base + sp - 4, 2, &cs) != 2 ||
1293 kvm_write_guest(vcpu, ss_base + sp - 6, 2, &ip) != 2) {
1294 vcpu_printf(vcpu, "%s: write guest err\n", __FUNCTION__);
1298 vmcs_writel(GUEST_RFLAGS, flags &
1299 ~( X86_EFLAGS_IF | X86_EFLAGS_AC | X86_EFLAGS_TF));
1300 vmcs_write16(GUEST_CS_SELECTOR, ent[1]) ;
1301 vmcs_writel(GUEST_CS_BASE, ent[1] << 4);
1302 vmcs_writel(GUEST_RIP, ent[0]);
1303 vmcs_writel(GUEST_RSP, (vmcs_readl(GUEST_RSP) & ~0xffff) | (sp - 6));
1306 static void kvm_do_inject_irq(struct kvm_vcpu *vcpu)
1308 int word_index = __ffs(vcpu->irq_summary);
1309 int bit_index = __ffs(vcpu->irq_pending[word_index]);
1310 int irq = word_index * BITS_PER_LONG + bit_index;
1312 clear_bit(bit_index, &vcpu->irq_pending[word_index]);
1313 if (!vcpu->irq_pending[word_index])
1314 clear_bit(word_index, &vcpu->irq_summary);
1316 if (vcpu->rmode.active) {
1317 inject_rmode_irq(vcpu, irq);
1320 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
1321 irq | INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1325 static void do_interrupt_requests(struct kvm_vcpu *vcpu,
1326 struct kvm_run *kvm_run)
1328 u32 cpu_based_vm_exec_control;
1330 vcpu->interrupt_window_open =
1331 ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
1332 (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0);
1334 if (vcpu->interrupt_window_open &&
1335 vcpu->irq_summary &&
1336 !(vmcs_read32(VM_ENTRY_INTR_INFO_FIELD) & INTR_INFO_VALID_MASK))
1338 * If interrupts enabled, and not blocked by sti or mov ss. Good.
1340 kvm_do_inject_irq(vcpu);
1342 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
1343 if (!vcpu->interrupt_window_open &&
1344 (vcpu->irq_summary || kvm_run->request_interrupt_window))
1346 * Interrupts blocked. Wait for unblock.
1348 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
1350 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
1351 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
1354 static void kvm_guest_debug_pre(struct kvm_vcpu *vcpu)
1356 struct kvm_guest_debug *dbg = &vcpu->guest_debug;
1358 set_debugreg(dbg->bp[0], 0);
1359 set_debugreg(dbg->bp[1], 1);
1360 set_debugreg(dbg->bp[2], 2);
1361 set_debugreg(dbg->bp[3], 3);
1363 if (dbg->singlestep) {
1364 unsigned long flags;
1366 flags = vmcs_readl(GUEST_RFLAGS);
1367 flags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
1368 vmcs_writel(GUEST_RFLAGS, flags);
1372 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
1373 int vec, u32 err_code)
1375 if (!vcpu->rmode.active)
1378 if (vec == GP_VECTOR && err_code == 0)
1379 if (emulate_instruction(vcpu, NULL, 0, 0) == EMULATE_DONE)
1384 static int handle_exception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1386 u32 intr_info, error_code;
1387 unsigned long cr2, rip;
1389 enum emulation_result er;
1392 vect_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
1393 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
1395 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
1396 !is_page_fault(intr_info)) {
1397 printk(KERN_ERR "%s: unexpected, vectoring info 0x%x "
1398 "intr info 0x%x\n", __FUNCTION__, vect_info, intr_info);
1401 if (is_external_interrupt(vect_info)) {
1402 int irq = vect_info & VECTORING_INFO_VECTOR_MASK;
1403 set_bit(irq, vcpu->irq_pending);
1404 set_bit(irq / BITS_PER_LONG, &vcpu->irq_summary);
1407 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200) { /* nmi */
1412 if (is_no_device(intr_info)) {
1413 vcpu->fpu_active = 1;
1414 vmcs_clear_bits(EXCEPTION_BITMAP, 1 << NM_VECTOR);
1415 if (!(vcpu->cr0 & CR0_TS_MASK))
1416 vmcs_clear_bits(GUEST_CR0, CR0_TS_MASK);
1421 rip = vmcs_readl(GUEST_RIP);
1422 if (intr_info & INTR_INFO_DELIEVER_CODE_MASK)
1423 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
1424 if (is_page_fault(intr_info)) {
1425 cr2 = vmcs_readl(EXIT_QUALIFICATION);
1427 spin_lock(&vcpu->kvm->lock);
1428 r = kvm_mmu_page_fault(vcpu, cr2, error_code);
1430 spin_unlock(&vcpu->kvm->lock);
1434 spin_unlock(&vcpu->kvm->lock);
1438 er = emulate_instruction(vcpu, kvm_run, cr2, error_code);
1439 spin_unlock(&vcpu->kvm->lock);
1444 case EMULATE_DO_MMIO:
1445 ++vcpu->stat.mmio_exits;
1446 kvm_run->exit_reason = KVM_EXIT_MMIO;
1449 vcpu_printf(vcpu, "%s: emulate fail\n", __FUNCTION__);
1456 if (vcpu->rmode.active &&
1457 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
1461 if ((intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK)) == (INTR_TYPE_EXCEPTION | 1)) {
1462 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1465 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
1466 kvm_run->ex.exception = intr_info & INTR_INFO_VECTOR_MASK;
1467 kvm_run->ex.error_code = error_code;
1471 static int handle_external_interrupt(struct kvm_vcpu *vcpu,
1472 struct kvm_run *kvm_run)
1474 ++vcpu->stat.irq_exits;
1478 static int handle_triple_fault(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1480 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1484 static int get_io_count(struct kvm_vcpu *vcpu, unsigned long *count)
1491 if ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_VM)) {
1494 u32 cs_ar = vmcs_read32(GUEST_CS_AR_BYTES);
1496 countr_size = (cs_ar & AR_L_MASK) ? 8:
1497 (cs_ar & AR_DB_MASK) ? 4: 2;
1500 rip = vmcs_readl(GUEST_RIP);
1501 if (countr_size != 8)
1502 rip += vmcs_readl(GUEST_CS_BASE);
1504 n = kvm_read_guest(vcpu, rip, sizeof(inst), &inst);
1506 for (i = 0; i < n; i++) {
1507 switch (((u8*)&inst)[i]) {
1520 countr_size = (countr_size == 2) ? 4: (countr_size >> 1);
1528 *count = vcpu->regs[VCPU_REGS_RCX] & (~0ULL >> (64 - countr_size));
1529 //printk("cx: %lx\n", vcpu->regs[VCPU_REGS_RCX]);
1533 static int handle_io(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1535 u64 exit_qualification;
1536 int size, down, in, string, rep;
1538 unsigned long count;
1541 ++vcpu->stat.io_exits;
1542 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
1543 in = (exit_qualification & 8) != 0;
1544 size = (exit_qualification & 7) + 1;
1545 string = (exit_qualification & 16) != 0;
1546 down = (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_DF) != 0;
1548 rep = (exit_qualification & 32) != 0;
1549 port = exit_qualification >> 16;
1552 if (rep && !get_io_count(vcpu, &count))
1554 address = vmcs_readl(GUEST_LINEAR_ADDRESS);
1556 return kvm_setup_pio(vcpu, kvm_run, in, size, count, string, down,
1557 address, rep, port);
1561 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
1564 * Patch in the VMCALL instruction:
1566 hypercall[0] = 0x0f;
1567 hypercall[1] = 0x01;
1568 hypercall[2] = 0xc1;
1569 hypercall[3] = 0xc3;
1572 static int handle_cr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1574 u64 exit_qualification;
1578 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
1579 cr = exit_qualification & 15;
1580 reg = (exit_qualification >> 8) & 15;
1581 switch ((exit_qualification >> 4) & 3) {
1582 case 0: /* mov to cr */
1585 vcpu_load_rsp_rip(vcpu);
1586 set_cr0(vcpu, vcpu->regs[reg]);
1587 skip_emulated_instruction(vcpu);
1590 vcpu_load_rsp_rip(vcpu);
1591 set_cr3(vcpu, vcpu->regs[reg]);
1592 skip_emulated_instruction(vcpu);
1595 vcpu_load_rsp_rip(vcpu);
1596 set_cr4(vcpu, vcpu->regs[reg]);
1597 skip_emulated_instruction(vcpu);
1600 vcpu_load_rsp_rip(vcpu);
1601 set_cr8(vcpu, vcpu->regs[reg]);
1602 skip_emulated_instruction(vcpu);
1607 vcpu_load_rsp_rip(vcpu);
1608 vcpu->fpu_active = 1;
1609 vmcs_clear_bits(EXCEPTION_BITMAP, 1 << NM_VECTOR);
1610 vmcs_clear_bits(GUEST_CR0, CR0_TS_MASK);
1611 vcpu->cr0 &= ~CR0_TS_MASK;
1612 vmcs_writel(CR0_READ_SHADOW, vcpu->cr0);
1613 skip_emulated_instruction(vcpu);
1615 case 1: /*mov from cr*/
1618 vcpu_load_rsp_rip(vcpu);
1619 vcpu->regs[reg] = vcpu->cr3;
1620 vcpu_put_rsp_rip(vcpu);
1621 skip_emulated_instruction(vcpu);
1624 vcpu_load_rsp_rip(vcpu);
1625 vcpu->regs[reg] = vcpu->cr8;
1626 vcpu_put_rsp_rip(vcpu);
1627 skip_emulated_instruction(vcpu);
1632 lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f);
1634 skip_emulated_instruction(vcpu);
1639 kvm_run->exit_reason = 0;
1640 printk(KERN_ERR "kvm: unhandled control register: op %d cr %d\n",
1641 (int)(exit_qualification >> 4) & 3, cr);
1645 static int handle_dr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1647 u64 exit_qualification;
1652 * FIXME: this code assumes the host is debugging the guest.
1653 * need to deal with guest debugging itself too.
1655 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
1656 dr = exit_qualification & 7;
1657 reg = (exit_qualification >> 8) & 15;
1658 vcpu_load_rsp_rip(vcpu);
1659 if (exit_qualification & 16) {
1671 vcpu->regs[reg] = val;
1675 vcpu_put_rsp_rip(vcpu);
1676 skip_emulated_instruction(vcpu);
1680 static int handle_cpuid(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1682 kvm_emulate_cpuid(vcpu);
1686 static int handle_rdmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1688 u32 ecx = vcpu->regs[VCPU_REGS_RCX];
1691 if (vmx_get_msr(vcpu, ecx, &data)) {
1692 vmx_inject_gp(vcpu, 0);
1696 /* FIXME: handling of bits 32:63 of rax, rdx */
1697 vcpu->regs[VCPU_REGS_RAX] = data & -1u;
1698 vcpu->regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
1699 skip_emulated_instruction(vcpu);
1703 static int handle_wrmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1705 u32 ecx = vcpu->regs[VCPU_REGS_RCX];
1706 u64 data = (vcpu->regs[VCPU_REGS_RAX] & -1u)
1707 | ((u64)(vcpu->regs[VCPU_REGS_RDX] & -1u) << 32);
1709 if (vmx_set_msr(vcpu, ecx, data) != 0) {
1710 vmx_inject_gp(vcpu, 0);
1714 skip_emulated_instruction(vcpu);
1718 static void post_kvm_run_save(struct kvm_vcpu *vcpu,
1719 struct kvm_run *kvm_run)
1721 kvm_run->if_flag = (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) != 0;
1722 kvm_run->cr8 = vcpu->cr8;
1723 kvm_run->apic_base = vcpu->apic_base;
1724 kvm_run->ready_for_interrupt_injection = (vcpu->interrupt_window_open &&
1725 vcpu->irq_summary == 0);
1728 static int handle_interrupt_window(struct kvm_vcpu *vcpu,
1729 struct kvm_run *kvm_run)
1732 * If the user space waits to inject interrupts, exit as soon as
1735 if (kvm_run->request_interrupt_window &&
1736 !vcpu->irq_summary) {
1737 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
1738 ++vcpu->stat.irq_window_exits;
1744 static int handle_halt(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1746 skip_emulated_instruction(vcpu);
1747 if (vcpu->irq_summary)
1750 kvm_run->exit_reason = KVM_EXIT_HLT;
1751 ++vcpu->stat.halt_exits;
1755 static int handle_vmcall(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1757 skip_emulated_instruction(vcpu);
1758 return kvm_hypercall(vcpu, kvm_run);
1762 * The exit handlers return 1 if the exit was handled fully and guest execution
1763 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
1764 * to be done to userspace and return 0.
1766 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu,
1767 struct kvm_run *kvm_run) = {
1768 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
1769 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
1770 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
1771 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
1772 [EXIT_REASON_CR_ACCESS] = handle_cr,
1773 [EXIT_REASON_DR_ACCESS] = handle_dr,
1774 [EXIT_REASON_CPUID] = handle_cpuid,
1775 [EXIT_REASON_MSR_READ] = handle_rdmsr,
1776 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
1777 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
1778 [EXIT_REASON_HLT] = handle_halt,
1779 [EXIT_REASON_VMCALL] = handle_vmcall,
1782 static const int kvm_vmx_max_exit_handlers =
1783 sizeof(kvm_vmx_exit_handlers) / sizeof(*kvm_vmx_exit_handlers);
1786 * The guest has exited. See if we can fix it or if we need userspace
1789 static int kvm_handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
1791 u32 vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
1792 u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
1794 if ( (vectoring_info & VECTORING_INFO_VALID_MASK) &&
1795 exit_reason != EXIT_REASON_EXCEPTION_NMI )
1796 printk(KERN_WARNING "%s: unexpected, valid vectoring info and "
1797 "exit reason is 0x%x\n", __FUNCTION__, exit_reason);
1798 if (exit_reason < kvm_vmx_max_exit_handlers
1799 && kvm_vmx_exit_handlers[exit_reason])
1800 return kvm_vmx_exit_handlers[exit_reason](vcpu, kvm_run);
1802 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
1803 kvm_run->hw.hardware_exit_reason = exit_reason;
1809 * Check if userspace requested an interrupt window, and that the
1810 * interrupt window is open.
1812 * No need to exit to userspace if we already have an interrupt queued.
1814 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu,
1815 struct kvm_run *kvm_run)
1817 return (!vcpu->irq_summary &&
1818 kvm_run->request_interrupt_window &&
1819 vcpu->interrupt_window_open &&
1820 (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF));
1823 static int vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1826 u16 fs_sel, gs_sel, ldt_sel;
1827 int fs_gs_ldt_reload_needed;
1832 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1833 * allow segment selectors with cpl > 0 or ti == 1.
1835 ldt_sel = read_ldt();
1836 fs_gs_ldt_reload_needed = ldt_sel;
1839 vmcs_write16(HOST_FS_SELECTOR, fs_sel);
1841 vmcs_write16(HOST_FS_SELECTOR, 0);
1842 fs_gs_ldt_reload_needed = 1;
1846 vmcs_write16(HOST_GS_SELECTOR, gs_sel);
1848 vmcs_write16(HOST_GS_SELECTOR, 0);
1849 fs_gs_ldt_reload_needed = 1;
1852 #ifdef CONFIG_X86_64
1853 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1854 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1856 vmcs_writel(HOST_FS_BASE, segment_base(fs_sel));
1857 vmcs_writel(HOST_GS_BASE, segment_base(gs_sel));
1860 if (!vcpu->mmio_read_completed)
1861 do_interrupt_requests(vcpu, kvm_run);
1863 if (vcpu->guest_debug.enabled)
1864 kvm_guest_debug_pre(vcpu);
1866 #ifdef CONFIG_X86_64
1867 if (is_long_mode(vcpu)) {
1868 save_msrs(vcpu->host_msrs + msr_offset_kernel_gs_base, 1);
1869 load_msrs(vcpu->guest_msrs, NR_BAD_MSRS);
1874 kvm_load_guest_fpu(vcpu);
1877 * Loading guest fpu may have cleared host cr0.ts
1879 vmcs_writel(HOST_CR0, read_cr0());
1882 /* Store host registers */
1884 #ifdef CONFIG_X86_64
1885 "push %%rax; push %%rbx; push %%rdx;"
1886 "push %%rsi; push %%rdi; push %%rbp;"
1887 "push %%r8; push %%r9; push %%r10; push %%r11;"
1888 "push %%r12; push %%r13; push %%r14; push %%r15;"
1890 ASM_VMX_VMWRITE_RSP_RDX "\n\t"
1892 "pusha; push %%ecx \n\t"
1893 ASM_VMX_VMWRITE_RSP_RDX "\n\t"
1895 /* Check if vmlaunch of vmresume is needed */
1897 /* Load guest registers. Don't clobber flags. */
1898 #ifdef CONFIG_X86_64
1899 "mov %c[cr2](%3), %%rax \n\t"
1900 "mov %%rax, %%cr2 \n\t"
1901 "mov %c[rax](%3), %%rax \n\t"
1902 "mov %c[rbx](%3), %%rbx \n\t"
1903 "mov %c[rdx](%3), %%rdx \n\t"
1904 "mov %c[rsi](%3), %%rsi \n\t"
1905 "mov %c[rdi](%3), %%rdi \n\t"
1906 "mov %c[rbp](%3), %%rbp \n\t"
1907 "mov %c[r8](%3), %%r8 \n\t"
1908 "mov %c[r9](%3), %%r9 \n\t"
1909 "mov %c[r10](%3), %%r10 \n\t"
1910 "mov %c[r11](%3), %%r11 \n\t"
1911 "mov %c[r12](%3), %%r12 \n\t"
1912 "mov %c[r13](%3), %%r13 \n\t"
1913 "mov %c[r14](%3), %%r14 \n\t"
1914 "mov %c[r15](%3), %%r15 \n\t"
1915 "mov %c[rcx](%3), %%rcx \n\t" /* kills %3 (rcx) */
1917 "mov %c[cr2](%3), %%eax \n\t"
1918 "mov %%eax, %%cr2 \n\t"
1919 "mov %c[rax](%3), %%eax \n\t"
1920 "mov %c[rbx](%3), %%ebx \n\t"
1921 "mov %c[rdx](%3), %%edx \n\t"
1922 "mov %c[rsi](%3), %%esi \n\t"
1923 "mov %c[rdi](%3), %%edi \n\t"
1924 "mov %c[rbp](%3), %%ebp \n\t"
1925 "mov %c[rcx](%3), %%ecx \n\t" /* kills %3 (ecx) */
1927 /* Enter guest mode */
1929 ASM_VMX_VMLAUNCH "\n\t"
1930 "jmp kvm_vmx_return \n\t"
1931 "launched: " ASM_VMX_VMRESUME "\n\t"
1932 ".globl kvm_vmx_return \n\t"
1934 /* Save guest registers, load host registers, keep flags */
1935 #ifdef CONFIG_X86_64
1936 "xchg %3, (%%rsp) \n\t"
1937 "mov %%rax, %c[rax](%3) \n\t"
1938 "mov %%rbx, %c[rbx](%3) \n\t"
1939 "pushq (%%rsp); popq %c[rcx](%3) \n\t"
1940 "mov %%rdx, %c[rdx](%3) \n\t"
1941 "mov %%rsi, %c[rsi](%3) \n\t"
1942 "mov %%rdi, %c[rdi](%3) \n\t"
1943 "mov %%rbp, %c[rbp](%3) \n\t"
1944 "mov %%r8, %c[r8](%3) \n\t"
1945 "mov %%r9, %c[r9](%3) \n\t"
1946 "mov %%r10, %c[r10](%3) \n\t"
1947 "mov %%r11, %c[r11](%3) \n\t"
1948 "mov %%r12, %c[r12](%3) \n\t"
1949 "mov %%r13, %c[r13](%3) \n\t"
1950 "mov %%r14, %c[r14](%3) \n\t"
1951 "mov %%r15, %c[r15](%3) \n\t"
1952 "mov %%cr2, %%rax \n\t"
1953 "mov %%rax, %c[cr2](%3) \n\t"
1954 "mov (%%rsp), %3 \n\t"
1956 "pop %%rcx; pop %%r15; pop %%r14; pop %%r13; pop %%r12;"
1957 "pop %%r11; pop %%r10; pop %%r9; pop %%r8;"
1958 "pop %%rbp; pop %%rdi; pop %%rsi;"
1959 "pop %%rdx; pop %%rbx; pop %%rax \n\t"
1961 "xchg %3, (%%esp) \n\t"
1962 "mov %%eax, %c[rax](%3) \n\t"
1963 "mov %%ebx, %c[rbx](%3) \n\t"
1964 "pushl (%%esp); popl %c[rcx](%3) \n\t"
1965 "mov %%edx, %c[rdx](%3) \n\t"
1966 "mov %%esi, %c[rsi](%3) \n\t"
1967 "mov %%edi, %c[rdi](%3) \n\t"
1968 "mov %%ebp, %c[rbp](%3) \n\t"
1969 "mov %%cr2, %%eax \n\t"
1970 "mov %%eax, %c[cr2](%3) \n\t"
1971 "mov (%%esp), %3 \n\t"
1973 "pop %%ecx; popa \n\t"
1978 : "r"(vcpu->launched), "d"((unsigned long)HOST_RSP),
1980 [rax]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RAX])),
1981 [rbx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RBX])),
1982 [rcx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RCX])),
1983 [rdx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RDX])),
1984 [rsi]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RSI])),
1985 [rdi]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RDI])),
1986 [rbp]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RBP])),
1987 #ifdef CONFIG_X86_64
1988 [r8 ]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R8 ])),
1989 [r9 ]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R9 ])),
1990 [r10]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R10])),
1991 [r11]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R11])),
1992 [r12]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R12])),
1993 [r13]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R13])),
1994 [r14]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R14])),
1995 [r15]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R15])),
1997 [cr2]"i"(offsetof(struct kvm_vcpu, cr2))
2002 vcpu->interrupt_window_open = (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0;
2004 asm ("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
2006 if (unlikely(fail)) {
2007 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2008 kvm_run->fail_entry.hardware_entry_failure_reason
2009 = vmcs_read32(VM_INSTRUCTION_ERROR);
2014 * Profile KVM exit RIPs:
2016 if (unlikely(prof_on == KVM_PROFILING))
2017 profile_hit(KVM_PROFILING, (void *)vmcs_readl(GUEST_RIP));
2020 r = kvm_handle_exit(kvm_run, vcpu);
2022 /* Give scheduler a change to reschedule. */
2023 if (signal_pending(current)) {
2025 kvm_run->exit_reason = KVM_EXIT_INTR;
2026 ++vcpu->stat.signal_exits;
2030 if (dm_request_for_irq_injection(vcpu, kvm_run)) {
2032 kvm_run->exit_reason = KVM_EXIT_INTR;
2033 ++vcpu->stat.request_irq_exits;
2036 if (!need_resched()) {
2037 ++vcpu->stat.light_exits;
2043 if (fs_gs_ldt_reload_needed) {
2047 * If we have to reload gs, we must take care to
2048 * preserve our gs base.
2050 local_irq_disable();
2052 #ifdef CONFIG_X86_64
2053 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
2059 #ifdef CONFIG_X86_64
2060 if (is_long_mode(vcpu)) {
2061 save_msrs(vcpu->guest_msrs, NR_BAD_MSRS);
2062 load_msrs(vcpu->host_msrs, NR_BAD_MSRS);
2071 post_kvm_run_save(vcpu, kvm_run);
2075 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
2077 vmcs_writel(GUEST_CR3, vmcs_readl(GUEST_CR3));
2080 static void vmx_inject_page_fault(struct kvm_vcpu *vcpu,
2084 u32 vect_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
2086 ++vcpu->stat.pf_guest;
2088 if (is_page_fault(vect_info)) {
2089 printk(KERN_DEBUG "inject_page_fault: "
2090 "double fault 0x%lx @ 0x%lx\n",
2091 addr, vmcs_readl(GUEST_RIP));
2092 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, 0);
2093 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2095 INTR_TYPE_EXCEPTION |
2096 INTR_INFO_DELIEVER_CODE_MASK |
2097 INTR_INFO_VALID_MASK);
2101 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, err_code);
2102 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2104 INTR_TYPE_EXCEPTION |
2105 INTR_INFO_DELIEVER_CODE_MASK |
2106 INTR_INFO_VALID_MASK);
2110 static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
2113 on_each_cpu(__vcpu_clear, vcpu, 0, 1);
2114 free_vmcs(vcpu->vmcs);
2119 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
2121 vmx_free_vmcs(vcpu);
2124 static int vmx_create_vcpu(struct kvm_vcpu *vcpu)
2128 vcpu->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
2129 if (!vcpu->guest_msrs)
2132 vcpu->host_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
2133 if (!vcpu->host_msrs)
2134 goto out_free_guest_msrs;
2136 vmcs = alloc_vmcs();
2143 vcpu->fpu_active = 1;
2148 kfree(vcpu->host_msrs);
2149 vcpu->host_msrs = NULL;
2151 out_free_guest_msrs:
2152 kfree(vcpu->guest_msrs);
2153 vcpu->guest_msrs = NULL;
2158 static struct kvm_arch_ops vmx_arch_ops = {
2159 .cpu_has_kvm_support = cpu_has_kvm_support,
2160 .disabled_by_bios = vmx_disabled_by_bios,
2161 .hardware_setup = hardware_setup,
2162 .hardware_unsetup = hardware_unsetup,
2163 .hardware_enable = hardware_enable,
2164 .hardware_disable = hardware_disable,
2166 .vcpu_create = vmx_create_vcpu,
2167 .vcpu_free = vmx_free_vcpu,
2169 .vcpu_load = vmx_vcpu_load,
2170 .vcpu_put = vmx_vcpu_put,
2171 .vcpu_decache = vmx_vcpu_decache,
2173 .set_guest_debug = set_guest_debug,
2174 .get_msr = vmx_get_msr,
2175 .set_msr = vmx_set_msr,
2176 .get_segment_base = vmx_get_segment_base,
2177 .get_segment = vmx_get_segment,
2178 .set_segment = vmx_set_segment,
2179 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
2180 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
2181 .set_cr0 = vmx_set_cr0,
2182 .set_cr3 = vmx_set_cr3,
2183 .set_cr4 = vmx_set_cr4,
2184 #ifdef CONFIG_X86_64
2185 .set_efer = vmx_set_efer,
2187 .get_idt = vmx_get_idt,
2188 .set_idt = vmx_set_idt,
2189 .get_gdt = vmx_get_gdt,
2190 .set_gdt = vmx_set_gdt,
2191 .cache_regs = vcpu_load_rsp_rip,
2192 .decache_regs = vcpu_put_rsp_rip,
2193 .get_rflags = vmx_get_rflags,
2194 .set_rflags = vmx_set_rflags,
2196 .tlb_flush = vmx_flush_tlb,
2197 .inject_page_fault = vmx_inject_page_fault,
2199 .inject_gp = vmx_inject_gp,
2201 .run = vmx_vcpu_run,
2202 .skip_emulated_instruction = skip_emulated_instruction,
2203 .vcpu_setup = vmx_vcpu_setup,
2204 .patch_hypercall = vmx_patch_hypercall,
2207 static int __init vmx_init(void)
2212 vmx_io_bitmap_a = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
2213 if (!vmx_io_bitmap_a)
2216 vmx_io_bitmap_b = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
2217 if (!vmx_io_bitmap_b) {
2223 * Allow direct access to the PC debug port (it is often used for I/O
2224 * delays, but the vmexits simply slow things down).
2226 iova = kmap(vmx_io_bitmap_a);
2227 memset(iova, 0xff, PAGE_SIZE);
2228 clear_bit(0x80, iova);
2231 iova = kmap(vmx_io_bitmap_b);
2232 memset(iova, 0xff, PAGE_SIZE);
2235 r = kvm_init_arch(&vmx_arch_ops, THIS_MODULE);
2242 __free_page(vmx_io_bitmap_b);
2244 __free_page(vmx_io_bitmap_a);
2248 static void __exit vmx_exit(void)
2250 __free_page(vmx_io_bitmap_b);
2251 __free_page(vmx_io_bitmap_a);
2256 module_init(vmx_init)
2257 module_exit(vmx_exit)