2 Driver for M88RS2000 demodulator and tuner
4 Copyright (C) 2012 Malcolm Priestley (tvboxspy@gmail.com)
7 Include various calculation code from DS3000 driver.
8 Copyright (C) 2009 Konstantin Dimitrov.
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2 of the License, or
13 (at your option) any later version.
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software
22 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 #include <linux/init.h>
26 #include <linux/module.h>
27 #include <linux/device.h>
28 #include <linux/jiffies.h>
29 #include <linux/string.h>
30 #include <linux/slab.h>
31 #include <linux/types.h>
34 #include "dvb_frontend.h"
35 #include "m88rs2000.h"
37 struct m88rs2000_state {
38 struct i2c_adapter *i2c;
39 const struct m88rs2000_config *config;
40 struct dvb_frontend frontend;
44 fe_code_rate_t fec_inner;
49 static int m88rs2000_debug;
51 module_param_named(debug, m88rs2000_debug, int, 0644);
52 MODULE_PARM_DESC(debug, "set debugging level (1=info (or-able)).");
54 #define dprintk(level, args...) do { \
55 if (level & m88rs2000_debug) \
56 printk(KERN_DEBUG "m88rs2000-fe: " args); \
59 #define deb_info(args...) dprintk(0x01, args)
60 #define info(format, arg...) \
61 printk(KERN_INFO "m88rs2000-fe: " format "\n" , ## arg)
63 static int m88rs2000_writereg(struct m88rs2000_state *state, u8 tuner,
67 u8 addr = (tuner == 0) ? state->config->tuner_addr :
68 state->config->demod_addr;
69 u8 buf[] = { reg, data };
70 struct i2c_msg msg = {
77 ret = i2c_transfer(state->i2c, &msg, 1);
80 deb_info("%s: writereg error (reg == 0x%02x, val == 0x%02x, "
81 "ret == %i)\n", __func__, reg, data, ret);
83 return (ret != 1) ? -EREMOTEIO : 0;
86 static int m88rs2000_demod_write(struct m88rs2000_state *state, u8 reg, u8 data)
88 return m88rs2000_writereg(state, 1, reg, data);
91 static int m88rs2000_tuner_write(struct m88rs2000_state *state, u8 reg, u8 data)
93 m88rs2000_demod_write(state, 0x81, 0x84);
95 return m88rs2000_writereg(state, 0, reg, data);
99 static int m88rs2000_write(struct dvb_frontend *fe, const u8 buf[], int len)
101 struct m88rs2000_state *state = fe->demodulator_priv;
106 return m88rs2000_writereg(state, 1, buf[0], buf[1]);
109 static u8 m88rs2000_readreg(struct m88rs2000_state *state, u8 tuner, u8 reg)
114 u8 addr = (tuner == 0) ? state->config->tuner_addr :
115 state->config->demod_addr;
116 struct i2c_msg msg[] = {
130 ret = i2c_transfer(state->i2c, msg, 2);
133 deb_info("%s: readreg error (reg == 0x%02x, ret == %i)\n",
139 static u8 m88rs2000_demod_read(struct m88rs2000_state *state, u8 reg)
141 return m88rs2000_readreg(state, 1, reg);
144 static u8 m88rs2000_tuner_read(struct m88rs2000_state *state, u8 reg)
146 m88rs2000_demod_write(state, 0x81, 0x85);
148 return m88rs2000_readreg(state, 0, reg);
151 static int m88rs2000_set_symbolrate(struct dvb_frontend *fe, u32 srate)
153 struct m88rs2000_state *state = fe->demodulator_priv;
158 if ((srate < 1000000) || (srate > 45000000))
166 b[0] = (u8) (temp >> 16) & 0xff;
167 b[1] = (u8) (temp >> 8) & 0xff;
168 b[2] = (u8) temp & 0xff;
169 ret = m88rs2000_demod_write(state, 0x93, b[2]);
170 ret |= m88rs2000_demod_write(state, 0x94, b[1]);
171 ret |= m88rs2000_demod_write(state, 0x95, b[0]);
173 deb_info("m88rs2000: m88rs2000_set_symbolrate\n");
177 static int m88rs2000_send_diseqc_msg(struct dvb_frontend *fe,
178 struct dvb_diseqc_master_cmd *m)
180 struct m88rs2000_state *state = fe->demodulator_priv;
184 deb_info("%s\n", __func__);
185 m88rs2000_demod_write(state, 0x9a, 0x30);
186 reg = m88rs2000_demod_read(state, 0xb2);
188 m88rs2000_demod_write(state, 0xb2, reg);
189 for (i = 0; i < m->msg_len; i++)
190 m88rs2000_demod_write(state, 0xb3 + i, m->msg[i]);
192 reg = m88rs2000_demod_read(state, 0xb1);
194 reg |= ((m->msg_len - 1) << 3) | 0x07;
196 m88rs2000_demod_write(state, 0xb1, reg);
198 for (i = 0; i < 15; i++) {
199 if ((m88rs2000_demod_read(state, 0xb1) & 0x40) == 0x0)
204 reg = m88rs2000_demod_read(state, 0xb1);
205 if ((reg & 0x40) > 0x0) {
208 m88rs2000_demod_write(state, 0xb1, reg);
211 reg = m88rs2000_demod_read(state, 0xb2);
214 m88rs2000_demod_write(state, 0xb2, reg);
215 m88rs2000_demod_write(state, 0x9a, 0xb0);
221 static int m88rs2000_send_diseqc_burst(struct dvb_frontend *fe,
222 fe_sec_mini_cmd_t burst)
224 struct m88rs2000_state *state = fe->demodulator_priv;
226 deb_info("%s\n", __func__);
227 m88rs2000_demod_write(state, 0x9a, 0x30);
229 reg0 = m88rs2000_demod_read(state, 0xb1);
230 reg1 = m88rs2000_demod_read(state, 0xb2);
231 /* TODO complete this section */
232 m88rs2000_demod_write(state, 0xb2, reg1);
233 m88rs2000_demod_write(state, 0xb1, reg0);
234 m88rs2000_demod_write(state, 0x9a, 0xb0);
239 static int m88rs2000_set_tone(struct dvb_frontend *fe, fe_sec_tone_mode_t tone)
241 struct m88rs2000_state *state = fe->demodulator_priv;
243 m88rs2000_demod_write(state, 0x9a, 0x30);
244 reg0 = m88rs2000_demod_read(state, 0xb1);
245 reg1 = m88rs2000_demod_read(state, 0xb2);
260 m88rs2000_demod_write(state, 0xb2, reg1);
261 m88rs2000_demod_write(state, 0xb1, reg0);
262 m88rs2000_demod_write(state, 0x9a, 0xb0);
272 struct inittab m88rs2000_setup[] = {
273 {DEMOD_WRITE, 0x9a, 0x30},
274 {DEMOD_WRITE, 0x00, 0x01},
275 {WRITE_DELAY, 0x19, 0x00},
276 {DEMOD_WRITE, 0x00, 0x00},
277 {DEMOD_WRITE, 0x9a, 0xb0},
278 {DEMOD_WRITE, 0x81, 0xc1},
279 {TUNER_WRITE, 0x42, 0x73},
280 {TUNER_WRITE, 0x05, 0x07},
281 {TUNER_WRITE, 0x20, 0x27},
282 {TUNER_WRITE, 0x07, 0x02},
283 {TUNER_WRITE, 0x11, 0xff},
284 {TUNER_WRITE, 0x60, 0xf9},
285 {TUNER_WRITE, 0x08, 0x01},
286 {TUNER_WRITE, 0x00, 0x41},
287 {DEMOD_WRITE, 0x81, 0x81},
288 {DEMOD_WRITE, 0x86, 0xc6},
289 {DEMOD_WRITE, 0x9a, 0x30},
290 {DEMOD_WRITE, 0xf0, 0x22},
291 {DEMOD_WRITE, 0xf1, 0xbf},
292 {DEMOD_WRITE, 0xb0, 0x45},
293 {DEMOD_WRITE, 0xb2, 0x01}, /* set voltage pin always set 1*/
294 {DEMOD_WRITE, 0x9a, 0xb0},
298 struct inittab m88rs2000_shutdown[] = {
299 {DEMOD_WRITE, 0x9a, 0x30},
300 {DEMOD_WRITE, 0xb0, 0x00},
301 {DEMOD_WRITE, 0xf1, 0x89},
302 {DEMOD_WRITE, 0x00, 0x01},
303 {DEMOD_WRITE, 0x9a, 0xb0},
304 {TUNER_WRITE, 0x00, 0x40},
305 {DEMOD_WRITE, 0x81, 0x81},
309 struct inittab tuner_reset[] = {
310 {TUNER_WRITE, 0x42, 0x73},
311 {TUNER_WRITE, 0x05, 0x07},
312 {TUNER_WRITE, 0x20, 0x27},
313 {TUNER_WRITE, 0x07, 0x02},
314 {TUNER_WRITE, 0x11, 0xff},
315 {TUNER_WRITE, 0x60, 0xf9},
316 {TUNER_WRITE, 0x08, 0x01},
317 {TUNER_WRITE, 0x00, 0x41},
321 struct inittab fe_reset[] = {
322 {DEMOD_WRITE, 0x00, 0x01},
323 {DEMOD_WRITE, 0xf1, 0xbf},
324 {DEMOD_WRITE, 0x00, 0x01},
325 {DEMOD_WRITE, 0x20, 0x81},
326 {DEMOD_WRITE, 0x21, 0x80},
327 {DEMOD_WRITE, 0x10, 0x33},
328 {DEMOD_WRITE, 0x11, 0x44},
329 {DEMOD_WRITE, 0x12, 0x07},
330 {DEMOD_WRITE, 0x18, 0x20},
331 {DEMOD_WRITE, 0x28, 0x04},
332 {DEMOD_WRITE, 0x29, 0x8e},
333 {DEMOD_WRITE, 0x3b, 0xff},
334 {DEMOD_WRITE, 0x32, 0x10},
335 {DEMOD_WRITE, 0x33, 0x02},
336 {DEMOD_WRITE, 0x34, 0x30},
337 {DEMOD_WRITE, 0x35, 0xff},
338 {DEMOD_WRITE, 0x38, 0x50},
339 {DEMOD_WRITE, 0x39, 0x68},
340 {DEMOD_WRITE, 0x3c, 0x7f},
341 {DEMOD_WRITE, 0x3d, 0x0f},
342 {DEMOD_WRITE, 0x45, 0x20},
343 {DEMOD_WRITE, 0x46, 0x24},
344 {DEMOD_WRITE, 0x47, 0x7c},
345 {DEMOD_WRITE, 0x48, 0x16},
346 {DEMOD_WRITE, 0x49, 0x04},
347 {DEMOD_WRITE, 0x4a, 0x01},
348 {DEMOD_WRITE, 0x4b, 0x78},
349 {DEMOD_WRITE, 0X4d, 0xd2},
350 {DEMOD_WRITE, 0x4e, 0x6d},
351 {DEMOD_WRITE, 0x50, 0x30},
352 {DEMOD_WRITE, 0x51, 0x30},
353 {DEMOD_WRITE, 0x54, 0x7b},
354 {DEMOD_WRITE, 0x56, 0x09},
355 {DEMOD_WRITE, 0x58, 0x59},
356 {DEMOD_WRITE, 0x59, 0x37},
357 {DEMOD_WRITE, 0x63, 0xfa},
361 struct inittab fe_trigger[] = {
362 {DEMOD_WRITE, 0x97, 0x04},
363 {DEMOD_WRITE, 0x99, 0x77},
364 {DEMOD_WRITE, 0x9b, 0x64},
365 {DEMOD_WRITE, 0x9e, 0x00},
366 {DEMOD_WRITE, 0x9f, 0xf8},
367 {DEMOD_WRITE, 0xa0, 0x20},
368 {DEMOD_WRITE, 0xa1, 0xe0},
369 {DEMOD_WRITE, 0xa3, 0x38},
370 {DEMOD_WRITE, 0x98, 0xff},
371 {DEMOD_WRITE, 0xc0, 0x0f},
372 {DEMOD_WRITE, 0x89, 0x01},
373 {DEMOD_WRITE, 0x00, 0x00},
374 {WRITE_DELAY, 0x0a, 0x00},
375 {DEMOD_WRITE, 0x00, 0x01},
376 {DEMOD_WRITE, 0x00, 0x00},
377 {DEMOD_WRITE, 0x9a, 0xb0},
381 static int m88rs2000_tab_set(struct m88rs2000_state *state,
389 for (i = 0; i < 255; i++) {
390 switch (tab[i].cmd) {
392 ret = m88rs2000_demod_write(state, tab[i].reg,
396 ret = m88rs2000_tuner_write(state, tab[i].reg,
404 if (tab[i].reg == 0xaa && tab[i].val == 0xff)
417 static int m88rs2000_set_voltage(struct dvb_frontend *fe, fe_sec_voltage_t volt)
419 struct m88rs2000_state *state = fe->demodulator_priv;
422 data = m88rs2000_demod_read(state, 0xb2);
423 data |= 0x03; /* bit0 V/H, bit1 off/on */
433 case SEC_VOLTAGE_OFF:
437 m88rs2000_demod_write(state, 0xb2, data);
442 static int m88rs2000_startup(struct m88rs2000_state *state)
447 reg = m88rs2000_tuner_read(state, 0x00);
448 if ((reg & 0x40) == 0)
454 static int m88rs2000_init(struct dvb_frontend *fe)
456 struct m88rs2000_state *state = fe->demodulator_priv;
459 deb_info("m88rs2000: init chip\n");
460 /* Setup frontend from shutdown/cold */
461 ret = m88rs2000_tab_set(state, m88rs2000_setup);
466 static int m88rs2000_sleep(struct dvb_frontend *fe)
468 struct m88rs2000_state *state = fe->demodulator_priv;
470 /* Shutdown the frondend */
471 ret = m88rs2000_tab_set(state, m88rs2000_shutdown);
475 static int m88rs2000_read_status(struct dvb_frontend *fe, fe_status_t *status)
477 struct m88rs2000_state *state = fe->demodulator_priv;
478 u8 reg = m88rs2000_demod_read(state, 0x8c);
482 if ((reg & 0x7) == 0x7) {
483 *status = FE_HAS_CARRIER | FE_HAS_SIGNAL | FE_HAS_VITERBI
485 if (state->config->set_ts_params)
486 state->config->set_ts_params(fe, CALL_IS_READ);
491 /* Extact code for these unknown but lmedm04 driver uses interupt callbacks */
493 static int m88rs2000_read_ber(struct dvb_frontend *fe, u32 *ber)
495 deb_info("m88rs2000_read_ber %d\n", *ber);
500 static int m88rs2000_read_signal_strength(struct dvb_frontend *fe,
507 static int m88rs2000_read_snr(struct dvb_frontend *fe, u16 *snr)
509 deb_info("m88rs2000_read_snr %d\n", *snr);
514 static int m88rs2000_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
516 deb_info("m88rs2000_read_ber %d\n", *ucblocks);
521 static int m88rs2000_tuner_gate_ctrl(struct m88rs2000_state *state, u8 offset)
524 ret = m88rs2000_tuner_write(state, 0x51, 0x1f - offset);
525 ret |= m88rs2000_tuner_write(state, 0x51, 0x1f);
526 ret |= m88rs2000_tuner_write(state, 0x50, offset);
527 ret |= m88rs2000_tuner_write(state, 0x50, 0x00);
532 static int m88rs2000_set_tuner_rf(struct dvb_frontend *fe)
534 struct m88rs2000_state *state = fe->demodulator_priv;
536 reg = m88rs2000_tuner_read(state, 0x3d);
540 else if (reg == 0x16)
545 m88rs2000_tuner_write(state, 0x60, reg);
546 reg = m88rs2000_tuner_gate_ctrl(state, 0x08);
548 if (fe->ops.i2c_gate_ctrl)
549 fe->ops.i2c_gate_ctrl(fe, 0);
553 static int m88rs2000_set_tuner(struct dvb_frontend *fe, u16 *offset)
555 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
556 struct m88rs2000_state *state = fe->demodulator_priv;
558 u32 frequency = c->frequency;
561 u32 symbol_rate = (c->symbol_rate / 1000);
563 u16 value, ndiv, lpf_coeff;
564 u8 lpf_mxdiv, mlpf_max, mlpf_min, nlpf;
565 u8 lo = 0x01, div4 = 0x0;
568 ret = m88rs2000_tab_set(state, tuner_reset);
570 /* Calculate frequency divider */
571 if (frequency < 1060000) {
574 ndiv = (frequency * 14 * 4) / FE_CRYSTAL_KHZ;
576 ndiv = (frequency * 14 * 2) / FE_CRYSTAL_KHZ;
577 ndiv = ndiv + ndiv % 2;
580 ret = m88rs2000_tuner_write(state, 0x10, 0x80 | lo);
582 /* Set frequency divider */
583 ret |= m88rs2000_tuner_write(state, 0x01, (ndiv >> 8) & 0xf);
584 ret |= m88rs2000_tuner_write(state, 0x02, ndiv & 0xff);
586 ret |= m88rs2000_tuner_write(state, 0x03, 0x06);
587 ret |= m88rs2000_tuner_gate_ctrl(state, 0x10);
591 /* Tuner Frequency Range */
592 ret = m88rs2000_tuner_write(state, 0x10, lo);
594 ret |= m88rs2000_tuner_gate_ctrl(state, 0x08);
597 ret |= m88rs2000_set_tuner_rf(fe);
599 gdiv28 = (FE_CRYSTAL_KHZ / 1000 * 1694 + 500) / 1000;
600 ret |= m88rs2000_tuner_write(state, 0x04, gdiv28 & 0xff);
601 ret |= m88rs2000_tuner_gate_ctrl(state, 0x04);
605 value = m88rs2000_tuner_read(state, 0x26);
607 f3db = (symbol_rate * 135) / 200 + 2000;
608 f3db += FREQ_OFFSET_LOW_SYM_RATE;
614 gdiv28 = gdiv28 * 207 / (value * 2 + 151);
615 mlpf_max = gdiv28 * 135 / 100;
616 mlpf_min = gdiv28 * 78 / 100;
622 nlpf = (f3db * gdiv28 * 2 / lpf_coeff /
623 (FE_CRYSTAL_KHZ / 1000) + 1) / 2;
629 lpf_mxdiv = (nlpf * (FE_CRYSTAL_KHZ / 1000)
630 * lpf_coeff * 2 / f3db + 1) / 2;
632 if (lpf_mxdiv < mlpf_min) {
634 lpf_mxdiv = (nlpf * (FE_CRYSTAL_KHZ / 1000)
635 * lpf_coeff * 2 / f3db + 1) / 2;
638 if (lpf_mxdiv > mlpf_max)
639 lpf_mxdiv = mlpf_max;
641 ret = m88rs2000_tuner_write(state, 0x04, lpf_mxdiv);
642 ret |= m88rs2000_tuner_write(state, 0x06, nlpf);
644 ret |= m88rs2000_tuner_gate_ctrl(state, 0x04);
646 ret |= m88rs2000_tuner_gate_ctrl(state, 0x01);
649 /* calculate offset assuming 96000kHz*/
650 offset_khz = (ndiv - ndiv % 2 + 1024) * FE_CRYSTAL_KHZ
651 / 14 / (div4 + 1) / 2;
653 offset_khz -= frequency;
658 tmp = (2 * tmp + 96000) / (2 * 96000);
662 *offset = tmp & 0xffff;
664 if (fe->ops.i2c_gate_ctrl)
665 fe->ops.i2c_gate_ctrl(fe, 0);
667 return (ret < 0) ? -EINVAL : 0;
670 static int m88rs2000_set_fec(struct m88rs2000_state *state,
675 /* This is not confirmed kept for reference */
695 m88rs2000_demod_write(state, 0x76, fec_set);
701 static fe_code_rate_t m88rs2000_get_fec(struct m88rs2000_state *state)
704 m88rs2000_demod_write(state, 0x9a, 0x30);
705 reg = m88rs2000_demod_read(state, 0x76);
706 m88rs2000_demod_write(state, 0x9a, 0xb0);
727 static int m88rs2000_set_frontend(struct dvb_frontend *fe)
729 struct m88rs2000_state *state = fe->demodulator_priv;
730 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
736 state->no_lock_count = 0;
738 if (c->delivery_system != SYS_DVBS) {
739 deb_info("%s: unsupported delivery "
740 "system selected (%d)\n",
741 __func__, c->delivery_system);
746 ret = m88rs2000_set_tuner(fe, &offset);
750 ret = m88rs2000_demod_write(state, 0x9a, 0x30);
751 /* Unknown usually 0xc6 sometimes 0xc1 */
752 reg = m88rs2000_demod_read(state, 0x86);
753 ret |= m88rs2000_demod_write(state, 0x86, reg);
754 /* Offset lower nibble always 0 */
755 ret |= m88rs2000_demod_write(state, 0x9c, (offset >> 8));
756 ret |= m88rs2000_demod_write(state, 0x9d, offset & 0xf0);
760 ret = m88rs2000_tab_set(state, fe_reset);
765 reg = m88rs2000_demod_read(state, 0x70);
766 ret = m88rs2000_demod_write(state, 0x70, reg);
769 ret |= m88rs2000_set_fec(state, c->fec_inner);
770 ret |= m88rs2000_demod_write(state, 0x85, 0x1);
771 ret |= m88rs2000_demod_write(state, 0x8a, 0xbf);
772 ret |= m88rs2000_demod_write(state, 0x8d, 0x1e);
773 ret |= m88rs2000_demod_write(state, 0x90, 0xf1);
774 ret |= m88rs2000_demod_write(state, 0x91, 0x08);
779 /* Set Symbol Rate */
780 ret = m88rs2000_set_symbolrate(fe, c->symbol_rate);
785 ret = m88rs2000_tab_set(state, fe_trigger);
789 for (i = 0; i < 25; i++) {
790 u8 reg = m88rs2000_demod_read(state, 0x8c);
791 if ((reg & 0x7) == 0x7) {
792 status = FE_HAS_LOCK;
795 state->no_lock_count++;
796 if (state->no_lock_count > 15) {
797 reg = m88rs2000_demod_read(state, 0x70);
799 m88rs2000_demod_write(state, 0x70, reg);
800 state->no_lock_count = 0;
802 if (state->no_lock_count == 20)
803 m88rs2000_set_tuner_rf(fe);
807 if (status & FE_HAS_LOCK) {
808 state->fec_inner = m88rs2000_get_fec(state);
809 /* Uknown suspect SNR level */
810 reg = m88rs2000_demod_read(state, 0x65);
813 state->tuner_frequency = c->frequency;
814 state->symbol_rate = c->symbol_rate;
818 static int m88rs2000_get_frontend(struct dvb_frontend *fe)
820 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
821 struct m88rs2000_state *state = fe->demodulator_priv;
822 c->fec_inner = state->fec_inner;
823 c->frequency = state->tuner_frequency;
824 c->symbol_rate = state->symbol_rate;
828 static int m88rs2000_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
830 struct m88rs2000_state *state = fe->demodulator_priv;
833 m88rs2000_demod_write(state, 0x81, 0x84);
835 m88rs2000_demod_write(state, 0x81, 0x81);
840 static void m88rs2000_release(struct dvb_frontend *fe)
842 struct m88rs2000_state *state = fe->demodulator_priv;
846 static struct dvb_frontend_ops m88rs2000_ops = {
847 .delsys = { SYS_DVBS },
849 .name = "M88RS2000 DVB-S",
850 .frequency_min = 950000,
851 .frequency_max = 2150000,
852 .frequency_stepsize = 1000, /* kHz for QPSK frontends */
853 .frequency_tolerance = 5000,
854 .symbol_rate_min = 1000000,
855 .symbol_rate_max = 45000000,
856 .symbol_rate_tolerance = 500, /* ppm */
857 .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
858 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
863 .release = m88rs2000_release,
864 .init = m88rs2000_init,
865 .sleep = m88rs2000_sleep,
866 .write = m88rs2000_write,
867 .i2c_gate_ctrl = m88rs2000_i2c_gate_ctrl,
868 .read_status = m88rs2000_read_status,
869 .read_ber = m88rs2000_read_ber,
870 .read_signal_strength = m88rs2000_read_signal_strength,
871 .read_snr = m88rs2000_read_snr,
872 .read_ucblocks = m88rs2000_read_ucblocks,
873 .diseqc_send_master_cmd = m88rs2000_send_diseqc_msg,
874 .diseqc_send_burst = m88rs2000_send_diseqc_burst,
875 .set_tone = m88rs2000_set_tone,
876 .set_voltage = m88rs2000_set_voltage,
878 .set_frontend = m88rs2000_set_frontend,
879 .get_frontend = m88rs2000_get_frontend,
882 struct dvb_frontend *m88rs2000_attach(const struct m88rs2000_config *config,
883 struct i2c_adapter *i2c)
885 struct m88rs2000_state *state = NULL;
887 /* allocate memory for the internal state */
888 state = kzalloc(sizeof(struct m88rs2000_state), GFP_KERNEL);
892 /* setup the state */
893 state->config = config;
895 state->tuner_frequency = 0;
896 state->symbol_rate = 0;
897 state->fec_inner = 0;
899 if (m88rs2000_startup(state) < 0)
902 /* create dvb_frontend */
903 memcpy(&state->frontend.ops, &m88rs2000_ops,
904 sizeof(struct dvb_frontend_ops));
905 state->frontend.demodulator_priv = state;
906 return &state->frontend;
913 EXPORT_SYMBOL(m88rs2000_attach);
915 MODULE_DESCRIPTION("M88RS2000 DVB-S Demodulator driver");
916 MODULE_AUTHOR("Malcolm Priestley tvboxspy@gmail.com");
917 MODULE_LICENSE("GPL");
918 MODULE_VERSION("1.13");