2 STV0900/0903 Multistandard Broadcast Frontend driver
3 Copyright (C) Manu Abraham <abraham.manu@gmail.com>
5 Copyright (C) ST Microelectronics
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 #include <linux/init.h>
23 #include <linux/kernel.h>
24 #include <linux/module.h>
25 #include <linux/string.h>
26 #include <linux/mutex.h>
28 #include <linux/dvb/frontend.h>
29 #include "dvb_frontend.h"
31 #include "stv6110x.h" /* for demodulator internal modes */
33 #include "stv090x_reg.h"
35 #include "stv090x_priv.h"
37 static unsigned int verbose;
38 module_param(verbose, int, 0644);
40 struct mutex demod_lock;
42 /* DVBS1 and DSS C/N Lookup table */
43 static const struct stv090x_tab stv090x_s1cn_tab[] = {
44 { 0, 8917 }, /* 0.0dB */
45 { 5, 8801 }, /* 0.5dB */
46 { 10, 8667 }, /* 1.0dB */
47 { 15, 8522 }, /* 1.5dB */
48 { 20, 8355 }, /* 2.0dB */
49 { 25, 8175 }, /* 2.5dB */
50 { 30, 7979 }, /* 3.0dB */
51 { 35, 7763 }, /* 3.5dB */
52 { 40, 7530 }, /* 4.0dB */
53 { 45, 7282 }, /* 4.5dB */
54 { 50, 7026 }, /* 5.0dB */
55 { 55, 6781 }, /* 5.5dB */
56 { 60, 6514 }, /* 6.0dB */
57 { 65, 6241 }, /* 6.5dB */
58 { 70, 5965 }, /* 7.0dB */
59 { 75, 5690 }, /* 7.5dB */
60 { 80, 5424 }, /* 8.0dB */
61 { 85, 5161 }, /* 8.5dB */
62 { 90, 4902 }, /* 9.0dB */
63 { 95, 4654 }, /* 9.5dB */
64 { 100, 4417 }, /* 10.0dB */
65 { 105, 4186 }, /* 10.5dB */
66 { 110, 3968 }, /* 11.0dB */
67 { 115, 3757 }, /* 11.5dB */
68 { 120, 3558 }, /* 12.0dB */
69 { 125, 3366 }, /* 12.5dB */
70 { 130, 3185 }, /* 13.0dB */
71 { 135, 3012 }, /* 13.5dB */
72 { 140, 2850 }, /* 14.0dB */
73 { 145, 2698 }, /* 14.5dB */
74 { 150, 2550 }, /* 15.0dB */
75 { 160, 2283 }, /* 16.0dB */
76 { 170, 2042 }, /* 17.0dB */
77 { 180, 1827 }, /* 18.0dB */
78 { 190, 1636 }, /* 19.0dB */
79 { 200, 1466 }, /* 20.0dB */
80 { 210, 1315 }, /* 21.0dB */
81 { 220, 1181 }, /* 22.0dB */
82 { 230, 1064 }, /* 23.0dB */
83 { 240, 960 }, /* 24.0dB */
84 { 250, 869 }, /* 25.0dB */
85 { 260, 792 }, /* 26.0dB */
86 { 270, 724 }, /* 27.0dB */
87 { 280, 665 }, /* 28.0dB */
88 { 290, 616 }, /* 29.0dB */
89 { 300, 573 }, /* 30.0dB */
90 { 310, 537 }, /* 31.0dB */
91 { 320, 507 }, /* 32.0dB */
92 { 330, 483 }, /* 33.0dB */
93 { 400, 398 }, /* 40.0dB */
94 { 450, 381 }, /* 45.0dB */
95 { 500, 377 } /* 50.0dB */
98 /* DVBS2 C/N Lookup table */
99 static const struct stv090x_tab stv090x_s2cn_tab[] = {
100 { -30, 13348 }, /* -3.0dB */
101 { -20, 12640 }, /* -2d.0B */
102 { -10, 11883 }, /* -1.0dB */
103 { 0, 11101 }, /* -0.0dB */
104 { 5, 10718 }, /* 0.5dB */
105 { 10, 10339 }, /* 1.0dB */
106 { 15, 9947 }, /* 1.5dB */
107 { 20, 9552 }, /* 2.0dB */
108 { 25, 9183 }, /* 2.5dB */
109 { 30, 8799 }, /* 3.0dB */
110 { 35, 8422 }, /* 3.5dB */
111 { 40, 8062 }, /* 4.0dB */
112 { 45, 7707 }, /* 4.5dB */
113 { 50, 7353 }, /* 5.0dB */
114 { 55, 7025 }, /* 5.5dB */
115 { 60, 6684 }, /* 6.0dB */
116 { 65, 6331 }, /* 6.5dB */
117 { 70, 6036 }, /* 7.0dB */
118 { 75, 5727 }, /* 7.5dB */
119 { 80, 5437 }, /* 8.0dB */
120 { 85, 5164 }, /* 8.5dB */
121 { 90, 4902 }, /* 9.0dB */
122 { 95, 4653 }, /* 9.5dB */
123 { 100, 4408 }, /* 10.0dB */
124 { 105, 4187 }, /* 10.5dB */
125 { 110, 3961 }, /* 11.0dB */
126 { 115, 3751 }, /* 11.5dB */
127 { 120, 3558 }, /* 12.0dB */
128 { 125, 3368 }, /* 12.5dB */
129 { 130, 3191 }, /* 13.0dB */
130 { 135, 3017 }, /* 13.5dB */
131 { 140, 2862 }, /* 14.0dB */
132 { 145, 2710 }, /* 14.5dB */
133 { 150, 2565 }, /* 15.0dB */
134 { 160, 2300 }, /* 16.0dB */
135 { 170, 2058 }, /* 17.0dB */
136 { 180, 1849 }, /* 18.0dB */
137 { 190, 1663 }, /* 19.0dB */
138 { 200, 1495 }, /* 20.0dB */
139 { 210, 1349 }, /* 21.0dB */
140 { 220, 1222 }, /* 22.0dB */
141 { 230, 1110 }, /* 23.0dB */
142 { 240, 1011 }, /* 24.0dB */
143 { 250, 925 }, /* 25.0dB */
144 { 260, 853 }, /* 26.0dB */
145 { 270, 789 }, /* 27.0dB */
146 { 280, 734 }, /* 28.0dB */
147 { 290, 690 }, /* 29.0dB */
148 { 300, 650 }, /* 30.0dB */
149 { 310, 619 }, /* 31.0dB */
150 { 320, 593 }, /* 32.0dB */
151 { 330, 571 }, /* 33.0dB */
152 { 400, 498 }, /* 40.0dB */
153 { 450, 484 }, /* 45.0dB */
154 { 500, 481 } /* 50.0dB */
157 /* RF level C/N lookup table */
158 static const struct stv090x_tab stv090x_rf_tab[] = {
159 { -5, 0xcaa1 }, /* -5dBm */
160 { -10, 0xc229 }, /* -10dBm */
161 { -15, 0xbb08 }, /* -15dBm */
162 { -20, 0xb4bc }, /* -20dBm */
163 { -25, 0xad5a }, /* -25dBm */
164 { -30, 0xa298 }, /* -30dBm */
165 { -35, 0x98a8 }, /* -35dBm */
166 { -40, 0x8389 }, /* -40dBm */
167 { -45, 0x59be }, /* -45dBm */
168 { -50, 0x3a14 }, /* -50dBm */
169 { -55, 0x2d11 }, /* -55dBm */
170 { -60, 0x210d }, /* -60dBm */
171 { -65, 0xa14f }, /* -65dBm */
172 { -70, 0x07aa } /* -70dBm */
176 static struct stv090x_reg stv0900_initval[] = {
178 { STV090x_OUTCFG, 0x00 },
179 { STV090x_AGCRF1CFG, 0x11 },
180 { STV090x_AGCRF2CFG, 0x13 },
181 { STV090x_TSTTNR2, 0x21 },
182 { STV090x_TSTTNR4, 0x21 },
183 { STV090x_P2_DISTXCTL, 0x22 },
184 { STV090x_P2_F22TX, 0xc0 },
185 { STV090x_P2_F22RX, 0xc0 },
186 { STV090x_P2_DISRXCTL, 0x00 },
187 { STV090x_P2_DMDCFGMD, 0xF9 },
188 { STV090x_P2_DEMOD, 0x08 },
189 { STV090x_P2_DMDCFG3, 0xc4 },
190 { STV090x_P2_CARFREQ, 0xed },
191 { STV090x_P2_LDT, 0xd0 },
192 { STV090x_P2_LDT2, 0xb8 },
193 { STV090x_P2_TMGCFG, 0xd2 },
194 { STV090x_P2_TMGTHRISE, 0x20 },
195 { STV090x_P1_TMGCFG, 0xd2 },
197 { STV090x_P2_TMGTHFALL, 0x00 },
198 { STV090x_P2_FECSPY, 0x88 },
199 { STV090x_P2_FSPYDATA, 0x3a },
200 { STV090x_P2_FBERCPT4, 0x00 },
201 { STV090x_P2_FSPYBER, 0x10 },
202 { STV090x_P2_ERRCTRL1, 0x35 },
203 { STV090x_P2_ERRCTRL2, 0xc1 },
204 { STV090x_P2_CFRICFG, 0xf8 },
205 { STV090x_P2_NOSCFG, 0x1c },
206 { STV090x_P2_CORRELMANT, 0x70 },
207 { STV090x_P2_CORRELABS, 0x88 },
208 { STV090x_P2_AGC2REF, 0x38 },
209 { STV090x_P2_CARCFG, 0xe4 },
210 { STV090x_P2_ACLC, 0x1A },
211 { STV090x_P2_BCLC, 0x09 },
212 { STV090x_P2_CARHDR, 0x08 },
213 { STV090x_P2_KREFTMG, 0xc1 },
214 { STV090x_P2_SFRUPRATIO, 0xf0 },
215 { STV090x_P2_SFRLOWRATIO, 0x70 },
216 { STV090x_P2_SFRSTEP, 0x58 },
217 { STV090x_P2_TMGCFG2, 0x01 },
218 { STV090x_P2_CAR2CFG, 0x26 },
219 { STV090x_P2_BCLC2S2Q, 0x86 },
220 { STV090x_P2_BCLC2S28, 0x86 },
221 { STV090x_P2_SMAPCOEF7, 0x77 },
222 { STV090x_P2_SMAPCOEF6, 0x85 },
223 { STV090x_P2_SMAPCOEF5, 0x77 },
224 { STV090x_P2_TSCFGL, 0x20 },
225 { STV090x_P2_DMDCFG2, 0x3b },
226 { STV090x_P2_MODCODLST0, 0xff },
227 { STV090x_P2_MODCODLST1, 0xff },
228 { STV090x_P2_MODCODLST2, 0xff },
229 { STV090x_P2_MODCODLST3, 0xff },
230 { STV090x_P2_MODCODLST4, 0xff },
231 { STV090x_P2_MODCODLST5, 0xff },
232 { STV090x_P2_MODCODLST6, 0xff },
233 { STV090x_P2_MODCODLST7, 0xcc },
234 { STV090x_P2_MODCODLST8, 0xcc },
235 { STV090x_P2_MODCODLST9, 0xcc },
236 { STV090x_P2_MODCODLSTA, 0xcc },
237 { STV090x_P2_MODCODLSTB, 0xcc },
238 { STV090x_P2_MODCODLSTC, 0xcc },
239 { STV090x_P2_MODCODLSTD, 0xcc },
240 { STV090x_P2_MODCODLSTE, 0xcc },
241 { STV090x_P2_MODCODLSTF, 0xcf },
242 { STV090x_P1_DISTXCTL, 0x22 },
243 { STV090x_P1_F22TX, 0xc0 },
244 { STV090x_P1_F22RX, 0xc0 },
245 { STV090x_P1_DISRXCTL, 0x00 },
246 { STV090x_P1_DMDCFGMD, 0xf9 },
247 { STV090x_P1_DEMOD, 0x08 },
248 { STV090x_P1_DMDCFG3, 0xc4 },
249 { STV090x_P1_CARFREQ, 0xed },
250 { STV090x_P1_LDT, 0xd0 },
251 { STV090x_P1_LDT2, 0xb8 },
252 { STV090x_P1_TMGCFG, 0xd2 },
253 { STV090x_P1_TMGTHRISE, 0x20 },
254 { STV090x_P1_TMGTHFALL, 0x00 },
255 { STV090x_P1_SFRUPRATIO, 0xf0 },
256 { STV090x_P1_SFRLOWRATIO, 0x70 },
257 { STV090x_P1_TSCFGL, 0x20 },
258 { STV090x_P1_FECSPY, 0x88 },
259 { STV090x_P1_FSPYDATA, 0x3a },
260 { STV090x_P1_FBERCPT4, 0x00 },
261 { STV090x_P1_FSPYBER, 0x10 },
262 { STV090x_P1_ERRCTRL1, 0x35 },
263 { STV090x_P1_ERRCTRL2, 0xc1 },
264 { STV090x_P1_CFRICFG, 0xf8 },
265 { STV090x_P1_NOSCFG, 0x1c },
266 { STV090x_P1_CORRELMANT, 0x70 },
267 { STV090x_P1_CORRELABS, 0x88 },
268 { STV090x_P1_AGC2REF, 0x38 },
269 { STV090x_P1_CARCFG, 0xe4 },
270 { STV090x_P1_ACLC, 0x1A },
271 { STV090x_P1_BCLC, 0x09 },
272 { STV090x_P1_CARHDR, 0x08 },
273 { STV090x_P1_KREFTMG, 0xc1 },
274 { STV090x_P1_SFRSTEP, 0x58 },
275 { STV090x_P1_TMGCFG2, 0x01 },
276 { STV090x_P1_CAR2CFG, 0x26 },
277 { STV090x_P1_BCLC2S2Q, 0x86 },
278 { STV090x_P1_BCLC2S28, 0x86 },
279 { STV090x_P1_SMAPCOEF7, 0x77 },
280 { STV090x_P1_SMAPCOEF6, 0x85 },
281 { STV090x_P1_SMAPCOEF5, 0x77 },
282 { STV090x_P1_DMDCFG2, 0x3b },
283 { STV090x_P1_MODCODLST0, 0xff },
284 { STV090x_P1_MODCODLST1, 0xff },
285 { STV090x_P1_MODCODLST2, 0xff },
286 { STV090x_P1_MODCODLST3, 0xff },
287 { STV090x_P1_MODCODLST4, 0xff },
288 { STV090x_P1_MODCODLST5, 0xff },
289 { STV090x_P1_MODCODLST6, 0xff },
290 { STV090x_P1_MODCODLST7, 0xcc },
291 { STV090x_P1_MODCODLST8, 0xcc },
292 { STV090x_P1_MODCODLST9, 0xcc },
293 { STV090x_P1_MODCODLSTA, 0xcc },
294 { STV090x_P1_MODCODLSTB, 0xcc },
295 { STV090x_P1_MODCODLSTC, 0xcc },
296 { STV090x_P1_MODCODLSTD, 0xcc },
297 { STV090x_P1_MODCODLSTE, 0xcc },
298 { STV090x_P1_MODCODLSTF, 0xcf },
299 { STV090x_GENCFG, 0x1d },
300 { STV090x_NBITER_NF4, 0x37 },
301 { STV090x_NBITER_NF5, 0x29 },
302 { STV090x_NBITER_NF6, 0x37 },
303 { STV090x_NBITER_NF7, 0x33 },
304 { STV090x_NBITER_NF8, 0x31 },
305 { STV090x_NBITER_NF9, 0x2f },
306 { STV090x_NBITER_NF10, 0x39 },
307 { STV090x_NBITER_NF11, 0x3a },
308 { STV090x_NBITER_NF12, 0x29 },
309 { STV090x_NBITER_NF13, 0x37 },
310 { STV090x_NBITER_NF14, 0x33 },
311 { STV090x_NBITER_NF15, 0x2f },
312 { STV090x_NBITER_NF16, 0x39 },
313 { STV090x_NBITER_NF17, 0x3a },
314 { STV090x_NBITERNOERR, 0x04 },
315 { STV090x_GAINLLR_NF4, 0x0C },
316 { STV090x_GAINLLR_NF5, 0x0F },
317 { STV090x_GAINLLR_NF6, 0x11 },
318 { STV090x_GAINLLR_NF7, 0x14 },
319 { STV090x_GAINLLR_NF8, 0x17 },
320 { STV090x_GAINLLR_NF9, 0x19 },
321 { STV090x_GAINLLR_NF10, 0x20 },
322 { STV090x_GAINLLR_NF11, 0x21 },
323 { STV090x_GAINLLR_NF12, 0x0D },
324 { STV090x_GAINLLR_NF13, 0x0F },
325 { STV090x_GAINLLR_NF14, 0x13 },
326 { STV090x_GAINLLR_NF15, 0x1A },
327 { STV090x_GAINLLR_NF16, 0x1F },
328 { STV090x_GAINLLR_NF17, 0x21 },
329 { STV090x_P1_FECM, 0x01 }, /* disable DSS modes */
330 { STV090x_P2_FECM, 0x01 }, /* disable DSS modes */
331 { STV090x_P1_PRVIT, 0x2F }, /* disable PR 6/7 */
332 { STV090x_P2_PRVIT, 0x2F }, /* disable PR 6/7 */
335 static struct stv090x_reg stv0903_initval[] = {
336 { STV090x_OUTCFG, 0x00 },
337 { STV090x_AGCRF1CFG, 0x11 },
338 { STV090x_STOPCLK1, 0x48 },
339 { STV090x_STOPCLK2, 0x14 },
340 { STV090x_TSTTNR1, 0x27 },
341 { STV090x_TSTTNR2, 0x21 },
342 { STV090x_P1_DISTXCTL, 0x22 },
343 { STV090x_P1_F22TX, 0xc0 },
344 { STV090x_P1_F22RX, 0xc0 },
345 { STV090x_P1_DISRXCTL, 0x00 },
346 { STV090x_P1_DMDCFGMD, 0xF9 },
347 { STV090x_P1_DEMOD, 0x08 },
348 { STV090x_P1_DMDCFG3, 0xc4 },
349 { STV090x_P1_CARFREQ, 0xed },
350 { STV090x_P1_TNRCFG2, 0x82 },
351 { STV090x_P1_LDT, 0xd0 },
352 { STV090x_P1_LDT2, 0xb8 },
353 { STV090x_P1_TMGCFG, 0xd2 },
354 { STV090x_P1_TMGTHRISE, 0x20 },
355 { STV090x_P1_TMGTHFALL, 0x00 },
356 { STV090x_P1_SFRUPRATIO, 0xf0 },
357 { STV090x_P1_SFRLOWRATIO, 0x70 },
358 { STV090x_P1_TSCFGL, 0x20 },
359 { STV090x_P1_FECSPY, 0x88 },
360 { STV090x_P1_FSPYDATA, 0x3a },
361 { STV090x_P1_FBERCPT4, 0x00 },
362 { STV090x_P1_FSPYBER, 0x10 },
363 { STV090x_P1_ERRCTRL1, 0x35 },
364 { STV090x_P1_ERRCTRL2, 0xc1 },
365 { STV090x_P1_CFRICFG, 0xf8 },
366 { STV090x_P1_NOSCFG, 0x1c },
367 { STV090x_P1_CORRELMANT, 0x70 },
368 { STV090x_P1_CORRELABS, 0x88 },
369 { STV090x_P1_AGC2REF, 0x38 } ,
370 { STV090x_P1_CARCFG, 0xe4 },
371 { STV090x_P1_ACLC, 0x1A },
372 { STV090x_P1_BCLC, 0x09 } ,
373 { STV090x_P1_CARHDR, 0x08 },
374 { STV090x_P1_KREFTMG, 0xc1 },
375 { STV090x_P1_SFRSTEP, 0x58 },
376 { STV090x_P1_TMGCFG2, 0x01 },
377 { STV090x_P1_CAR2CFG, 0x26 },
378 { STV090x_P1_BCLC2S2Q, 0x86 },
379 { STV090x_P1_BCLC2S28, 0x86 },
380 { STV090x_P1_SMAPCOEF7, 0x77 },
381 { STV090x_P1_SMAPCOEF6, 0x85 },
382 { STV090x_P1_SMAPCOEF5, 0x77 },
383 { STV090x_P1_DMDCFG2, 0x3b },
384 { STV090x_P1_MODCODLST0, 0xff },
385 { STV090x_P1_MODCODLST1, 0xff },
386 { STV090x_P1_MODCODLST2, 0xff },
387 { STV090x_P1_MODCODLST3, 0xff },
388 { STV090x_P1_MODCODLST4, 0xff },
389 { STV090x_P1_MODCODLST5, 0xff },
390 { STV090x_P1_MODCODLST6, 0xff },
391 { STV090x_P1_MODCODLST7, 0xcc },
392 { STV090x_P1_MODCODLST8, 0xcc },
393 { STV090x_P1_MODCODLST9, 0xcc },
394 { STV090x_P1_MODCODLSTA, 0xcc },
395 { STV090x_P1_MODCODLSTB, 0xcc },
396 { STV090x_P1_MODCODLSTC, 0xcc },
397 { STV090x_P1_MODCODLSTD, 0xcc },
398 { STV090x_P1_MODCODLSTE, 0xcc },
399 { STV090x_P1_MODCODLSTF, 0xcf },
400 { STV090x_GENCFG, 0x1c },
401 { STV090x_NBITER_NF4, 0x37 },
402 { STV090x_NBITER_NF5, 0x29 },
403 { STV090x_NBITER_NF6, 0x37 },
404 { STV090x_NBITER_NF7, 0x33 },
405 { STV090x_NBITER_NF8, 0x31 },
406 { STV090x_NBITER_NF9, 0x2f },
407 { STV090x_NBITER_NF10, 0x39 },
408 { STV090x_NBITER_NF11, 0x3a },
409 { STV090x_NBITER_NF12, 0x29 },
410 { STV090x_NBITER_NF13, 0x37 },
411 { STV090x_NBITER_NF14, 0x33 },
412 { STV090x_NBITER_NF15, 0x2f },
413 { STV090x_NBITER_NF16, 0x39 },
414 { STV090x_NBITER_NF17, 0x3a },
415 { STV090x_NBITERNOERR, 0x04 },
416 { STV090x_GAINLLR_NF4, 0x0C },
417 { STV090x_GAINLLR_NF5, 0x0F },
418 { STV090x_GAINLLR_NF6, 0x11 },
419 { STV090x_GAINLLR_NF7, 0x14 },
420 { STV090x_GAINLLR_NF8, 0x17 },
421 { STV090x_GAINLLR_NF9, 0x19 },
422 { STV090x_GAINLLR_NF10, 0x20 },
423 { STV090x_GAINLLR_NF11, 0x21 },
424 { STV090x_GAINLLR_NF12, 0x0D },
425 { STV090x_GAINLLR_NF13, 0x0F },
426 { STV090x_GAINLLR_NF14, 0x13 },
427 { STV090x_GAINLLR_NF15, 0x1A },
428 { STV090x_GAINLLR_NF16, 0x1F },
429 { STV090x_GAINLLR_NF17, 0x21 },
430 { STV090x_P1_FECM, 0x01 }, /*disable the DSS mode */
431 { STV090x_P1_PRVIT, 0x2f } /*disable puncture rate 6/7*/
434 static struct stv090x_reg stv0900_cut20_val[] = {
436 { STV090x_P2_DMDCFG3, 0xe8 },
437 { STV090x_P2_CARFREQ, 0x38 },
438 { STV090x_P2_CARHDR, 0x20 },
439 { STV090x_P2_KREFTMG, 0x5a },
440 { STV090x_P2_SMAPCOEF7, 0x06 },
441 { STV090x_P2_SMAPCOEF6, 0x00 },
442 { STV090x_P2_SMAPCOEF5, 0x04 },
443 { STV090x_P2_NOSCFG, 0x0c },
444 { STV090x_P1_DMDCFG3, 0xe8 },
445 { STV090x_P1_CARFREQ, 0x38 },
446 { STV090x_P1_CARHDR, 0x20 },
447 { STV090x_P1_KREFTMG, 0x5a },
448 { STV090x_P1_SMAPCOEF7, 0x06 },
449 { STV090x_P1_SMAPCOEF6, 0x00 },
450 { STV090x_P1_SMAPCOEF5, 0x04 },
451 { STV090x_P1_NOSCFG, 0x0c },
452 { STV090x_GAINLLR_NF4, 0x21 },
453 { STV090x_GAINLLR_NF5, 0x21 },
454 { STV090x_GAINLLR_NF6, 0x20 },
455 { STV090x_GAINLLR_NF7, 0x1F },
456 { STV090x_GAINLLR_NF8, 0x1E },
457 { STV090x_GAINLLR_NF9, 0x1E },
458 { STV090x_GAINLLR_NF10, 0x1D },
459 { STV090x_GAINLLR_NF11, 0x1B },
460 { STV090x_GAINLLR_NF12, 0x20 },
461 { STV090x_GAINLLR_NF13, 0x20 },
462 { STV090x_GAINLLR_NF14, 0x20 },
463 { STV090x_GAINLLR_NF15, 0x20 },
464 { STV090x_GAINLLR_NF16, 0x20 },
465 { STV090x_GAINLLR_NF17, 0x21 },
468 static struct stv090x_reg stv0903_cut20_val[] = {
469 { STV090x_P1_DMDCFG3, 0xe8 },
470 { STV090x_P1_CARFREQ, 0x38 },
471 { STV090x_P1_CARHDR, 0x20 },
472 { STV090x_P1_KREFTMG, 0x5a },
473 { STV090x_P1_SMAPCOEF7, 0x06 },
474 { STV090x_P1_SMAPCOEF6, 0x00 },
475 { STV090x_P1_SMAPCOEF5, 0x04 },
476 { STV090x_P1_NOSCFG, 0x0c },
477 { STV090x_GAINLLR_NF4, 0x21 },
478 { STV090x_GAINLLR_NF5, 0x21 },
479 { STV090x_GAINLLR_NF6, 0x20 },
480 { STV090x_GAINLLR_NF7, 0x1F },
481 { STV090x_GAINLLR_NF8, 0x1E },
482 { STV090x_GAINLLR_NF9, 0x1E },
483 { STV090x_GAINLLR_NF10, 0x1D },
484 { STV090x_GAINLLR_NF11, 0x1B },
485 { STV090x_GAINLLR_NF12, 0x20 },
486 { STV090x_GAINLLR_NF13, 0x20 },
487 { STV090x_GAINLLR_NF14, 0x20 },
488 { STV090x_GAINLLR_NF15, 0x20 },
489 { STV090x_GAINLLR_NF16, 0x20 },
490 { STV090x_GAINLLR_NF17, 0x21 }
493 /* Cut 1.x Long Frame Tracking CR loop */
494 static struct stv090x_long_frame_crloop stv090x_s2_crl[] = {
495 /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
496 { STV090x_QPSK_12, 0x1c, 0x0d, 0x1b, 0x2c, 0x3a, 0x1c, 0x2a, 0x3b, 0x2a, 0x1b },
497 { STV090x_QPSK_35, 0x2c, 0x0d, 0x2b, 0x2c, 0x3a, 0x0c, 0x3a, 0x2b, 0x2a, 0x0b },
498 { STV090x_QPSK_23, 0x2c, 0x0d, 0x2b, 0x2c, 0x0b, 0x0c, 0x3a, 0x1b, 0x2a, 0x3a },
499 { STV090x_QPSK_34, 0x3c, 0x0d, 0x3b, 0x1c, 0x0b, 0x3b, 0x3a, 0x0b, 0x2a, 0x3a },
500 { STV090x_QPSK_45, 0x3c, 0x0d, 0x3b, 0x1c, 0x0b, 0x3b, 0x3a, 0x0b, 0x2a, 0x3a },
501 { STV090x_QPSK_56, 0x0d, 0x0d, 0x3b, 0x1c, 0x0b, 0x3b, 0x3a, 0x0b, 0x2a, 0x3a },
502 { STV090x_QPSK_89, 0x0d, 0x0d, 0x3b, 0x1c, 0x1b, 0x3b, 0x3a, 0x0b, 0x2a, 0x3a },
503 { STV090x_QPSK_910, 0x1d, 0x0d, 0x3b, 0x1c, 0x1b, 0x3b, 0x3a, 0x0b, 0x2a, 0x3a },
504 { STV090x_8PSK_35, 0x29, 0x3b, 0x09, 0x2b, 0x38, 0x0b, 0x18, 0x1a, 0x08, 0x0a },
505 { STV090x_8PSK_23, 0x0a, 0x3b, 0x29, 0x2b, 0x19, 0x0b, 0x38, 0x1a, 0x18, 0x0a },
506 { STV090x_8PSK_34, 0x3a, 0x3b, 0x2a, 0x2b, 0x39, 0x0b, 0x19, 0x1a, 0x38, 0x0a },
507 { STV090x_8PSK_56, 0x1b, 0x3b, 0x0b, 0x2b, 0x1a, 0x0b, 0x39, 0x1a, 0x19, 0x0a },
508 { STV090x_8PSK_89, 0x3b, 0x3b, 0x0b, 0x2b, 0x2a, 0x0b, 0x39, 0x1a, 0x29, 0x39 },
509 { STV090x_8PSK_910, 0x3b, 0x3b, 0x0b, 0x2b, 0x2a, 0x0b, 0x39, 0x1a, 0x29, 0x39 }
512 /* Cut 2.0 Long Frame Tracking CR loop */
513 static struct stv090x_long_frame_crloop stv090x_s2_crl_cut20[] = {
514 /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
515 { STV090x_QPSK_12, 0x1f, 0x3f, 0x1e, 0x3f, 0x3d, 0x1f, 0x3d, 0x3e, 0x3d, 0x1e },
516 { STV090x_QPSK_35, 0x2f, 0x3f, 0x2e, 0x2f, 0x3d, 0x0f, 0x0e, 0x2e, 0x3d, 0x0e },
517 { STV090x_QPSK_23, 0x2f, 0x3f, 0x2e, 0x2f, 0x0e, 0x0f, 0x0e, 0x1e, 0x3d, 0x3d },
518 { STV090x_QPSK_34, 0x3f, 0x3f, 0x3e, 0x1f, 0x0e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
519 { STV090x_QPSK_45, 0x3f, 0x3f, 0x3e, 0x1f, 0x0e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
520 { STV090x_QPSK_56, 0x3f, 0x3f, 0x3e, 0x1f, 0x0e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
521 { STV090x_QPSK_89, 0x3f, 0x3f, 0x3e, 0x1f, 0x1e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
522 { STV090x_QPSK_910, 0x3f, 0x3f, 0x3e, 0x1f, 0x1e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
523 { STV090x_8PSK_35, 0x3c, 0x3e, 0x1c, 0x2e, 0x0c, 0x1e, 0x2b, 0x2d, 0x1b, 0x1d },
524 { STV090x_8PSK_23, 0x1d, 0x3e, 0x3c, 0x2e, 0x2c, 0x1e, 0x0c, 0x2d, 0x2b, 0x1d },
525 { STV090x_8PSK_34, 0x0e, 0x3e, 0x3d, 0x2e, 0x0d, 0x1e, 0x2c, 0x2d, 0x0c, 0x1d },
526 { STV090x_8PSK_56, 0x2e, 0x3e, 0x1e, 0x2e, 0x2d, 0x1e, 0x3c, 0x2d, 0x2c, 0x1d },
527 { STV090x_8PSK_89, 0x3e, 0x3e, 0x1e, 0x2e, 0x3d, 0x1e, 0x0d, 0x2d, 0x3c, 0x1d },
528 { STV090x_8PSK_910, 0x3e, 0x3e, 0x1e, 0x2e, 0x3d, 0x1e, 0x1d, 0x2d, 0x0d, 0x1d }
532 /* Cut 2.0 Long Frame Tracking CR Loop */
533 static struct stv090x_long_frame_crloop stv090x_s2_apsk_crl_cut20[] = {
534 /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
535 { STV090x_16APSK_23, 0x0c, 0x0c, 0x0c, 0x0c, 0x1d, 0x0c, 0x3c, 0x0c, 0x2c, 0x0c },
536 { STV090x_16APSK_34, 0x0c, 0x0c, 0x0c, 0x0c, 0x0e, 0x0c, 0x2d, 0x0c, 0x1d, 0x0c },
537 { STV090x_16APSK_45, 0x0c, 0x0c, 0x0c, 0x0c, 0x1e, 0x0c, 0x3d, 0x0c, 0x2d, 0x0c },
538 { STV090x_16APSK_56, 0x0c, 0x0c, 0x0c, 0x0c, 0x1e, 0x0c, 0x3d, 0x0c, 0x2d, 0x0c },
539 { STV090x_16APSK_89, 0x0c, 0x0c, 0x0c, 0x0c, 0x2e, 0x0c, 0x0e, 0x0c, 0x3d, 0x0c },
540 { STV090x_16APSK_910, 0x0c, 0x0c, 0x0c, 0x0c, 0x2e, 0x0c, 0x0e, 0x0c, 0x3d, 0x0c },
541 { STV090x_32APSK_34, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c },
542 { STV090x_32APSK_45, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c },
543 { STV090x_32APSK_56, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c },
544 { STV090x_32APSK_89, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c },
545 { STV090x_32APSK_910, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c }
549 static struct stv090x_long_frame_crloop stv090x_s2_lowqpsk_crl_cut20[] = {
550 /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
551 { STV090x_QPSK_14, 0x0f, 0x3f, 0x0e, 0x3f, 0x2d, 0x2f, 0x2d, 0x1f, 0x3d, 0x3e },
552 { STV090x_QPSK_13, 0x0f, 0x3f, 0x0e, 0x3f, 0x2d, 0x2f, 0x3d, 0x0f, 0x3d, 0x2e },
553 { STV090x_QPSK_25, 0x1f, 0x3f, 0x1e, 0x3f, 0x3d, 0x1f, 0x3d, 0x3e, 0x3d, 0x2e }
557 /* Cut 1.2 & 2.0 Short Frame Tracking CR Loop */
558 static struct stv090x_short_frame_crloop stv090x_s2_short_crl[] = {
559 /* MODCOD 2M_cut1.2 2M_cut2.0 5M_cut1.2 5M_cut2.0 10M_cut1.2 10M_cut2.0 20M_cut1.2 20M_cut2.0 30M_cut1.2 30M_cut2.0 */
560 { STV090x_QPSK, 0x3c, 0x2f, 0x2b, 0x2e, 0x0b, 0x0e, 0x3a, 0x0e, 0x2a, 0x3d },
561 { STV090x_8PSK, 0x0b, 0x3e, 0x2a, 0x0e, 0x0a, 0x2d, 0x19, 0x0d, 0x09, 0x3c },
562 { STV090x_16APSK, 0x1b, 0x1e, 0x1b, 0x1e, 0x1b, 0x1e, 0x3a, 0x3d, 0x2a, 0x2d },
563 { STV090x_32APSK, 0x1b, 0x1e, 0x1b, 0x1e, 0x1b, 0x1e, 0x3a, 0x3d, 0x2a, 0x2d }
567 static inline s32 comp2(s32 __x, s32 __width)
572 return (__x >= (1 << (__width - 1))) ? (__x - (1 << __width)) : __x;
575 static int stv090x_read_reg(struct stv090x_state *state, unsigned int reg)
577 const struct stv090x_config *config = state->config;
580 u8 b0[] = { reg >> 8, reg & 0xff };
583 struct i2c_msg msg[] = {
584 { .addr = config->address, .flags = 0, .buf = b0, .len = 2 },
585 { .addr = config->address, .flags = I2C_M_RD, .buf = &buf, .len = 1 }
588 ret = i2c_transfer(state->i2c, msg, 2);
590 if (ret != -ERESTARTSYS)
592 "Read error, Reg=[0x%02x], Status=%d",
595 return ret < 0 ? ret : -EREMOTEIO;
597 if (unlikely(*state->verbose >= FE_DEBUGREG))
598 dprintk(FE_ERROR, 1, "Reg=[0x%02x], data=%02x",
601 return (unsigned int) buf;
604 static int stv090x_write_regs(struct stv090x_state *state, unsigned int reg, u8 *data, u32 count)
606 const struct stv090x_config *config = state->config;
609 struct i2c_msg i2c_msg = { .addr = config->address, .flags = 0, .buf = buf, .len = 2 + count };
613 memcpy(&buf[2], data, count);
615 if (unlikely(*state->verbose >= FE_DEBUGREG)) {
618 printk(KERN_DEBUG "%s [0x%04x]:", __func__, reg);
619 for (i = 0; i < count; i++)
620 printk(" %02x", data[i]);
624 ret = i2c_transfer(state->i2c, &i2c_msg, 1);
626 if (ret != -ERESTARTSYS)
627 dprintk(FE_ERROR, 1, "Reg=[0x%04x], Data=[0x%02x ...], Count=%u, Status=%d",
628 reg, data[0], count, ret);
629 return ret < 0 ? ret : -EREMOTEIO;
635 static int stv090x_write_reg(struct stv090x_state *state, unsigned int reg, u8 data)
637 return stv090x_write_regs(state, reg, &data, 1);
640 static int stv090x_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
642 struct stv090x_state *state = fe->demodulator_priv;
645 reg = STV090x_READ_DEMOD(state, I2CRPT);
648 STV090x_SETFIELD_Px(reg, I2CT_ON_FIELD, 1);
649 if (STV090x_WRITE_DEMOD(state, I2CRPT, reg) < 0)
653 STV090x_SETFIELD_Px(reg, I2CT_ON_FIELD, 0);
654 if ((STV090x_WRITE_DEMOD(state, I2CRPT, reg)) < 0)
659 dprintk(FE_ERROR, 1, "I/O error");
663 static void stv090x_get_lock_tmg(struct stv090x_state *state)
665 switch (state->algo) {
666 case STV090x_BLIND_SEARCH:
667 dprintk(FE_DEBUG, 1, "Blind Search");
668 if (state->srate <= 1500000) { /*10Msps< SR <=15Msps*/
669 state->DemodTimeout = 1500;
670 state->FecTimeout = 400;
671 } else if (state->srate <= 5000000) { /*10Msps< SR <=15Msps*/
672 state->DemodTimeout = 1000;
673 state->FecTimeout = 300;
674 } else { /*SR >20Msps*/
675 state->DemodTimeout = 700;
676 state->FecTimeout = 100;
680 case STV090x_COLD_SEARCH:
681 case STV090x_WARM_SEARCH:
683 dprintk(FE_DEBUG, 1, "Normal Search");
684 if (state->srate <= 1000000) { /*SR <=1Msps*/
685 state->DemodTimeout = 4500;
686 state->FecTimeout = 1700;
687 } else if (state->srate <= 2000000) { /*1Msps < SR <= 2Msps */
688 state->DemodTimeout = 2500;
689 state->FecTimeout = 1100;
690 } else if (state->srate <= 5000000) { /*2Msps < SR <= 5Msps */
691 state->DemodTimeout = 1000;
692 state->FecTimeout = 550;
693 } else if (state->srate <= 10000000) { /*5Msps < SR <= 10Msps */
694 state->DemodTimeout = 700;
695 state->FecTimeout = 250;
696 } else if (state->srate <= 20000000) { /*10Msps < SR <= 20Msps */
697 state->DemodTimeout = 400;
698 state->FecTimeout = 130;
699 } else { /*SR >20Msps*/
700 state->DemodTimeout = 300;
701 state->FecTimeout = 100;
706 if (state->algo == STV090x_WARM_SEARCH)
707 state->DemodTimeout /= 2;
710 static int stv090x_set_srate(struct stv090x_state *state, u32 srate)
714 if (srate > 6000000) {
715 sym = (srate / 1000) * 65536;
716 sym /= (state->mclk / 1000);
718 sym = (srate / 100) * 65536;
719 sym /= (state->mclk / 100);
722 if (STV090x_WRITE_DEMOD(state, SFRINIT1, (sym >> 8) & 0xff) < 0) /* MSB */
724 if (STV090x_WRITE_DEMOD(state, SFRINIT0, (sym & 0xff)) < 0) /* LSB */
728 dprintk(FE_ERROR, 1, "I/O error");
732 static int stv090x_set_max_srate(struct stv090x_state *state, u32 clk, u32 srate)
736 srate = 105 * (srate / 100);
737 if (srate > 6000000) {
738 sym = (srate / 1000) * 65536;
741 sym = (srate / 100) * 65536;
744 if (STV090x_WRITE_DEMOD(state, SFRUP1, (sym >> 8) & 0x7f) < 0) /* MSB */
746 if (STV090x_WRITE_DEMOD(state, SFRUP0, sym & 0xff) < 0) /* LSB */
750 dprintk(FE_ERROR, 1, "I/O error");
754 static int stv090x_set_min_srate(struct stv090x_state *state, u32 clk, u32 srate)
758 srate = 95 * (srate / 100);
759 if (srate > 6000000) {
760 sym = (srate / 1000) * 65536;
763 sym = (srate / 100) * 65536;
766 if (STV090x_WRITE_DEMOD(state, SFRLOW1, ((sym >> 8) & 0xff)) < 0) /* MSB */
768 if (STV090x_WRITE_DEMOD(state, SFRLOW0, (sym & 0xff)) < 0) /* LSB */
772 dprintk(FE_ERROR, 1, "I/O error");
776 static u32 stv090x_car_width(u32 srate, u32 rolloff)
778 return srate + (srate * rolloff) / 100;
781 static int stv090x_set_vit_thacq(struct stv090x_state *state)
783 if (STV090x_WRITE_DEMOD(state, VTH12, 0x96) < 0)
785 if (STV090x_WRITE_DEMOD(state, VTH23, 0x64) < 0)
787 if (STV090x_WRITE_DEMOD(state, VTH34, 0x36) < 0)
789 if (STV090x_WRITE_DEMOD(state, VTH56, 0x23) < 0)
791 if (STV090x_WRITE_DEMOD(state, VTH67, 0x1e) < 0)
793 if (STV090x_WRITE_DEMOD(state, VTH78, 0x19) < 0)
797 dprintk(FE_ERROR, 1, "I/O error");
801 static int stv090x_set_vit_thtracq(struct stv090x_state *state)
803 if (STV090x_WRITE_DEMOD(state, VTH12, 0xd0) < 0)
805 if (STV090x_WRITE_DEMOD(state, VTH23, 0x7d) < 0)
807 if (STV090x_WRITE_DEMOD(state, VTH34, 0x53) < 0)
809 if (STV090x_WRITE_DEMOD(state, VTH56, 0x2f) < 0)
811 if (STV090x_WRITE_DEMOD(state, VTH67, 0x24) < 0)
813 if (STV090x_WRITE_DEMOD(state, VTH78, 0x1f) < 0)
817 dprintk(FE_ERROR, 1, "I/O error");
821 static int stv090x_set_viterbi(struct stv090x_state *state)
823 switch (state->search_mode) {
824 case STV090x_SEARCH_AUTO:
825 if (STV090x_WRITE_DEMOD(state, FECM, 0x10) < 0) /* DVB-S and DVB-S2 */
827 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x3f) < 0) /* all puncture rate */
830 case STV090x_SEARCH_DVBS1:
831 if (STV090x_WRITE_DEMOD(state, FECM, 0x00) < 0) /* disable DSS */
833 switch (state->fec) {
835 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x01) < 0)
840 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x02) < 0)
845 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x04) < 0)
850 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x08) < 0)
855 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x20) < 0)
860 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x2f) < 0) /* all */
865 case STV090x_SEARCH_DSS:
866 if (STV090x_WRITE_DEMOD(state, FECM, 0x80) < 0)
868 switch (state->fec) {
870 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x01) < 0)
875 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x02) < 0)
880 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x10) < 0)
885 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x13) < 0) /* 1/2, 2/3, 6/7 */
895 dprintk(FE_ERROR, 1, "I/O error");
899 static int stv090x_stop_modcod(struct stv090x_state *state)
901 if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0)
903 if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xff) < 0)
905 if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0xff) < 0)
907 if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0xff) < 0)
909 if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0xff) < 0)
911 if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0xff) < 0)
913 if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0xff) < 0)
915 if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0xff) < 0)
917 if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0xff) < 0)
919 if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0xff) < 0)
921 if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0xff) < 0)
923 if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0xff) < 0)
925 if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0xff) < 0)
927 if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0xff) < 0)
929 if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0xff) < 0)
931 if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0xff) < 0)
935 dprintk(FE_ERROR, 1, "I/O error");
939 static int stv090x_activate_modcod(struct stv090x_state *state)
941 u32 matype, modcod, f_mod, index;
943 if (state->dev_ver <= 0x11) {
945 modcod = STV090x_READ_DEMOD(state, PLHMODCOD);
946 matype = modcod & 0x03;
947 modcod = (modcod & 0x7f) >> 2;
948 index = STV090x_ADDR_OFFST(state, MODCODLSTF) - (modcod / 2);
967 if (stv090x_write_reg(state, index, 0xf0 | f_mod) < 0)
970 if (stv090x_write_reg(state, index, (f_mod << 4) | 0x0f) < 0)
974 } else if (state->dev_ver >= 0x12) {
975 if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0)
977 if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xfc) < 0)
979 if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0xcc) < 0)
981 if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0xcc) < 0)
983 if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0xcc) < 0)
985 if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0xcc) < 0)
987 if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0xcc) < 0)
989 if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0xcc) < 0)
991 if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0xcc) < 0)
993 if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0xcc) < 0)
995 if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0xcc) < 0)
997 if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0xcc) < 0)
999 if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0xcc) < 0)
1001 if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0xcc) < 0)
1003 if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0xcc) < 0)
1005 if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0xcf) < 0)
1010 dprintk(FE_ERROR, 1, "I/O error");
1014 static int stv090x_vitclk_ctl(struct stv090x_state *state, int enable)
1018 switch (state->demod) {
1019 case STV090x_DEMODULATOR_0:
1020 mutex_lock(&demod_lock);
1021 reg = stv090x_read_reg(state, STV090x_STOPCLK2);
1022 STV090x_SETFIELD(reg, STOP_CLKVIT1_FIELD, enable);
1023 if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0)
1025 mutex_unlock(&demod_lock);
1028 case STV090x_DEMODULATOR_1:
1029 mutex_lock(&demod_lock);
1030 reg = stv090x_read_reg(state, STV090x_STOPCLK2);
1031 STV090x_SETFIELD(reg, STOP_CLKVIT2_FIELD, enable);
1032 if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0)
1034 mutex_unlock(&demod_lock);
1038 dprintk(FE_ERROR, 1, "Wrong demodulator!");
1043 mutex_unlock(&demod_lock);
1044 dprintk(FE_ERROR, 1, "I/O error");
1048 static int stv090x_delivery_search(struct stv090x_state *state)
1052 switch (state->search_mode) {
1053 case STV090x_SEARCH_DVBS1:
1054 case STV090x_SEARCH_DSS:
1055 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1056 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
1057 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
1058 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1061 /* Activate Viterbi decoder in legacy search, do not use FRESVIT1, might impact VITERBI2 */
1062 if (stv090x_vitclk_ctl(state, 0) < 0)
1065 if (STV090x_WRITE_DEMOD(state, ACLC, 0x1a) < 0)
1067 if (STV090x_WRITE_DEMOD(state, BCLC, 0x09) < 0)
1069 if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x22) < 0) /* disable DVB-S2 */
1072 stv090x_set_vit_thacq(state);
1073 stv090x_set_viterbi(state);
1076 case STV090x_SEARCH_DVBS2:
1077 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1078 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 0);
1079 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
1080 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1082 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
1083 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
1084 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1087 if (stv090x_vitclk_ctl(state, 1) < 0)
1090 if (STV090x_WRITE_DEMOD(state, ACLC, 0x1a) < 0) /* stop DVB-S CR loop */
1092 if (STV090x_WRITE_DEMOD(state, BCLC, 0x09) < 0)
1094 if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x26) < 0)
1097 if (state->demod_mode != STV090x_SINGLE) {
1098 if (state->dev_ver <= 0x11) /* 900 in dual TS mode */
1099 stv090x_stop_modcod(state);
1101 stv090x_activate_modcod(state);
1105 case STV090x_SEARCH_AUTO:
1107 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1108 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 0);
1109 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
1110 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1112 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
1113 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
1114 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1117 if (stv090x_vitclk_ctl(state, 1) < 0)
1120 if (STV090x_WRITE_DEMOD(state, ACLC, 0x1a) < 0)
1122 if (STV090x_WRITE_DEMOD(state, ACLC, 0x09) < 0)
1124 if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x26) < 0)
1127 if (state->demod_mode != STV090x_SINGLE) {
1128 if (state->dev_ver <= 0x11) /* 900 in dual TS mode */
1129 stv090x_stop_modcod(state);
1131 stv090x_activate_modcod(state);
1133 stv090x_set_vit_thacq(state);
1134 stv090x_set_viterbi(state);
1139 dprintk(FE_ERROR, 1, "I/O error");
1143 static int stv090x_start_search(struct stv090x_state *state)
1147 reg = STV090x_READ_DEMOD(state, DMDISTATE);
1148 STV090x_SETFIELD_Px(reg, I2C_DEMOD_MODE_FIELD, 0x1f);
1149 if (STV090x_WRITE_DEMOD(state, DMDISTATE, reg) < 0)
1152 if (state->dev_ver == 0x10) {
1153 if (STV090x_WRITE_DEMOD(state, CORRELEXP, 0xaa) < 0)
1156 if (state->dev_ver < 0x20) {
1157 if (STV090x_WRITE_DEMOD(state, CARHDR, 0x55) < 0)
1160 if (state->srate <= 5000000) {
1161 if (STV090x_WRITE_DEMOD(state, CARCFG, 0x44) < 0)
1163 if (STV090x_WRITE_DEMOD(state, CFRUP1, 0x0f) < 0)
1165 if (STV090x_WRITE_DEMOD(state, CFRUP1, 0xff) < 0)
1167 if (STV090x_WRITE_DEMOD(state, CFRLOW1, 0xf0) < 0)
1169 if (STV090x_WRITE_DEMOD(state, CFRLOW0, 0x00) < 0)
1172 /*enlarge the timing bandwith for Low SR*/
1173 if (STV090x_WRITE_DEMOD(state, RTCS2, 0x68) < 0)
1176 /* If the symbol rate is >5 Msps
1177 Set The carrier search up and low to auto mode */
1178 if (STV090x_WRITE_DEMOD(state, CARCFG, 0xc4) < 0)
1180 /*reduce the timing bandwith for high SR*/
1181 if (STV090x_WRITE_DEMOD(state, RTCS2, 0x44) < 0)
1184 if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0) < 0)
1186 if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0) < 0)
1189 if (state->dev_ver >= 0x20) {
1190 if (STV090x_WRITE_DEMOD(state, EQUALCFG, 0x41) < 0)
1192 if (STV090x_WRITE_DEMOD(state, FFECFG, 0x41) < 0)
1195 if ((state->search_mode == STV090x_DVBS1) ||
1196 (state->search_mode == STV090x_DSS) ||
1197 (state->search_mode == STV090x_SEARCH_AUTO)) {
1199 if (STV090x_WRITE_DEMOD(state, VITSCALE, 0x82) < 0)
1201 if (STV090x_WRITE_DEMOD(state, VAVSRVIT, 0x00) < 0)
1206 if (STV090x_WRITE_DEMOD(state, SFRSTEP, 0x00) < 0)
1208 if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0xe0) < 0)
1210 if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0xc0) < 0)
1213 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1214 STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 0);
1215 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0);
1216 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1218 reg = STV090x_READ_DEMOD(state, DMDCFG2);
1219 STV090x_SETFIELD_Px(reg, S1S2_SEQUENTIAL_FIELD, 0x0);
1220 if (STV090x_WRITE_DEMOD(state, DMDCFG2, reg) < 0)
1223 if (state->dev_ver >= 0x20) { /*Frequency offset detector setting*/
1224 if (state->srate < 10000000) {
1225 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x4c) < 0)
1228 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x4b) < 0)
1232 if (state->srate < 10000000) {
1233 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0xef) < 0)
1236 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0xed) < 0)
1241 switch (state->algo) {
1242 case STV090x_WARM_SEARCH:/*The symbol rate and the exact carrier Frequency are known */
1243 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
1245 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0)
1249 case STV090x_COLD_SEARCH:/*The symbol rate is known*/
1250 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
1252 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0)
1261 dprintk(FE_ERROR, 1, "I/O error");
1265 static int stv090x_get_agc2_min_level(struct stv090x_state *state)
1267 u32 agc2_min = 0, agc2 = 0, freq_init, freq_step, reg;
1268 s32 i, j, steps, dir;
1270 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
1272 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1273 STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 1);
1274 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 1);
1275 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1278 if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x83) < 0) /* SR = 65 Msps Max */
1280 if (STV090x_WRITE_DEMOD(state, SFRUP0, 0xc0) < 0)
1282 if (STV090x_WRITE_DEMOD(state, SFRLOW1, 0x82) < 0) /* SR= 400 ksps Min */
1284 if (STV090x_WRITE_DEMOD(state, SFRLOW0, 0xa0) < 0)
1286 if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x00) < 0) /* stop acq @ coarse carrier state */
1288 stv090x_set_srate(state, 1000000);
1290 steps = -1 + state->search_range / 1000000;
1292 steps = (2 * steps) + 1;
1297 freq_step = (1000000 * 256) / (state->mclk / 256);
1300 for (i = 0; i < steps; i++) {
1302 freq_init = freq_init + (freq_step * i);
1304 freq_init = freq_init - (freq_step * i);
1308 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5c) < 0) /* Demod RESET */
1310 if (STV090x_WRITE_DEMOD(state, CFRINIT1, (freq_init >> 8) & 0xff) < 0)
1312 if (STV090x_WRITE_DEMOD(state, CFRINIT0, freq_init & 0xff) < 0)
1314 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x58) < 0) /* Demod RESET */
1317 for (j = 0; j < 10; j++) {
1318 agc2 += STV090x_READ_DEMOD(state, AGC2I1) << 8;
1319 agc2 |= STV090x_READ_DEMOD(state, AGC2I0);
1329 dprintk(FE_ERROR, 1, "I/O error");
1333 static u32 stv090x_get_srate(struct stv090x_state *state, u32 clk)
1336 s32 srate, int_1, int_2, tmp_1, tmp_2;
1339 r3 = STV090x_READ_DEMOD(state, SFR3);
1340 r2 = STV090x_READ_DEMOD(state, SFR2);
1341 r1 = STV090x_READ_DEMOD(state, SFR1);
1342 r0 = STV090x_READ_DEMOD(state, SFR0);
1344 srate = ((r3 << 24) | (r2 << 16) | (r1 << 8) | r0);
1348 int_2 = srate / pow2;
1351 tmp_2 = srate % pow2;
1353 srate = (int_1 * int_2) +
1354 ((int_1 * tmp_2) / pow2) +
1355 ((int_2 * tmp_1) / pow2);
1360 static u32 stv090x_srate_srch_coarse(struct stv090x_state *state)
1362 struct dvb_frontend *fe = &state->frontend;
1364 int tmg_lock = 0, i;
1365 s32 tmg_cpt = 0, dir = 1, steps, cur_step = 0, freq;
1366 u32 srate_coarse = 0, agc2 = 0, car_step = 1200, reg;
1368 reg = STV090x_READ_DEMOD(state, DMDISTATE);
1369 STV090x_SETFIELD_Px(reg, I2C_DEMOD_MODE_FIELD, 0x1f); /* Demod RESET */
1370 if (STV090x_WRITE_DEMOD(state, DMDISTATE, reg) < 0)
1372 if (STV090x_WRITE_DEMOD(state, TMGCFG, 0x12) < 0)
1374 if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0xf0) < 0)
1376 if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0xe0) < 0)
1378 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1379 STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 1);
1380 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 1);
1381 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1384 if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x83) < 0)
1386 if (STV090x_WRITE_DEMOD(state, SFRUP0, 0xc0) < 0)
1388 if (STV090x_WRITE_DEMOD(state, SFRLOW1, 0x82) < 0)
1390 if (STV090x_WRITE_DEMOD(state, SFRLOW0, 0xa0) < 0)
1392 if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x00) < 0)
1394 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x60) < 0)
1397 if (state->dev_ver >= 0x20) {
1398 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x6a) < 0)
1400 if (STV090x_WRITE_DEMOD(state, SFRSTEP, 0x95) < 0)
1403 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0xed) < 0)
1405 if (STV090x_WRITE_DEMOD(state, SFRSTEP, 0x73) < 0)
1409 if (state->srate <= 2000000)
1411 else if (state->srate <= 5000000)
1413 else if (state->srate <= 12000000)
1418 steps = -1 + ((state->search_range / 1000) / car_step);
1420 steps = (2 * steps) + 1;
1423 else if (steps > 10) {
1425 car_step = (state->search_range / 1000) / 10;
1429 freq = state->frequency;
1431 while ((!tmg_lock) && (cur_step < steps)) {
1432 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5f) < 0) /* Demod RESET */
1434 reg = STV090x_READ_DEMOD(state, DMDISTATE);
1435 STV090x_SETFIELD_Px(reg, I2C_DEMOD_MODE_FIELD, 0x00); /* trigger acquisition */
1436 if (STV090x_WRITE_DEMOD(state, DMDISTATE, reg) < 0)
1439 for (i = 0; i < 10; i++) {
1440 reg = STV090x_READ_DEMOD(state, DSTATUS);
1441 if (STV090x_GETFIELD_Px(reg, TMGLOCK_QUALITY_FIELD) >= 2)
1443 agc2 += STV090x_READ_DEMOD(state, AGC2I1) << 8;
1444 agc2 |= STV090x_READ_DEMOD(state, AGC2I0);
1447 srate_coarse = stv090x_get_srate(state, state->mclk);
1450 if ((tmg_cpt >= 5) && (agc2 < 0x1f00) && (srate_coarse < 55000000) && (srate_coarse > 850000))
1452 else if (cur_step < steps) {
1454 freq += cur_step * car_step;
1456 freq -= cur_step * car_step;
1459 stv090x_i2c_gate_ctrl(fe, 1);
1461 if (state->config->tuner_set_frequency)
1462 state->config->tuner_set_frequency(fe, state->frequency);
1464 if (state->config->tuner_set_bandwidth)
1465 state->config->tuner_set_bandwidth(fe, state->tuner_bw);
1467 stv090x_i2c_gate_ctrl(fe, 0);
1469 stv090x_i2c_gate_ctrl(fe, 1);
1471 if (state->config->tuner_get_status)
1472 state->config->tuner_get_status(fe, ®);
1475 dprintk(FE_DEBUG, 1, "Tuner phase locked");
1477 dprintk(FE_DEBUG, 1, "Tuner unlocked");
1479 stv090x_i2c_gate_ctrl(fe, 0);
1486 srate_coarse = stv090x_get_srate(state, state->mclk);
1488 return srate_coarse;
1490 dprintk(FE_ERROR, 1, "I/O error");
1494 static u32 stv090x_srate_srch_fine(struct stv090x_state *state)
1496 u32 srate_coarse, freq_coarse, sym, reg;
1498 srate_coarse = stv090x_get_srate(state, state->mclk);
1499 freq_coarse = STV090x_READ_DEMOD(state, CFR2) << 8;
1500 freq_coarse |= STV090x_READ_DEMOD(state, CFR1);
1501 sym = 13 * (srate_coarse / 10); /* SFRUP = SFR + 30% */
1503 if (sym < state->srate)
1506 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0) /* Demod RESET */
1508 if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0x01) < 0)
1510 if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0x20) < 0)
1512 if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0x00) < 0)
1514 if (STV090x_WRITE_DEMOD(state, TMGCFG, 0xd2) < 0)
1516 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1517 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0x00);
1518 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1521 if (state->dev_ver >= 0x20) {
1522 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x49) < 0)
1525 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0xed) < 0)
1529 if (srate_coarse > 3000000) {
1530 sym = 13 * (srate_coarse / 10); /* SFRUP = SFR + 30% */
1531 sym = (sym / 1000) * 65536;
1532 sym /= (state->mclk / 1000);
1533 if (STV090x_WRITE_DEMOD(state, SFRUP1, (sym >> 8) & 0x7f) < 0)
1535 if (STV090x_WRITE_DEMOD(state, SFRUP0, sym & 0xff) < 0)
1537 sym = 10 * (srate_coarse / 13); /* SFRLOW = SFR - 30% */
1538 sym = (sym / 1000) * 65536;
1539 sym /= (state->mclk / 1000);
1540 if (STV090x_WRITE_DEMOD(state, SFRLOW1, (sym >> 8) & 0x7f) < 0)
1542 if (STV090x_WRITE_DEMOD(state, SFRLOW0, sym & 0xff) < 0)
1544 sym = (srate_coarse / 1000) * 65536;
1545 sym /= (state->mclk / 1000);
1546 if (STV090x_WRITE_DEMOD(state, SFRINIT1, (sym >> 8) & 0xff) < 0)
1548 if (STV090x_WRITE_DEMOD(state, SFRINIT0, sym & 0xff) < 0)
1551 sym = 13 * (srate_coarse / 10); /* SFRUP = SFR + 30% */
1552 sym = (sym / 100) * 65536;
1553 sym /= (state->mclk / 100);
1554 if (STV090x_WRITE_DEMOD(state, SFRUP1, (sym >> 8) & 0x7f) < 0)
1556 if (STV090x_WRITE_DEMOD(state, SFRUP0, sym & 0xff) < 0)
1558 sym = 10 * (srate_coarse / 14); /* SFRLOW = SFR - 30% */
1559 sym = (sym / 100) * 65536;
1560 sym /= (state->mclk / 100);
1561 if (STV090x_WRITE_DEMOD(state, SFRLOW1, (sym >> 8) & 0x7f) < 0)
1563 if (STV090x_WRITE_DEMOD(state, SFRLOW0, sym & 0xff) < 0)
1565 sym = (srate_coarse / 100) * 65536;
1566 sym /= (state->mclk / 100);
1567 if (STV090x_WRITE_DEMOD(state, SFRINIT1, (sym >> 8) & 0xff) < 0)
1569 if (STV090x_WRITE_DEMOD(state, SFRINIT0, sym & 0xff) < 0)
1572 if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x20) < 0)
1574 if (STV090x_WRITE_DEMOD(state, CFRINIT1, (freq_coarse >> 8) & 0xff) < 0)
1576 if (STV090x_WRITE_DEMOD(state, CFRINIT0, freq_coarse & 0xff) < 0)
1578 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0) /* trigger acquisition */
1582 return srate_coarse;
1585 dprintk(FE_ERROR, 1, "I/O error");
1589 static int stv090x_get_dmdlock(struct stv090x_state *state, s32 timeout)
1591 s32 timer = 0, lock = 0;
1595 while ((timer < timeout) && (!lock)) {
1596 reg = STV090x_READ_DEMOD(state, DMDSTATE);
1597 stat = STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD);
1600 case 0: /* searching */
1601 case 1: /* first PLH detected */
1603 dprintk(FE_DEBUG, 1, "Demodulator searching ..");
1606 case 2: /* DVB-S2 mode */
1607 case 3: /* DVB-S1/legacy mode */
1608 reg = STV090x_READ_DEMOD(state, DSTATUS);
1609 lock = STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD);
1616 dprintk(FE_DEBUG, 1, "Demodulator acquired LOCK");
1623 static int stv090x_blind_search(struct stv090x_state *state)
1625 u32 agc2, reg, srate_coarse;
1626 s32 timeout_dmd = 500, cpt_fail, agc2_ovflw, i;
1627 u8 k_ref, k_max, k_min;
1628 int coarse_fail, lock;
1630 if (state->dev_ver < 0x20) {
1638 agc2 = stv090x_get_agc2_min_level(state);
1640 if (agc2 > STV090x_SEARCH_AGC2_TH) {
1643 if (state->dev_ver == 0x10) {
1644 if (STV090x_WRITE_DEMOD(state, CORRELEXP, 0xaa) < 0)
1647 if (state->dev_ver < 0x20) {
1648 if (STV090x_WRITE_DEMOD(state, CARHDR, 0x55) < 0)
1652 if (STV090x_WRITE_DEMOD(state, CARCFG, 0xc4) < 0)
1654 if (STV090x_WRITE_DEMOD(state, RTCS2, 0x44) < 0)
1656 if (state->dev_ver >= 0x20) {
1657 if (STV090x_WRITE_DEMOD(state, EQUALCFG, 0x41) < 0)
1659 if (STV090x_WRITE_DEMOD(state, FFECFG, 0x41) < 0)
1661 if (STV090x_WRITE_DEMOD(state, VITSCALE, 0x82) < 0)
1663 if (STV090x_WRITE_DEMOD(state, VAVSRVIT, 0x00) < 0) /* set viterbi hysteresis */
1669 if (STV090x_WRITE_DEMOD(state, KREFTMG, k_ref) < 0)
1671 if (stv090x_srate_srch_coarse(state) != 0) {
1672 srate_coarse = stv090x_srate_srch_fine(state);
1673 if (srate_coarse != 0) {
1674 stv090x_get_lock_tmg(state);
1675 lock = stv090x_get_dmdlock(state, timeout_dmd);
1682 for (i = 0; i < 10; i++) {
1683 agc2 = STV090x_READ_DEMOD(state, AGC2I1) << 8;
1684 agc2 |= STV090x_READ_DEMOD(state, AGC2I0);
1687 reg = STV090x_READ_DEMOD(state, DSTATUS2);
1688 if ((STV090x_GETFIELD_Px(reg, CFR_OVERFLOW_FIELD) == 0x01) &&
1689 (STV090x_GETFIELD_Px(reg, DEMOD_DELOCK_FIELD) == 0x01))
1693 if ((cpt_fail > 7) || (agc2_ovflw > 7))
1699 } while ((k_ref >= k_min) && (!lock) && (!coarse_fail));
1705 dprintk(FE_ERROR, 1, "I/O error");
1709 static int stv090x_chk_tmg(struct stv090x_state *state)
1713 u8 freq, tmg_thh, tmg_thl;
1716 freq = STV090x_READ_DEMOD(state, CARFREQ);
1717 tmg_thh = STV090x_READ_DEMOD(state, TMGTHRISE);
1718 tmg_thl = STV090x_READ_DEMOD(state, TMGTHFALL);
1719 if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0x20) < 0)
1721 if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0x00) < 0)
1724 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1725 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0x00); /* stop carrier offset search */
1726 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1728 if (STV090x_WRITE_DEMOD(state, RTC, 0x80) < 0)
1731 if (STV090x_WRITE_DEMOD(state, RTCS2, 0x40) < 0)
1733 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x00) < 0)
1736 if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0x00) < 0) /* set car ofset to 0 */
1738 if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0x00) < 0)
1740 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x65) < 0)
1743 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0) /* trigger acquisition */
1747 for (i = 0; i < 10; i++) {
1748 reg = STV090x_READ_DEMOD(state, DSTATUS);
1749 if (STV090x_GETFIELD_Px(reg, TMGLOCK_QUALITY_FIELD) >= 2)
1756 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
1758 if (STV090x_WRITE_DEMOD(state, RTC, 0x88) < 0) /* DVB-S1 timing */
1760 if (STV090x_WRITE_DEMOD(state, RTCS2, 0x68) < 0) /* DVB-S2 timing */
1763 if (STV090x_WRITE_DEMOD(state, CARFREQ, freq) < 0)
1765 if (STV090x_WRITE_DEMOD(state, TMGTHRISE, tmg_thh) < 0)
1767 if (STV090x_WRITE_DEMOD(state, TMGTHFALL, tmg_thl) < 0)
1773 dprintk(FE_ERROR, 1, "I/O error");
1777 static int stv090x_get_coldlock(struct stv090x_state *state, s32 timeout_dmd)
1779 struct dvb_frontend *fe = &state->frontend;
1782 s32 car_step, steps, cur_step, dir, freq, timeout_lock;
1785 if (state->srate >= 10000000)
1786 timeout_lock = timeout_dmd / 3;
1788 timeout_lock = timeout_dmd / 2;
1790 lock = stv090x_get_dmdlock(state, timeout_lock); /* cold start wait */
1792 if (state->srate >= 10000000) {
1793 if (stv090x_chk_tmg(state)) {
1794 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
1796 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0)
1798 lock = stv090x_get_dmdlock(state, timeout_dmd);
1803 if (state->srate <= 4000000)
1805 else if (state->srate <= 7000000)
1807 else if (state->srate <= 10000000)
1812 steps = (state->search_range / 1000) / car_step;
1814 steps = 2 * (steps + 1);
1817 else if (steps > 12)
1824 freq = state->frequency;
1825 state->tuner_bw = stv090x_car_width(state->srate, state->rolloff) + state->srate;
1826 while ((cur_step <= steps) && (!lock)) {
1828 freq += cur_step * car_step;
1830 freq -= cur_step * car_step;
1833 stv090x_i2c_gate_ctrl(fe, 1);
1835 if (state->config->tuner_set_frequency)
1836 state->config->tuner_set_frequency(fe, state->frequency);
1838 if (state->config->tuner_set_bandwidth)
1839 state->config->tuner_set_bandwidth(fe, state->tuner_bw);
1841 stv090x_i2c_gate_ctrl(fe, 0);
1845 stv090x_i2c_gate_ctrl(fe, 1);
1847 if (state->config->tuner_get_status)
1848 state->config->tuner_get_status(fe, ®);
1851 dprintk(FE_DEBUG, 1, "Tuner phase locked");
1853 dprintk(FE_DEBUG, 1, "Tuner unlocked");
1855 stv090x_i2c_gate_ctrl(fe, 0);
1857 STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1c);
1858 if (state->delsys == STV090x_DVBS2) {
1859 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1860 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 0);
1861 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
1862 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1864 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
1865 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
1866 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1869 if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0x00) < 0)
1871 if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0x00) < 0)
1873 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
1875 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0)
1877 lock = stv090x_get_dmdlock(state, (timeout_dmd / 3));
1889 dprintk(FE_ERROR, 1, "I/O error");
1893 static int stv090x_get_loop_params(struct stv090x_state *state, s32 *freq_inc, s32 *timeout_sw, s32 *steps)
1895 s32 timeout, inc, steps_max, srate, car_max;
1897 srate = state->srate;
1898 car_max = state->search_range / 1000;
1899 car_max = 65536 * (car_max / 2);
1900 car_max /= (state->mclk / 1000);
1902 if (car_max > 0x4000)
1903 car_max = 0x4000 ; /* maxcarrier should be<= +-1/4 Mclk */
1906 inc /= state->mclk / 1000;
1911 switch (state->algo) {
1912 case STV090x_SEARCH_DVBS1:
1913 case STV090x_SEARCH_DSS:
1914 inc *= 3; /* freq step = 3% of srate */
1918 case STV090x_SEARCH_DVBS2:
1923 case STV090x_SEARCH_AUTO:
1930 if ((inc > car_max) || (inc < 0))
1931 inc = car_max / 2; /* increment <= 1/8 Mclk */
1933 timeout *= 27500; /* 27.5 Msps reference */
1935 timeout /= (srate / 1000);
1937 if ((timeout > 100) || (timeout < 0))
1940 steps_max = (car_max / inc) + 1; /* min steps = 3 */
1941 if ((steps_max > 100) || (steps_max < 0)) {
1942 steps_max = 100; /* max steps <= 100 */
1943 inc = car_max / steps_max;
1946 *timeout_sw = timeout;
1952 static int stv090x_chk_signal(struct stv090x_state *state)
1954 s32 offst_car, agc2, car_max;
1957 offst_car = STV090x_READ_DEMOD(state, CFR2) << 8;
1958 offst_car |= STV090x_READ_DEMOD(state, CFR1);
1960 agc2 = STV090x_READ_DEMOD(state, AGC2I1) << 8;
1961 agc2 |= STV090x_READ_DEMOD(state, AGC2I0);
1962 car_max = state->search_range / 1000;
1964 car_max += (car_max / 10); /* 10% margin */
1965 car_max = (65536 * car_max / 2);
1966 car_max /= state->mclk / 1000;
1968 if (car_max > 0x4000)
1971 if ((agc2 > 0x2000) || (offst_car > 2 * car_max) || (offst_car < -2 * car_max)) {
1973 dprintk(FE_DEBUG, 1, "No Signal");
1976 dprintk(FE_DEBUG, 1, "Found Signal");
1982 static int stv090x_search_car_loop(struct stv090x_state *state, s32 inc, s32 timeout, int zigzag, s32 steps_max)
1984 int no_signal, lock = 0;
1985 s32 cpt_step, offst_freq, car_max;
1988 car_max = state->search_range / 1000;
1989 car_max += (car_max / 10);
1990 car_max = (65536 * car_max / 2);
1991 car_max /= (state->mclk / 1000);
1992 if (car_max > 0x4000)
1998 offst_freq = -car_max + inc;
2002 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1c) < 0)
2004 if (STV090x_WRITE_DEMOD(state, CFRINIT1, ((offst_freq / 256) & 0xff)) < 0)
2006 if (STV090x_WRITE_DEMOD(state, CFRINIT0, offst_freq & 0xff) < 0)
2008 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0)
2011 reg = STV090x_READ_DEMOD(state, PDELCTRL1);
2012 STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0x1); /* stop DVB-S2 packet delin */
2013 if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
2016 if (state->dev_ver == 0x12) {
2017 reg = STV090x_READ_DEMOD(state, TSCFGH);
2018 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x1);
2019 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
2024 if (offst_freq >= 0)
2025 offst_freq = -offst_freq - 2 * inc;
2027 offst_freq = -offst_freq;
2029 offst_freq += 2 * inc;
2032 lock = stv090x_get_dmdlock(state, timeout);
2033 no_signal = stv090x_chk_signal(state);
2037 ((offst_freq - inc) < car_max) &&
2038 ((offst_freq + inc) > -car_max) &&
2039 (cpt_step < steps_max));
2041 reg = STV090x_READ_DEMOD(state, PDELCTRL1);
2042 STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0);
2043 if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
2048 dprintk(FE_ERROR, 1, "I/O error");
2052 static int stv090x_sw_algo(struct stv090x_state *state)
2054 int no_signal, zigzag, lock = 0;
2057 s32 dvbs2_fly_wheel;
2058 s32 inc, timeout_step, trials, steps_max;
2060 stv090x_get_loop_params(state, &inc, &timeout_step, &steps_max); /* get params */
2062 switch (state->algo) {
2063 case STV090x_SEARCH_DVBS1:
2064 case STV090x_SEARCH_DSS:
2065 /* accelerate the frequency detector */
2066 if (state->dev_ver >= 0x20) {
2067 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x3B) < 0)
2070 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0xef) < 0)
2073 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x49) < 0)
2078 case STV090x_SEARCH_DVBS2:
2079 if (state->dev_ver >= 0x20) {
2080 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x79) < 0)
2083 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x68) < 0)
2086 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x89) < 0)
2091 case STV090x_SEARCH_AUTO:
2093 /* accelerate the frequency detector */
2094 if (state->dev_ver >= 0x20) {
2095 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x3b) < 0)
2097 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x79) < 0)
2100 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0xef) < 0)
2102 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x68) < 0)
2105 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x69) < 0)
2113 lock = stv090x_search_car_loop(state, inc, timeout_step, zigzag, steps_max);
2114 no_signal = stv090x_chk_signal(state);
2117 /*run the SW search 2 times maximum*/
2118 if (lock || no_signal || (trials == 2)) {
2119 /*Check if the demod is not losing lock in DVBS2*/
2120 if (state->dev_ver >= 0x20) {
2121 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x49) < 0)
2123 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x9e) < 0)
2126 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0xed) < 0)
2128 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x88) < 0)
2132 reg = STV090x_READ_DEMOD(state, DMDSTATE);
2133 if ((lock) && (STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD) == STV090x_DVBS2)) {
2134 /*Check if the demod is not losing lock in DVBS2*/
2135 msleep(timeout_step);
2136 reg = STV090x_READ_DEMOD(state, DMDFLYW);
2137 dvbs2_fly_wheel = STV090x_GETFIELD_Px(reg, FLYWHEEL_CPT_FIELD);
2138 if (dvbs2_fly_wheel < 0xd) { /*if correct frames is decrementing */
2139 msleep(timeout_step);
2140 reg = STV090x_READ_DEMOD(state, DMDFLYW);
2141 dvbs2_fly_wheel = STV090x_GETFIELD_Px(reg, FLYWHEEL_CPT_FIELD);
2143 if (dvbs2_fly_wheel < 0xd) {
2144 /*FALSE lock, The demod is loosing lock */
2147 if (state->dev_ver >= 0x20) {
2148 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x79) < 0)
2151 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x68) < 0)
2154 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x89) < 0)
2160 } while ((!lock) && (trials < 2) && (!no_signal));
2164 dprintk(FE_ERROR, 1, "I/O error");
2168 static enum stv090x_delsys stv090x_get_std(struct stv090x_state *state)
2171 enum stv090x_delsys delsys;
2173 reg = STV090x_READ_DEMOD(state, DMDSTATE);
2174 if (STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD) == 2)
2175 delsys = STV090x_DVBS2;
2176 else if (STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD) == 3) {
2177 reg = STV090x_READ_DEMOD(state, FECM);
2178 if (STV090x_GETFIELD_Px(reg, DSS_DVB_FIELD) == 1)
2179 delsys = STV090x_DSS;
2181 delsys = STV090x_DVBS1;
2183 delsys = STV090x_ERROR;
2190 static s32 stv090x_get_car_freq(struct stv090x_state *state, u32 mclk)
2192 s32 derot, int_1, int_2, tmp_1, tmp_2;
2195 derot = STV090x_READ_DEMOD(state, CFR2) << 16;
2196 derot |= STV090x_READ_DEMOD(state, CFR1) << 8;
2197 derot |= STV090x_READ_DEMOD(state, CFR0);
2199 derot = comp2(derot, 24);
2201 int_1 = state->mclk / pow2;
2202 int_2 = derot / pow2;
2204 tmp_1 = state->mclk % pow2;
2205 tmp_2 = derot % pow2;
2207 derot = (int_1 * int_2) +
2208 ((int_1 * tmp_2) / pow2) +
2209 ((int_1 * tmp_1) / pow2);
2214 static int stv090x_get_viterbi(struct stv090x_state *state)
2218 reg = STV090x_READ_DEMOD(state, VITCURPUN);
2219 rate = STV090x_GETFIELD_Px(reg, VIT_CURPUN_FIELD);
2223 state->fec = STV090x_PR12;
2227 state->fec = STV090x_PR23;
2231 state->fec = STV090x_PR34;
2235 state->fec = STV090x_PR56;
2239 state->fec = STV090x_PR67;
2243 state->fec = STV090x_PR78;
2247 state->fec = STV090x_PRERR;
2254 static enum stv090x_signal_state stv090x_get_sig_params(struct stv090x_state *state)
2256 struct dvb_frontend *fe = &state->frontend;
2260 s32 i = 0, offst_freq;
2264 if (state->algo == STV090x_BLIND_SEARCH) {
2265 tmg = STV090x_READ_DEMOD(state, TMGREG2);
2266 STV090x_WRITE_DEMOD(state, SFRSTEP, 0x5c);
2267 while ((i <= 50) && (!tmg) && (tmg != 0xff)) {
2268 tmg = STV090x_READ_DEMOD(state, TMGREG2);
2273 state->delsys = stv090x_get_std(state);
2275 stv090x_i2c_gate_ctrl(fe, 1);
2277 if (state->config->tuner_get_frequency)
2278 state->config->tuner_get_frequency(fe, &state->frequency);
2280 stv090x_i2c_gate_ctrl(fe, 0);
2282 offst_freq = stv090x_get_car_freq(state, state->mclk) / 1000;
2283 state->frequency += offst_freq;
2284 stv090x_get_viterbi(state);
2285 reg = STV090x_READ_DEMOD(state, DMDMODCOD);
2286 state->modcod = STV090x_GETFIELD_Px(reg, DEMOD_MODCOD_FIELD);
2287 state->pilots = STV090x_GETFIELD_Px(reg, DEMOD_TYPE_FIELD) & 0x01;
2288 state->frame_len = STV090x_GETFIELD_Px(reg, DEMOD_TYPE_FIELD) >> 1;
2289 reg = STV090x_READ_DEMOD(state, TMGOBS);
2290 state->rolloff = STV090x_GETFIELD_Px(reg, ROLLOFF_STATUS_FIELD);
2291 reg = STV090x_READ_DEMOD(state, FECM);
2292 state->inversion = STV090x_GETFIELD_Px(reg, IQINV_FIELD);
2294 if ((state->algo == STV090x_BLIND_SEARCH) || (state->srate < 10000000)) {
2296 stv090x_i2c_gate_ctrl(fe, 1);
2298 if (state->config->tuner_get_frequency)
2299 state->config->tuner_get_frequency(fe, &state->frequency);
2301 stv090x_i2c_gate_ctrl(fe, 0);
2303 if (abs(offst_freq) <= ((state->search_range / 2000) + 500))
2304 return STV090x_RANGEOK;
2305 else if (abs(offst_freq) <= (stv090x_car_width(state->srate, state->rolloff) / 2000))
2306 return STV090x_RANGEOK;
2308 return STV090x_OUTOFRANGE; /* Out of Range */
2310 if (abs(offst_freq) <= ((state->search_range / 2000) + 500))
2311 return STV090x_RANGEOK;
2313 return STV090x_OUTOFRANGE;
2316 return STV090x_OUTOFRANGE;
2319 static u32 stv090x_get_tmgoffst(struct stv090x_state *state, u32 srate)
2324 offst_tmg = STV090x_READ_DEMOD(state, TMGREG2) << 16;
2325 offst_tmg |= STV090x_READ_DEMOD(state, TMGREG1) << 8;
2326 offst_tmg |= STV090x_READ_DEMOD(state, TMGREG0);
2330 offst_tmg = comp2(offst_tmg, 24); /* 2's complement */
2334 offst_tmg = ((s32) srate * 10) / (pow2 / offst_tmg);
2340 static u8 stv090x_optimize_carloop(struct stv090x_state *state, enum stv090x_modcod modcod, s32 pilots)
2344 struct stv090x_long_frame_crloop *car_loop;
2346 if (state->dev_ver <= 0x12)
2347 car_loop = stv090x_s2_crl;
2348 else if (state->dev_ver == 0x20)
2349 car_loop = stv090x_s2_crl_cut20;
2351 car_loop = stv090x_s2_crl;
2354 if (modcod < STV090x_QPSK_12) {
2356 while ((i < 3) && (modcod != stv090x_s2_lowqpsk_crl_cut20[i].modcod))
2364 while ((i < 14) && (modcod != car_loop[i].modcod))
2369 while ((i < 11) && (modcod != stv090x_s2_lowqpsk_crl_cut20[i].modcod))
2377 if (modcod <= STV090x_QPSK_25) {
2379 if (state->srate <= 3000000)
2380 aclc = stv090x_s2_lowqpsk_crl_cut20[i].crl_pilots_on_2;
2381 else if (state->srate <= 7000000)
2382 aclc = stv090x_s2_lowqpsk_crl_cut20[i].crl_pilots_on_5;
2383 else if (state->srate <= 15000000)
2384 aclc = stv090x_s2_lowqpsk_crl_cut20[i].crl_pilots_on_10;
2385 else if (state->srate <= 25000000)
2386 aclc = stv090x_s2_lowqpsk_crl_cut20[i].crl_pilots_on_20;
2388 aclc = stv090x_s2_lowqpsk_crl_cut20[i].crl_pilots_on_30;
2390 if (state->srate <= 3000000)
2391 aclc = stv090x_s2_lowqpsk_crl_cut20[i].crl_pilots_off_2;
2392 else if (state->srate <= 7000000)
2393 aclc = stv090x_s2_lowqpsk_crl_cut20[i].crl_pilots_off_5;
2394 else if (state->srate <= 15000000)
2395 aclc = stv090x_s2_lowqpsk_crl_cut20[i].crl_pilots_off_10;
2396 else if (state->srate <= 25000000)
2397 aclc = stv090x_s2_lowqpsk_crl_cut20[i].crl_pilots_off_20;
2399 aclc = stv090x_s2_lowqpsk_crl_cut20[i].crl_pilots_off_30;
2402 } else if (modcod <= STV090x_8PSK_910) {
2404 if (state->srate <= 3000000)
2405 aclc = car_loop[i].crl_pilots_on_2;
2406 else if (state->srate <= 7000000)
2407 aclc = car_loop[i].crl_pilots_on_5;
2408 else if (state->srate <= 15000000)
2409 aclc = car_loop[i].crl_pilots_on_10;
2410 else if (state->srate <= 25000000)
2411 aclc = car_loop[i].crl_pilots_on_20;
2413 aclc = car_loop[i].crl_pilots_on_30;
2415 if (state->srate <= 3000000)
2416 aclc = car_loop[i].crl_pilots_off_2;
2417 else if (state->srate <= 7000000)
2418 aclc = car_loop[i].crl_pilots_off_5;
2419 else if (state->srate <= 15000000)
2420 aclc = car_loop[i].crl_pilots_off_10;
2421 else if (state->srate <= 25000000)
2422 aclc = car_loop[i].crl_pilots_off_20;
2424 aclc = car_loop[i].crl_pilots_off_30;
2426 } else { /* 16APSK and 32APSK */
2427 if (state->srate <= 3000000)
2428 aclc = stv090x_s2_apsk_crl_cut20[i].crl_pilots_on_2;
2429 else if (state->srate <= 7000000)
2430 aclc = stv090x_s2_apsk_crl_cut20[i].crl_pilots_on_5;
2431 else if (state->srate <= 15000000)
2432 aclc = stv090x_s2_apsk_crl_cut20[i].crl_pilots_on_10;
2433 else if (state->srate <= 25000000)
2434 aclc = stv090x_s2_apsk_crl_cut20[i].crl_pilots_on_20;
2436 aclc = stv090x_s2_apsk_crl_cut20[i].crl_pilots_on_30;
2442 static u8 stv090x_optimize_carloop_short(struct stv090x_state *state)
2447 switch (state->modulation) {
2455 case STV090x_16APSK:
2458 case STV090x_32APSK:
2463 switch (state->dev_ver) {
2465 if (state->srate <= 3000000)
2466 aclc = stv090x_s2_short_crl[index].crl_cut20_2;
2467 else if (state->srate <= 7000000)
2468 aclc = stv090x_s2_short_crl[index].crl_cut20_5;
2469 else if (state->srate <= 15000000)
2470 aclc = stv090x_s2_short_crl[index].crl_cut20_10;
2471 else if (state->srate <= 25000000)
2472 aclc = stv090x_s2_short_crl[index].crl_cut20_20;
2474 aclc = stv090x_s2_short_crl[index].crl_cut20_30;
2479 if (state->srate <= 3000000)
2480 aclc = stv090x_s2_short_crl[index].crl_cut12_2;
2481 else if (state->srate <= 7000000)
2482 aclc = stv090x_s2_short_crl[index].crl_cut12_5;
2483 else if (state->srate <= 15000000)
2484 aclc = stv090x_s2_short_crl[index].crl_cut12_10;
2485 else if (state->srate <= 25000000)
2486 aclc = stv090x_s2_short_crl[index].crl_cut12_20;
2488 aclc = stv090x_s2_short_crl[index].crl_cut12_30;
2495 static int stv090x_optimize_track(struct stv090x_state *state)
2497 struct dvb_frontend *fe = &state->frontend;
2499 enum stv090x_rolloff rolloff;
2500 enum stv090x_modcod modcod;
2502 s32 srate, pilots, aclc, f_1, f_0, i = 0, blind_tune = 0;
2505 srate = stv090x_get_srate(state, state->mclk);
2506 srate += stv090x_get_tmgoffst(state, srate);
2508 switch (state->delsys) {
2511 if (state->algo == STV090x_SEARCH_AUTO) {
2512 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
2513 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
2514 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
2515 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
2518 reg = STV090x_READ_DEMOD(state, DEMOD);
2519 STV090x_SETFIELD_Px(reg, ROLLOFF_CONTROL_FIELD, state->rolloff);
2520 STV090x_SETFIELD_Px(reg, MANUAL_ROLLOFF_FIELD, 0x01);
2521 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
2523 if (STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x75) < 0)
2528 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
2529 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
2530 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
2531 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
2533 if (STV090x_WRITE_DEMOD(state, ACLC, 0) < 0)
2535 if (STV090x_WRITE_DEMOD(state, BCLC, 0) < 0)
2537 if (state->frame_len == STV090x_LONG_FRAME) {
2538 reg = STV090x_READ_DEMOD(state, DMDMODCOD);
2539 modcod = STV090x_GETFIELD_Px(reg, DEMOD_MODCOD_FIELD);
2540 pilots = STV090x_GETFIELD_Px(reg, DEMOD_TYPE_FIELD) & 0x01;
2541 aclc = stv090x_optimize_carloop(state, modcod, pilots);
2542 if (modcod <= STV090x_QPSK_910) {
2543 STV090x_WRITE_DEMOD(state, ACLC2S2Q, aclc);
2544 } else if (modcod <= STV090x_8PSK_910) {
2545 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
2547 if (STV090x_WRITE_DEMOD(state, ACLC2S28, aclc) < 0)
2550 if ((state->demod_mode == STV090x_SINGLE) && (modcod > STV090x_8PSK_910)) {
2551 if (modcod <= STV090x_16APSK_910) {
2552 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
2554 if (STV090x_WRITE_DEMOD(state, ACLC2S216A, aclc) < 0)
2557 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
2559 if (STV090x_WRITE_DEMOD(state, ACLC2S232A, aclc) < 0)
2564 /*Carrier loop setting for short frame*/
2565 aclc = stv090x_optimize_carloop_short(state);
2566 if (state->modulation == STV090x_QPSK) {
2567 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, aclc) < 0)
2569 } else if (state->modulation == STV090x_8PSK) {
2570 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
2572 if (STV090x_WRITE_DEMOD(state, ACLC2S28, aclc) < 0)
2574 } else if (state->modulation == STV090x_16APSK) {
2575 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
2577 if (STV090x_WRITE_DEMOD(state, ACLC2S216A, aclc) < 0)
2579 } else if (state->modulation == STV090x_32APSK) {
2580 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
2582 if (STV090x_WRITE_DEMOD(state, ACLC2S232A, aclc) < 0)
2586 if (state->dev_ver <= 0x11) {
2587 if (state->demod_mode != STV090x_SINGLE)
2588 stv090x_activate_modcod(state); /* link to LDPC after demod LOCK */
2590 STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x67); /* PER */
2593 case STV090x_UNKNOWN:
2595 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
2596 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
2597 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
2598 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
2603 f_1 = STV090x_READ_DEMOD(state, CFR2);
2604 f_0 = STV090x_READ_DEMOD(state, CFR1);
2605 reg = STV090x_READ_DEMOD(state, TMGOBS);
2606 rolloff = STV090x_GETFIELD_Px(reg, ROLLOFF_STATUS_FIELD);
2608 if (state->algo == STV090x_BLIND_SEARCH) {
2609 STV090x_WRITE_DEMOD(state, SFRSTEP, 0x00);
2610 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
2611 STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 0x00);
2612 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0x00);
2613 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
2615 if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0x01) < 0)
2617 stv090x_set_srate(state, srate);
2618 stv090x_set_max_srate(state, state->mclk, srate);
2619 stv090x_set_min_srate(state, state->mclk, srate);
2623 if (state->dev_ver >= 0x20) {
2624 if ((state->search_mode == STV090x_SEARCH_DVBS1) ||
2625 (state->search_mode == STV090x_SEARCH_DSS) ||
2626 (state->search_mode == STV090x_SEARCH_AUTO)) {
2628 if (STV090x_WRITE_DEMOD(state, VAVSRVIT, 0x0a) < 0)
2630 if (STV090x_WRITE_DEMOD(state, VITSCALE, 0x00) < 0)
2635 if (state->dev_ver < 0x20) {
2636 if (STV090x_WRITE_DEMOD(state, CARHDR, 0x08) < 0)
2639 if (state->dev_ver == 0x10) {
2640 if (STV090x_WRITE_DEMOD(state, CORRELEXP, 0x0a) < 0)
2644 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
2647 if ((state->dev_ver >= 0x20) || (blind_tune == 1) || (state->srate < 10000000)) {
2649 if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0)
2651 if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_0) < 0)
2653 state->tuner_bw = stv090x_car_width(srate, state->rolloff) + 10000000;
2655 if ((state->dev_ver >= 0x20) || (blind_tune == 1)) {
2657 if (state->algo != STV090x_WARM_SEARCH) {
2659 stv090x_i2c_gate_ctrl(fe, 1);
2661 if (state->config->tuner_set_bandwidth)
2662 state->config->tuner_set_bandwidth(fe, state->tuner_bw);
2664 stv090x_i2c_gate_ctrl(fe, 0);
2668 if ((state->algo == STV090x_BLIND_SEARCH) || (state->srate < 10000000))
2669 msleep(50); /* blind search: wait 50ms for SR stabilization */
2673 stv090x_get_lock_tmg(state);
2675 if (!(stv090x_get_dmdlock(state, (state->DemodTimeout / 2)))) {
2676 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
2678 if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0)
2680 if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_0) < 0)
2682 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0)
2687 while ((!(stv090x_get_dmdlock(state, (state->DemodTimeout / 2)))) && (i <= 2)) {
2689 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
2691 if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0)
2693 if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_0) < 0)
2695 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0)
2703 if (state->dev_ver >= 0x20) {
2704 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x49) < 0)
2707 if ((state->delsys == STV090x_DVBS1) || (state->delsys == STV090x_DSS))
2708 stv090x_set_vit_thtracq(state);
2712 dprintk(FE_ERROR, 1, "I/O error");
2716 static int stv090x_get_feclock(struct stv090x_state *state, s32 timeout)
2718 s32 timer = 0, lock = 0, stat;
2721 while ((timer < timeout) && (!lock)) {
2722 reg = STV090x_READ_DEMOD(state, DMDSTATE);
2723 stat = STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD);
2726 case 0: /* searching */
2727 case 1: /* first PLH detected */
2732 case 2: /* DVB-S2 mode */
2733 reg = STV090x_READ_DEMOD(state, PDELSTATUS1);
2734 lock = STV090x_GETFIELD_Px(reg, PKTDELIN_LOCK_FIELD);
2737 case 3: /* DVB-S1/legacy mode */
2738 reg = STV090x_READ_DEMOD(state, VSTATUSVIT);
2739 lock = STV090x_GETFIELD_Px(reg, LOCKEDVIT_FIELD);
2750 static int stv090x_get_lock(struct stv090x_state *state, s32 timeout_dmd, s32 timeout_fec)
2756 lock = stv090x_get_dmdlock(state, timeout_dmd);
2758 lock = stv090x_get_feclock(state, timeout_fec);
2763 while ((timer < timeout_fec) && (!lock)) {
2764 reg = STV090x_READ_DEMOD(state, TSSTATUS);
2765 lock = STV090x_GETFIELD_Px(reg, TSFIFO_LINEOK_FIELD);
2774 static int stv090x_set_s2rolloff(struct stv090x_state *state)
2779 if (state->dev_ver == 0x10) {
2780 reg = STV090x_READ_DEMOD(state, DEMOD);
2781 STV090x_SETFIELD_Px(reg, MANUAL_ROLLOFF_FIELD, 0x01);
2782 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
2784 rolloff = STV090x_READ_DEMOD(state, MATSTR1) & 0x03;
2785 reg = STV090x_READ_DEMOD(state, DEMOD);
2786 STV090x_SETFIELD_Px(reg, ROLLOFF_CONTROL_FIELD, reg);
2787 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
2790 reg = STV090x_READ_DEMOD(state, DEMOD);
2791 STV090x_SETFIELD_Px(reg, MANUAL_ROLLOFF_FIELD, 0x00);
2792 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
2797 dprintk(FE_ERROR, 1, "I/O error");
2801 static enum stv090x_signal_state stv090x_acq_fixs1(struct stv090x_state *state)
2803 s32 srate, f_1, f_2;
2804 enum stv090x_signal_state signal_state = STV090x_NODATA;
2808 reg = STV090x_READ_DEMOD(state, DMDSTATE);
2809 if (STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD) == 3) { /* DVB-S mode */
2810 srate = stv090x_get_srate(state, state->mclk);
2811 srate += stv090x_get_tmgoffst(state, state->srate);
2813 if (state->algo == STV090x_BLIND_SEARCH)
2814 stv090x_set_srate(state, state->srate);
2816 stv090x_get_lock_tmg(state);
2818 f_1 = STV090x_READ_DEMOD(state, CFR2);
2819 f_2 = STV090x_READ_DEMOD(state, CFR1);
2821 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
2822 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0);
2823 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
2826 reg = STV090x_READ_DEMOD(state, DEMOD);
2827 STV090x_SETFIELD_Px(reg, SPECINV_CONTROL_FIELD, STV090x_IQ_SWAP);
2828 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
2830 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1c) < 0) /* stop demod */
2832 if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0)
2834 if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_2) < 0)
2836 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0) /* warm start trigger */
2839 if (stv090x_get_lock(state, state->DemodTimeout, state->FecTimeout)) {
2841 stv090x_get_sig_params(state);
2842 stv090x_optimize_track(state);
2844 reg = STV090x_READ_DEMOD(state, DEMOD);
2845 STV090x_SETFIELD_Px(reg, SPECINV_CONTROL_FIELD, STV090x_IQ_NORMAL);
2846 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
2848 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1c) < 0)
2850 if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0)
2852 if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_2) < 0)
2854 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0) /* warm start trigger */
2856 if (stv090x_get_lock(state, state->DemodTimeout, state->FecTimeout)) {
2858 signal_state = stv090x_get_sig_params(state);
2859 stv090x_optimize_track(state);
2866 return signal_state;
2869 dprintk(FE_ERROR, 1, "I/O error");
2873 static enum stv090x_signal_state stv090x_algo(struct stv090x_state *state)
2875 struct dvb_frontend *fe = &state->frontend;
2876 enum stv090x_signal_state signal_state = STV090x_NOCARRIER;
2878 s32 timeout_dmd = 500, timeout_fec = 50;
2879 int lock = 0, low_sr, no_signal = 0;
2881 reg = STV090x_READ_DEMOD(state, TSCFGH);
2882 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 1); /* Stop path 1 stream merger */
2883 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
2886 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5c) < 0) /* Demod stop */
2889 if (state->dev_ver >= 0x20) {
2890 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x9e) < 0) /* cut 2.0 */
2893 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x88) < 0) /* cut 1.x */
2897 stv090x_get_lock_tmg(state);
2899 if (state->algo == STV090x_BLIND_SEARCH) {
2900 state->tuner_bw = 2 * 36000000; /* wide bw for unknown srate */
2901 if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0x00) < 0) /* wider srate scan */
2903 stv090x_set_srate(state, 1000000); /* inital srate = 1Msps */
2906 if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x20) < 0)
2908 if (STV090x_WRITE_DEMOD(state, TMGCFG, 0xd2) < 0)
2911 if (state->srate >= 10000000) {
2912 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0) /* High SR */
2915 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x60) < 0) /* Low SR */
2919 if (state->dev_ver >= 0x20) {
2920 if (STV090x_WRITE_DEMOD(state, KREFTMG, 0x5a) < 0)
2922 if (state->algo == STV090x_COLD_SEARCH)
2923 state->tuner_bw = (15 * (stv090x_car_width(state->srate, state->rolloff) + 1000000)) / 10;
2924 else if (state->algo == STV090x_WARM_SEARCH)
2925 state->tuner_bw = stv090x_car_width(state->srate, state->rolloff) + 10000000;
2927 if (STV090x_WRITE_DEMOD(state, KREFTMG, 0xc1) < 0)
2929 state->tuner_bw = (15 * (stv090x_car_width(state->srate, state->rolloff) + 10000000)) / 10;
2931 if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0x01) < 0) /* narrow srate scan */
2933 stv090x_set_srate(state, state->srate);
2934 stv090x_set_max_srate(state, state->mclk, state->srate);
2935 stv090x_set_min_srate(state, state->mclk, state->srate);
2937 if (state->srate >= 10000000)
2942 stv090x_i2c_gate_ctrl(fe, 1);
2944 if (state->config->tuner_set_bbgain)
2945 state->config->tuner_set_bbgain(fe, 10); /* 10dB */
2947 if (state->config->tuner_set_frequency)
2948 state->config->tuner_set_frequency(fe, state->frequency);
2950 if (state->config->tuner_set_bandwidth)
2951 state->config->tuner_set_bandwidth(fe, state->tuner_bw);
2953 stv090x_i2c_gate_ctrl(fe, 0);
2957 stv090x_i2c_gate_ctrl(fe, 1);
2959 if (state->config->tuner_get_status)
2960 state->config->tuner_get_status(fe, ®);
2963 dprintk(FE_DEBUG, 1, "Tuner phase locked");
2965 dprintk(FE_DEBUG, 1, "Tuner unlocked");
2967 stv090x_i2c_gate_ctrl(fe, 0);
2969 reg = STV090x_READ_DEMOD(state, DEMOD);
2970 STV090x_SETFIELD_Px(reg, SPECINV_CONTROL_FIELD, state->inversion);
2971 STV090x_SETFIELD_Px(reg, MANUAL_ROLLOFF_FIELD, 1);
2972 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
2974 stv090x_delivery_search(state);
2975 if (state->algo == STV090x_BLIND_SEARCH)
2976 stv090x_start_search(state);
2978 if (state->dev_ver == 0x12) {
2979 reg = STV090x_READ_DEMOD(state, TSCFGH);
2980 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0); /* release merger reset */
2981 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
2984 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 1); /* merger reset */
2985 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
2987 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0); /* release merger reset */
2988 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
2992 if (state->algo == STV090x_BLIND_SEARCH)
2993 lock = stv090x_blind_search(state);
2994 else if (state->algo == STV090x_COLD_SEARCH)
2995 lock = stv090x_get_coldlock(state, timeout_dmd);
2996 else if (state->algo == STV090x_WARM_SEARCH)
2997 lock = stv090x_get_dmdlock(state, timeout_dmd);
2999 if ((!lock) && (state->algo == STV090x_COLD_SEARCH)) {
3001 if (stv090x_chk_tmg(state))
3002 lock = stv090x_sw_algo(state);
3007 signal_state = stv090x_get_sig_params(state);
3009 if ((lock) && (signal_state == STV090x_RANGEOK)) { /* signal within Range */
3010 stv090x_optimize_track(state);
3011 if (state->dev_ver <= 0x11) { /*workaround for dual DVBS1 cut 1.1 and 1.0 only*/
3012 if (stv090x_get_std(state) == STV090x_DVBS1) {
3014 reg = STV090x_READ_DEMOD(state, TSCFGH);
3015 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0); /* release merger reset */
3016 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
3019 reg = STV090x_READ_DEMOD(state, TSCFGH);
3020 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0); /* release merger reset */
3021 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
3024 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 1); /* merger reset */
3025 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
3027 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0); /* release merger reset */
3028 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
3031 } else if (state->dev_ver == 0x20) { /*cut 2.0 :release TS reset after demod lock and TrackingOptimization*/
3032 reg = STV090x_READ_DEMOD(state, TSCFGH);
3033 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0); /* release merger reset */
3034 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
3037 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 1); /* merger reset */
3038 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
3041 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0); /* release merger reset */
3042 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
3046 if (stv090x_get_lock(state, timeout_fec, timeout_fec)) {
3048 if (state->delsys == STV090x_DVBS2) {
3049 stv090x_set_s2rolloff(state);
3050 if (STV090x_WRITE_DEMOD(state, PDELCTRL2, 0x40) < 0)
3052 if (STV090x_WRITE_DEMOD(state, PDELCTRL2, 0x00) < 0) /* RESET counter */
3054 if (STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x67) < 0) /* PER */
3057 if (STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x75) < 0)
3060 if (STV090x_WRITE_DEMOD(state, FBERCPT4, 0x00) < 0)
3062 if (STV090x_WRITE_DEMOD(state, ERRCTRL2, 0xc1) < 0)
3066 signal_state = STV090x_NODATA;
3067 no_signal = stv090x_chk_signal(state);
3070 if ((signal_state == STV090x_NODATA) && (!no_signal)) {
3071 if (state->dev_ver <= 0x11) {
3072 reg = STV090x_READ_DEMOD(state, DMDSTATE);
3073 if (((STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD)) == STV090x_DVBS2) && (state->inversion == INVERSION_AUTO))
3074 signal_state = stv090x_acq_fixs1(state);
3077 return signal_state;
3080 dprintk(FE_ERROR, 1, "I/O error");
3084 static enum dvbfe_search stv090x_search(struct dvb_frontend *fe, struct dvb_frontend_parameters *p)
3086 struct stv090x_state *state = fe->demodulator_priv;
3087 struct dtv_frontend_properties *props = &fe->dtv_property_cache;
3089 state->delsys = props->delivery_system;
3090 state->frequency = p->frequency;
3091 state->srate = p->u.qpsk.symbol_rate;
3093 if (!stv090x_algo(state)) {
3094 dprintk(FE_DEBUG, 1, "Search success!");
3095 return DVBFE_ALGO_SEARCH_SUCCESS;
3097 dprintk(FE_DEBUG, 1, "Search failed!");
3098 return DVBFE_ALGO_SEARCH_FAILED;
3101 return DVBFE_ALGO_SEARCH_ERROR;
3105 static int stv090x_read_status(struct dvb_frontend *fe, enum fe_status *status)
3107 struct stv090x_state *state = fe->demodulator_priv;
3112 reg = STV090x_READ_DEMOD(state, DMDSTATE);
3113 search_state = STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD);
3115 switch (search_state) {
3116 case 0: /* searching */
3117 case 1: /* first PLH detected */
3119 dprintk(FE_DEBUG, 1, "Status: Unlocked (Searching ..)");
3123 case 2: /* DVB-S2 mode */
3124 dprintk(FE_DEBUG, 1, "Delivery system: DVB-S2");
3125 reg = STV090x_READ_DEMOD(state, DSTATUS);
3126 if (STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD)) {
3127 reg = STV090x_READ_DEMOD(state, TSSTATUS);
3128 if (STV090x_GETFIELD_Px(reg, TSFIFO_LINEOK_FIELD)) {
3130 *status = FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
3135 case 3: /* DVB-S1/legacy mode */
3136 dprintk(FE_DEBUG, 1, "Delivery system: DVB-S");
3137 reg = STV090x_READ_DEMOD(state, DSTATUS);
3138 if (STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD)) {
3139 reg = STV090x_READ_DEMOD(state, VSTATUSVIT);
3140 if (STV090x_GETFIELD_Px(reg, LOCKEDVIT_FIELD)) {
3141 reg = STV090x_READ_DEMOD(state, TSSTATUS);
3142 if (STV090x_GETFIELD_Px(reg, TSFIFO_LINEOK_FIELD)) {
3144 *status = FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
3154 static int stv090x_read_per(struct dvb_frontend *fe, u32 *per)
3156 struct stv090x_state *state = fe->demodulator_priv;
3158 s32 count_4, count_3, count_2, count_1, count_0, count;
3160 enum fe_status status;
3162 if (!stv090x_read_status(fe, &status)) {
3163 *per = 1 << 23; /* Max PER */
3166 reg = STV090x_READ_DEMOD(state, ERRCNT22);
3167 h = STV090x_GETFIELD_Px(reg, ERR_CNT2_FIELD);
3169 reg = STV090x_READ_DEMOD(state, ERRCNT21);
3170 m = STV090x_GETFIELD_Px(reg, ERR_CNT21_FIELD);
3172 reg = STV090x_READ_DEMOD(state, ERRCNT20);
3173 l = STV090x_GETFIELD_Px(reg, ERR_CNT20_FIELD);
3175 *per = ((h << 16) | (m << 8) | l);
3177 count_4 = STV090x_READ_DEMOD(state, FBERCPT4);
3178 count_3 = STV090x_READ_DEMOD(state, FBERCPT3);
3179 count_2 = STV090x_READ_DEMOD(state, FBERCPT2);
3180 count_1 = STV090x_READ_DEMOD(state, FBERCPT1);
3181 count_0 = STV090x_READ_DEMOD(state, FBERCPT0);
3183 if ((!count_4) && (!count_3)) {
3184 count = (count_2 & 0xff) << 16;
3185 count |= (count_1 & 0xff) << 8;
3186 count |= count_0 & 0xff;
3193 if (STV090x_WRITE_DEMOD(state, FBERCPT4, 0) < 0)
3195 if (STV090x_WRITE_DEMOD(state, ERRCTRL2, 0xc1) < 0)
3200 dprintk(FE_ERROR, 1, "I/O error");
3204 static int stv090x_table_lookup(const struct stv090x_tab *tab, int max, int val)
3209 if (val < tab[min].read)
3210 res = tab[min].real;
3211 else if (val >= tab[max].read)
3212 res = tab[max].real;
3214 while ((max - min) > 1) {
3215 med = (max + min) / 2;
3216 if (val >= tab[min].read && val < tab[med].read)
3221 res = ((val - tab[min].read) *
3222 (tab[max].real - tab[min].real) /
3223 (tab[max].read - tab[min].read)) +
3230 static int stv090x_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
3232 struct stv090x_state *state = fe->demodulator_priv;
3236 reg = STV090x_READ_DEMOD(state, AGCIQIN1);
3237 agc = STV090x_GETFIELD_Px(reg, AGCIQ_VALUE_FIELD);
3239 *strength = stv090x_table_lookup(stv090x_rf_tab, ARRAY_SIZE(stv090x_rf_tab) - 1, agc);
3240 if (agc > stv090x_rf_tab[0].read)
3242 else if (agc < stv090x_rf_tab[ARRAY_SIZE(stv090x_rf_tab) - 1].read)
3248 static int stv090x_read_cnr(struct dvb_frontend *fe, u16 *cnr)
3250 struct stv090x_state *state = fe->demodulator_priv;
3251 u32 reg_0, reg_1, reg, i;
3252 s32 val_0, val_1, val = 0;
3255 switch (state->delsys) {
3257 reg = STV090x_READ_DEMOD(state, DSTATUS);
3258 lock_f = STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD);
3261 for (i = 0; i < 16; i++) {
3262 reg_1 = STV090x_READ_DEMOD(state, NNOSPLHT1);
3263 val_1 = STV090x_GETFIELD_Px(reg_1, NOSPLHT_NORMED_FIELD);
3264 reg_0 = STV090x_READ_DEMOD(state, NNOSPLHT0);
3265 val_0 = STV090x_GETFIELD_Px(reg_1, NOSPLHT_NORMED_FIELD);
3266 val += MAKEWORD16(val_1, val_0);
3270 *cnr = stv090x_table_lookup(stv090x_s2cn_tab, ARRAY_SIZE(stv090x_s2cn_tab) - 1, val);
3271 if (val < stv090x_s2cn_tab[ARRAY_SIZE(stv090x_s2cn_tab) - 1].read)
3278 reg = STV090x_READ_DEMOD(state, DSTATUS);
3279 lock_f = STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD);
3282 for (i = 0; i < 16; i++) {
3283 reg_1 = STV090x_READ_DEMOD(state, NOSDATAT1);
3284 val_1 = STV090x_GETFIELD_Px(reg_1, NOSDATAT_UNNORMED_FIELD);
3285 reg_0 = STV090x_READ_DEMOD(state, NOSDATAT0);
3286 val_0 = STV090x_GETFIELD_Px(reg_1, NOSDATAT_UNNORMED_FIELD);
3287 val += MAKEWORD16(val_1, val_0);
3291 *cnr = stv090x_table_lookup(stv090x_s1cn_tab, ARRAY_SIZE(stv090x_s1cn_tab) - 1, val);
3292 if (val < stv090x_s2cn_tab[ARRAY_SIZE(stv090x_s1cn_tab) - 1].read)
3303 static int stv090x_set_tone(struct dvb_frontend *fe, fe_sec_tone_mode_t tone)
3305 struct stv090x_state *state = fe->demodulator_priv;
3308 reg = STV090x_READ_DEMOD(state, DISTXCTL);
3311 STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, 0);
3312 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1);
3313 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3315 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 0);
3316 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3321 STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, 0);
3322 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1);
3323 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3332 dprintk(FE_ERROR, 1, "I/O error");
3337 static enum dvbfe_algo stv090x_frontend_algo(struct dvb_frontend *fe)
3339 return DVBFE_ALGO_CUSTOM;
3342 static int stv090x_send_diseqc_msg(struct dvb_frontend *fe, struct dvb_diseqc_master_cmd *cmd)
3344 struct stv090x_state *state = fe->demodulator_priv;
3345 u32 reg, idle = 0, fifo_full = 1;
3348 reg = STV090x_READ_DEMOD(state, DISTXCTL);
3349 STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 1);
3350 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3353 for (i = 0; i < cmd->msg_len; i++) {
3356 reg = STV090x_READ_DEMOD(state, DISTXSTATUS);
3357 fifo_full = STV090x_GETFIELD_Px(reg, FIFO_FULL_FIELD);
3360 if (STV090x_WRITE_DEMOD(state, DISTXDATA, cmd->msg[i]) < 0)
3364 reg = STV090x_READ_DEMOD(state, DISTXCTL);
3365 STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 0);
3366 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3371 while ((!idle) && (i < 10)) {
3372 reg = STV090x_READ_DEMOD(state, DISTXSTATUS);
3373 idle = STV090x_GETFIELD_Px(reg, TX_IDLE_FIELD);
3380 dprintk(FE_ERROR, 1, "I/O error");
3384 static int stv090x_recv_slave_reply(struct dvb_frontend *fe, struct dvb_diseqc_slave_reply *reply)
3386 struct stv090x_state *state = fe->demodulator_priv;
3387 u32 reg = 0, i = 0, rx_end = 0;
3389 while ((rx_end != 1) && (i < 10)) {
3392 reg = STV090x_READ_DEMOD(state, DISRX_ST0);
3393 rx_end = STV090x_GETFIELD_Px(reg, RX_END_FIELD);
3397 reply->msg_len = STV090x_GETFIELD_Px(reg, FIFO_BYTENBR_FIELD);
3398 for (i = 0; i < reply->msg_len; i++)
3399 reply->msg[i] = STV090x_READ_DEMOD(state, DISRXDATA);
3405 static int stv090x_sleep(struct dvb_frontend *fe)
3407 struct stv090x_state *state = fe->demodulator_priv;
3410 dprintk(FE_DEBUG, 1, "Set %s to sleep",
3411 state->device == STV0900 ? "STV0900" : "STV0903");
3413 reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
3414 STV090x_SETFIELD(reg, STANDBY_FIELD, 0x01);
3415 if (stv090x_write_reg(state, STV090x_SYNTCTRL, reg) < 0)
3420 dprintk(FE_ERROR, 1, "I/O error");
3424 static int stv090x_wakeup(struct dvb_frontend *fe)
3426 struct stv090x_state *state = fe->demodulator_priv;
3429 dprintk(FE_DEBUG, 1, "Wake %s from standby",
3430 state->device == STV0900 ? "STV0900" : "STV0903");
3432 reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
3433 STV090x_SETFIELD(reg, STANDBY_FIELD, 0x00);
3434 if (stv090x_write_reg(state, STV090x_SYNTCTRL, reg) < 0)
3439 dprintk(FE_ERROR, 1, "I/O error");
3443 static void stv090x_release(struct dvb_frontend *fe)
3445 struct stv090x_state *state = fe->demodulator_priv;
3450 static int stv090x_ldpc_mode(struct stv090x_state *state, enum stv090x_mode ldpc_mode)
3454 switch (ldpc_mode) {
3457 reg = stv090x_read_reg(state, STV090x_GENCFG);
3458 if ((state->demod_mode != STV090x_DUAL) || (STV090x_GETFIELD(reg, DDEMOD_FIELD) != 1)) {
3459 /* follow LDPC default state */
3460 if (stv090x_write_reg(state, STV090x_GENCFG, reg) < 0)
3462 state->demod_mode = STV090x_DUAL;
3463 reg = stv090x_read_reg(state, STV090x_TSTRES0);
3464 STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x1);
3465 if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
3467 STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x0);
3468 if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
3473 case STV090x_SINGLE:
3474 if (state->demod == STV090x_DEMODULATOR_1) {
3475 if (stv090x_write_reg(state, STV090x_GENCFG, 0x06) < 0) /* path 2 */
3478 if (stv090x_write_reg(state, STV090x_GENCFG, 0x04) < 0) /* path 1 */
3482 reg = stv090x_read_reg(state, STV090x_TSTRES0);
3483 STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x1);
3484 if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
3486 STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x0);
3487 if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
3490 reg = STV090x_READ_DEMOD(state, PDELCTRL1);
3491 STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0x01);
3492 if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
3494 STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0x00);
3495 if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
3502 dprintk(FE_ERROR, 1, "I/O error");
3506 /* return (Hz), clk in Hz*/
3507 static u32 stv090x_get_mclk(struct stv090x_state *state)
3509 const struct stv090x_config *config = state->config;
3513 div = stv090x_read_reg(state, STV090x_NCOARSE);
3514 reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
3515 ratio = STV090x_GETFIELD(reg, SELX1RATIO_FIELD) ? 4 : 6;
3517 return (div + 1) * config->xtal / ratio; /* kHz */
3520 static int stv090x_set_mclk(struct stv090x_state *state, u32 mclk, u32 clk)
3522 const struct stv090x_config *config = state->config;
3523 u32 reg, div, clk_sel;
3525 reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
3526 clk_sel = ((STV090x_GETFIELD(reg, SELX1RATIO_FIELD) == 1) ? 4 : 6);
3528 div = ((clk_sel * mclk) / config->xtal) - 1;
3530 reg = stv090x_read_reg(state, STV090x_NCOARSE);
3531 STV090x_SETFIELD(reg, M_DIV_FIELD, div);
3532 if (stv090x_write_reg(state, STV090x_NCOARSE, reg) < 0)
3535 state->mclk = stv090x_get_mclk(state);
3539 dprintk(FE_ERROR, 1, "I/O error");
3543 static int stv090x_set_tspath(struct stv090x_state *state)
3547 if (state->dev_ver >= 0x20) {
3548 switch (state->config->ts1_mode) {
3549 case STV090x_TSMODE_PARALLEL_PUNCTURED:
3550 case STV090x_TSMODE_DVBCI:
3551 switch (state->config->ts2_mode) {
3552 case STV090x_TSMODE_SERIAL_PUNCTURED:
3553 case STV090x_TSMODE_SERIAL_CONTINUOUS:
3555 stv090x_write_reg(state, STV090x_TSGENERAL, 0x00);
3558 case STV090x_TSMODE_PARALLEL_PUNCTURED:
3559 case STV090x_TSMODE_DVBCI:
3560 if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x06) < 0) /* Mux'd stream mode */
3562 reg = stv090x_read_reg(state, STV090x_P1_TSCFGM);
3563 STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
3564 if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0)
3566 reg = stv090x_read_reg(state, STV090x_P2_TSCFGM);
3567 STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
3568 if (stv090x_write_reg(state, STV090x_P2_TSCFGM, reg) < 0)
3570 if (stv090x_write_reg(state, STV090x_P1_TSSPEED, 0x14) < 0)
3572 if (stv090x_write_reg(state, STV090x_P2_TSSPEED, 0x28) < 0)
3578 case STV090x_TSMODE_SERIAL_PUNCTURED:
3579 case STV090x_TSMODE_SERIAL_CONTINUOUS:
3581 switch (state->config->ts2_mode) {
3582 case STV090x_TSMODE_SERIAL_PUNCTURED:
3583 case STV090x_TSMODE_SERIAL_CONTINUOUS:
3585 if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x0c) < 0)
3589 case STV090x_TSMODE_PARALLEL_PUNCTURED:
3590 case STV090x_TSMODE_DVBCI:
3591 if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x0a) < 0)
3598 switch (state->config->ts1_mode) {
3599 case STV090x_TSMODE_PARALLEL_PUNCTURED:
3600 case STV090x_TSMODE_DVBCI:
3601 switch (state->config->ts2_mode) {
3602 case STV090x_TSMODE_SERIAL_PUNCTURED:
3603 case STV090x_TSMODE_SERIAL_CONTINUOUS:
3607 case STV090x_TSMODE_PARALLEL_PUNCTURED:
3608 case STV090x_TSMODE_DVBCI:
3609 reg = stv090x_read_reg(state, STV090x_P1_TSCFGM);
3610 STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
3611 if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0)
3613 reg = stv090x_read_reg(state, STV090x_P1_TSCFGM);
3614 STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 0);
3615 if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0)
3617 if (stv090x_write_reg(state, STV090x_P1_TSSPEED, 0x14) < 0)
3619 if (stv090x_write_reg(state, STV090x_P2_TSSPEED, 0x28) < 0)
3625 case STV090x_TSMODE_SERIAL_PUNCTURED:
3626 case STV090x_TSMODE_SERIAL_CONTINUOUS:
3628 switch (state->config->ts2_mode) {
3629 case STV090x_TSMODE_SERIAL_PUNCTURED:
3630 case STV090x_TSMODE_SERIAL_CONTINUOUS:
3634 case STV090x_TSMODE_PARALLEL_PUNCTURED:
3635 case STV090x_TSMODE_DVBCI:
3642 switch (state->config->ts1_mode) {
3643 case STV090x_TSMODE_PARALLEL_PUNCTURED:
3644 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
3645 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
3646 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
3647 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
3651 case STV090x_TSMODE_DVBCI:
3652 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
3653 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
3654 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
3655 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
3659 case STV090x_TSMODE_SERIAL_PUNCTURED:
3660 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
3661 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
3662 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
3663 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
3667 case STV090x_TSMODE_SERIAL_CONTINUOUS:
3668 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
3669 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
3670 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
3671 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
3679 switch (state->config->ts2_mode) {
3680 case STV090x_TSMODE_PARALLEL_PUNCTURED:
3681 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
3682 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
3683 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
3684 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
3688 case STV090x_TSMODE_DVBCI:
3689 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
3690 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
3691 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
3692 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
3696 case STV090x_TSMODE_SERIAL_PUNCTURED:
3697 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
3698 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
3699 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
3700 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
3704 case STV090x_TSMODE_SERIAL_CONTINUOUS:
3705 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
3706 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
3707 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
3708 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
3715 reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
3716 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x01);
3717 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
3719 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x00);
3720 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
3723 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
3724 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x01);
3725 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
3727 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x00);
3728 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
3733 dprintk(FE_ERROR, 1, "I/O error");
3737 static int stv090x_init(struct dvb_frontend *fe)
3739 struct stv090x_state *state = fe->demodulator_priv;
3740 const struct stv090x_config *config = state->config;
3743 stv090x_ldpc_mode(state, state->demod_mode);
3745 reg = STV090x_READ_DEMOD(state, TNRCFG2);
3746 STV090x_SETFIELD_Px(reg, TUN_IQSWAP_FIELD, state->inversion);
3747 if (STV090x_WRITE_DEMOD(state, TNRCFG2, reg) < 0)
3749 reg = STV090x_READ_DEMOD(state, DEMOD);
3750 STV090x_SETFIELD_Px(reg, ROLLOFF_CONTROL_FIELD, state->rolloff);
3751 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
3754 stv090x_i2c_gate_ctrl(fe, 1);
3756 if (config->tuner_init)
3757 config->tuner_init(fe);
3759 stv090x_i2c_gate_ctrl(fe, 0);
3761 stv090x_set_tspath(state);
3765 dprintk(FE_ERROR, 1, "I/O error");
3769 static int stv090x_setup(struct dvb_frontend *fe)
3771 struct stv090x_state *state = fe->demodulator_priv;
3772 const struct stv090x_config *config = state->config;
3773 const struct stv090x_reg *stv090x_initval = NULL;
3774 const struct stv090x_reg *stv090x_cut20_val = NULL;
3775 unsigned long t1_size = 0, t2_size = 0;
3779 if (state->device == STV0900) {
3780 dprintk(FE_DEBUG, 1, "Initializing STV0900");
3781 stv090x_initval = stv0900_initval;
3782 t1_size = ARRAY_SIZE(stv0900_initval);
3783 stv090x_cut20_val = stv0900_cut20_val;
3784 t2_size = ARRAY_SIZE(stv0900_cut20_val);
3785 } else if (state->device == STV0903) {
3786 dprintk(FE_DEBUG, 1, "Initializing STV0903");
3787 stv090x_initval = stv0903_initval;
3788 t1_size = ARRAY_SIZE(stv0903_initval);
3789 stv090x_cut20_val = stv0903_cut20_val;
3790 t2_size = ARRAY_SIZE(stv0903_cut20_val);
3794 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5c) < 0) /* Stop Demod */
3799 if (STV090x_WRITE_DEMOD(state, TNRCFG, 0x6c) < 0) /* check register ! (No Tuner Mode) */
3802 if (STV090x_WRITE_DEMOD(state, I2CRPT, 0x00) < 0) /* repeater OFF */
3805 if (stv090x_write_reg(state, STV090x_NCOARSE, 0x13) < 0) /* set PLL divider */
3808 if (stv090x_write_reg(state, STV090x_I2CCFG, 0x08) < 0) /* 1/41 oversampling */
3810 if (stv090x_write_reg(state, STV090x_SYNTCTRL, 0x20 | config->clk_mode) < 0) /* enable PLL */
3815 for (i = 0; i < t1_size; i++) {
3816 dprintk(FE_DEBUG, 1, "Setting up initial values");
3817 if (stv090x_write_reg(state, stv090x_initval[i].addr, stv090x_initval[i].data) < 0)
3821 if (state->dev_ver >= 0x20) {
3822 if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x0c) < 0)
3825 /* write cut20_val*/
3826 dprintk(FE_DEBUG, 1, "Setting up Cut 2.0 initial values");
3827 for (i = 0; i < t2_size; i++) {
3828 if (stv090x_write_reg(state, stv090x_cut20_val[i].addr, stv090x_cut20_val[i].data) < 0)
3833 if (stv090x_write_reg(state, STV090x_TSTRES0, 0x80) < 0)
3835 if (stv090x_write_reg(state, STV090x_TSTRES0, 0x00) < 0)
3838 stv090x_set_mclk(state, 135000000, config->xtal); /* 135 Mhz */
3840 if (stv090x_write_reg(state, STV090x_SYNTCTRL, 0x20 | config->clk_mode) < 0)
3842 stv090x_get_mclk(state);
3846 dprintk(FE_ERROR, 1, "I/O error");
3850 static struct dvb_frontend_ops stv090x_ops = {
3853 .name = "STV090x Multistandard",
3856 .release = stv090x_release,
3857 .init = stv090x_init,
3859 .sleep = stv090x_sleep,
3860 .get_frontend_algo = stv090x_frontend_algo,
3862 .i2c_gate_ctrl = stv090x_i2c_gate_ctrl,
3864 .diseqc_send_master_cmd = stv090x_send_diseqc_msg,
3865 .diseqc_recv_slave_reply = stv090x_recv_slave_reply,
3866 .set_tone = stv090x_set_tone,
3868 .search = stv090x_search,
3869 .read_status = stv090x_read_status,
3870 .read_ber = stv090x_read_per,
3871 .read_signal_strength = stv090x_read_signal_strength,
3872 .read_snr = stv090x_read_cnr
3876 struct dvb_frontend *stv090x_attach(const struct stv090x_config *config,
3877 struct i2c_adapter *i2c,
3878 enum stv090x_demodulator demod)
3880 struct stv090x_state *state = NULL;
3882 state = kzalloc(sizeof (struct stv090x_state), GFP_KERNEL);
3886 state->verbose = &verbose;
3887 state->config = config;
3889 state->frontend.ops = stv090x_ops;
3890 state->frontend.demodulator_priv = state;
3891 state->demod_mode = config->demod_mode; /* Single or Dual mode */
3892 state->device = config->device;
3893 state->rolloff = 35; /* default */
3895 if (state->demod == STV090x_DEMODULATOR_0)
3896 mutex_init(&demod_lock);
3898 if (stv090x_sleep(&state->frontend) < 0) {
3899 dprintk(FE_ERROR, 1, "Error putting device to sleep");
3903 if (stv090x_setup(&state->frontend) < 0) {
3904 dprintk(FE_ERROR, 1, "Error setting up device");
3907 if (stv090x_wakeup(&state->frontend) < 0) {
3908 dprintk(FE_ERROR, 1, "Error waking device");
3911 state->dev_ver = stv090x_read_reg(state, STV090x_MID);
3913 dprintk(FE_ERROR, 1, "Attaching %s demodulator(%d) Cut=0x%02x\n",
3914 state->device == STV0900 ? "STV0900" : "STV0903",
3918 return &state->frontend;
3924 EXPORT_SYMBOL(stv090x_attach);
3925 MODULE_PARM_DESC(verbose, "Set Verbosity level");
3926 MODULE_AUTHOR("Manu Abraham");
3927 MODULE_DESCRIPTION("STV090x Multi-Std Broadcast frontend");
3928 MODULE_LICENSE("GPL");