drivers/media/dvb-frontends/lgdt3306a.c

   1 /*
   2  *    Support for LGDT3306A - 8VSB/QAM-B
   3  *
   4  *    Copyright (C) 2013 Fred Richter <frichter@hauppauge.com>
   5  *    - driver structure based on lgdt3305.[ch] by Michael Krufky
   6  *    - code based on LG3306_V0.35 API by LG Electronics Inc.
   7  *
   8  *    This program is free software; you can redistribute it and/or modify
   9  *    it under the terms of the GNU General Public License as published by
  10  *    the Free Software Foundation; either version 2 of the License, or
  11  *    (at your option) any later version.
  12  *
  13  *    This program is distributed in the hope that it will be useful,
  14  *    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  *    GNU General Public License for more details.
  17  */
  18
  19 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  20
  21 #include <asm/div64.h>
  22 #include <linux/dvb/frontend.h>
  23 #include "dvb_math.h"
  24 #include "lgdt3306a.h"
  25
  26
  27 static int debug;
  28 module_param(debug, int, 0644);
  29 MODULE_PARM_DESC(debug, "set debug level (info=1, reg=2 (or-able))");
  30
  31 #define DBG_INFO 1
  32 #define DBG_REG  2
  33 #define DBG_DUMP 4 /* FGR - comment out to remove dump code */
  34
  35 #define lg_debug(fmt, arg...) \
  36         printk(KERN_DEBUG pr_fmt(fmt), ## arg)
  37
  38 #define dbg_info(fmt, arg...)                                   \
  39         do {                                                    \
  40                 if (debug & DBG_INFO)                           \
  41                         lg_debug(fmt, ## arg);                  \
  42         } while (0)
  43
  44 #define dbg_reg(fmt, arg...)                                    \
  45         do {                                                    \
  46                 if (debug & DBG_REG)                            \
  47                         lg_debug(fmt, ## arg);                  \
  48         } while (0)
  49
  50 #define lg_chkerr(ret)                                                  \
  51 ({                                                                      \
  52         int __ret;                                                      \
  53         __ret = (ret < 0);                                              \
  54         if (__ret)                                                      \
  55                 pr_err("error %d on line %d\n", ret, __LINE__);         \
  56         __ret;                                                          \
  57 })
  58
  59 struct lgdt3306a_state {
  60         struct i2c_adapter *i2c_adap;
  61         const struct lgdt3306a_config *cfg;
  62
  63         struct dvb_frontend frontend;
  64
  65         fe_modulation_t current_modulation;
  66         u32 current_frequency;
  67         u32 snr;
  68 };
  69
  70 /* -----------------------------------------------
  71  LG3306A Register Usage
  72    (LG does not really name the registers, so this code does not either)
  73  0000 -> 00FF Common control and status
  74  1000 -> 10FF Synchronizer control and status
  75  1F00 -> 1FFF Smart Antenna control and status
  76  2100 -> 21FF VSB Equalizer control and status
  77  2800 -> 28FF QAM Equalizer control and status
  78  3000 -> 30FF FEC control and status
  79  ---------------------------------------------- */
  80
  81 enum lgdt3306a_lock_status {
  82         LG3306_UNLOCK       = 0x00,
  83         LG3306_LOCK         = 0x01,
  84         LG3306_UNKNOWN_LOCK = 0xff
  85 };
  86
  87 enum lgdt3306a_neverlock_status {
  88         LG3306_NL_INIT    = 0x00,
  89         LG3306_NL_PROCESS = 0x01,
  90         LG3306_NL_LOCK    = 0x02,
  91         LG3306_NL_FAIL    = 0x03,
  92         LG3306_NL_UNKNOWN = 0xff
  93 };
  94
  95 enum lgdt3306a_modulation {
  96         LG3306_VSB          = 0x00,
  97         LG3306_QAM64        = 0x01,
  98         LG3306_QAM256       = 0x02,
  99         LG3306_UNKNOWN_MODE = 0xff
 100 };
 101
 102 enum lgdt3306a_lock_check {
 103         LG3306_SYNC_LOCK,
 104         LG3306_FEC_LOCK,
 105         LG3306_TR_LOCK,
 106         LG3306_AGC_LOCK,
 107 };
 108
 109
 110 #ifdef DBG_DUMP
 111 static void lgdt3306a_DumpAllRegs(struct lgdt3306a_state *state);
 112 static void lgdt3306a_DumpRegs(struct lgdt3306a_state *state);
 113 #endif
 114
 115
 116 static int lgdt3306a_write_reg(struct lgdt3306a_state *state, u16 reg, u8 val)
 117 {
 118         int ret;
 119         u8 buf[] = { reg >> 8, reg & 0xff, val };
 120         struct i2c_msg msg = {
 121                 .addr = state->cfg->i2c_addr, .flags = 0,
 122                 .buf = buf, .len = 3,
 123         };
 124
 125         dbg_reg("reg: 0x%04x, val: 0x%02x\n", reg, val);
 126
 127         ret = i2c_transfer(state->i2c_adap, &msg, 1);
 128
 129         if (ret != 1) {
 130                 pr_err("error (addr %02x %02x <- %02x, err = %i)\n",
 131                        msg.buf[0], msg.buf[1], msg.buf[2], ret);
 132                 if (ret < 0)
 133                         return ret;
 134                 else
 135                         return -EREMOTEIO;
 136         }
 137         return 0;
 138 }
 139
 140 static int lgdt3306a_read_reg(struct lgdt3306a_state *state, u16 reg, u8 *val)
 141 {
 142         int ret;
 143         u8 reg_buf[] = { reg >> 8, reg & 0xff };
 144         struct i2c_msg msg[] = {
 145                 { .addr = state->cfg->i2c_addr,
 146                   .flags = 0, .buf = reg_buf, .len = 2 },
 147                 { .addr = state->cfg->i2c_addr,
 148                   .flags = I2C_M_RD, .buf = val, .len = 1 },
 149         };
 150
 151         ret = i2c_transfer(state->i2c_adap, msg, 2);
 152
 153         if (ret != 2) {
 154                 pr_err("error (addr %02x reg %04x error (ret == %i)\n",
 155                        state->cfg->i2c_addr, reg, ret);
 156                 if (ret < 0)
 157                         return ret;
 158                 else
 159                         return -EREMOTEIO;
 160         }
 161         dbg_reg("reg: 0x%04x, val: 0x%02x\n", reg, *val);
 162
 163         return 0;
 164 }
 165
 166 #define read_reg(state, reg)                                            \
 167 ({                                                                      \
 168         u8 __val;                                                       \
 169         int ret = lgdt3306a_read_reg(state, reg, &__val);               \
 170         if (lg_chkerr(ret))                                             \
 171                 __val = 0;                                              \
 172         __val;                                                          \
 173 })
 174
 175 static int lgdt3306a_set_reg_bit(struct lgdt3306a_state *state,
 176                                 u16 reg, int bit, int onoff)
 177 {
 178         u8 val;
 179         int ret;
 180
 181         dbg_reg("reg: 0x%04x, bit: %d, level: %d\n", reg, bit, onoff);
 182
 183         ret = lgdt3306a_read_reg(state, reg, &val);
 184         if (lg_chkerr(ret))
 185                 goto fail;
 186
 187         val &= ~(1 << bit);
 188         val |= (onoff & 1) << bit;
 189
 190         ret = lgdt3306a_write_reg(state, reg, val);
 191         lg_chkerr(ret);
 192 fail:
 193         return ret;
 194 }
 195
 196 /* ------------------------------------------------------------------------ */
 197
 198 static int lgdt3306a_soft_reset(struct lgdt3306a_state *state)
 199 {
 200         int ret;
 201
 202         dbg_info("\n");
 203
 204         ret = lgdt3306a_set_reg_bit(state, 0x0000, 7, 0);
 205         if (lg_chkerr(ret))
 206                 goto fail;
 207
 208         msleep(20);
 209         ret = lgdt3306a_set_reg_bit(state, 0x0000, 7, 1);
 210         lg_chkerr(ret);
 211
 212 fail:
 213         return ret;
 214 }
 215
 216 static int lgdt3306a_mpeg_mode(struct lgdt3306a_state *state,
 217                                      enum lgdt3306a_mpeg_mode mode)
 218 {
 219         u8 val;
 220         int ret;
 221
 222         dbg_info("(%d)\n", mode);
 223         /* transport packet format - TPSENB=0x80 */
 224         ret = lgdt3306a_set_reg_bit(state, 0x0071, 7,
 225                                      mode == LGDT3306A_MPEG_PARALLEL ? 1 : 0);
 226         if (lg_chkerr(ret))
 227                 goto fail;
 228
 229         /*
 230          * start of packet signal duration
 231          * TPSSOPBITEN=0x40; 0=byte duration, 1=bit duration
 232          */
 233         ret = lgdt3306a_set_reg_bit(state, 0x0071, 6, 0);
 234         if (lg_chkerr(ret))
 235                 goto fail;
 236
 237         ret = lgdt3306a_read_reg(state, 0x0070, &val);
 238         if (lg_chkerr(ret))
 239                 goto fail;
 240
 241         val |= 0x10; /* TPCLKSUPB=0x10 */
 242
 243         if (mode == LGDT3306A_MPEG_PARALLEL)
 244                 val &= ~0x10;
 245
 246         ret = lgdt3306a_write_reg(state, 0x0070, val);
 247         lg_chkerr(ret);
 248
 249 fail:
 250         return ret;
 251 }
 252
 253 static int lgdt3306a_mpeg_mode_polarity(struct lgdt3306a_state *state,
 254                                        enum lgdt3306a_tp_clock_edge edge,
 255                                        enum lgdt3306a_tp_valid_polarity valid)
 256 {
 257         u8 val;
 258         int ret;
 259
 260         dbg_info("edge=%d, valid=%d\n", edge, valid);
 261
 262         ret = lgdt3306a_read_reg(state, 0x0070, &val);
 263         if (lg_chkerr(ret))
 264                 goto fail;
 265
 266         val &= ~0x06; /* TPCLKPOL=0x04, TPVALPOL=0x02 */
 267
 268         if (edge == LGDT3306A_TPCLK_RISING_EDGE)
 269                 val |= 0x04;
 270         if (valid == LGDT3306A_TP_VALID_HIGH)
 271                 val |= 0x02;
 272
 273         ret = lgdt3306a_write_reg(state, 0x0070, val);
 274         lg_chkerr(ret);
 275
 276 fail:
 277         return ret;
 278 }
 279
 280 static int lgdt3306a_mpeg_tristate(struct lgdt3306a_state *state,
 281                                      int mode)
 282 {
 283         u8 val;
 284         int ret;
 285
 286         dbg_info("(%d)\n", mode);
 287
 288         if (mode) {
 289                 ret = lgdt3306a_read_reg(state, 0x0070, &val);
 290                 if (lg_chkerr(ret))
 291                         goto fail;
 292                 /*
 293                  * Tristate bus; TPOUTEN=0x80, TPCLKOUTEN=0x20,
 294                  * TPDATAOUTEN=0x08
 295                  */
 296                 val &= ~0xa8;
 297                 ret = lgdt3306a_write_reg(state, 0x0070, val);
 298                 if (lg_chkerr(ret))
 299                         goto fail;
 300
 301                 /* AGCIFOUTENB=0x40; 1=Disable IFAGC pin */
 302                 ret = lgdt3306a_set_reg_bit(state, 0x0003, 6, 1);
 303                 if (lg_chkerr(ret))
 304                         goto fail;
 305
 306         } else {
 307                 /* enable IFAGC pin */
 308                 ret = lgdt3306a_set_reg_bit(state, 0x0003, 6, 0);
 309                 if (lg_chkerr(ret))
 310                         goto fail;
 311
 312                 ret = lgdt3306a_read_reg(state, 0x0070, &val);
 313                 if (lg_chkerr(ret))
 314                         goto fail;
 315
 316                 val |= 0xa8; /* enable bus */
 317                 ret = lgdt3306a_write_reg(state, 0x0070, val);
 318                 if (lg_chkerr(ret))
 319                         goto fail;
 320         }
 321
 322 fail:
 323         return ret;
 324 }
 325
 326 static int lgdt3306a_ts_bus_ctrl(struct dvb_frontend *fe, int acquire)
 327 {
 328         struct lgdt3306a_state *state = fe->demodulator_priv;
 329
 330         dbg_info("acquire=%d\n", acquire);
 331
 332         return lgdt3306a_mpeg_tristate(state, acquire ? 0 : 1);
 333
 334 }
 335
 336 static int lgdt3306a_power(struct lgdt3306a_state *state,
 337                                      int mode)
 338 {
 339         int ret;
 340
 341         dbg_info("(%d)\n", mode);
 342
 343         if (mode == 0) {
 344                 /* into reset */
 345                 ret = lgdt3306a_set_reg_bit(state, 0x0000, 7, 0);
 346                 if (lg_chkerr(ret))
 347                         goto fail;
 348
 349                 /* power down */
 350                 ret = lgdt3306a_set_reg_bit(state, 0x0000, 0, 0);
 351                 if (lg_chkerr(ret))
 352                         goto fail;
 353
 354         } else {
 355                 /* out of reset */
 356                 ret = lgdt3306a_set_reg_bit(state, 0x0000, 7, 1);
 357                 if (lg_chkerr(ret))
 358                         goto fail;
 359
 360                 /* power up */
 361                 ret = lgdt3306a_set_reg_bit(state, 0x0000, 0, 1);
 362                 if (lg_chkerr(ret))
 363                         goto fail;
 364         }
 365
 366 #ifdef DBG_DUMP
 367         lgdt3306a_DumpAllRegs(state);
 368 #endif
 369 fail:
 370         return ret;
 371 }
 372
 373
 374 static int lgdt3306a_set_vsb(struct lgdt3306a_state *state)
 375 {
 376         u8 val;
 377         int ret;
 378
 379         dbg_info("\n");
 380
 381         /* 0. Spectrum inversion detection manual; spectrum inverted */
 382         ret = lgdt3306a_read_reg(state, 0x0002, &val);
 383         val &= 0xf7; /* SPECINVAUTO Off */
 384         val |= 0x04; /* SPECINV On */
 385         ret = lgdt3306a_write_reg(state, 0x0002, val);
 386         if (lg_chkerr(ret))
 387                 goto fail;
 388
 389         /* 1. Selection of standard mode(0x08=QAM, 0x80=VSB) */
 390         ret = lgdt3306a_write_reg(state, 0x0008, 0x80);
 391         if (lg_chkerr(ret))
 392                 goto fail;
 393
 394         /* 2. Bandwidth mode for VSB(6MHz) */
 395         ret = lgdt3306a_read_reg(state, 0x0009, &val);
 396         val &= 0xe3;
 397         val |= 0x0c; /* STDOPDETTMODE[2:0]=3 */
 398         ret = lgdt3306a_write_reg(state, 0x0009, val);
 399         if (lg_chkerr(ret))
 400                 goto fail;
 401
 402         /* 3. QAM mode detection mode(None) */
 403         ret = lgdt3306a_read_reg(state, 0x0009, &val);
 404         val &= 0xfc; /* STDOPDETCMODE[1:0]=0 */
 405         ret = lgdt3306a_write_reg(state, 0x0009, val);
 406         if (lg_chkerr(ret))
 407                 goto fail;
 408
 409         /* 4. ADC sampling frequency rate(2x sampling) */
 410         ret = lgdt3306a_read_reg(state, 0x000d, &val);
 411         val &= 0xbf; /* SAMPLING4XFEN=0 */
 412         ret = lgdt3306a_write_reg(state, 0x000d, val);
 413         if (lg_chkerr(ret))
 414                 goto fail;
 415
 416 #if 0
 417         /* FGR - disable any AICC filtering, testing only */
 418
 419         ret = lgdt3306a_write_reg(state, 0x0024, 0x00);
 420         if (lg_chkerr(ret))
 421                 goto fail;
 422
 423         /* AICCFIXFREQ0 NT N-1(Video rejection) */
 424         ret = lgdt3306a_write_reg(state, 0x002e, 0x00);
 425         ret = lgdt3306a_write_reg(state, 0x002f, 0x00);
 426         ret = lgdt3306a_write_reg(state, 0x0030, 0x00);
 427
 428         /* AICCFIXFREQ1 NT N-1(Audio rejection) */
 429         ret = lgdt3306a_write_reg(state, 0x002b, 0x00);
 430         ret = lgdt3306a_write_reg(state, 0x002c, 0x00);
 431         ret = lgdt3306a_write_reg(state, 0x002d, 0x00);
 432
 433         /* AICCFIXFREQ2 NT Co-Channel(Video rejection) */
 434         ret = lgdt3306a_write_reg(state, 0x0028, 0x00);
 435         ret = lgdt3306a_write_reg(state, 0x0029, 0x00);
 436         ret = lgdt3306a_write_reg(state, 0x002a, 0x00);
 437
 438         /* AICCFIXFREQ3 NT Co-Channel(Audio rejection) */
 439         ret = lgdt3306a_write_reg(state, 0x0025, 0x00);
 440         ret = lgdt3306a_write_reg(state, 0x0026, 0x00);
 441         ret = lgdt3306a_write_reg(state, 0x0027, 0x00);
 442
 443 #else
 444         /* FGR - this works well for HVR-1955,1975 */
 445
 446         /* 5. AICCOPMODE  NT N-1 Adj. */
 447         ret = lgdt3306a_write_reg(state, 0x0024, 0x5A);
 448         if (lg_chkerr(ret))
 449                 goto fail;
 450
 451         /* AICCFIXFREQ0 NT N-1(Video rejection) */
 452         ret = lgdt3306a_write_reg(state, 0x002e, 0x5A);
 453         ret = lgdt3306a_write_reg(state, 0x002f, 0x00);
 454         ret = lgdt3306a_write_reg(state, 0x0030, 0x00);
 455
 456         /* AICCFIXFREQ1 NT N-1(Audio rejection) */
 457         ret = lgdt3306a_write_reg(state, 0x002b, 0x36);
 458         ret = lgdt3306a_write_reg(state, 0x002c, 0x00);
 459         ret = lgdt3306a_write_reg(state, 0x002d, 0x00);
 460
 461         /* AICCFIXFREQ2 NT Co-Channel(Video rejection) */
 462         ret = lgdt3306a_write_reg(state, 0x0028, 0x2A);
 463         ret = lgdt3306a_write_reg(state, 0x0029, 0x00);
 464         ret = lgdt3306a_write_reg(state, 0x002a, 0x00);
 465
 466         /* AICCFIXFREQ3 NT Co-Channel(Audio rejection) */
 467         ret = lgdt3306a_write_reg(state, 0x0025, 0x06);
 468         ret = lgdt3306a_write_reg(state, 0x0026, 0x00);
 469         ret = lgdt3306a_write_reg(state, 0x0027, 0x00);
 470 #endif
 471
 472         ret = lgdt3306a_read_reg(state, 0x001e, &val);
 473         val &= 0x0f;
 474         val |= 0xa0;
 475         ret = lgdt3306a_write_reg(state, 0x001e, val);
 476
 477         ret = lgdt3306a_write_reg(state, 0x0022, 0x08);
 478
 479         ret = lgdt3306a_write_reg(state, 0x0023, 0xFF);
 480
 481         ret = lgdt3306a_read_reg(state, 0x211f, &val);
 482         val &= 0xef;
 483         ret = lgdt3306a_write_reg(state, 0x211f, val);
 484
 485         ret = lgdt3306a_write_reg(state, 0x2173, 0x01);
 486
 487         ret = lgdt3306a_read_reg(state, 0x1061, &val);
 488         val &= 0xf8;
 489         val |= 0x04;
 490         ret = lgdt3306a_write_reg(state, 0x1061, val);
 491
 492         ret = lgdt3306a_read_reg(state, 0x103d, &val);
 493         val &= 0xcf;
 494         ret = lgdt3306a_write_reg(state, 0x103d, val);
 495
 496         ret = lgdt3306a_write_reg(state, 0x2122, 0x40);
 497
 498         ret = lgdt3306a_read_reg(state, 0x2141, &val);
 499         val &= 0x3f;
 500         ret = lgdt3306a_write_reg(state, 0x2141, val);
 501
 502         ret = lgdt3306a_read_reg(state, 0x2135, &val);
 503         val &= 0x0f;
 504         val |= 0x70;
 505         ret = lgdt3306a_write_reg(state, 0x2135, val);
 506
 507         ret = lgdt3306a_read_reg(state, 0x0003, &val);
 508         val &= 0xf7;
 509         ret = lgdt3306a_write_reg(state, 0x0003, val);
 510
 511         ret = lgdt3306a_read_reg(state, 0x001c, &val);
 512         val &= 0x7f;
 513         ret = lgdt3306a_write_reg(state, 0x001c, val);
 514
 515         /* 6. EQ step size */
 516         ret = lgdt3306a_read_reg(state, 0x2179, &val);
 517         val &= 0xf8;
 518         ret = lgdt3306a_write_reg(state, 0x2179, val);
 519
 520         ret = lgdt3306a_read_reg(state, 0x217a, &val);
 521         val &= 0xf8;
 522         ret = lgdt3306a_write_reg(state, 0x217a, val);
 523
 524         /* 7. Reset */
 525         ret = lgdt3306a_soft_reset(state);
 526         if (lg_chkerr(ret))
 527                 goto fail;
 528
 529         dbg_info("complete\n");
 530 fail:
 531         return ret;
 532 }
 533
 534 static int lgdt3306a_set_qam(struct lgdt3306a_state *state, int modulation)
 535 {
 536         u8 val;
 537         int ret;
 538
 539         dbg_info("modulation=%d\n", modulation);
 540
 541         /* 1. Selection of standard mode(0x08=QAM, 0x80=VSB) */
 542         ret = lgdt3306a_write_reg(state, 0x0008, 0x08);
 543         if (lg_chkerr(ret))
 544                 goto fail;
 545
 546         /* 1a. Spectrum inversion detection to Auto */
 547         ret = lgdt3306a_read_reg(state, 0x0002, &val);
 548         val &= 0xfb; /* SPECINV Off */
 549         val |= 0x08; /* SPECINVAUTO On */
 550         ret = lgdt3306a_write_reg(state, 0x0002, val);
 551         if (lg_chkerr(ret))
 552                 goto fail;
 553
 554         /* 2. Bandwidth mode for QAM */
 555         ret = lgdt3306a_read_reg(state, 0x0009, &val);
 556         val &= 0xe3; /* STDOPDETTMODE[2:0]=0 VSB Off */
 557         ret = lgdt3306a_write_reg(state, 0x0009, val);
 558         if (lg_chkerr(ret))
 559                 goto fail;
 560
 561         /* 3. : 64QAM/256QAM detection(manual, auto) */
 562         ret = lgdt3306a_read_reg(state, 0x0009, &val);
 563         val &= 0xfc;
 564         val |= 0x02; /* STDOPDETCMODE[1:0]=1=Manual 2=Auto */
 565         ret = lgdt3306a_write_reg(state, 0x0009, val);
 566         if (lg_chkerr(ret))
 567                 goto fail;
 568
 569         /* 3a. : 64QAM/256QAM selection for manual */
 570         ret = lgdt3306a_read_reg(state, 0x101a, &val);
 571         val &= 0xf8;
 572         if (modulation == QAM_64)
 573                 val |= 0x02; /* QMDQMODE[2:0]=2=QAM64 */
 574         else
 575                 val |= 0x04; /* QMDQMODE[2:0]=4=QAM256 */
 576
 577         ret = lgdt3306a_write_reg(state, 0x101a, val);
 578         if (lg_chkerr(ret))
 579                 goto fail;
 580
 581         /* 4. ADC sampling frequency rate(4x sampling) */
 582         ret = lgdt3306a_read_reg(state, 0x000d, &val);
 583         val &= 0xbf;
 584         val |= 0x40; /* SAMPLING4XFEN=1 */
 585         ret = lgdt3306a_write_reg(state, 0x000d, val);
 586         if (lg_chkerr(ret))
 587                 goto fail;
 588
 589         /* 5. No AICC operation in QAM mode */
 590         ret = lgdt3306a_read_reg(state, 0x0024, &val);
 591         val &= 0x00;
 592         ret = lgdt3306a_write_reg(state, 0x0024, val);
 593         if (lg_chkerr(ret))
 594                 goto fail;
 595
 596         /* 6. Reset */
 597         ret = lgdt3306a_soft_reset(state);
 598         if (lg_chkerr(ret))
 599                 goto fail;
 600
 601         dbg_info("complete\n");
 602 fail:
 603         return ret;
 604 }
 605
 606 static int lgdt3306a_set_modulation(struct lgdt3306a_state *state,
 607                                    struct dtv_frontend_properties *p)
 608 {
 609         int ret;
 610
 611         dbg_info("\n");
 612
 613         switch (p->modulation) {
 614         case VSB_8:
 615                 ret = lgdt3306a_set_vsb(state);
 616                 break;
 617         case QAM_64:
 618                 ret = lgdt3306a_set_qam(state, QAM_64);
 619                 break;
 620         case QAM_256:
 621                 ret = lgdt3306a_set_qam(state, QAM_256);
 622                 break;
 623         default:
 624                 return -EINVAL;
 625         }
 626         if (lg_chkerr(ret))
 627                 goto fail;
 628
 629         state->current_modulation = p->modulation;
 630
 631 fail:
 632         return ret;
 633 }
 634
 635 /* ------------------------------------------------------------------------ */
 636
 637 static int lgdt3306a_agc_setup(struct lgdt3306a_state *state,
 638                               struct dtv_frontend_properties *p)
 639 {
 640         /* TODO: anything we want to do here??? */
 641         dbg_info("\n");
 642
 643         switch (p->modulation) {
 644         case VSB_8:
 645                 break;
 646         case QAM_64:
 647         case QAM_256:
 648                 break;
 649         default:
 650                 return -EINVAL;
 651         }
 652         return 0;
 653 }
 654
 655 /* ------------------------------------------------------------------------ */
 656
 657 static int lgdt3306a_set_inversion(struct lgdt3306a_state *state,
 658                                        int inversion)
 659 {
 660         int ret;
 661
 662         dbg_info("(%d)\n", inversion);
 663
 664         ret = lgdt3306a_set_reg_bit(state, 0x0002, 2, inversion ? 1 : 0);
 665         return ret;
 666 }
 667
 668 static int lgdt3306a_set_inversion_auto(struct lgdt3306a_state *state,
 669                                        int enabled)
 670 {
 671         int ret;
 672
 673         dbg_info("(%d)\n", enabled);
 674
 675         /* 0=Manual 1=Auto(QAM only) - SPECINVAUTO=0x04 */
 676         ret = lgdt3306a_set_reg_bit(state, 0x0002, 3, enabled);
 677         return ret;
 678 }
 679
 680 static int lgdt3306a_spectral_inversion(struct lgdt3306a_state *state,
 681                                        struct dtv_frontend_properties *p,
 682                                        int inversion)
 683 {
 684         int ret = 0;
 685
 686         dbg_info("(%d)\n", inversion);
 687 #if 0
 688         /*
 689          * FGR - spectral_inversion defaults already set for VSB and QAM;
 690          * can enable later if desired
 691          */
 692
 693         ret = lgdt3306a_set_inversion(state, inversion);
 694
 695         switch (p->modulation) {
 696         case VSB_8:
 697                 /* Manual only for VSB */
 698                 ret = lgdt3306a_set_inversion_auto(state, 0);
 699                 break;
 700         case QAM_64:
 701         case QAM_256:
 702                 /* Auto ok for QAM */
 703                 ret = lgdt3306a_set_inversion_auto(state, 1);
 704                 break;
 705         default:
 706                 ret = -EINVAL;
 707         }
 708 #endif
 709         return ret;
 710 }
 711
 712 static int lgdt3306a_set_if(struct lgdt3306a_state *state,
 713                            struct dtv_frontend_properties *p)
 714 {
 715         int ret;
 716         u16 if_freq_khz;
 717         u8 nco1, nco2;
 718
 719         switch (p->modulation) {
 720         case VSB_8:
 721                 if_freq_khz = state->cfg->vsb_if_khz;
 722                 break;
 723         case QAM_64:
 724         case QAM_256:
 725                 if_freq_khz = state->cfg->qam_if_khz;
 726                 break;
 727         default:
 728                 return -EINVAL;
 729         }
 730
 731         switch (if_freq_khz) {
 732         default:
 733                 pr_warn("IF=%d KHz is not supportted, 3250 assumed\n",
 734                         if_freq_khz);
 735                 /* fallthrough */
 736         case 3250: /* 3.25Mhz */
 737                 nco1 = 0x34;
 738                 nco2 = 0x00;
 739                 break;
 740         case 3500: /* 3.50Mhz */
 741                 nco1 = 0x38;
 742                 nco2 = 0x00;
 743                 break;
 744         case 4000: /* 4.00Mhz */
 745                 nco1 = 0x40;
 746                 nco2 = 0x00;
 747                 break;
 748         case 5000: /* 5.00Mhz */
 749                 nco1 = 0x50;
 750                 nco2 = 0x00;
 751                 break;
 752         case 5380: /* 5.38Mhz */
 753                 nco1 = 0x56;
 754                 nco2 = 0x14;
 755                 break;
 756         }
 757         ret = lgdt3306a_write_reg(state, 0x0010, nco1);
 758         if (ret)
 759                 return ret;
 760         ret = lgdt3306a_write_reg(state, 0x0011, nco2);
 761         if (ret)
 762                 return ret;
 763
 764         dbg_info("if_freq=%d KHz->[%04x]\n", if_freq_khz, nco1<<8 | nco2);
 765
 766         return 0;
 767 }
 768
 769 /* ------------------------------------------------------------------------ */
 770
 771 static int lgdt3306a_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
 772 {
 773         struct lgdt3306a_state *state = fe->demodulator_priv;
 774
 775         if (state->cfg->deny_i2c_rptr) {
 776                 dbg_info("deny_i2c_rptr=%d\n", state->cfg->deny_i2c_rptr);
 777                 return 0;
 778         }
 779         dbg_info("(%d)\n", enable);
 780
 781         /* NI2CRPTEN=0x80 */
 782         return lgdt3306a_set_reg_bit(state, 0x0002, 7, enable ? 0 : 1);
 783 }
 784
 785 static int lgdt3306a_sleep(struct lgdt3306a_state *state)
 786 {
 787         int ret;
 788
 789         dbg_info("\n");
 790         state->current_frequency = -1; /* force re-tune, when we wake */
 791
 792         ret = lgdt3306a_mpeg_tristate(state, 1); /* disable data bus */
 793         if (lg_chkerr(ret))
 794                 goto fail;
 795
 796         ret = lgdt3306a_power(state, 0); /* power down */
 797         lg_chkerr(ret);
 798
 799 fail:
 800         return 0;
 801 }
 802
 803 static int lgdt3306a_fe_sleep(struct dvb_frontend *fe)
 804 {
 805         struct lgdt3306a_state *state = fe->demodulator_priv;
 806
 807         return lgdt3306a_sleep(state);
 808 }
 809
 810 static int lgdt3306a_init(struct dvb_frontend *fe)
 811 {
 812         struct lgdt3306a_state *state = fe->demodulator_priv;
 813         u8 val;
 814         int ret;
 815
 816         dbg_info("\n");
 817
 818         /* 1. Normal operation mode */
 819         ret = lgdt3306a_set_reg_bit(state, 0x0001, 0, 1); /* SIMFASTENB=0x01 */
 820         if (lg_chkerr(ret))
 821                 goto fail;
 822
 823         /* 2. Spectrum inversion auto detection (Not valid for VSB) */
 824         ret = lgdt3306a_set_inversion_auto(state, 0);
 825         if (lg_chkerr(ret))
 826                 goto fail;
 827
 828         /* 3. Spectrum inversion(According to the tuner configuration) */
 829         ret = lgdt3306a_set_inversion(state, 1);
 830         if (lg_chkerr(ret))
 831                 goto fail;
 832
 833         /* 4. Peak-to-peak voltage of ADC input signal */
 834
 835         /* ADCSEL1V=0x80=1Vpp; 0x00=2Vpp */
 836         ret = lgdt3306a_set_reg_bit(state, 0x0004, 7, 1);
 837         if (lg_chkerr(ret))
 838                 goto fail;
 839
 840         /* 5. ADC output data capture clock phase */
 841
 842         /* 0=same phase as ADC clock */
 843         ret = lgdt3306a_set_reg_bit(state, 0x0004, 2, 0);
 844         if (lg_chkerr(ret))
 845                 goto fail;
 846
 847         /* 5a. ADC sampling clock source */
 848
 849         /* ADCCLKPLLSEL=0x08; 0=use ext clock, not PLL */
 850         ret = lgdt3306a_set_reg_bit(state, 0x0004, 3, 0);
 851         if (lg_chkerr(ret))
 852                 goto fail;
 853
 854         /* 6. Automatic PLL set */
 855
 856         /* PLLSETAUTO=0x40; 0=off */
 857         ret = lgdt3306a_set_reg_bit(state, 0x0005, 6, 0);
 858         if (lg_chkerr(ret))
 859                 goto fail;
 860
 861         if (state->cfg->xtalMHz == 24) {        /* 24MHz */
 862                 /* 7. Frequency for PLL output(0x2564 for 192MHz for 24MHz) */
 863                 ret = lgdt3306a_read_reg(state, 0x0005, &val);
 864                 if (lg_chkerr(ret))
 865                         goto fail;
 866                 val &= 0xc0;
 867                 val |= 0x25;
 868                 ret = lgdt3306a_write_reg(state, 0x0005, val);
 869                 if (lg_chkerr(ret))
 870                         goto fail;
 871                 ret = lgdt3306a_write_reg(state, 0x0006, 0x64);
 872                 if (lg_chkerr(ret))
 873                         goto fail;
 874
 875                 /* 8. ADC sampling frequency(0x180000 for 24MHz sampling) */
 876                 ret = lgdt3306a_read_reg(state, 0x000d, &val);
 877                 if (lg_chkerr(ret))
 878                         goto fail;
 879                 val &= 0xc0;
 880                 val |= 0x18;
 881                 ret = lgdt3306a_write_reg(state, 0x000d, val);
 882                 if (lg_chkerr(ret))
 883                         goto fail;
 884
 885         } else if (state->cfg->xtalMHz == 25) { /* 25MHz */
 886                 /* 7. Frequency for PLL output */
 887                 ret = lgdt3306a_read_reg(state, 0x0005, &val);
 888                 if (lg_chkerr(ret))
 889                         goto fail;
 890                 val &= 0xc0;
 891                 val |= 0x25;
 892                 ret = lgdt3306a_write_reg(state, 0x0005, val);
 893                 if (lg_chkerr(ret))
 894                         goto fail;
 895                 ret = lgdt3306a_write_reg(state, 0x0006, 0x64);
 896                 if (lg_chkerr(ret))
 897                         goto fail;
 898
 899                 /* 8. ADC sampling frequency(0x190000 for 25MHz sampling) */
 900                 ret = lgdt3306a_read_reg(state, 0x000d, &val);
 901                 if (lg_chkerr(ret))
 902                         goto fail;
 903                 val &= 0xc0;
 904                 val |= 0x19;
 905                 ret = lgdt3306a_write_reg(state, 0x000d, val);
 906                 if (lg_chkerr(ret))
 907                         goto fail;
 908         } else {
 909                 pr_err("Bad xtalMHz=%d\n", state->cfg->xtalMHz);
 910         }
 911 #if 0
 912         ret = lgdt3306a_write_reg(state, 0x000e, 0x00);
 913         ret = lgdt3306a_write_reg(state, 0x000f, 0x00);
 914 #endif
 915
 916         /* 9. Center frequency of input signal of ADC */
 917         ret = lgdt3306a_write_reg(state, 0x0010, 0x34); /* 3.25MHz */
 918         ret = lgdt3306a_write_reg(state, 0x0011, 0x00);
 919
 920         /* 10. Fixed gain error value */
 921         ret = lgdt3306a_write_reg(state, 0x0014, 0); /* gain error=0 */
 922
 923         /* 10a. VSB TR BW gear shift initial step */
 924         ret = lgdt3306a_read_reg(state, 0x103c, &val);
 925         val &= 0x0f;
 926         val |= 0x20; /* SAMGSAUTOSTL_V[3:0] = 2 */
 927         ret = lgdt3306a_write_reg(state, 0x103c, val);
 928
 929         /* 10b. Timing offset calibration in low temperature for VSB */
 930         ret = lgdt3306a_read_reg(state, 0x103d, &val);
 931         val &= 0xfc;
 932         val |= 0x03;
 933         ret = lgdt3306a_write_reg(state, 0x103d, val);
 934
 935         /* 10c. Timing offset calibration in low temperature for QAM */
 936         ret = lgdt3306a_read_reg(state, 0x1036, &val);
 937         val &= 0xf0;
 938         val |= 0x0c;
 939         ret = lgdt3306a_write_reg(state, 0x1036, val);
 940
 941         /* 11. Using the imaginary part of CIR in CIR loading */
 942         ret = lgdt3306a_read_reg(state, 0x211f, &val);
 943         val &= 0xef; /* do not use imaginary of CIR */
 944         ret = lgdt3306a_write_reg(state, 0x211f, val);
 945
 946         /* 12. Control of no signal detector function */
 947         ret = lgdt3306a_read_reg(state, 0x2849, &val);
 948         val &= 0xef; /* NOUSENOSIGDET=0, enable no signal detector */
 949         ret = lgdt3306a_write_reg(state, 0x2849, val);
 950
 951         /* FGR - put demod in some known mode */
 952         ret = lgdt3306a_set_vsb(state);
 953
 954         /* 13. TP stream format */
 955         ret = lgdt3306a_mpeg_mode(state, state->cfg->mpeg_mode);
 956
 957         /* 14. disable output buses */
 958         ret = lgdt3306a_mpeg_tristate(state, 1);
 959
 960         /* 15. Sleep (in reset) */
 961         ret = lgdt3306a_sleep(state);
 962         lg_chkerr(ret);
 963
 964 fail:
 965         return ret;
 966 }
 967
 968 static int lgdt3306a_set_parameters(struct dvb_frontend *fe)
 969 {
 970         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
 971         struct lgdt3306a_state *state = fe->demodulator_priv;
 972         int ret;
 973
 974         dbg_info("(%d, %d)\n", p->frequency, p->modulation);
 975
 976         if (state->current_frequency  == p->frequency &&
 977            state->current_modulation == p->modulation) {
 978                 dbg_info(" (already set, skipping ...)\n");
 979                 return 0;
 980         }
 981         state->current_frequency = -1;
 982         state->current_modulation = -1;
 983
 984         ret = lgdt3306a_power(state, 1); /* power up */
 985         if (lg_chkerr(ret))
 986                 goto fail;
 987
 988         if (fe->ops.tuner_ops.set_params) {
 989                 ret = fe->ops.tuner_ops.set_params(fe);
 990                 if (fe->ops.i2c_gate_ctrl)
 991                         fe->ops.i2c_gate_ctrl(fe, 0);
 992 #if 0
 993                 if (lg_chkerr(ret))
 994                         goto fail;
 995                 state->current_frequency = p->frequency;
 996 #endif
 997         }
 998
 999         ret = lgdt3306a_set_modulation(state, p);
1000         if (lg_chkerr(ret))
1001                 goto fail;
1002
1003         ret = lgdt3306a_agc_setup(state, p);
1004         if (lg_chkerr(ret))
1005                 goto fail;
1006
1007         ret = lgdt3306a_set_if(state, p);
1008         if (lg_chkerr(ret))
1009                 goto fail;
1010
1011         ret = lgdt3306a_spectral_inversion(state, p,
1012                                         state->cfg->spectral_inversion ? 1 : 0);
1013         if (lg_chkerr(ret))
1014                 goto fail;
1015
1016         ret = lgdt3306a_mpeg_mode(state, state->cfg->mpeg_mode);
1017         if (lg_chkerr(ret))
1018                 goto fail;
1019
1020         ret = lgdt3306a_mpeg_mode_polarity(state,
1021                                           state->cfg->tpclk_edge,
1022                                           state->cfg->tpvalid_polarity);
1023         if (lg_chkerr(ret))
1024                 goto fail;
1025
1026         ret = lgdt3306a_mpeg_tristate(state, 0); /* enable data bus */
1027         if (lg_chkerr(ret))
1028                 goto fail;
1029
1030         ret = lgdt3306a_soft_reset(state);
1031         if (lg_chkerr(ret))
1032                 goto fail;
1033
1034 #ifdef DBG_DUMP
1035         lgdt3306a_DumpAllRegs(state);
1036 #endif
1037         state->current_frequency = p->frequency;
1038 fail:
1039         return ret;
1040 }
1041
1042 static int lgdt3306a_get_frontend(struct dvb_frontend *fe)
1043 {
1044         struct lgdt3306a_state *state = fe->demodulator_priv;
1045         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1046
1047         dbg_info("(%u, %d)\n",
1048                  state->current_frequency, state->current_modulation);
1049
1050         p->modulation = state->current_modulation;
1051         p->frequency = state->current_frequency;
1052         return 0;
1053 }
1054
1055 static enum dvbfe_algo lgdt3306a_get_frontend_algo(struct dvb_frontend *fe)
1056 {
1057 #if 1
1058         return DVBFE_ALGO_CUSTOM;
1059 #else
1060         return DVBFE_ALGO_HW;
1061 #endif
1062 }
1063
1064 /* ------------------------------------------------------------------------ */
1065 static int lgdt3306a_monitor_vsb(struct lgdt3306a_state *state)
1066 {
1067         u8 val;
1068         int ret;
1069         u8 snrRef, maxPowerMan, nCombDet;
1070         u16 fbDlyCir;
1071
1072         ret = lgdt3306a_read_reg(state, 0x21a1, &val);
1073         if (ret)
1074                 return ret;
1075         snrRef = val & 0x3f;
1076
1077         ret = lgdt3306a_read_reg(state, 0x2185, &maxPowerMan);
1078         if (ret)
1079                 return ret;
1080
1081         ret = lgdt3306a_read_reg(state, 0x2191, &val);
1082         if (ret)
1083                 return ret;
1084         nCombDet = (val & 0x80) >> 7;
1085
1086         ret = lgdt3306a_read_reg(state, 0x2180, &val);
1087         if (ret)
1088                 return ret;
1089         fbDlyCir = (val & 0x03) << 8;
1090
1091         ret = lgdt3306a_read_reg(state, 0x2181, &val);
1092         if (ret)
1093                 return ret;
1094         fbDlyCir |= val;
1095
1096         dbg_info("snrRef=%d maxPowerMan=0x%x nCombDet=%d fbDlyCir=0x%x\n",
1097                 snrRef, maxPowerMan, nCombDet, fbDlyCir);
1098
1099         /* Carrier offset sub loop bandwidth */
1100         ret = lgdt3306a_read_reg(state, 0x1061, &val);
1101         if (ret)
1102                 return ret;
1103         val &= 0xf8;
1104         if ((snrRef > 18) && (maxPowerMan > 0x68)
1105             && (nCombDet == 0x01)
1106             && ((fbDlyCir == 0x03FF) || (fbDlyCir < 0x6C))) {
1107                 /* SNR is over 18dB and no ghosting */
1108                 val |= 0x00; /* final bandwidth = 0 */
1109         } else {
1110                 val |= 0x04; /* final bandwidth = 4 */
1111         }
1112         ret = lgdt3306a_write_reg(state, 0x1061, val);
1113         if (ret)
1114                 return ret;
1115
1116         /* Adjust Notch Filter */
1117         ret = lgdt3306a_read_reg(state, 0x0024, &val);
1118         if (ret)
1119                 return ret;
1120         val &= 0x0f;
1121         if (nCombDet == 0) { /* Turn on the Notch Filter */
1122                 val |= 0x50;
1123         }
1124         ret = lgdt3306a_write_reg(state, 0x0024, val);
1125         if (ret)
1126                 return ret;
1127
1128         /* VSB Timing Recovery output normalization */
1129         ret = lgdt3306a_read_reg(state, 0x103d, &val);
1130         if (ret)
1131                 return ret;
1132         val &= 0xcf;
1133         val |= 0x20;
1134         ret = lgdt3306a_write_reg(state, 0x103d, val);
1135
1136         return ret;
1137 }
1138
1139 static enum lgdt3306a_modulation
1140 lgdt3306a_check_oper_mode(struct lgdt3306a_state *state)
1141 {
1142         u8 val = 0;
1143         int ret;
1144
1145         ret = lgdt3306a_read_reg(state, 0x0081, &val);
1146         if (ret)
1147                 goto err;
1148
1149         if (val & 0x80) {
1150                 dbg_info("VSB\n");
1151                 return LG3306_VSB;
1152         }
1153         if (val & 0x08) {
1154                 ret = lgdt3306a_read_reg(state, 0x00a6, &val);
1155                 if (ret)
1156                         goto err;
1157                 val = val >> 2;
1158                 if (val & 0x01) {
1159                         dbg_info("QAM256\n");
1160                         return LG3306_QAM256;
1161                 }
1162                 dbg_info("QAM64\n");
1163                 return LG3306_QAM64;
1164         }
1165 err:
1166         pr_warn("UNKNOWN\n");
1167         return LG3306_UNKNOWN_MODE;
1168 }
1169
1170 static enum lgdt3306a_lock_status
1171 lgdt3306a_check_lock_status(struct lgdt3306a_state *state,
1172                             enum lgdt3306a_lock_check whatLock)
1173 {
1174         u8 val = 0;
1175         int ret;
1176         enum lgdt3306a_modulation       modeOper;
1177         enum lgdt3306a_lock_status lockStatus;
1178
1179         modeOper = LG3306_UNKNOWN_MODE;
1180
1181         switch (whatLock) {
1182         case LG3306_SYNC_LOCK:
1183         {
1184                 ret = lgdt3306a_read_reg(state, 0x00a6, &val);
1185                 if (ret)
1186                         return ret;
1187
1188                 if ((val & 0x80) == 0x80)
1189                         lockStatus = LG3306_LOCK;
1190                 else
1191                         lockStatus = LG3306_UNLOCK;
1192
1193                 dbg_info("SYNC_LOCK=%x\n", lockStatus);
1194                 break;
1195         }
1196         case LG3306_AGC_LOCK:
1197         {
1198                 ret = lgdt3306a_read_reg(state, 0x0080, &val);
1199                 if (ret)
1200                         return ret;
1201
1202                 if ((val & 0x40) == 0x40)
1203                         lockStatus = LG3306_LOCK;
1204                 else
1205                         lockStatus = LG3306_UNLOCK;
1206
1207                 dbg_info("AGC_LOCK=%x\n", lockStatus);
1208                 break;
1209         }
1210         case LG3306_TR_LOCK:
1211         {
1212                 modeOper = lgdt3306a_check_oper_mode(state);
1213                 if ((modeOper == LG3306_QAM64) || (modeOper == LG3306_QAM256)) {
1214                         ret = lgdt3306a_read_reg(state, 0x1094, &val);
1215                         if (ret)
1216                                 return ret;
1217
1218                         if ((val & 0x80) == 0x80)
1219                                 lockStatus = LG3306_LOCK;
1220                         else
1221                                 lockStatus = LG3306_UNLOCK;
1222                 } else
1223                         lockStatus = LG3306_UNKNOWN_LOCK;
1224
1225                 dbg_info("TR_LOCK=%x\n", lockStatus);
1226                 break;
1227         }
1228         case LG3306_FEC_LOCK:
1229         {
1230                 modeOper = lgdt3306a_check_oper_mode(state);
1231                 if ((modeOper == LG3306_QAM64) || (modeOper == LG3306_QAM256)) {
1232                         ret = lgdt3306a_read_reg(state, 0x0080, &val);
1233                         if (ret)
1234                                 return ret;
1235
1236                         if ((val & 0x10) == 0x10)
1237                                 lockStatus = LG3306_LOCK;
1238                         else
1239                                 lockStatus = LG3306_UNLOCK;
1240                 } else
1241                         lockStatus = LG3306_UNKNOWN_LOCK;
1242
1243                 dbg_info("FEC_LOCK=%x\n", lockStatus);
1244                 break;
1245         }
1246
1247         default:
1248                 lockStatus = LG3306_UNKNOWN_LOCK;
1249                 pr_warn("UNKNOWN whatLock=%d\n", whatLock);
1250                 break;
1251         }
1252
1253         return lockStatus;
1254 }
1255
1256 static enum lgdt3306a_neverlock_status
1257 lgdt3306a_check_neverlock_status(struct lgdt3306a_state *state)
1258 {
1259         u8 val = 0;
1260         int ret;
1261         enum lgdt3306a_neverlock_status lockStatus;
1262
1263         ret = lgdt3306a_read_reg(state, 0x0080, &val);
1264         if (ret)
1265                 return ret;
1266         lockStatus = (enum lgdt3306a_neverlock_status)(val & 0x03);
1267
1268         dbg_info("NeverLock=%d", lockStatus);
1269
1270         return lockStatus;
1271 }
1272
1273 static int lgdt3306a_pre_monitoring(struct lgdt3306a_state *state)
1274 {
1275         u8 val = 0;
1276         int ret;
1277         u8 currChDiffACQ, snrRef, mainStrong, aiccrejStatus;
1278
1279         /* Channel variation */
1280         ret = lgdt3306a_read_reg(state, 0x21bc, &currChDiffACQ);
1281         if (ret)
1282                 return ret;
1283
1284         /* SNR of Frame sync */
1285         ret = lgdt3306a_read_reg(state, 0x21a1, &val);
1286         if (ret)
1287                 return ret;
1288         snrRef = val & 0x3f;
1289
1290         /* Strong Main CIR */
1291         ret = lgdt3306a_read_reg(state, 0x2199, &val);
1292         if (ret)
1293                 return ret;
1294         mainStrong = (val & 0x40) >> 6;
1295
1296         ret = lgdt3306a_read_reg(state, 0x0090, &val);
1297         if (ret)
1298                 return ret;
1299         aiccrejStatus = (val & 0xf0) >> 4;
1300
1301         dbg_info("snrRef=%d mainStrong=%d aiccrejStatus=%d currChDiffACQ=0x%x\n",
1302                 snrRef, mainStrong, aiccrejStatus, currChDiffACQ);
1303
1304 #if 0
1305         /* Dynamic ghost exists */
1306         if ((mainStrong == 0) && (currChDiffACQ > 0x70))
1307 #endif
1308         if (mainStrong == 0) {
1309                 ret = lgdt3306a_read_reg(state, 0x2135, &val);
1310                 if (ret)
1311                         return ret;
1312                 val &= 0x0f;
1313                 val |= 0xa0;
1314                 ret = lgdt3306a_write_reg(state, 0x2135, val);
1315                 if (ret)
1316                         return ret;
1317
1318                 ret = lgdt3306a_read_reg(state, 0x2141, &val);
1319                 if (ret)
1320                         return ret;
1321                 val &= 0x3f;
1322                 val |= 0x80;
1323                 ret = lgdt3306a_write_reg(state, 0x2141, val);
1324                 if (ret)
1325                         return ret;
1326
1327                 ret = lgdt3306a_write_reg(state, 0x2122, 0x70);
1328                 if (ret)
1329                         return ret;
1330         } else { /* Weak ghost or static channel */
1331                 ret = lgdt3306a_read_reg(state, 0x2135, &val);
1332                 if (ret)
1333                         return ret;
1334                 val &= 0x0f;
1335                 val |= 0x70;
1336                 ret = lgdt3306a_write_reg(state, 0x2135, val);
1337                 if (ret)
1338                         return ret;
1339
1340                 ret = lgdt3306a_read_reg(state, 0x2141, &val);
1341                 if (ret)
1342                         return ret;
1343                 val &= 0x3f;
1344                 val |= 0x40;
1345                 ret = lgdt3306a_write_reg(state, 0x2141, val);
1346                 if (ret)
1347                         return ret;
1348
1349                 ret = lgdt3306a_write_reg(state, 0x2122, 0x40);
1350                 if (ret)
1351                         return ret;
1352         }
1353         return 0;
1354 }
1355
1356 static enum lgdt3306a_lock_status
1357 lgdt3306a_sync_lock_poll(struct lgdt3306a_state *state)
1358 {
1359         enum lgdt3306a_lock_status syncLockStatus = LG3306_UNLOCK;
1360         int     i;
1361
1362         for (i = 0; i < 2; i++) {
1363                 msleep(30);
1364
1365                 syncLockStatus = lgdt3306a_check_lock_status(state,
1366                                                              LG3306_SYNC_LOCK);
1367
1368                 if (syncLockStatus == LG3306_LOCK) {
1369                         dbg_info("locked(%d)\n", i);
1370                         return LG3306_LOCK;
1371                 }
1372         }
1373         dbg_info("not locked\n");
1374         return LG3306_UNLOCK;
1375 }
1376
1377 static enum lgdt3306a_lock_status
1378 lgdt3306a_fec_lock_poll(struct lgdt3306a_state *state)
1379 {
1380         enum lgdt3306a_lock_status FECLockStatus = LG3306_UNLOCK;
1381         int     i;
1382
1383         for (i = 0; i < 2; i++) {
1384                 msleep(30);
1385
1386                 FECLockStatus = lgdt3306a_check_lock_status(state,
1387                                                             LG3306_FEC_LOCK);
1388
1389                 if (FECLockStatus == LG3306_LOCK) {
1390                         dbg_info("locked(%d)\n", i);
1391                         return FECLockStatus;
1392                 }
1393         }
1394         dbg_info("not locked\n");
1395         return FECLockStatus;
1396 }
1397
1398 static enum lgdt3306a_neverlock_status
1399 lgdt3306a_neverlock_poll(struct lgdt3306a_state *state)
1400 {
1401         enum lgdt3306a_neverlock_status NLLockStatus = LG3306_NL_FAIL;
1402         int     i;
1403
1404         for (i = 0; i < 5; i++) {
1405                 msleep(30);
1406
1407                 NLLockStatus = lgdt3306a_check_neverlock_status(state);
1408
1409                 if (NLLockStatus == LG3306_NL_LOCK) {
1410                         dbg_info("NL_LOCK(%d)\n", i);
1411                         return NLLockStatus;
1412                 }
1413         }
1414         dbg_info("NLLockStatus=%d\n", NLLockStatus);
1415         return NLLockStatus;
1416 }
1417
1418 static u8 lgdt3306a_get_packet_error(struct lgdt3306a_state *state)
1419 {
1420         u8 val;
1421         int ret;
1422
1423         ret = lgdt3306a_read_reg(state, 0x00fa, &val);
1424         if (ret)
1425                 return ret;
1426
1427         return val;
1428 }
1429
1430 static const u32 valx_x10[] = {
1431         10,  11,  13,  15,  17,  20,  25,  33,  41,  50,  59,  73,  87,  100
1432 };
1433 static const u32 log10x_x1000[] = {
1434         0,  41, 114, 176, 230, 301, 398, 518, 613, 699, 771, 863, 939, 1000
1435 };
1436
1437 static u32 log10_x1000(u32 x)
1438 {
1439         u32 diff_val, step_val, step_log10;
1440         u32 log_val = 0;
1441         u32 i;
1442
1443         if (x <= 0)
1444                 return -1000000; /* signal error */
1445
1446         if (x == 10)
1447                 return 0; /* log(1)=0 */
1448
1449         if (x < 10) {
1450                 while (x < 10) {
1451                         x = x * 10;
1452                         log_val--;
1453                 }
1454         } else {        /* x > 10 */
1455                 while (x >= 100) {
1456                         x = x / 10;
1457                         log_val++;
1458                 }
1459         }
1460         log_val *= 1000;
1461
1462         if (x == 10) /* was our input an exact multiple of 10 */
1463                 return log_val; /* don't need to interpolate */
1464
1465         /* find our place on the log curve */
1466         for (i = 1; i < ARRAY_SIZE(valx_x10); i++) {
1467                 if (valx_x10[i] >= x)
1468                         break;
1469         }
1470         if (i == ARRAY_SIZE(valx_x10))
1471                 return log_val + log10x_x1000[i - 1];
1472
1473         diff_val   = x - valx_x10[i-1];
1474         step_val   = valx_x10[i] - valx_x10[i - 1];
1475         step_log10 = log10x_x1000[i] - log10x_x1000[i - 1];
1476
1477         /* do a linear interpolation to get in-between values */
1478         return log_val + log10x_x1000[i - 1] +
1479                 ((diff_val*step_log10) / step_val);
1480 }
1481
1482 static u32 lgdt3306a_calculate_snr_x100(struct lgdt3306a_state *state)
1483 {
1484         u32 mse; /* Mean-Square Error */
1485         u32 pwr; /* Constelation power */
1486         u32 snr_x100;
1487
1488         mse = (read_reg(state, 0x00ec) << 8) |
1489               (read_reg(state, 0x00ed));
1490         pwr = (read_reg(state, 0x00e8) << 8) |
1491               (read_reg(state, 0x00e9));
1492
1493         if (mse == 0) /* no signal */
1494                 return 0;
1495
1496         snr_x100 = log10_x1000((pwr * 10000) / mse) - 3000;
1497         dbg_info("mse=%u, pwr=%u, snr_x100=%d\n", mse, pwr, snr_x100);
1498
1499         return snr_x100;
1500 }
1501
1502 static enum lgdt3306a_lock_status
1503 lgdt3306a_vsb_lock_poll(struct lgdt3306a_state *state)
1504 {
1505         int ret;
1506         u8 cnt = 0;
1507         u8 packet_error;
1508         u32 snr;
1509
1510         for (cnt = 0; cnt < 10; cnt++) {
1511                 if (lgdt3306a_sync_lock_poll(state) == LG3306_UNLOCK) {
1512                         dbg_info("no sync lock!\n");
1513                         return LG3306_UNLOCK;
1514                 }
1515
1516                 msleep(20);
1517                 ret = lgdt3306a_pre_monitoring(state);
1518                 if (ret)
1519                         break;
1520
1521                 packet_error = lgdt3306a_get_packet_error(state);
1522                 snr = lgdt3306a_calculate_snr_x100(state);
1523                 dbg_info("cnt=%d errors=%d snr=%d\n", cnt, packet_error, snr);
1524
1525                 if ((snr >= 1500) && (packet_error < 0xff))
1526                         return LG3306_LOCK;
1527         }
1528
1529         dbg_info("not locked!\n");
1530         return LG3306_UNLOCK;
1531 }
1532
1533 static enum lgdt3306a_lock_status
1534 lgdt3306a_qam_lock_poll(struct lgdt3306a_state *state)
1535 {
1536         u8 cnt;
1537         u8 packet_error;
1538         u32     snr;
1539
1540         for (cnt = 0; cnt < 10; cnt++) {
1541                 if (lgdt3306a_fec_lock_poll(state) == LG3306_UNLOCK) {
1542                         dbg_info("no fec lock!\n");
1543                         return LG3306_UNLOCK;
1544                 }
1545
1546                 msleep(20);
1547
1548                 packet_error = lgdt3306a_get_packet_error(state);
1549                 snr = lgdt3306a_calculate_snr_x100(state);
1550                 dbg_info("cnt=%d errors=%d snr=%d\n", cnt, packet_error, snr);
1551
1552                 if ((snr >= 1500) && (packet_error < 0xff))
1553                         return LG3306_LOCK;
1554         }
1555
1556         dbg_info("not locked!\n");
1557         return LG3306_UNLOCK;
1558 }
1559
1560 static int lgdt3306a_read_status(struct dvb_frontend *fe, fe_status_t *status)
1561 {
1562         struct lgdt3306a_state *state = fe->demodulator_priv;
1563         u16 strength = 0;
1564         int ret = 0;
1565
1566         if (fe->ops.tuner_ops.get_rf_strength) {
1567                 ret = fe->ops.tuner_ops.get_rf_strength(fe, &strength);
1568                 if (ret == 0)
1569                         dbg_info("strength=%d\n", strength);
1570                 else
1571                         dbg_info("fe->ops.tuner_ops.get_rf_strength() failed\n");
1572         }
1573
1574         *status = 0;
1575         if (lgdt3306a_neverlock_poll(state) == LG3306_NL_LOCK) {
1576                 *status |= FE_HAS_SIGNAL;
1577                 *status |= FE_HAS_CARRIER;
1578
1579                 switch (state->current_modulation) {
1580                 case QAM_256:
1581                 case QAM_64:
1582                         if (lgdt3306a_qam_lock_poll(state) == LG3306_LOCK) {
1583                                 *status |= FE_HAS_VITERBI;
1584                                 *status |= FE_HAS_SYNC;
1585
1586                                 *status |= FE_HAS_LOCK;
1587                         }
1588                         break;
1589                 case VSB_8:
1590                         if (lgdt3306a_vsb_lock_poll(state) == LG3306_LOCK) {
1591                                 *status |= FE_HAS_VITERBI;
1592                                 *status |= FE_HAS_SYNC;
1593
1594                                 *status |= FE_HAS_LOCK;
1595
1596                                 ret = lgdt3306a_monitor_vsb(state);
1597                         }
1598                         break;
1599                 default:
1600                         ret = -EINVAL;
1601                 }
1602         }
1603         return ret;
1604 }
1605
1606
1607 static int lgdt3306a_read_snr(struct dvb_frontend *fe, u16 *snr)
1608 {
1609         struct lgdt3306a_state *state = fe->demodulator_priv;
1610
1611         state->snr = lgdt3306a_calculate_snr_x100(state);
1612         /* report SNR in dB * 10 */
1613         *snr = state->snr/10;
1614
1615         return 0;
1616 }
1617
1618 static int lgdt3306a_read_signal_strength(struct dvb_frontend *fe,
1619                                          u16 *strength)
1620 {
1621         /*
1622          * Calculate some sort of "strength" from SNR
1623          */
1624         struct lgdt3306a_state *state = fe->demodulator_priv;
1625         u16 snr; /* snr_x10 */
1626         int ret;
1627         u32 ref_snr; /* snr*100 */
1628         u32 str;
1629
1630         *strength = 0;
1631
1632         switch (state->current_modulation) {
1633         case VSB_8:
1634                  ref_snr = 1600; /* 16dB */
1635                  break;
1636         case QAM_64:
1637                  ref_snr = 2200; /* 22dB */
1638                  break;
1639         case QAM_256:
1640                  ref_snr = 2800; /* 28dB */
1641                  break;
1642         default:
1643                 return -EINVAL;
1644         }
1645
1646         ret = fe->ops.read_snr(fe, &snr);
1647         if (lg_chkerr(ret))
1648                 goto fail;
1649
1650         if (state->snr <= (ref_snr - 100))
1651                 str = 0;
1652         else if (state->snr <= ref_snr)
1653                 str = (0xffff * 65) / 100; /* 65% */
1654         else {
1655                 str = state->snr - ref_snr;
1656                 str /= 50;
1657                 str += 78; /* 78%-100% */
1658                 if (str > 100)
1659                         str = 100;
1660                 str = (0xffff * str) / 100;
1661         }
1662         *strength = (u16)str;
1663         dbg_info("strength=%u\n", *strength);
1664
1665 fail:
1666         return ret;
1667 }
1668
1669 /* ------------------------------------------------------------------------ */
1670
1671 static int lgdt3306a_read_ber(struct dvb_frontend *fe, u32 *ber)
1672 {
1673         struct lgdt3306a_state *state = fe->demodulator_priv;
1674         u32 tmp;
1675
1676         *ber = 0;
1677 #if 1
1678         /* FGR - FIXME - I don't know what value is expected by dvb_core
1679          * what is the scale of the value?? */
1680         tmp =              read_reg(state, 0x00fc); /* NBERVALUE[24-31] */
1681         tmp = (tmp << 8) | read_reg(state, 0x00fd); /* NBERVALUE[16-23] */
1682         tmp = (tmp << 8) | read_reg(state, 0x00fe); /* NBERVALUE[8-15] */
1683         tmp = (tmp << 8) | read_reg(state, 0x00ff); /* NBERVALUE[0-7] */
1684         *ber = tmp;
1685         dbg_info("ber=%u\n", tmp);
1686 #endif
1687         return 0;
1688 }
1689
1690 static int lgdt3306a_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
1691 {
1692         struct lgdt3306a_state *state = fe->demodulator_priv;
1693
1694         *ucblocks = 0;
1695 #if 1
1696         /* FGR - FIXME - I don't know what value is expected by dvb_core
1697          * what happens when value wraps? */
1698         *ucblocks = read_reg(state, 0x00f4); /* TPIFTPERRCNT[0-7] */
1699         dbg_info("ucblocks=%u\n", *ucblocks);
1700 #endif
1701
1702         return 0;
1703 }
1704
1705 static int lgdt3306a_tune(struct dvb_frontend *fe, bool re_tune,
1706                           unsigned int mode_flags, unsigned int *delay,
1707                           fe_status_t *status)
1708 {
1709         int ret = 0;
1710         struct lgdt3306a_state *state = fe->demodulator_priv;
1711
1712         dbg_info("re_tune=%u\n", re_tune);
1713
1714         if (re_tune) {
1715                 state->current_frequency = -1; /* force re-tune */
1716                 ret = lgdt3306a_set_parameters(fe);
1717                 if (ret != 0)
1718                         return ret;
1719         }
1720         *delay = 125;
1721         ret = lgdt3306a_read_status(fe, status);
1722
1723         return ret;
1724 }
1725
1726 static int lgdt3306a_get_tune_settings(struct dvb_frontend *fe,
1727                                        struct dvb_frontend_tune_settings
1728                                        *fe_tune_settings)
1729 {
1730         fe_tune_settings->min_delay_ms = 100;
1731         dbg_info("\n");
1732         return 0;
1733 }
1734
1735 static int lgdt3306a_search(struct dvb_frontend *fe)
1736 {
1737         fe_status_t status = 0;
1738         int i, ret;
1739
1740         /* set frontend */
1741         ret = lgdt3306a_set_parameters(fe);
1742         if (ret)
1743                 goto error;
1744
1745         /* wait frontend lock */
1746         for (i = 20; i > 0; i--) {
1747                 dbg_info(": loop=%d\n", i);
1748                 msleep(50);
1749                 ret = lgdt3306a_read_status(fe, &status);
1750                 if (ret)
1751                         goto error;
1752
1753                 if (status & FE_HAS_LOCK)
1754                         break;
1755         }
1756
1757         /* check if we have a valid signal */
1758         if (status & FE_HAS_LOCK)
1759                 return DVBFE_ALGO_SEARCH_SUCCESS;
1760         else
1761                 return DVBFE_ALGO_SEARCH_AGAIN;
1762
1763 error:
1764         dbg_info("failed (%d)\n", ret);
1765         return DVBFE_ALGO_SEARCH_ERROR;
1766 }
1767
1768 static void lgdt3306a_release(struct dvb_frontend *fe)
1769 {
1770         struct lgdt3306a_state *state = fe->demodulator_priv;
1771
1772         dbg_info("\n");
1773         kfree(state);
1774 }
1775
1776 static struct dvb_frontend_ops lgdt3306a_ops;
1777
1778 struct dvb_frontend *lgdt3306a_attach(const struct lgdt3306a_config *config,
1779                                       struct i2c_adapter *i2c_adap)
1780 {
1781         struct lgdt3306a_state *state = NULL;
1782         int ret;
1783         u8 val;
1784
1785         dbg_info("(%d-%04x)\n",
1786                i2c_adap ? i2c_adapter_id(i2c_adap) : 0,
1787                config ? config->i2c_addr : 0);
1788
1789         state = kzalloc(sizeof(struct lgdt3306a_state), GFP_KERNEL);
1790         if (state == NULL)
1791                 goto fail;
1792
1793         state->cfg = config;
1794         state->i2c_adap = i2c_adap;
1795
1796         memcpy(&state->frontend.ops, &lgdt3306a_ops,
1797                sizeof(struct dvb_frontend_ops));
1798         state->frontend.demodulator_priv = state;
1799
1800         /* verify that we're talking to a lg3306a */
1801         /* FGR - NOTE - there is no obvious ChipId to check; we check
1802          * some "known" bits after reset, but it's still just a guess */
1803         ret = lgdt3306a_read_reg(state, 0x0000, &val);
1804         if (lg_chkerr(ret))
1805                 goto fail;
1806         if ((val & 0x74) != 0x74) {
1807                 pr_warn("expected 0x74, got 0x%x\n", (val & 0x74));
1808 #if 0
1809                 /* FIXME - re-enable when we know this is right */
1810                 goto fail;
1811 #endif
1812         }
1813         ret = lgdt3306a_read_reg(state, 0x0001, &val);
1814         if (lg_chkerr(ret))
1815                 goto fail;
1816         if ((val & 0xf6) != 0xc6) {
1817                 pr_warn("expected 0xc6, got 0x%x\n", (val & 0xf6));
1818 #if 0
1819                 /* FIXME - re-enable when we know this is right */
1820                 goto fail;
1821 #endif
1822         }
1823         ret = lgdt3306a_read_reg(state, 0x0002, &val);
1824         if (lg_chkerr(ret))
1825                 goto fail;
1826         if ((val & 0x73) != 0x03) {
1827                 pr_warn("expected 0x03, got 0x%x\n", (val & 0x73));
1828 #if 0
1829                 /* FIXME - re-enable when we know this is right */
1830                 goto fail;
1831 #endif
1832         }
1833
1834         state->current_frequency = -1;
1835         state->current_modulation = -1;
1836
1837         lgdt3306a_sleep(state);
1838
1839         return &state->frontend;
1840
1841 fail:
1842         pr_warn("unable to detect LGDT3306A hardware\n");
1843         kfree(state);
1844         return NULL;
1845 }
1846 EXPORT_SYMBOL(lgdt3306a_attach);
1847
1848 #ifdef DBG_DUMP
1849
1850 static const short regtab[] = {
1851         0x0000, /* SOFTRSTB 1'b1 1'b1 1'b1 ADCPDB 1'b1 PLLPDB GBBPDB 11111111 */
1852         0x0001, /* 1'b1 1'b1 1'b0 1'b0 AUTORPTRS */
1853         0x0002, /* NI2CRPTEN 1'b0 1'b0 1'b0 SPECINVAUT */
1854         0x0003, /* AGCRFOUT */
1855         0x0004, /* ADCSEL1V ADCCNT ADCCNF ADCCNS ADCCLKPLL */
1856         0x0005, /* PLLINDIVSE */
1857         0x0006, /* PLLCTRL[7:0] 11100001 */
1858         0x0007, /* SYSINITWAITTIME[7:0] (msec) 00001000 */
1859         0x0008, /* STDOPMODE[7:0] 10000000 */
1860         0x0009, /* 1'b0 1'b0 1'b0 STDOPDETTMODE[2:0] STDOPDETCMODE[1:0] 00011110 */
1861         0x000a, /* DAFTEN 1'b1 x x SCSYSLOCK */
1862         0x000b, /* SCSYSLOCKCHKTIME[7:0] (10msec) 01100100 */
1863         0x000d, /* x SAMPLING4 */
1864         0x000e, /* SAMFREQ[15:8] 00000000 */
1865         0x000f, /* SAMFREQ[7:0] 00000000 */
1866         0x0010, /* IFFREQ[15:8] 01100000 */
1867         0x0011, /* IFFREQ[7:0] 00000000 */
1868         0x0012, /* AGCEN AGCREFMO */
1869         0x0013, /* AGCRFFIXB AGCIFFIXB AGCLOCKDETRNGSEL[1:0] 1'b1 1'b0 1'b0 1'b0 11101000 */
1870         0x0014, /* AGCFIXVALUE[7:0] 01111111 */
1871         0x0015, /* AGCREF[15:8] 00001010 */
1872         0x0016, /* AGCREF[7:0] 11100100 */
1873         0x0017, /* AGCDELAY[7:0] 00100000 */
1874         0x0018, /* AGCRFBW[3:0] AGCIFBW[3:0] 10001000 */
1875         0x0019, /* AGCUDOUTMODE[1:0] AGCUDCTRLLEN[1:0] AGCUDCTRL */
1876         0x001c, /* 1'b1 PFEN MFEN AICCVSYNC */
1877         0x001d, /* 1'b0 1'b1 1'b0 1'b1 AICCVSYNC */
1878         0x001e, /* AICCALPHA[3:0] 1'b1 1'b0 1'b1 1'b0 01111010 */
1879         0x001f, /* AICCDETTH[19:16] AICCOFFTH[19:16] 00000000 */
1880         0x0020, /* AICCDETTH[15:8] 01111100 */
1881         0x0021, /* AICCDETTH[7:0] 00000000 */
1882         0x0022, /* AICCOFFTH[15:8] 00000101 */
1883         0x0023, /* AICCOFFTH[7:0] 11100000 */
1884         0x0024, /* AICCOPMODE3[1:0] AICCOPMODE2[1:0] AICCOPMODE1[1:0] AICCOPMODE0[1:0] 00000000 */
1885         0x0025, /* AICCFIXFREQ3[23:16] 00000000 */
1886         0x0026, /* AICCFIXFREQ3[15:8] 00000000 */
1887         0x0027, /* AICCFIXFREQ3[7:0] 00000000 */
1888         0x0028, /* AICCFIXFREQ2[23:16] 00000000 */
1889         0x0029, /* AICCFIXFREQ2[15:8] 00000000 */
1890         0x002a, /* AICCFIXFREQ2[7:0] 00000000 */
1891         0x002b, /* AICCFIXFREQ1[23:16] 00000000 */
1892         0x002c, /* AICCFIXFREQ1[15:8] 00000000 */
1893         0x002d, /* AICCFIXFREQ1[7:0] 00000000 */
1894         0x002e, /* AICCFIXFREQ0[23:16] 00000000 */
1895         0x002f, /* AICCFIXFREQ0[15:8] 00000000 */
1896         0x0030, /* AICCFIXFREQ0[7:0] 00000000 */
1897         0x0031, /* 1'b0 1'b1 1'b0 1'b0 x DAGC1STER */
1898         0x0032, /* DAGC1STEN DAGC1STER */
1899         0x0033, /* DAGC1STREF[15:8] 00001010 */
1900         0x0034, /* DAGC1STREF[7:0] 11100100 */
1901         0x0035, /* DAGC2NDE */
1902         0x0036, /* DAGC2NDREF[15:8] 00001010 */
1903         0x0037, /* DAGC2NDREF[7:0] 10000000 */
1904         0x0038, /* DAGC2NDLOCKDETRNGSEL[1:0] */
1905         0x003d, /* 1'b1 SAMGEARS */
1906         0x0040, /* SAMLFGMA */
1907         0x0041, /* SAMLFBWM */
1908         0x0044, /* 1'b1 CRGEARSHE */
1909         0x0045, /* CRLFGMAN */
1910         0x0046, /* CFLFBWMA */
1911         0x0047, /* CRLFGMAN */
1912         0x0048, /* x x x x CRLFGSTEP_VS[3:0] xxxx1001 */
1913         0x0049, /* CRLFBWMA */
1914         0x004a, /* CRLFBWMA */
1915         0x0050, /* 1'b0 1'b1 1'b1 1'b0 MSECALCDA */
1916         0x0070, /* TPOUTEN TPIFEN TPCLKOUTE */
1917         0x0071, /* TPSENB TPSSOPBITE */
1918         0x0073, /* TP47HINS x x CHBERINT PERMODE[1:0] PERINT[1:0] 1xx11100 */
1919         0x0075, /* x x x x x IQSWAPCTRL[2:0] xxxxx000 */
1920         0x0076, /* NBERCON NBERST NBERPOL NBERWSYN */
1921         0x0077, /* x NBERLOSTTH[2:0] NBERACQTH[3:0] x0000000 */
1922         0x0078, /* NBERPOLY[31:24] 00000000 */
1923         0x0079, /* NBERPOLY[23:16] 00000000 */
1924         0x007a, /* NBERPOLY[15:8] 00000000 */
1925         0x007b, /* NBERPOLY[7:0] 00000000 */
1926         0x007c, /* NBERPED[31:24] 00000000 */
1927         0x007d, /* NBERPED[23:16] 00000000 */
1928         0x007e, /* NBERPED[15:8] 00000000 */
1929         0x007f, /* NBERPED[7:0] 00000000 */
1930         0x0080, /* x AGCLOCK DAGCLOCK SYSLOCK x x NEVERLOCK[1:0] */
1931         0x0085, /* SPECINVST */
1932         0x0088, /* SYSLOCKTIME[15:8] */
1933         0x0089, /* SYSLOCKTIME[7:0] */
1934         0x008c, /* FECLOCKTIME[15:8] */
1935         0x008d, /* FECLOCKTIME[7:0] */
1936         0x008e, /* AGCACCOUT[15:8] */
1937         0x008f, /* AGCACCOUT[7:0] */
1938         0x0090, /* AICCREJSTATUS[3:0] AICCREJBUSY[3:0] */
1939         0x0091, /* AICCVSYNC */
1940         0x009c, /* CARRFREQOFFSET[15:8] */
1941         0x009d, /* CARRFREQOFFSET[7:0] */
1942         0x00a1, /* SAMFREQOFFSET[23:16] */
1943         0x00a2, /* SAMFREQOFFSET[15:8] */
1944         0x00a3, /* SAMFREQOFFSET[7:0] */
1945         0x00a6, /* SYNCLOCK SYNCLOCKH */
1946 #if 0 /* covered elsewhere */
1947         0x00e8, /* CONSTPWR[15:8] */
1948         0x00e9, /* CONSTPWR[7:0] */
1949         0x00ea, /* BMSE[15:8] */
1950         0x00eb, /* BMSE[7:0] */
1951         0x00ec, /* MSE[15:8] */
1952         0x00ed, /* MSE[7:0] */
1953         0x00ee, /* CONSTI[7:0] */
1954         0x00ef, /* CONSTQ[7:0] */
1955 #endif
1956         0x00f4, /* TPIFTPERRCNT[7:0] */
1957         0x00f5, /* TPCORREC */
1958         0x00f6, /* VBBER[15:8] */
1959         0x00f7, /* VBBER[7:0] */
1960         0x00f8, /* VABER[15:8] */
1961         0x00f9, /* VABER[7:0] */
1962         0x00fa, /* TPERRCNT[7:0] */
1963         0x00fb, /* NBERLOCK x x x x x x x */
1964         0x00fc, /* NBERVALUE[31:24] */
1965         0x00fd, /* NBERVALUE[23:16] */
1966         0x00fe, /* NBERVALUE[15:8] */
1967         0x00ff, /* NBERVALUE[7:0] */
1968         0x1000, /* 1'b0 WODAGCOU */
1969         0x1005, /* x x 1'b1 1'b1 x SRD_Q_QM */
1970         0x1009, /* SRDWAITTIME[7:0] (10msec) 00100011 */
1971         0x100a, /* SRDWAITTIME_CQS[7:0] (msec) 01100100 */
1972         0x101a, /* x 1'b1 1'b0 1'b0 x QMDQAMMODE[2:0] x100x010 */
1973         0x1036, /* 1'b0 1'b1 1'b0 1'b0 SAMGSEND_CQS[3:0] 01001110 */
1974         0x103c, /* SAMGSAUTOSTL_V[3:0] SAMGSAUTOEDL_V[3:0] 01000110 */
1975         0x103d, /* 1'b1 1'b1 SAMCNORMBP_V[1:0] 1'b0 1'b0 SAMMODESEL_V[1:0] 11100001 */
1976         0x103f, /* SAMZTEDSE */
1977         0x105d, /* EQSTATUSE */
1978         0x105f, /* x PMAPG2_V[2:0] x DMAPG2_V[2:0] x001x011 */
1979         0x1060, /* 1'b1 EQSTATUSE */
1980         0x1061, /* CRMAPBWSTL_V[3:0] CRMAPBWEDL_V[3:0] 00000100 */
1981         0x1065, /* 1'b0 x CRMODE_V[1:0] 1'b1 x 1'b1 x 0x111x1x */
1982         0x1066, /* 1'b0 1'b0 1'b1 1'b0 1'b1 PNBOOSTSE */
1983         0x1068, /* CREPHNGAIN2_V[3:0] CREPHNPBW_V[3:0] 10010001 */
1984         0x106e, /* x x x x x CREPHNEN_ */
1985         0x106f, /* CREPHNTH_V[7:0] 00010101 */
1986         0x1072, /* CRSWEEPN */
1987         0x1073, /* CRPGAIN_V[3:0] x x 1'b1 1'b1 1001xx11 */
1988         0x1074, /* CRPBW_V[3:0] x x 1'b1 1'b1 0001xx11 */
1989         0x1080, /* DAFTSTATUS[1:0] x x x x x x */
1990         0x1081, /* SRDSTATUS[1:0] x x x x x SRDLOCK */
1991         0x10a9, /* EQSTATUS_CQS[1:0] x x x x x x */
1992         0x10b7, /* EQSTATUS_V[1:0] x x x x x x */
1993 #if 0 /* SMART_ANT */
1994         0x1f00, /* MODEDETE */
1995         0x1f01, /* x x x x x x x SFNRST xxxxxxx0 */
1996         0x1f03, /* NUMOFANT[7:0] 10000000 */
1997         0x1f04, /* x SELMASK[6:0] x0000000 */
1998         0x1f05, /* x SETMASK[6:0] x0000000 */
1999         0x1f06, /* x TXDATA[6:0] x0000000 */
2000         0x1f07, /* x CHNUMBER[6:0] x0000000 */
2001         0x1f09, /* AGCTIME[23:16] 10011000 */
2002         0x1f0a, /* AGCTIME[15:8] 10010110 */
2003         0x1f0b, /* AGCTIME[7:0] 10000000 */
2004         0x1f0c, /* ANTTIME[31:24] 00000000 */
2005         0x1f0d, /* ANTTIME[23:16] 00000011 */
2006         0x1f0e, /* ANTTIME[15:8] 10010000 */
2007         0x1f0f, /* ANTTIME[7:0] 10010000 */
2008         0x1f11, /* SYNCTIME[23:16] 10011000 */
2009         0x1f12, /* SYNCTIME[15:8] 10010110 */
2010         0x1f13, /* SYNCTIME[7:0] 10000000 */
2011         0x1f14, /* SNRTIME[31:24] 00000001 */
2012         0x1f15, /* SNRTIME[23:16] 01111101 */
2013         0x1f16, /* SNRTIME[15:8] 01111000 */
2014         0x1f17, /* SNRTIME[7:0] 01000000 */
2015         0x1f19, /* FECTIME[23:16] 00000000 */
2016         0x1f1a, /* FECTIME[15:8] 01110010 */
2017         0x1f1b, /* FECTIME[7:0] 01110000 */
2018         0x1f1d, /* FECTHD[7:0] 00000011 */
2019         0x1f1f, /* SNRTHD[23:16] 00001000 */
2020         0x1f20, /* SNRTHD[15:8] 01111111 */
2021         0x1f21, /* SNRTHD[7:0] 10000101 */
2022         0x1f80, /* IRQFLG x x SFSDRFLG MODEBFLG SAVEFLG SCANFLG TRACKFLG */
2023         0x1f81, /* x SYNCCON SNRCON FECCON x STDBUSY SYNCRST AGCFZCO */
2024         0x1f82, /* x x x SCANOPCD[4:0] */
2025         0x1f83, /* x x x x MAINOPCD[3:0] */
2026         0x1f84, /* x x RXDATA[13:8] */
2027         0x1f85, /* RXDATA[7:0] */
2028         0x1f86, /* x x SDTDATA[13:8] */
2029         0x1f87, /* SDTDATA[7:0] */
2030         0x1f89, /* ANTSNR[23:16] */
2031         0x1f8a, /* ANTSNR[15:8] */
2032         0x1f8b, /* ANTSNR[7:0] */
2033         0x1f8c, /* x x x x ANTFEC[13:8] */
2034         0x1f8d, /* ANTFEC[7:0] */
2035         0x1f8e, /* MAXCNT[7:0] */
2036         0x1f8f, /* SCANCNT[7:0] */
2037         0x1f91, /* MAXPW[23:16] */
2038         0x1f92, /* MAXPW[15:8] */
2039         0x1f93, /* MAXPW[7:0] */
2040         0x1f95, /* CURPWMSE[23:16] */
2041         0x1f96, /* CURPWMSE[15:8] */
2042         0x1f97, /* CURPWMSE[7:0] */
2043 #endif /* SMART_ANT */
2044         0x211f, /* 1'b1 1'b1 1'b1 CIRQEN x x 1'b0 1'b0 1111xx00 */
2045         0x212a, /* EQAUTOST */
2046         0x2122, /* CHFAST[7:0] 01100000 */
2047         0x212b, /* FFFSTEP_V[3:0] x FBFSTEP_V[2:0] 0001x001 */
2048         0x212c, /* PHDEROTBWSEL[3:0] 1'b1 1'b1 1'b1 1'b0 10001110 */
2049         0x212d, /* 1'b1 1'b1 1'b1 1'b1 x x TPIFLOCKS */
2050         0x2135, /* DYNTRACKFDEQ[3:0] x 1'b0 1'b0 1'b0 1010x000 */
2051         0x2141, /* TRMODE[1:0] 1'b1 1'b1 1'b0 1'b1 1'b1 1'b1 01110111 */
2052         0x2162, /* AICCCTRLE */
2053         0x2173, /* PHNCNFCNT[7:0] 00000100 */
2054         0x2179, /* 1'b0 1'b0 1'b0 1'b1 x BADSINGLEDYNTRACKFBF[2:0] 0001x001 */
2055         0x217a, /* 1'b0 1'b0 1'b0 1'b1 x BADSLOWSINGLEDYNTRACKFBF[2:0] 0001x001 */
2056         0x217e, /* CNFCNTTPIF[7:0] 00001000 */
2057         0x217f, /* TPERRCNTTPIF[7:0] 00000001 */
2058         0x2180, /* x x x x x x FBDLYCIR[9:8] */
2059         0x2181, /* FBDLYCIR[7:0] */
2060         0x2185, /* MAXPWRMAIN[7:0] */
2061         0x2191, /* NCOMBDET x x x x x x x */
2062         0x2199, /* x MAINSTRON */
2063         0x219a, /* FFFEQSTEPOUT_V[3:0] FBFSTEPOUT_V[2:0] */
2064         0x21a1, /* x x SNRREF[5:0] */
2065         0x2845, /* 1'b0 1'b1 x x FFFSTEP_CQS[1:0] FFFCENTERTAP[1:0] 01xx1110 */
2066         0x2846, /* 1'b0 x 1'b0 1'b1 FBFSTEP_CQS[1:0] 1'b1 1'b0 0x011110 */
2067         0x2847, /* ENNOSIGDE */
2068         0x2849, /* 1'b1 1'b1 NOUSENOSI */
2069         0x284a, /* EQINITWAITTIME[7:0] 01100100 */
2070         0x3000, /* 1'b1 1'b1 1'b1 x x x 1'b0 RPTRSTM */
2071         0x3001, /* RPTRSTWAITTIME[7:0] (100msec) 00110010 */
2072         0x3031, /* FRAMELOC */
2073         0x3032, /* 1'b1 1'b0 1'b0 1'b0 x x FRAMELOCKMODE_CQS[1:0] 1000xx11 */
2074         0x30a9, /* VDLOCK_Q FRAMELOCK */
2075         0x30aa, /* MPEGLOCK */
2076 };
2077
2078 #define numDumpRegs (sizeof(regtab)/sizeof(regtab[0]))
2079 static u8 regval1[numDumpRegs] = {0, };
2080 static u8 regval2[numDumpRegs] = {0, };
2081
2082 static void lgdt3306a_DumpAllRegs(struct lgdt3306a_state *state)
2083 {
2084                 memset(regval2, 0xff, sizeof(regval2));
2085                 lgdt3306a_DumpRegs(state);
2086 }
2087
2088 static void lgdt3306a_DumpRegs(struct lgdt3306a_state *state)
2089 {
2090         int i;
2091         int sav_debug = debug;
2092
2093         if ((debug & DBG_DUMP) == 0)
2094                 return;
2095         debug &= ~DBG_REG; /* suppress DBG_REG during reg dump */
2096
2097         lg_debug("\n");
2098
2099         for (i = 0; i < numDumpRegs; i++) {
2100                 lgdt3306a_read_reg(state, regtab[i], &regval1[i]);
2101                 if (regval1[i] != regval2[i]) {
2102                         lg_debug(" %04X = %02X\n", regtab[i], regval1[i]);
2103                                  regval2[i] = regval1[i];
2104                 }
2105         }
2106         debug = sav_debug;
2107 }
2108 #endif /* DBG_DUMP */
2109
2110
2111
2112 static struct dvb_frontend_ops lgdt3306a_ops = {
2113         .delsys = { SYS_ATSC, SYS_DVBC_ANNEX_B },
2114         .info = {
2115                 .name = "LG Electronics LGDT3306A VSB/QAM Frontend",
2116 #if 0
2117                 .type               = FE_ATSC,
2118 #endif
2119                 .frequency_min      = 54000000,
2120                 .frequency_max      = 858000000,
2121                 .frequency_stepsize = 62500,
2122                 .caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB
2123         },
2124         .i2c_gate_ctrl        = lgdt3306a_i2c_gate_ctrl,
2125         .init                 = lgdt3306a_init,
2126         .sleep                = lgdt3306a_fe_sleep,
2127         /* if this is set, it overrides the default swzigzag */
2128         .tune                 = lgdt3306a_tune,
2129         .set_frontend         = lgdt3306a_set_parameters,
2130         .get_frontend         = lgdt3306a_get_frontend,
2131         .get_frontend_algo    = lgdt3306a_get_frontend_algo,
2132         .get_tune_settings    = lgdt3306a_get_tune_settings,
2133         .read_status          = lgdt3306a_read_status,
2134         .read_ber             = lgdt3306a_read_ber,
2135         .read_signal_strength = lgdt3306a_read_signal_strength,
2136         .read_snr             = lgdt3306a_read_snr,
2137         .read_ucblocks        = lgdt3306a_read_ucblocks,
2138         .release              = lgdt3306a_release,
2139         .ts_bus_ctrl          = lgdt3306a_ts_bus_ctrl,
2140         .search               = lgdt3306a_search,
2141 };
2142
2143 MODULE_DESCRIPTION("LG Electronics LGDT3306A ATSC/QAM-B Demodulator Driver");
2144 MODULE_AUTHOR("Fred Richter <frichter@hauppauge.com>");
2145 MODULE_LICENSE("GPL");
2146 MODULE_VERSION("0.2");
2147
2148 /*
2149  * Local variables:
2150  * c-basic-offset: 8
2151  * End:
2152  */