2 * Support for LGDT3306A - 8VSB/QAM-B
4 * Copyright (C) 2013 Fred Richter <frichter@hauppauge.com>
5 * - driver structure based on lgdt3305.[ch] by Michael Krufky
6 * - code based on LG3306_V0.35 API by LG Electronics Inc.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 #include <asm/div64.h>
25 #include <linux/dvb/frontend.h>
27 #include "lgdt3306a.h"
31 module_param(debug, int, 0644);
32 MODULE_PARM_DESC(debug, "set debug level (info=1, reg=2 (or-able))");
36 #define DBG_DUMP 4 /* FGR - comment out to remove dump code */
38 #define lg_printk(kern, fmt, arg...) \
39 printk(kern "%s(): " fmt, __func__, ##arg)
41 #define lg_info(fmt, arg...) printk(KERN_INFO "lgdt3306a: " fmt, ##arg)
42 #define lg_warn(fmt, arg...) lg_printk(KERN_WARNING, fmt, ##arg)
43 #define lg_err(fmt, arg...) lg_printk(KERN_ERR, fmt, ##arg)
44 #define lg_dbg(fmt, arg...) if (debug & DBG_INFO) \
45 lg_printk(KERN_DEBUG, fmt, ##arg)
46 #define lg_reg(fmt, arg...) if (debug & DBG_REG) \
47 lg_printk(KERN_DEBUG, fmt, ##arg)
49 #define lg_chkerr(ret) \
54 lg_err("error %d on line %d\n", ret, __LINE__); \
58 struct lgdt3306a_state {
59 struct i2c_adapter *i2c_adap;
60 const struct lgdt3306a_config *cfg;
62 struct dvb_frontend frontend;
64 fe_modulation_t current_modulation;
65 u32 current_frequency;
69 /* -----------------------------------------------
70 LG3306A Register Usage
71 (LG does not really name the registers, so this code does not either)
72 0000 -> 00FF Common control and status
73 1000 -> 10FF Synchronizer control and status
74 1F00 -> 1FFF Smart Antenna control and status
75 2100 -> 21FF VSB Equalizer control and status
76 2800 -> 28FF QAM Equalizer control and status
77 3000 -> 30FF FEC control and status
78 ---------------------------------------------- */
80 enum lgdt3306a_lock_status {
83 LG3306_UNKNOWN_LOCK = 0xFF
86 enum lgdt3306a_neverlock_status {
87 LG3306_NL_INIT = 0x00,
88 LG3306_NL_PROCESS = 0x01,
89 LG3306_NL_LOCK = 0x02,
90 LG3306_NL_FAIL = 0x03,
91 LG3306_NL_UNKNOWN = 0xFF
94 enum lgdt3306a_modulation {
98 LG3306_UNKNOWN_MODE = 0xFF
101 enum lgdt3306a_lock_check {
110 static void lgdt3306a_DumpAllRegs(struct lgdt3306a_state *state);
111 static void lgdt3306a_DumpRegs(struct lgdt3306a_state *state);
115 static int lgdt3306a_write_reg(struct lgdt3306a_state *state, u16 reg, u8 val)
118 u8 buf[] = { reg >> 8, reg & 0xff, val };
119 struct i2c_msg msg = {
120 .addr = state->cfg->i2c_addr, .flags = 0,
121 .buf = buf, .len = 3,
124 lg_reg("reg: 0x%04x, val: 0x%02x\n", reg, val);
126 ret = i2c_transfer(state->i2c_adap, &msg, 1);
129 lg_err("error (addr %02x %02x <- %02x, err = %i)\n",
130 msg.buf[0], msg.buf[1], msg.buf[2], ret);
139 static int lgdt3306a_read_reg(struct lgdt3306a_state *state, u16 reg, u8 *val)
142 u8 reg_buf[] = { reg >> 8, reg & 0xff };
143 struct i2c_msg msg[] = {
144 { .addr = state->cfg->i2c_addr,
145 .flags = 0, .buf = reg_buf, .len = 2 },
146 { .addr = state->cfg->i2c_addr,
147 .flags = I2C_M_RD, .buf = val, .len = 1 },
150 ret = i2c_transfer(state->i2c_adap, msg, 2);
153 lg_err("error (addr %02x reg %04x error (ret == %i)\n",
154 state->cfg->i2c_addr, reg, ret);
160 lg_reg("reg: 0x%04x, val: 0x%02x\n", reg, *val);
165 #define read_reg(state, reg) \
168 int ret = lgdt3306a_read_reg(state, reg, &__val); \
169 if (lg_chkerr(ret)) \
174 static int lgdt3306a_set_reg_bit(struct lgdt3306a_state *state,
175 u16 reg, int bit, int onoff)
180 lg_reg("reg: 0x%04x, bit: %d, level: %d\n", reg, bit, onoff);
182 ret = lgdt3306a_read_reg(state, reg, &val);
187 val |= (onoff & 1) << bit;
189 ret = lgdt3306a_write_reg(state, reg, val);
195 /* ------------------------------------------------------------------------ */
197 static int lgdt3306a_soft_reset(struct lgdt3306a_state *state)
203 ret = lgdt3306a_set_reg_bit(state, 0x0000, 7, 0);
208 ret = lgdt3306a_set_reg_bit(state, 0x0000, 7, 1);
215 static int lgdt3306a_mpeg_mode(struct lgdt3306a_state *state,
216 enum lgdt3306a_mpeg_mode mode)
221 lg_dbg("(%d)\n", mode);
222 /* transport packet format */
223 ret = lgdt3306a_set_reg_bit(state, 0x0071, 7, mode == LGDT3306A_MPEG_PARALLEL?1:0); /* TPSENB=0x80 */
227 /* start of packet signal duration */
228 ret = lgdt3306a_set_reg_bit(state, 0x0071, 6, 0); /* TPSSOPBITEN=0x40; 0=byte duration, 1=bit duration */
232 ret = lgdt3306a_read_reg(state, 0x0070, &val);
236 val |= 0x10; /* TPCLKSUPB=0x10 */
238 if (mode == LGDT3306A_MPEG_PARALLEL)
241 ret = lgdt3306a_write_reg(state, 0x0070, val);
248 static int lgdt3306a_mpeg_mode_polarity(struct lgdt3306a_state *state,
249 enum lgdt3306a_tp_clock_edge edge,
250 enum lgdt3306a_tp_valid_polarity valid)
255 lg_dbg("edge=%d, valid=%d\n", edge, valid);
257 ret = lgdt3306a_read_reg(state, 0x0070, &val);
261 val &= ~0x06; /* TPCLKPOL=0x04, TPVALPOL=0x02 */
263 if (edge == LGDT3306A_TPCLK_RISING_EDGE)
265 if (valid == LGDT3306A_TP_VALID_HIGH)
268 ret = lgdt3306a_write_reg(state, 0x0070, val);
275 static int lgdt3306a_mpeg_tristate(struct lgdt3306a_state *state,
281 lg_dbg("(%d)\n", mode);
284 ret = lgdt3306a_read_reg(state, 0x0070, &val);
287 val &= ~0xA8; /* Tristate bus; TPOUTEN=0x80, TPCLKOUTEN=0x20, TPDATAOUTEN=0x08 */
288 ret = lgdt3306a_write_reg(state, 0x0070, val);
292 ret = lgdt3306a_set_reg_bit(state, 0x0003, 6, 1); /* AGCIFOUTENB=0x40; 1=Disable IFAGC pin */
297 ret = lgdt3306a_set_reg_bit(state, 0x0003, 6, 0); /* enable IFAGC pin */
301 ret = lgdt3306a_read_reg(state, 0x0070, &val);
305 val |= 0xA8; /* enable bus */
306 ret = lgdt3306a_write_reg(state, 0x0070, val);
315 static int lgdt3306a_ts_bus_ctrl(struct dvb_frontend *fe, int acquire)
317 struct lgdt3306a_state *state = fe->demodulator_priv;
319 lg_dbg("acquire=%d\n", acquire);
321 return lgdt3306a_mpeg_tristate(state, acquire ? 0 : 1);
325 static int lgdt3306a_power(struct lgdt3306a_state *state,
330 lg_dbg("(%d)\n", mode);
333 ret = lgdt3306a_set_reg_bit(state, 0x0000, 7, 0); /* into reset */
337 ret = lgdt3306a_set_reg_bit(state, 0x0000, 0, 0); /* power down */
342 ret = lgdt3306a_set_reg_bit(state, 0x0000, 7, 1); /* out of reset */
346 ret = lgdt3306a_set_reg_bit(state, 0x0000, 0, 1); /* power up */
352 lgdt3306a_DumpAllRegs(state);
359 static int lgdt3306a_set_vsb(struct lgdt3306a_state *state)
366 /* 0. Spectrum inversion detection manual; spectrum inverted */
367 ret = lgdt3306a_read_reg(state, 0x0002, &val);
368 val &= 0xF7; /* SPECINVAUTO Off */
369 val |= 0x04; /* SPECINV On */
370 ret = lgdt3306a_write_reg(state, 0x0002, val);
374 /* 1. Selection of standard mode(0x08=QAM, 0x80=VSB) */
375 ret = lgdt3306a_write_reg(state, 0x0008, 0x80);
379 /* 2. Bandwidth mode for VSB(6MHz) */
380 ret = lgdt3306a_read_reg(state, 0x0009, &val);
382 val |= 0x0C; /* STDOPDETTMODE[2:0]=3 */
383 ret = lgdt3306a_write_reg(state, 0x0009, val);
387 /* 3. QAM mode detection mode(None) */
388 ret = lgdt3306a_read_reg(state, 0x0009, &val);
389 val &= 0xFC; /* STDOPDETCMODE[1:0]=0 */
390 ret = lgdt3306a_write_reg(state, 0x0009, val);
394 /* 4. ADC sampling frequency rate(2x sampling) */
395 ret = lgdt3306a_read_reg(state, 0x000D, &val);
396 val &= 0xBF; /* SAMPLING4XFEN=0 */
397 ret = lgdt3306a_write_reg(state, 0x000D, val);
402 /* FGR - disable any AICC filtering, testing only */
404 ret = lgdt3306a_write_reg(state, 0x0024, 0x00);
408 /* AICCFIXFREQ0 NT N-1(Video rejection) */
409 ret = lgdt3306a_write_reg(state, 0x002E, 0x00);
410 ret = lgdt3306a_write_reg(state, 0x002F, 0x00);
411 ret = lgdt3306a_write_reg(state, 0x0030, 0x00);
413 /* AICCFIXFREQ1 NT N-1(Audio rejection) */
414 ret = lgdt3306a_write_reg(state, 0x002B, 0x00);
415 ret = lgdt3306a_write_reg(state, 0x002C, 0x00);
416 ret = lgdt3306a_write_reg(state, 0x002D, 0x00);
418 /* AICCFIXFREQ2 NT Co-Channel(Video rejection) */
419 ret = lgdt3306a_write_reg(state, 0x0028, 0x00);
420 ret = lgdt3306a_write_reg(state, 0x0029, 0x00);
421 ret = lgdt3306a_write_reg(state, 0x002A, 0x00);
423 /* AICCFIXFREQ3 NT Co-Channel(Audio rejection) */
424 ret = lgdt3306a_write_reg(state, 0x0025, 0x00);
425 ret = lgdt3306a_write_reg(state, 0x0026, 0x00);
426 ret = lgdt3306a_write_reg(state, 0x0027, 0x00);
429 /* FGR - this works well for HVR-1955,1975 */
431 /* 5. AICCOPMODE NT N-1 Adj. */
432 ret = lgdt3306a_write_reg(state, 0x0024, 0x5A);
436 /* AICCFIXFREQ0 NT N-1(Video rejection) */
437 ret = lgdt3306a_write_reg(state, 0x002E, 0x5A);
438 ret = lgdt3306a_write_reg(state, 0x002F, 0x00);
439 ret = lgdt3306a_write_reg(state, 0x0030, 0x00);
441 /* AICCFIXFREQ1 NT N-1(Audio rejection) */
442 ret = lgdt3306a_write_reg(state, 0x002B, 0x36);
443 ret = lgdt3306a_write_reg(state, 0x002C, 0x00);
444 ret = lgdt3306a_write_reg(state, 0x002D, 0x00);
446 /* AICCFIXFREQ2 NT Co-Channel(Video rejection) */
447 ret = lgdt3306a_write_reg(state, 0x0028, 0x2A);
448 ret = lgdt3306a_write_reg(state, 0x0029, 0x00);
449 ret = lgdt3306a_write_reg(state, 0x002A, 0x00);
451 /* AICCFIXFREQ3 NT Co-Channel(Audio rejection) */
452 ret = lgdt3306a_write_reg(state, 0x0025, 0x06);
453 ret = lgdt3306a_write_reg(state, 0x0026, 0x00);
454 ret = lgdt3306a_write_reg(state, 0x0027, 0x00);
457 ret = lgdt3306a_read_reg(state, 0x001E, &val);
460 ret = lgdt3306a_write_reg(state, 0x001E, val);
462 ret = lgdt3306a_write_reg(state, 0x0022, 0x08);
464 ret = lgdt3306a_write_reg(state, 0x0023, 0xFF);
466 ret = lgdt3306a_read_reg(state, 0x211F, &val);
468 ret = lgdt3306a_write_reg(state, 0x211F, val);
470 ret = lgdt3306a_write_reg(state, 0x2173, 0x01);
472 ret = lgdt3306a_read_reg(state, 0x1061, &val);
475 ret = lgdt3306a_write_reg(state, 0x1061, val);
477 ret = lgdt3306a_read_reg(state, 0x103D, &val);
479 ret = lgdt3306a_write_reg(state, 0x103D, val);
481 ret = lgdt3306a_write_reg(state, 0x2122, 0x40);
483 ret = lgdt3306a_read_reg(state, 0x2141, &val);
485 ret = lgdt3306a_write_reg(state, 0x2141, val);
487 ret = lgdt3306a_read_reg(state, 0x2135, &val);
490 ret = lgdt3306a_write_reg(state, 0x2135, val);
492 ret = lgdt3306a_read_reg(state, 0x0003, &val);
494 ret = lgdt3306a_write_reg(state, 0x0003, val);
496 ret = lgdt3306a_read_reg(state, 0x001C, &val);
498 ret = lgdt3306a_write_reg(state, 0x001C, val);
500 /* 6. EQ step size */
501 ret = lgdt3306a_read_reg(state, 0x2179, &val);
503 ret = lgdt3306a_write_reg(state, 0x2179, val);
505 ret = lgdt3306a_read_reg(state, 0x217A, &val);
507 ret = lgdt3306a_write_reg(state, 0x217A, val);
510 ret = lgdt3306a_soft_reset(state);
514 lg_dbg("complete\n");
519 static int lgdt3306a_set_qam(struct lgdt3306a_state *state, int modulation)
524 lg_dbg("modulation=%d\n", modulation);
526 /* 1. Selection of standard mode(0x08=QAM, 0x80=VSB) */
527 ret = lgdt3306a_write_reg(state, 0x0008, 0x08);
531 /* 1a. Spectrum inversion detection to Auto */
532 ret = lgdt3306a_read_reg(state, 0x0002, &val);
533 val &= 0xFB; /* SPECINV Off */
534 val |= 0x08; /* SPECINVAUTO On */
535 ret = lgdt3306a_write_reg(state, 0x0002, val);
539 /* 2. Bandwidth mode for QAM */
540 ret = lgdt3306a_read_reg(state, 0x0009, &val);
541 val &= 0xE3; /* STDOPDETTMODE[2:0]=0 VSB Off */
542 ret = lgdt3306a_write_reg(state, 0x0009, val);
546 /* 3. : 64QAM/256QAM detection(manual, auto) */
547 ret = lgdt3306a_read_reg(state, 0x0009, &val);
549 val |= 0x02; /* STDOPDETCMODE[1:0]=1=Manual 2=Auto */
550 ret = lgdt3306a_write_reg(state, 0x0009, val);
554 /* 3a. : 64QAM/256QAM selection for manual */
555 ret = lgdt3306a_read_reg(state, 0x101a, &val);
557 if (modulation == QAM_64)
558 val |= 0x02; /* QMDQMODE[2:0]=2=QAM64 */
560 val |= 0x04; /* QMDQMODE[2:0]=4=QAM256 */
562 ret = lgdt3306a_write_reg(state, 0x101a, val);
566 /* 4. ADC sampling frequency rate(4x sampling) */
567 ret = lgdt3306a_read_reg(state, 0x000D, &val);
569 val |= 0x40; /* SAMPLING4XFEN=1 */
570 ret = lgdt3306a_write_reg(state, 0x000D, val);
574 /* 5. No AICC operation in QAM mode */
575 ret = lgdt3306a_read_reg(state, 0x0024, &val);
577 ret = lgdt3306a_write_reg(state, 0x0024, val);
582 ret = lgdt3306a_soft_reset(state);
586 lg_dbg("complete\n");
591 static int lgdt3306a_set_modulation(struct lgdt3306a_state *state,
592 struct dtv_frontend_properties *p)
598 switch (p->modulation) {
600 ret = lgdt3306a_set_vsb(state);
603 ret = lgdt3306a_set_qam(state, QAM_64);
606 ret = lgdt3306a_set_qam(state, QAM_256);
614 state->current_modulation = p->modulation;
620 /* ------------------------------------------------------------------------ */
622 static int lgdt3306a_agc_setup(struct lgdt3306a_state *state,
623 struct dtv_frontend_properties *p)
625 /* TODO: anything we want to do here??? */
628 switch (p->modulation) {
640 /* ------------------------------------------------------------------------ */
642 static int lgdt3306a_set_inversion(struct lgdt3306a_state *state,
647 lg_dbg("(%d)\n", inversion);
649 ret = lgdt3306a_set_reg_bit(state, 0x0002, 2, inversion ? 1 : 0);
653 static int lgdt3306a_set_inversion_auto(struct lgdt3306a_state *state,
658 lg_dbg("(%d)\n", enabled);
660 /* 0=Manual 1=Auto(QAM only) */
661 ret = lgdt3306a_set_reg_bit(state, 0x0002, 3, enabled);/* SPECINVAUTO=0x04 */
665 static int lgdt3306a_spectral_inversion(struct lgdt3306a_state *state,
666 struct dtv_frontend_properties *p,
671 lg_dbg("(%d)\n", inversion);
673 /* FGR - spectral_inversion defaults already set for VSB and QAM; can enable later if desired */
675 ret = lgdt3306a_set_inversion(state, inversion);
677 switch (p->modulation) {
679 ret = lgdt3306a_set_inversion_auto(state, 0); /* Manual only for VSB */
683 ret = lgdt3306a_set_inversion_auto(state, 1); /* Auto ok for QAM */
692 static int lgdt3306a_set_if(struct lgdt3306a_state *state,
693 struct dtv_frontend_properties *p)
699 switch (p->modulation) {
701 if_freq_khz = state->cfg->vsb_if_khz;
705 if_freq_khz = state->cfg->qam_if_khz;
711 switch (if_freq_khz) {
713 lg_warn("IF=%d KHz is not supportted, 3250 assumed\n", if_freq_khz);
715 case 3250: /* 3.25Mhz */
719 case 3500: /* 3.50Mhz */
723 case 4000: /* 4.00Mhz */
727 case 5000: /* 5.00Mhz */
731 case 5380: /* 5.38Mhz */
736 ret = lgdt3306a_write_reg(state, 0x0010, nco1);
737 ret = lgdt3306a_write_reg(state, 0x0011, nco2);
739 lg_dbg("if_freq=%d KHz->[%04x]\n", if_freq_khz, nco1<<8 | nco2);
744 /* ------------------------------------------------------------------------ */
746 static int lgdt3306a_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
748 struct lgdt3306a_state *state = fe->demodulator_priv;
750 if (state->cfg->deny_i2c_rptr) {
751 lg_dbg("deny_i2c_rptr=%d\n", state->cfg->deny_i2c_rptr);
754 lg_dbg("(%d)\n", enable);
756 return lgdt3306a_set_reg_bit(state, 0x0002, 7, enable ? 0 : 1); /* NI2CRPTEN=0x80 */
759 static int lgdt3306a_sleep(struct lgdt3306a_state *state)
764 state->current_frequency = -1; /* force re-tune, when we wake */
766 ret = lgdt3306a_mpeg_tristate(state, 1); /* disable data bus */
770 ret = lgdt3306a_power(state, 0); /* power down */
777 static int lgdt3306a_fe_sleep(struct dvb_frontend *fe)
779 struct lgdt3306a_state *state = fe->demodulator_priv;
781 return lgdt3306a_sleep(state);
784 static int lgdt3306a_init(struct dvb_frontend *fe)
786 struct lgdt3306a_state *state = fe->demodulator_priv;
792 /* 1. Normal operation mode */
793 ret = lgdt3306a_set_reg_bit(state, 0x0001, 0, 1); /* SIMFASTENB=0x01 */
797 /* 2. Spectrum inversion auto detection (Not valid for VSB) */
798 ret = lgdt3306a_set_inversion_auto(state, 0);
802 /* 3. Spectrum inversion(According to the tuner configuration) */
803 ret = lgdt3306a_set_inversion(state, 1);
807 /* 4. Peak-to-peak voltage of ADC input signal */
808 ret = lgdt3306a_set_reg_bit(state, 0x0004, 7, 1); /* ADCSEL1V=0x80=1Vpp; 0x00=2Vpp */
812 /* 5. ADC output data capture clock phase */
813 ret = lgdt3306a_set_reg_bit(state, 0x0004, 2, 0); /* 0=same phase as ADC clock */
817 /* 5a. ADC sampling clock source */
818 ret = lgdt3306a_set_reg_bit(state, 0x0004, 3, 0); /* ADCCLKPLLSEL=0x08; 0=use ext clock, not PLL */
822 /* 6. Automatic PLL set */
823 ret = lgdt3306a_set_reg_bit(state, 0x0005, 6, 0); /* PLLSETAUTO=0x40; 0=off */
827 if (state->cfg->xtalMHz == 24) { /* 24MHz */
828 /* 7. Frequency for PLL output(0x2564 for 192MHz for 24MHz) */
829 ret = lgdt3306a_read_reg(state, 0x0005, &val);
834 ret = lgdt3306a_write_reg(state, 0x0005, val);
837 ret = lgdt3306a_write_reg(state, 0x0006, 0x64);
841 /* 8. ADC sampling frequency(0x180000 for 24MHz sampling) */
842 ret = lgdt3306a_read_reg(state, 0x000D, &val);
847 ret = lgdt3306a_write_reg(state, 0x000D, val);
851 } else if (state->cfg->xtalMHz == 25) { /* 25MHz */
852 /* 7. Frequency for PLL output */
853 ret = lgdt3306a_read_reg(state, 0x0005, &val);
858 ret = lgdt3306a_write_reg(state, 0x0005, val);
861 ret = lgdt3306a_write_reg(state, 0x0006, 0x64);
865 /* 8. ADC sampling frequency(0x190000 for 25MHz sampling) */
866 ret = lgdt3306a_read_reg(state, 0x000D, &val);
871 ret = lgdt3306a_write_reg(state, 0x000D, val);
875 lg_err("Bad xtalMHz=%d\n", state->cfg->xtalMHz);
878 ret = lgdt3306a_write_reg(state, 0x000E, 0x00);
879 ret = lgdt3306a_write_reg(state, 0x000F, 0x00);
882 /* 9. Center frequency of input signal of ADC */
883 ret = lgdt3306a_write_reg(state, 0x0010, 0x34); /* 3.25MHz */
884 ret = lgdt3306a_write_reg(state, 0x0011, 0x00);
886 /* 10. Fixed gain error value */
887 ret = lgdt3306a_write_reg(state, 0x0014, 0); /* gain error=0 */
889 /* 10a. VSB TR BW gear shift initial step */
890 ret = lgdt3306a_read_reg(state, 0x103C, &val);
892 val |= 0x20; /* SAMGSAUTOSTL_V[3:0] = 2 */
893 ret = lgdt3306a_write_reg(state, 0x103C, val);
895 /* 10b. Timing offset calibration in low temperature for VSB */
896 ret = lgdt3306a_read_reg(state, 0x103D, &val);
899 ret = lgdt3306a_write_reg(state, 0x103D, val);
901 /* 10c. Timing offset calibration in low temperature for QAM */
902 ret = lgdt3306a_read_reg(state, 0x1036, &val);
905 ret = lgdt3306a_write_reg(state, 0x1036, val);
907 /* 11. Using the imaginary part of CIR in CIR loading */
908 ret = lgdt3306a_read_reg(state, 0x211F, &val);
909 val &= 0xEF; /* do not use imaginary of CIR */
910 ret = lgdt3306a_write_reg(state, 0x211F, val);
912 /* 12. Control of no signal detector function */
913 ret = lgdt3306a_read_reg(state, 0x2849, &val);
914 val &= 0xEF; /* NOUSENOSIGDET=0, enable no signal detector */
915 ret = lgdt3306a_write_reg(state, 0x2849, val);
917 /* FGR - put demod in some known mode */
918 ret = lgdt3306a_set_vsb(state);
920 /* 13. TP stream format */
921 ret = lgdt3306a_mpeg_mode(state, state->cfg->mpeg_mode);
923 /* 14. disable output buses */
924 ret = lgdt3306a_mpeg_tristate(state, 1);
926 /* 15. Sleep (in reset) */
927 ret = lgdt3306a_sleep(state);
934 static int lgdt3306a_set_parameters(struct dvb_frontend *fe)
936 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
937 struct lgdt3306a_state *state = fe->demodulator_priv;
940 lg_dbg("(%d, %d)\n", p->frequency, p->modulation);
942 if (state->current_frequency == p->frequency &&
943 state->current_modulation == p->modulation) {
944 lg_dbg(" (already set, skipping ...)\n");
947 state->current_frequency = -1;
948 state->current_modulation = -1;
950 ret = lgdt3306a_power(state, 1); /* power up */
954 if (fe->ops.tuner_ops.set_params) {
955 ret = fe->ops.tuner_ops.set_params(fe);
956 if (fe->ops.i2c_gate_ctrl)
957 fe->ops.i2c_gate_ctrl(fe, 0);
961 state->current_frequency = p->frequency;
965 ret = lgdt3306a_set_modulation(state, p);
969 ret = lgdt3306a_agc_setup(state, p);
973 ret = lgdt3306a_set_if(state, p);
977 ret = lgdt3306a_spectral_inversion(state, p,
978 state->cfg->spectral_inversion ? 1 : 0);
982 ret = lgdt3306a_mpeg_mode(state, state->cfg->mpeg_mode);
986 ret = lgdt3306a_mpeg_mode_polarity(state,
987 state->cfg->tpclk_edge,
988 state->cfg->tpvalid_polarity);
992 ret = lgdt3306a_mpeg_tristate(state, 0); /* enable data bus */
996 ret = lgdt3306a_soft_reset(state);
1001 lgdt3306a_DumpAllRegs(state);
1003 state->current_frequency = p->frequency;
1008 static int lgdt3306a_get_frontend(struct dvb_frontend *fe)
1010 struct lgdt3306a_state *state = fe->demodulator_priv;
1011 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1013 lg_dbg("(%u, %d)\n", state->current_frequency, state->current_modulation);
1015 p->modulation = state->current_modulation;
1016 p->frequency = state->current_frequency;
1020 static enum dvbfe_algo lgdt3306a_get_frontend_algo(struct dvb_frontend *fe)
1023 return DVBFE_ALGO_CUSTOM;
1025 return DVBFE_ALGO_HW;
1029 /* ------------------------------------------------------------------------ */
1030 static void lgdt3306a_monitor_vsb(struct lgdt3306a_state *state)
1034 u8 snrRef, maxPowerMan, nCombDet;
1037 ret = lgdt3306a_read_reg(state, 0x21A1, &val);
1038 snrRef = val & 0x3F;
1040 ret = lgdt3306a_read_reg(state, 0x2185, &maxPowerMan);
1042 ret = lgdt3306a_read_reg(state, 0x2191, &val);
1043 nCombDet = (val & 0x80) >> 7;
1045 ret = lgdt3306a_read_reg(state, 0x2180, &val);
1046 fbDlyCir = (val & 0x03) << 8;
1047 ret = lgdt3306a_read_reg(state, 0x2181, &val);
1050 lg_dbg("snrRef=%d maxPowerMan=0x%x nCombDet=%d fbDlyCir=0x%x\n",
1051 snrRef, maxPowerMan, nCombDet, fbDlyCir);
1053 /* Carrier offset sub loop bandwidth */
1054 ret = lgdt3306a_read_reg(state, 0x1061, &val);
1056 if ((snrRef > 18) && (maxPowerMan > 0x68) && (nCombDet == 0x01) && ((fbDlyCir == 0x03FF) || (fbDlyCir < 0x6C))) {
1057 /* SNR is over 18dB and no ghosting */
1058 val |= 0x00; /* final bandwidth = 0 */
1060 val |= 0x04; /* final bandwidth = 4 */
1062 ret = lgdt3306a_write_reg(state, 0x1061, val);
1064 /* Adjust Notch Filter */
1065 ret = lgdt3306a_read_reg(state, 0x0024, &val);
1067 if (nCombDet == 0) { /* Turn on the Notch Filter */
1070 ret = lgdt3306a_write_reg(state, 0x0024, val);
1072 /* VSB Timing Recovery output normalization */
1073 ret = lgdt3306a_read_reg(state, 0x103D, &val);
1076 ret = lgdt3306a_write_reg(state, 0x103D, val);
1079 static enum lgdt3306a_modulation lgdt3306a_check_oper_mode(struct lgdt3306a_state *state)
1084 ret = lgdt3306a_read_reg(state, 0x0081, &val);
1091 ret = lgdt3306a_read_reg(state, 0x00A6, &val);
1095 return LG3306_QAM256;
1098 return LG3306_QAM64;
1101 lg_warn("UNKNOWN\n");
1102 return LG3306_UNKNOWN_MODE;
1105 static enum lgdt3306a_lock_status lgdt3306a_check_lock_status(struct lgdt3306a_state *state,
1106 enum lgdt3306a_lock_check whatLock)
1110 enum lgdt3306a_modulation modeOper;
1111 enum lgdt3306a_lock_status lockStatus;
1113 modeOper = LG3306_UNKNOWN_MODE;
1116 case LG3306_SYNC_LOCK:
1118 ret = lgdt3306a_read_reg(state, 0x00A6, &val);
1120 if ((val & 0x80) == 0x80)
1121 lockStatus = LG3306_LOCK;
1123 lockStatus = LG3306_UNLOCK;
1125 lg_dbg("SYNC_LOCK=%x\n", lockStatus);
1128 case LG3306_AGC_LOCK:
1130 ret = lgdt3306a_read_reg(state, 0x0080, &val);
1132 if ((val & 0x40) == 0x40)
1133 lockStatus = LG3306_LOCK;
1135 lockStatus = LG3306_UNLOCK;
1137 lg_dbg("AGC_LOCK=%x\n", lockStatus);
1140 case LG3306_TR_LOCK:
1142 modeOper = lgdt3306a_check_oper_mode(state);
1143 if ((modeOper == LG3306_QAM64) || (modeOper == LG3306_QAM256)) {
1144 ret = lgdt3306a_read_reg(state, 0x1094, &val);
1146 if ((val & 0x80) == 0x80)
1147 lockStatus = LG3306_LOCK;
1149 lockStatus = LG3306_UNLOCK;
1151 lockStatus = LG3306_UNKNOWN_LOCK;
1153 lg_dbg("TR_LOCK=%x\n", lockStatus);
1156 case LG3306_FEC_LOCK:
1158 modeOper = lgdt3306a_check_oper_mode(state);
1159 if ((modeOper == LG3306_QAM64) || (modeOper == LG3306_QAM256)) {
1160 ret = lgdt3306a_read_reg(state, 0x0080, &val);
1162 if ((val & 0x10) == 0x10)
1163 lockStatus = LG3306_LOCK;
1165 lockStatus = LG3306_UNLOCK;
1167 lockStatus = LG3306_UNKNOWN_LOCK;
1169 lg_dbg("FEC_LOCK=%x\n", lockStatus);
1174 lockStatus = LG3306_UNKNOWN_LOCK;
1175 lg_warn("UNKNOWN whatLock=%d\n", whatLock);
1182 static enum lgdt3306a_neverlock_status lgdt3306a_check_neverlock_status(struct lgdt3306a_state *state)
1186 enum lgdt3306a_neverlock_status lockStatus;
1188 ret = lgdt3306a_read_reg(state, 0x0080, &val);
1189 lockStatus = (enum lgdt3306a_neverlock_status)(val & 0x03);
1191 lg_dbg("NeverLock=%d", lockStatus);
1196 static void lgdt3306a_pre_monitoring(struct lgdt3306a_state *state)
1200 u8 currChDiffACQ, snrRef, mainStrong, aiccrejStatus;
1202 /* Channel variation */
1203 ret = lgdt3306a_read_reg(state, 0x21BC, &currChDiffACQ);
1205 /* SNR of Frame sync */
1206 ret = lgdt3306a_read_reg(state, 0x21A1, &val);
1207 snrRef = val & 0x3F;
1209 /* Strong Main CIR */
1210 ret = lgdt3306a_read_reg(state, 0x2199, &val);
1211 mainStrong = (val & 0x40) >> 6;
1213 ret = lgdt3306a_read_reg(state, 0x0090, &val);
1214 aiccrejStatus = (val & 0xF0) >> 4;
1216 lg_dbg("snrRef=%d mainStrong=%d aiccrejStatus=%d currChDiffACQ=0x%x\n",
1217 snrRef, mainStrong, aiccrejStatus, currChDiffACQ);
1220 if ((mainStrong == 0) && (currChDiffACQ > 0x70)) /* Dynamic ghost exists */
1222 if (mainStrong == 0) {
1223 ret = lgdt3306a_read_reg(state, 0x2135, &val);
1226 ret = lgdt3306a_write_reg(state, 0x2135, val);
1228 ret = lgdt3306a_read_reg(state, 0x2141, &val);
1231 ret = lgdt3306a_write_reg(state, 0x2141, val);
1233 ret = lgdt3306a_write_reg(state, 0x2122, 0x70);
1234 } else { /* Weak ghost or static channel */
1235 ret = lgdt3306a_read_reg(state, 0x2135, &val);
1238 ret = lgdt3306a_write_reg(state, 0x2135, val);
1240 ret = lgdt3306a_read_reg(state, 0x2141, &val);
1243 ret = lgdt3306a_write_reg(state, 0x2141, val);
1245 ret = lgdt3306a_write_reg(state, 0x2122, 0x40);
1250 static enum lgdt3306a_lock_status lgdt3306a_sync_lock_poll(struct lgdt3306a_state *state)
1252 enum lgdt3306a_lock_status syncLockStatus = LG3306_UNLOCK;
1255 for (i = 0; i < 2; i++) {
1258 syncLockStatus = lgdt3306a_check_lock_status(state, LG3306_SYNC_LOCK);
1260 if (syncLockStatus == LG3306_LOCK) {
1261 lg_dbg("locked(%d)\n", i);
1265 lg_dbg("not locked\n");
1266 return LG3306_UNLOCK;
1269 static enum lgdt3306a_lock_status lgdt3306a_fec_lock_poll(struct lgdt3306a_state *state)
1271 enum lgdt3306a_lock_status FECLockStatus = LG3306_UNLOCK;
1274 for (i = 0; i < 2; i++) {
1277 FECLockStatus = lgdt3306a_check_lock_status(state, LG3306_FEC_LOCK);
1279 if (FECLockStatus == LG3306_LOCK) {
1280 lg_dbg("locked(%d)\n", i);
1281 return FECLockStatus;
1284 lg_dbg("not locked\n");
1285 return FECLockStatus;
1288 static enum lgdt3306a_neverlock_status lgdt3306a_neverlock_poll(struct lgdt3306a_state *state)
1290 enum lgdt3306a_neverlock_status NLLockStatus = LG3306_NL_FAIL;
1293 for (i = 0; i < 5; i++) {
1296 NLLockStatus = lgdt3306a_check_neverlock_status(state);
1298 if (NLLockStatus == LG3306_NL_LOCK) {
1299 lg_dbg("NL_LOCK(%d)\n", i);
1300 return NLLockStatus;
1303 lg_dbg("NLLockStatus=%d\n", NLLockStatus);
1304 return NLLockStatus;
1307 static u8 lgdt3306a_get_packet_error(struct lgdt3306a_state *state)
1312 ret = lgdt3306a_read_reg(state, 0x00FA, &val);
1317 static u32 log10_x1000(u32 x)
1319 static u32 valx_x10[] = { 10, 11, 13, 15, 17, 20, 25, 33, 41, 50, 59, 73, 87, 100 };
1320 static u32 log10x_x1000[] = { 0, 41, 114, 176, 230, 301, 398, 518, 613, 699, 771, 863, 939, 1000 };
1321 static u32 nelems = sizeof(valx_x10)/sizeof(valx_x10[0]);
1326 return -1000000; /* signal error */
1333 } else if (x == 10) {
1334 return 0; /* log(1)=0 */
1343 if (x == 10) /* was our input an exact multiple of 10 */
1344 return log_val; /* don't need to interpolate */
1346 /* find our place on the log curve */
1347 for (i = 1; i < nelems; i++) {
1348 if (valx_x10[i] >= x)
1353 u32 diff_val = x - valx_x10[i-1];
1354 u32 step_val = valx_x10[i] - valx_x10[i-1];
1355 u32 step_log10 = log10x_x1000[i] - log10x_x1000[i-1];
1356 /* do a linear interpolation to get in-between values */
1357 return log_val + log10x_x1000[i-1] +
1358 ((diff_val*step_log10) / step_val);
1362 static u32 lgdt3306a_calculate_snr_x100(struct lgdt3306a_state *state)
1364 u32 mse; /* Mean-Square Error */
1365 u32 pwr; /* Constelation power */
1368 mse = (read_reg(state, 0x00EC) << 8) |
1369 (read_reg(state, 0x00ED));
1370 pwr = (read_reg(state, 0x00E8) << 8) |
1371 (read_reg(state, 0x00E9));
1373 if (mse == 0) /* no signal */
1376 snr_x100 = log10_x1000((pwr * 10000) / mse) - 3000;
1377 lg_dbg("mse=%u, pwr=%u, snr_x100=%d\n", mse, pwr, snr_x100);
1382 static enum lgdt3306a_lock_status lgdt3306a_vsb_lock_poll(struct lgdt3306a_state *state)
1389 if (lgdt3306a_sync_lock_poll(state) == LG3306_UNLOCK) {
1390 lg_dbg("no sync lock!\n");
1391 return LG3306_UNLOCK;
1394 lgdt3306a_pre_monitoring(state);
1396 packet_error = lgdt3306a_get_packet_error(state);
1397 snr = lgdt3306a_calculate_snr_x100(state);
1398 lg_dbg("cnt=%d errors=%d snr=%d\n",
1399 cnt, packet_error, snr);
1401 if ((snr < 1500) || (packet_error >= 0xff))
1407 lg_dbg("not locked!\n");
1408 return LG3306_UNLOCK;
1412 return LG3306_UNLOCK;
1415 static enum lgdt3306a_lock_status lgdt3306a_qam_lock_poll(struct lgdt3306a_state *state)
1422 if (lgdt3306a_fec_lock_poll(state) == LG3306_UNLOCK) {
1423 lg_dbg("no fec lock!\n");
1424 return LG3306_UNLOCK;
1428 packet_error = lgdt3306a_get_packet_error(state);
1429 snr = lgdt3306a_calculate_snr_x100(state);
1430 lg_dbg("cnt=%d errors=%d snr=%d\n",
1431 cnt, packet_error, snr);
1433 if ((snr < 1500) || (packet_error >= 0xff))
1439 lg_dbg("not locked!\n");
1440 return LG3306_UNLOCK;
1444 return LG3306_UNLOCK;
1447 static int lgdt3306a_read_status(struct dvb_frontend *fe, fe_status_t *status)
1449 struct lgdt3306a_state *state = fe->demodulator_priv;
1453 if (fe->ops.tuner_ops.get_rf_strength) {
1454 ret = fe->ops.tuner_ops.get_rf_strength(fe, &strength);
1456 lg_dbg("strength=%d\n", strength);
1458 lg_dbg("fe->ops.tuner_ops.get_rf_strength() failed\n");
1463 if (lgdt3306a_neverlock_poll(state) == LG3306_NL_LOCK) {
1464 *status |= FE_HAS_SIGNAL;
1465 *status |= FE_HAS_CARRIER;
1467 switch (state->current_modulation) {
1470 if (lgdt3306a_qam_lock_poll(state) == LG3306_LOCK) {
1471 *status |= FE_HAS_VITERBI;
1472 *status |= FE_HAS_SYNC;
1474 *status |= FE_HAS_LOCK;
1478 if (lgdt3306a_vsb_lock_poll(state) == LG3306_LOCK) {
1479 *status |= FE_HAS_VITERBI;
1480 *status |= FE_HAS_SYNC;
1482 *status |= FE_HAS_LOCK;
1484 lgdt3306a_monitor_vsb(state);
1495 static int lgdt3306a_read_snr(struct dvb_frontend *fe, u16 *snr)
1497 struct lgdt3306a_state *state = fe->demodulator_priv;
1499 state->snr = lgdt3306a_calculate_snr_x100(state);
1500 /* report SNR in dB * 10 */
1501 *snr = state->snr/10;
1506 static int lgdt3306a_read_signal_strength(struct dvb_frontend *fe,
1510 * Calculate some sort of "strength" from SNR
1512 struct lgdt3306a_state *state = fe->demodulator_priv;
1513 u16 snr; /* snr_x10 */
1515 u32 ref_snr; /* snr*100 */
1520 switch (state->current_modulation) {
1522 ref_snr = 1600; /* 16dB */
1525 ref_snr = 2200; /* 22dB */
1528 ref_snr = 2800; /* 28dB */
1534 ret = fe->ops.read_snr(fe, &snr);
1538 if (state->snr <= (ref_snr - 100))
1540 else if (state->snr <= ref_snr)
1541 str = (0xffff * 65) / 100; /* 65% */
1543 str = state->snr - ref_snr;
1545 str += 78; /* 78%-100% */
1548 str = (0xffff * str) / 100;
1550 *strength = (u16)str;
1551 lg_dbg("strength=%u\n", *strength);
1557 /* ------------------------------------------------------------------------ */
1559 static int lgdt3306a_read_ber(struct dvb_frontend *fe, u32 *ber)
1561 struct lgdt3306a_state *state = fe->demodulator_priv;
1566 /* FGR - BUGBUG - I don't know what value is expected by dvb_core
1567 * what is the scale of the value?? */
1568 tmp = read_reg(state, 0x00FC); /* NBERVALUE[24-31] */
1569 tmp = (tmp << 8) | read_reg(state, 0x00FD); /* NBERVALUE[16-23] */
1570 tmp = (tmp << 8) | read_reg(state, 0x00FE); /* NBERVALUE[8-15] */
1571 tmp = (tmp << 8) | read_reg(state, 0x00FF); /* NBERVALUE[0-7] */
1573 lg_dbg("ber=%u\n", tmp);
1578 static int lgdt3306a_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
1580 struct lgdt3306a_state *state = fe->demodulator_priv;
1584 /* FGR - BUGBUG - I don't know what value is expected by dvb_core
1585 * what happens when value wraps? */
1586 *ucblocks = read_reg(state, 0x00F4); /* TPIFTPERRCNT[0-7] */
1587 lg_dbg("ucblocks=%u\n", *ucblocks);
1593 static int lgdt3306a_tune(struct dvb_frontend *fe, bool re_tune, unsigned int mode_flags, unsigned int *delay, fe_status_t *status)
1596 struct lgdt3306a_state *state = fe->demodulator_priv;
1598 lg_dbg("re_tune=%u\n", re_tune);
1601 state->current_frequency = -1; /* force re-tune */
1602 ret = lgdt3306a_set_parameters(fe);
1607 ret = lgdt3306a_read_status(fe, status);
1612 static int lgdt3306a_get_tune_settings(struct dvb_frontend *fe,
1613 struct dvb_frontend_tune_settings
1616 fe_tune_settings->min_delay_ms = 100;
1621 static int lgdt3306a_search(struct dvb_frontend *fe)
1623 fe_status_t status = 0;
1627 ret = lgdt3306a_set_parameters(fe);
1631 /* wait frontend lock */
1632 for (i = 20; i > 0; i--) {
1633 lg_dbg(": loop=%d\n", i);
1635 ret = lgdt3306a_read_status(fe, &status);
1639 if (status & FE_HAS_LOCK)
1643 /* check if we have a valid signal */
1644 if (status & FE_HAS_LOCK)
1645 return DVBFE_ALGO_SEARCH_SUCCESS;
1647 return DVBFE_ALGO_SEARCH_AGAIN;
1650 lg_dbg("failed (%d)\n", ret);
1651 return DVBFE_ALGO_SEARCH_ERROR;
1654 static void lgdt3306a_release(struct dvb_frontend *fe)
1656 struct lgdt3306a_state *state = fe->demodulator_priv;
1662 static struct dvb_frontend_ops lgdt3306a_ops;
1664 struct dvb_frontend *lgdt3306a_attach(const struct lgdt3306a_config *config,
1665 struct i2c_adapter *i2c_adap)
1667 struct lgdt3306a_state *state = NULL;
1671 lg_dbg("(%d-%04x)\n",
1672 i2c_adap ? i2c_adapter_id(i2c_adap) : 0,
1673 config ? config->i2c_addr : 0);
1675 state = kzalloc(sizeof(struct lgdt3306a_state), GFP_KERNEL);
1679 state->cfg = config;
1680 state->i2c_adap = i2c_adap;
1682 memcpy(&state->frontend.ops, &lgdt3306a_ops,
1683 sizeof(struct dvb_frontend_ops));
1684 state->frontend.demodulator_priv = state;
1686 /* verify that we're talking to a lg3306a */
1687 /* FGR - NOTE - there is no obvious ChipId to check; we check
1688 * some "known" bits after reset, but it's still just a guess */
1689 ret = lgdt3306a_read_reg(state, 0x0000, &val);
1692 if ((val & 0x74) != 0x74) {
1693 lg_warn("expected 0x74, got 0x%x\n", (val & 0x74));
1695 goto fail; /* BUGBUG - re-enable when we know this is right */
1698 ret = lgdt3306a_read_reg(state, 0x0001, &val);
1701 if ((val & 0xF6) != 0xC6) {
1702 lg_warn("expected 0xC6, got 0x%x\n", (val & 0xF6));
1704 goto fail; /* BUGBUG - re-enable when we know this is right */
1707 ret = lgdt3306a_read_reg(state, 0x0002, &val);
1710 if ((val & 0x73) != 0x03) {
1711 lg_warn("expected 0x03, got 0x%x\n", (val & 0x73));
1713 goto fail; /* BUGBUG - re-enable when we know this is right */
1717 state->current_frequency = -1;
1718 state->current_modulation = -1;
1720 lgdt3306a_sleep(state);
1722 return &state->frontend;
1725 lg_warn("unable to detect LGDT3306A hardware\n");
1729 EXPORT_SYMBOL(lgdt3306a_attach);
1733 static const short regtab[] = {
1734 0x0000, /* SOFTRSTB 1'b1 1'b1 1'b1 ADCPDB 1'b1 PLLPDB GBBPDB 11111111 */
1735 0x0001, /* 1'b1 1'b1 1'b0 1'b0 AUTORPTRS */
1736 0x0002, /* NI2CRPTEN 1'b0 1'b0 1'b0 SPECINVAUT */
1737 0x0003, /* AGCRFOUT */
1738 0x0004, /* ADCSEL1V ADCCNT ADCCNF ADCCNS ADCCLKPLL */
1739 0x0005, /* PLLINDIVSE */
1740 0x0006, /* PLLCTRL[7:0] 11100001 */
1741 0x0007, /* SYSINITWAITTIME[7:0] (msec) 00001000 */
1742 0x0008, /* STDOPMODE[7:0] 10000000 */
1743 0x0009, /* 1'b0 1'b0 1'b0 STDOPDETTMODE[2:0] STDOPDETCMODE[1:0] 00011110 */
1744 0x000A, /* DAFTEN 1'b1 x x SCSYSLOCK */
1745 0x000B, /* SCSYSLOCKCHKTIME[7:0] (10msec) 01100100 */
1746 0x000D, /* x SAMPLING4 */
1747 0x000E, /* SAMFREQ[15:8] 00000000 */
1748 0x000F, /* SAMFREQ[7:0] 00000000 */
1749 0x0010, /* IFFREQ[15:8] 01100000 */
1750 0x0011, /* IFFREQ[7:0] 00000000 */
1751 0x0012, /* AGCEN AGCREFMO */
1752 0x0013, /* AGCRFFIXB AGCIFFIXB AGCLOCKDETRNGSEL[1:0] 1'b1 1'b0 1'b0 1'b0 11101000 */
1753 0x0014, /* AGCFIXVALUE[7:0] 01111111 */
1754 0x0015, /* AGCREF[15:8] 00001010 */
1755 0x0016, /* AGCREF[7:0] 11100100 */
1756 0x0017, /* AGCDELAY[7:0] 00100000 */
1757 0x0018, /* AGCRFBW[3:0] AGCIFBW[3:0] 10001000 */
1758 0x0019, /* AGCUDOUTMODE[1:0] AGCUDCTRLLEN[1:0] AGCUDCTRL */
1759 0x001C, /* 1'b1 PFEN MFEN AICCVSYNC */
1760 0x001D, /* 1'b0 1'b1 1'b0 1'b1 AICCVSYNC */
1761 0x001E, /* AICCALPHA[3:0] 1'b1 1'b0 1'b1 1'b0 01111010 */
1762 0x001F, /* AICCDETTH[19:16] AICCOFFTH[19:16] 00000000 */
1763 0x0020, /* AICCDETTH[15:8] 01111100 */
1764 0x0021, /* AICCDETTH[7:0] 00000000 */
1765 0x0022, /* AICCOFFTH[15:8] 00000101 */
1766 0x0023, /* AICCOFFTH[7:0] 11100000 */
1767 0x0024, /* AICCOPMODE3[1:0] AICCOPMODE2[1:0] AICCOPMODE1[1:0] AICCOPMODE0[1:0] 00000000 */
1768 0x0025, /* AICCFIXFREQ3[23:16] 00000000 */
1769 0x0026, /* AICCFIXFREQ3[15:8] 00000000 */
1770 0x0027, /* AICCFIXFREQ3[7:0] 00000000 */
1771 0x0028, /* AICCFIXFREQ2[23:16] 00000000 */
1772 0x0029, /* AICCFIXFREQ2[15:8] 00000000 */
1773 0x002A, /* AICCFIXFREQ2[7:0] 00000000 */
1774 0x002B, /* AICCFIXFREQ1[23:16] 00000000 */
1775 0x002C, /* AICCFIXFREQ1[15:8] 00000000 */
1776 0x002D, /* AICCFIXFREQ1[7:0] 00000000 */
1777 0x002E, /* AICCFIXFREQ0[23:16] 00000000 */
1778 0x002F, /* AICCFIXFREQ0[15:8] 00000000 */
1779 0x0030, /* AICCFIXFREQ0[7:0] 00000000 */
1780 0x0031, /* 1'b0 1'b1 1'b0 1'b0 x DAGC1STER */
1781 0x0032, /* DAGC1STEN DAGC1STER */
1782 0x0033, /* DAGC1STREF[15:8] 00001010 */
1783 0x0034, /* DAGC1STREF[7:0] 11100100 */
1784 0x0035, /* DAGC2NDE */
1785 0x0036, /* DAGC2NDREF[15:8] 00001010 */
1786 0x0037, /* DAGC2NDREF[7:0] 10000000 */
1787 0x0038, /* DAGC2NDLOCKDETRNGSEL[1:0] */
1788 0x003D, /* 1'b1 SAMGEARS */
1789 0x0040, /* SAMLFGMA */
1790 0x0041, /* SAMLFBWM */
1791 0x0044, /* 1'b1 CRGEARSHE */
1792 0x0045, /* CRLFGMAN */
1793 0x0046, /* CFLFBWMA */
1794 0x0047, /* CRLFGMAN */
1795 0x0048, /* x x x x CRLFGSTEP_VS[3:0] xxxx1001 */
1796 0x0049, /* CRLFBWMA */
1797 0x004A, /* CRLFBWMA */
1798 0x0050, /* 1'b0 1'b1 1'b1 1'b0 MSECALCDA */
1799 0x0070, /* TPOUTEN TPIFEN TPCLKOUTE */
1800 0x0071, /* TPSENB TPSSOPBITE */
1801 0x0073, /* TP47HINS x x CHBERINT PERMODE[1:0] PERINT[1:0] 1xx11100 */
1802 0x0075, /* x x x x x IQSWAPCTRL[2:0] xxxxx000 */
1803 0x0076, /* NBERCON NBERST NBERPOL NBERWSYN */
1804 0x0077, /* x NBERLOSTTH[2:0] NBERACQTH[3:0] x0000000 */
1805 0x0078, /* NBERPOLY[31:24] 00000000 */
1806 0x0079, /* NBERPOLY[23:16] 00000000 */
1807 0x007A, /* NBERPOLY[15:8] 00000000 */
1808 0x007B, /* NBERPOLY[7:0] 00000000 */
1809 0x007C, /* NBERPED[31:24] 00000000 */
1810 0x007D, /* NBERPED[23:16] 00000000 */
1811 0x007E, /* NBERPED[15:8] 00000000 */
1812 0x007F, /* NBERPED[7:0] 00000000 */
1813 0x0080, /* x AGCLOCK DAGCLOCK SYSLOCK x x NEVERLOCK[1:0] */
1814 0x0085, /* SPECINVST */
1815 0x0088, /* SYSLOCKTIME[15:8] */
1816 0x0089, /* SYSLOCKTIME[7:0] */
1817 0x008C, /* FECLOCKTIME[15:8] */
1818 0x008D, /* FECLOCKTIME[7:0] */
1819 0x008E, /* AGCACCOUT[15:8] */
1820 0x008F, /* AGCACCOUT[7:0] */
1821 0x0090, /* AICCREJSTATUS[3:0] AICCREJBUSY[3:0] */
1822 0x0091, /* AICCVSYNC */
1823 0x009C, /* CARRFREQOFFSET[15:8] */
1824 0x009D, /* CARRFREQOFFSET[7:0] */
1825 0x00A1, /* SAMFREQOFFSET[23:16] */
1826 0x00A2, /* SAMFREQOFFSET[15:8] */
1827 0x00A3, /* SAMFREQOFFSET[7:0] */
1828 0x00A6, /* SYNCLOCK SYNCLOCKH */
1829 #if 0 /* covered elsewhere */
1830 0x00E8, /* CONSTPWR[15:8] */
1831 0x00E9, /* CONSTPWR[7:0] */
1832 0x00EA, /* BMSE[15:8] */
1833 0x00EB, /* BMSE[7:0] */
1834 0x00EC, /* MSE[15:8] */
1835 0x00ED, /* MSE[7:0] */
1836 0x00EE, /* CONSTI[7:0] */
1837 0x00EF, /* CONSTQ[7:0] */
1839 0x00F4, /* TPIFTPERRCNT[7:0] */
1840 0x00F5, /* TPCORREC */
1841 0x00F6, /* VBBER[15:8] */
1842 0x00F7, /* VBBER[7:0] */
1843 0x00F8, /* VABER[15:8] */
1844 0x00F9, /* VABER[7:0] */
1845 0x00FA, /* TPERRCNT[7:0] */
1846 0x00FB, /* NBERLOCK x x x x x x x */
1847 0x00FC, /* NBERVALUE[31:24] */
1848 0x00FD, /* NBERVALUE[23:16] */
1849 0x00FE, /* NBERVALUE[15:8] */
1850 0x00FF, /* NBERVALUE[7:0] */
1851 0x1000, /* 1'b0 WODAGCOU */
1852 0x1005, /* x x 1'b1 1'b1 x SRD_Q_QM */
1853 0x1009, /* SRDWAITTIME[7:0] (10msec) 00100011 */
1854 0x100A, /* SRDWAITTIME_CQS[7:0] (msec) 01100100 */
1855 0x101A, /* x 1'b1 1'b0 1'b0 x QMDQAMMODE[2:0] x100x010 */
1856 0x1036, /* 1'b0 1'b1 1'b0 1'b0 SAMGSEND_CQS[3:0] 01001110 */
1857 0x103C, /* SAMGSAUTOSTL_V[3:0] SAMGSAUTOEDL_V[3:0] 01000110 */
1858 0x103D, /* 1'b1 1'b1 SAMCNORMBP_V[1:0] 1'b0 1'b0 SAMMODESEL_V[1:0] 11100001 */
1859 0x103F, /* SAMZTEDSE */
1860 0x105D, /* EQSTATUSE */
1861 0x105F, /* x PMAPG2_V[2:0] x DMAPG2_V[2:0] x001x011 */
1862 0x1060, /* 1'b1 EQSTATUSE */
1863 0x1061, /* CRMAPBWSTL_V[3:0] CRMAPBWEDL_V[3:0] 00000100 */
1864 0x1065, /* 1'b0 x CRMODE_V[1:0] 1'b1 x 1'b1 x 0x111x1x */
1865 0x1066, /* 1'b0 1'b0 1'b1 1'b0 1'b1 PNBOOSTSE */
1866 0x1068, /* CREPHNGAIN2_V[3:0] CREPHNPBW_V[3:0] 10010001 */
1867 0x106E, /* x x x x x CREPHNEN_ */
1868 0x106F, /* CREPHNTH_V[7:0] 00010101 */
1869 0x1072, /* CRSWEEPN */
1870 0x1073, /* CRPGAIN_V[3:0] x x 1'b1 1'b1 1001xx11 */
1871 0x1074, /* CRPBW_V[3:0] x x 1'b1 1'b1 0001xx11 */
1872 0x1080, /* DAFTSTATUS[1:0] x x x x x x */
1873 0x1081, /* SRDSTATUS[1:0] x x x x x SRDLOCK */
1874 0x10A9, /* EQSTATUS_CQS[1:0] x x x x x x */
1875 0x10B7, /* EQSTATUS_V[1:0] x x x x x x */
1876 #if 0 /* SMART_ANT */
1877 0x1F00, /* MODEDETE */
1878 0x1F01, /* x x x x x x x SFNRST xxxxxxx0 */
1879 0x1F03, /* NUMOFANT[7:0] 10000000 */
1880 0x1F04, /* x SELMASK[6:0] x0000000 */
1881 0x1F05, /* x SETMASK[6:0] x0000000 */
1882 0x1F06, /* x TXDATA[6:0] x0000000 */
1883 0x1F07, /* x CHNUMBER[6:0] x0000000 */
1884 0x1F09, /* AGCTIME[23:16] 10011000 */
1885 0x1F0A, /* AGCTIME[15:8] 10010110 */
1886 0x1F0B, /* AGCTIME[7:0] 10000000 */
1887 0x1F0C, /* ANTTIME[31:24] 00000000 */
1888 0x1F0D, /* ANTTIME[23:16] 00000011 */
1889 0x1F0E, /* ANTTIME[15:8] 10010000 */
1890 0x1F0F, /* ANTTIME[7:0] 10010000 */
1891 0x1F11, /* SYNCTIME[23:16] 10011000 */
1892 0x1F12, /* SYNCTIME[15:8] 10010110 */
1893 0x1F13, /* SYNCTIME[7:0] 10000000 */
1894 0x1F14, /* SNRTIME[31:24] 00000001 */
1895 0x1F15, /* SNRTIME[23:16] 01111101 */
1896 0x1F16, /* SNRTIME[15:8] 01111000 */
1897 0x1F17, /* SNRTIME[7:0] 01000000 */
1898 0x1F19, /* FECTIME[23:16] 00000000 */
1899 0x1F1A, /* FECTIME[15:8] 01110010 */
1900 0x1F1B, /* FECTIME[7:0] 01110000 */
1901 0x1F1D, /* FECTHD[7:0] 00000011 */
1902 0x1F1F, /* SNRTHD[23:16] 00001000 */
1903 0x1F20, /* SNRTHD[15:8] 01111111 */
1904 0x1F21, /* SNRTHD[7:0] 10000101 */
1905 0x1F80, /* IRQFLG x x SFSDRFLG MODEBFLG SAVEFLG SCANFLG TRACKFLG */
1906 0x1F81, /* x SYNCCON SNRCON FECCON x STDBUSY SYNCRST AGCFZCO */
1907 0x1F82, /* x x x SCANOPCD[4:0] */
1908 0x1F83, /* x x x x MAINOPCD[3:0] */
1909 0x1F84, /* x x RXDATA[13:8] */
1910 0x1F85, /* RXDATA[7:0] */
1911 0x1F86, /* x x SDTDATA[13:8] */
1912 0x1F87, /* SDTDATA[7:0] */
1913 0x1F89, /* ANTSNR[23:16] */
1914 0x1F8A, /* ANTSNR[15:8] */
1915 0x1F8B, /* ANTSNR[7:0] */
1916 0x1F8C, /* x x x x ANTFEC[13:8] */
1917 0x1F8D, /* ANTFEC[7:0] */
1918 0x1F8E, /* MAXCNT[7:0] */
1919 0x1F8F, /* SCANCNT[7:0] */
1920 0x1F91, /* MAXPW[23:16] */
1921 0x1F92, /* MAXPW[15:8] */
1922 0x1F93, /* MAXPW[7:0] */
1923 0x1F95, /* CURPWMSE[23:16] */
1924 0x1F96, /* CURPWMSE[15:8] */
1925 0x1F97, /* CURPWMSE[7:0] */
1926 #endif /* SMART_ANT */
1927 0x211F, /* 1'b1 1'b1 1'b1 CIRQEN x x 1'b0 1'b0 1111xx00 */
1928 0x212A, /* EQAUTOST */
1929 0x2122, /* CHFAST[7:0] 01100000 */
1930 0x212B, /* FFFSTEP_V[3:0] x FBFSTEP_V[2:0] 0001x001 */
1931 0x212C, /* PHDEROTBWSEL[3:0] 1'b1 1'b1 1'b1 1'b0 10001110 */
1932 0x212D, /* 1'b1 1'b1 1'b1 1'b1 x x TPIFLOCKS */
1933 0x2135, /* DYNTRACKFDEQ[3:0] x 1'b0 1'b0 1'b0 1010x000 */
1934 0x2141, /* TRMODE[1:0] 1'b1 1'b1 1'b0 1'b1 1'b1 1'b1 01110111 */
1935 0x2162, /* AICCCTRLE */
1936 0x2173, /* PHNCNFCNT[7:0] 00000100 */
1937 0x2179, /* 1'b0 1'b0 1'b0 1'b1 x BADSINGLEDYNTRACKFBF[2:0] 0001x001 */
1938 0x217A, /* 1'b0 1'b0 1'b0 1'b1 x BADSLOWSINGLEDYNTRACKFBF[2:0] 0001x001 */
1939 0x217E, /* CNFCNTTPIF[7:0] 00001000 */
1940 0x217F, /* TPERRCNTTPIF[7:0] 00000001 */
1941 0x2180, /* x x x x x x FBDLYCIR[9:8] */
1942 0x2181, /* FBDLYCIR[7:0] */
1943 0x2185, /* MAXPWRMAIN[7:0] */
1944 0x2191, /* NCOMBDET x x x x x x x */
1945 0x2199, /* x MAINSTRON */
1946 0x219A, /* FFFEQSTEPOUT_V[3:0] FBFSTEPOUT_V[2:0] */
1947 0x21A1, /* x x SNRREF[5:0] */
1948 0x2845, /* 1'b0 1'b1 x x FFFSTEP_CQS[1:0] FFFCENTERTAP[1:0] 01xx1110 */
1949 0x2846, /* 1'b0 x 1'b0 1'b1 FBFSTEP_CQS[1:0] 1'b1 1'b0 0x011110 */
1950 0x2847, /* ENNOSIGDE */
1951 0x2849, /* 1'b1 1'b1 NOUSENOSI */
1952 0x284A, /* EQINITWAITTIME[7:0] 01100100 */
1953 0x3000, /* 1'b1 1'b1 1'b1 x x x 1'b0 RPTRSTM */
1954 0x3001, /* RPTRSTWAITTIME[7:0] (100msec) 00110010 */
1955 0x3031, /* FRAMELOC */
1956 0x3032, /* 1'b1 1'b0 1'b0 1'b0 x x FRAMELOCKMODE_CQS[1:0] 1000xx11 */
1957 0x30A9, /* VDLOCK_Q FRAMELOCK */
1958 0x30AA, /* MPEGLOCK */
1961 #define numDumpRegs (sizeof(regtab)/sizeof(regtab[0]))
1962 static u8 regval1[numDumpRegs] = {0, };
1963 static u8 regval2[numDumpRegs] = {0, };
1965 static void lgdt3306a_DumpAllRegs(struct lgdt3306a_state *state)
1967 memset(regval2, 0xff, sizeof(regval2));
1968 lgdt3306a_DumpRegs(state);
1971 static void lgdt3306a_DumpRegs(struct lgdt3306a_state *state)
1974 int sav_debug = debug;
1976 if ((debug & DBG_DUMP) == 0)
1978 debug &= ~DBG_REG; /* supress DBG_REG during reg dump */
1982 for (i = 0; i < numDumpRegs; i++) {
1983 lgdt3306a_read_reg(state, regtab[i], ®val1[i]);
1984 if (regval1[i] != regval2[i]) {
1985 lg_info(" %04X = %02X\n", regtab[i], regval1[i]);
1986 regval2[i] = regval1[i];
1991 #endif /* DBG_DUMP */
1995 static struct dvb_frontend_ops lgdt3306a_ops = {
1996 .delsys = { SYS_ATSC, SYS_DVBC_ANNEX_B },
1998 .name = "LG Electronics LGDT3306A VSB/QAM Frontend",
2002 .frequency_min = 54000000,
2003 .frequency_max = 858000000,
2004 .frequency_stepsize = 62500,
2005 .caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB
2007 .i2c_gate_ctrl = lgdt3306a_i2c_gate_ctrl,
2008 .init = lgdt3306a_init,
2009 .sleep = lgdt3306a_fe_sleep,
2010 /* if this is set, it overrides the default swzigzag */
2011 .tune = lgdt3306a_tune,
2012 .set_frontend = lgdt3306a_set_parameters,
2013 .get_frontend = lgdt3306a_get_frontend,
2014 .get_frontend_algo = lgdt3306a_get_frontend_algo,
2015 .get_tune_settings = lgdt3306a_get_tune_settings,
2016 .read_status = lgdt3306a_read_status,
2017 .read_ber = lgdt3306a_read_ber,
2018 .read_signal_strength = lgdt3306a_read_signal_strength,
2019 .read_snr = lgdt3306a_read_snr,
2020 .read_ucblocks = lgdt3306a_read_ucblocks,
2021 .release = lgdt3306a_release,
2022 .ts_bus_ctrl = lgdt3306a_ts_bus_ctrl,
2023 .search = lgdt3306a_search,
2026 MODULE_DESCRIPTION("LG Electronics LGDT3306A ATSC/QAM-B Demodulator Driver");
2027 MODULE_AUTHOR("Fred Richter <frichter@hauppauge.com>");
2028 MODULE_LICENSE("GPL");
2029 MODULE_VERSION("0.2");