drivers/media/dvb-frontends/lgdt3306a.c

   1 /*
   2  *    Support for LGDT3306A - 8VSB/QAM-B
   3  *
   4  *    Copyright (C) 2013 Fred Richter <frichter@hauppauge.com>
   5  *    - driver structure based on lgdt3305.[ch] by Michael Krufky
   6  *    - code based on LG3306_V0.35 API by LG Electronics Inc.
   7  *
   8  *    This program is free software; you can redistribute it and/or modify
   9  *    it under the terms of the GNU General Public License as published by
  10  *    the Free Software Foundation; either version 2 of the License, or
  11  *    (at your option) any later version.
  12  *
  13  *    This program is distributed in the hope that it will be useful,
  14  *    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  *    GNU General Public License for more details.
  17  */
  18
  19 #include <asm/div64.h>
  20 #include <linux/dvb/frontend.h>
  21 #include "dvb_math.h"
  22 #include "lgdt3306a.h"
  23
  24
  25 static int debug;
  26 module_param(debug, int, 0644);
  27 MODULE_PARM_DESC(debug, "set debug level (info=1, reg=2 (or-able))");
  28
  29 #define DBG_INFO 1
  30 #define DBG_REG  2
  31 #define DBG_DUMP 4 /* FGR - comment out to remove dump code */
  32
  33 #define lg_printk(kern, fmt, arg...)                                    \
  34         printk(kern "%s(): " fmt, __func__, ##arg)
  35
  36 #define lg_info(fmt, arg...)    printk(KERN_INFO "lgdt3306a: " fmt, ##arg)
  37 #define lg_warn(fmt, arg...)    lg_printk(KERN_WARNING,       fmt, ##arg)
  38 #define lg_err(fmt, arg...)     lg_printk(KERN_ERR,           fmt, ##arg)
  39 #define lg_dbg(fmt, arg...) if (debug & DBG_INFO)                       \
  40                                 lg_printk(KERN_DEBUG,         fmt, ##arg)
  41 #define lg_reg(fmt, arg...) if (debug & DBG_REG)                        \
  42                                 lg_printk(KERN_DEBUG,         fmt, ##arg)
  43
  44 #define lg_chkerr(ret)                                                  \
  45 ({                                                                      \
  46         int __ret;                                                      \
  47         __ret = (ret < 0);                                              \
  48         if (__ret)                                                      \
  49                 lg_err("error %d on line %d\n", ret, __LINE__);         \
  50         __ret;                                                          \
  51 })
  52
  53 struct lgdt3306a_state {
  54         struct i2c_adapter *i2c_adap;
  55         const struct lgdt3306a_config *cfg;
  56
  57         struct dvb_frontend frontend;
  58
  59         fe_modulation_t current_modulation;
  60         u32 current_frequency;
  61         u32 snr;
  62 };
  63
  64 /* -----------------------------------------------
  65  LG3306A Register Usage
  66    (LG does not really name the registers, so this code does not either)
  67  0000 -> 00FF Common control and status
  68  1000 -> 10FF Synchronizer control and status
  69  1F00 -> 1FFF Smart Antenna control and status
  70  2100 -> 21FF VSB Equalizer control and status
  71  2800 -> 28FF QAM Equalizer control and status
  72  3000 -> 30FF FEC control and status
  73  ---------------------------------------------- */
  74
  75 enum lgdt3306a_lock_status {
  76         LG3306_UNLOCK       = 0x00,
  77         LG3306_LOCK         = 0x01,
  78         LG3306_UNKNOWN_LOCK = 0xff
  79 };
  80
  81 enum lgdt3306a_neverlock_status {
  82         LG3306_NL_INIT    = 0x00,
  83         LG3306_NL_PROCESS = 0x01,
  84         LG3306_NL_LOCK    = 0x02,
  85         LG3306_NL_FAIL    = 0x03,
  86         LG3306_NL_UNKNOWN = 0xff
  87 };
  88
  89 enum lgdt3306a_modulation {
  90         LG3306_VSB          = 0x00,
  91         LG3306_QAM64        = 0x01,
  92         LG3306_QAM256       = 0x02,
  93         LG3306_UNKNOWN_MODE = 0xff
  94 };
  95
  96 enum lgdt3306a_lock_check {
  97         LG3306_SYNC_LOCK,
  98         LG3306_FEC_LOCK,
  99         LG3306_TR_LOCK,
 100         LG3306_AGC_LOCK,
 101 };
 102
 103
 104 #ifdef DBG_DUMP
 105 static void lgdt3306a_DumpAllRegs(struct lgdt3306a_state *state);
 106 static void lgdt3306a_DumpRegs(struct lgdt3306a_state *state);
 107 #endif
 108
 109
 110 static int lgdt3306a_write_reg(struct lgdt3306a_state *state, u16 reg, u8 val)
 111 {
 112         int ret;
 113         u8 buf[] = { reg >> 8, reg & 0xff, val };
 114         struct i2c_msg msg = {
 115                 .addr = state->cfg->i2c_addr, .flags = 0,
 116                 .buf = buf, .len = 3,
 117         };
 118
 119         lg_reg("reg: 0x%04x, val: 0x%02x\n", reg, val);
 120
 121         ret = i2c_transfer(state->i2c_adap, &msg, 1);
 122
 123         if (ret != 1) {
 124                 lg_err("error (addr %02x %02x <- %02x, err = %i)\n",
 125                        msg.buf[0], msg.buf[1], msg.buf[2], ret);
 126                 if (ret < 0)
 127                         return ret;
 128                 else
 129                         return -EREMOTEIO;
 130         }
 131         return 0;
 132 }
 133
 134 static int lgdt3306a_read_reg(struct lgdt3306a_state *state, u16 reg, u8 *val)
 135 {
 136         int ret;
 137         u8 reg_buf[] = { reg >> 8, reg & 0xff };
 138         struct i2c_msg msg[] = {
 139                 { .addr = state->cfg->i2c_addr,
 140                   .flags = 0, .buf = reg_buf, .len = 2 },
 141                 { .addr = state->cfg->i2c_addr,
 142                   .flags = I2C_M_RD, .buf = val, .len = 1 },
 143         };
 144
 145         ret = i2c_transfer(state->i2c_adap, msg, 2);
 146
 147         if (ret != 2) {
 148                 lg_err("error (addr %02x reg %04x error (ret == %i)\n",
 149                        state->cfg->i2c_addr, reg, ret);
 150                 if (ret < 0)
 151                         return ret;
 152                 else
 153                         return -EREMOTEIO;
 154         }
 155         lg_reg("reg: 0x%04x, val: 0x%02x\n", reg, *val);
 156
 157         return 0;
 158 }
 159
 160 #define read_reg(state, reg)                                            \
 161 ({                                                                      \
 162         u8 __val;                                                       \
 163         int ret = lgdt3306a_read_reg(state, reg, &__val);               \
 164         if (lg_chkerr(ret))                                             \
 165                 __val = 0;                                              \
 166         __val;                                                          \
 167 })
 168
 169 static int lgdt3306a_set_reg_bit(struct lgdt3306a_state *state,
 170                                 u16 reg, int bit, int onoff)
 171 {
 172         u8 val;
 173         int ret;
 174
 175         lg_reg("reg: 0x%04x, bit: %d, level: %d\n", reg, bit, onoff);
 176
 177         ret = lgdt3306a_read_reg(state, reg, &val);
 178         if (lg_chkerr(ret))
 179                 goto fail;
 180
 181         val &= ~(1 << bit);
 182         val |= (onoff & 1) << bit;
 183
 184         ret = lgdt3306a_write_reg(state, reg, val);
 185         lg_chkerr(ret);
 186 fail:
 187         return ret;
 188 }
 189
 190 /* ------------------------------------------------------------------------ */
 191
 192 static int lgdt3306a_soft_reset(struct lgdt3306a_state *state)
 193 {
 194         int ret;
 195
 196         lg_dbg("\n");
 197
 198         ret = lgdt3306a_set_reg_bit(state, 0x0000, 7, 0);
 199         if (lg_chkerr(ret))
 200                 goto fail;
 201
 202         msleep(20);
 203         ret = lgdt3306a_set_reg_bit(state, 0x0000, 7, 1);
 204         lg_chkerr(ret);
 205
 206 fail:
 207         return ret;
 208 }
 209
 210 static int lgdt3306a_mpeg_mode(struct lgdt3306a_state *state,
 211                                      enum lgdt3306a_mpeg_mode mode)
 212 {
 213         u8 val;
 214         int ret;
 215
 216         lg_dbg("(%d)\n", mode);
 217         /* transport packet format */
 218         ret = lgdt3306a_set_reg_bit(state, 0x0071, 7, mode == LGDT3306A_MPEG_PARALLEL?1:0); /* TPSENB=0x80 */
 219         if (lg_chkerr(ret))
 220                 goto fail;
 221
 222         /* start of packet signal duration */
 223         ret = lgdt3306a_set_reg_bit(state, 0x0071, 6, 0); /* TPSSOPBITEN=0x40; 0=byte duration, 1=bit duration */
 224         if (lg_chkerr(ret))
 225                 goto fail;
 226
 227         ret = lgdt3306a_read_reg(state, 0x0070, &val);
 228         if (lg_chkerr(ret))
 229                 goto fail;
 230
 231         val |= 0x10; /* TPCLKSUPB=0x10 */
 232
 233         if (mode == LGDT3306A_MPEG_PARALLEL)
 234                 val &= ~0x10;
 235
 236         ret = lgdt3306a_write_reg(state, 0x0070, val);
 237         lg_chkerr(ret);
 238
 239 fail:
 240         return ret;
 241 }
 242
 243 static int lgdt3306a_mpeg_mode_polarity(struct lgdt3306a_state *state,
 244                                        enum lgdt3306a_tp_clock_edge edge,
 245                                        enum lgdt3306a_tp_valid_polarity valid)
 246 {
 247         u8 val;
 248         int ret;
 249
 250         lg_dbg("edge=%d, valid=%d\n", edge, valid);
 251
 252         ret = lgdt3306a_read_reg(state, 0x0070, &val);
 253         if (lg_chkerr(ret))
 254                 goto fail;
 255
 256         val &= ~0x06; /* TPCLKPOL=0x04, TPVALPOL=0x02 */
 257
 258         if (edge == LGDT3306A_TPCLK_RISING_EDGE)
 259                 val |= 0x04;
 260         if (valid == LGDT3306A_TP_VALID_HIGH)
 261                 val |= 0x02;
 262
 263         ret = lgdt3306a_write_reg(state, 0x0070, val);
 264         lg_chkerr(ret);
 265
 266 fail:
 267         return ret;
 268 }
 269
 270 static int lgdt3306a_mpeg_tristate(struct lgdt3306a_state *state,
 271                                      int mode)
 272 {
 273         u8 val;
 274         int ret;
 275
 276         lg_dbg("(%d)\n", mode);
 277
 278         if (mode) {
 279                 ret = lgdt3306a_read_reg(state, 0x0070, &val);
 280                 if (lg_chkerr(ret))
 281                         goto fail;
 282                 val &= ~0xa8; /* Tristate bus; TPOUTEN=0x80, TPCLKOUTEN=0x20, TPDATAOUTEN=0x08 */
 283                 ret = lgdt3306a_write_reg(state, 0x0070, val);
 284                 if (lg_chkerr(ret))
 285                         goto fail;
 286
 287                 ret = lgdt3306a_set_reg_bit(state, 0x0003, 6, 1); /* AGCIFOUTENB=0x40; 1=Disable IFAGC pin */
 288                 if (lg_chkerr(ret))
 289                         goto fail;
 290
 291         } else {
 292                 ret = lgdt3306a_set_reg_bit(state, 0x0003, 6, 0); /* enable IFAGC pin */
 293                 if (lg_chkerr(ret))
 294                         goto fail;
 295
 296                 ret = lgdt3306a_read_reg(state, 0x0070, &val);
 297                 if (lg_chkerr(ret))
 298                         goto fail;
 299
 300                 val |= 0xa8; /* enable bus */
 301                 ret = lgdt3306a_write_reg(state, 0x0070, val);
 302                 if (lg_chkerr(ret))
 303                         goto fail;
 304         }
 305
 306 fail:
 307         return ret;
 308 }
 309
 310 static int lgdt3306a_ts_bus_ctrl(struct dvb_frontend *fe, int acquire)
 311 {
 312         struct lgdt3306a_state *state = fe->demodulator_priv;
 313
 314         lg_dbg("acquire=%d\n", acquire);
 315
 316         return lgdt3306a_mpeg_tristate(state, acquire ? 0 : 1);
 317
 318 }
 319
 320 static int lgdt3306a_power(struct lgdt3306a_state *state,
 321                                      int mode)
 322 {
 323         int ret;
 324
 325         lg_dbg("(%d)\n", mode);
 326
 327         if (mode == 0) {
 328                 ret = lgdt3306a_set_reg_bit(state, 0x0000, 7, 0); /* into reset */
 329                 if (lg_chkerr(ret))
 330                         goto fail;
 331
 332                 ret = lgdt3306a_set_reg_bit(state, 0x0000, 0, 0); /* power down */
 333                 if (lg_chkerr(ret))
 334                         goto fail;
 335
 336         } else {
 337                 ret = lgdt3306a_set_reg_bit(state, 0x0000, 7, 1); /* out of reset */
 338                 if (lg_chkerr(ret))
 339                         goto fail;
 340
 341                 ret = lgdt3306a_set_reg_bit(state, 0x0000, 0, 1); /* power up */
 342                 if (lg_chkerr(ret))
 343                         goto fail;
 344         }
 345
 346 #ifdef DBG_DUMP
 347         lgdt3306a_DumpAllRegs(state);
 348 #endif
 349 fail:
 350         return ret;
 351 }
 352
 353
 354 static int lgdt3306a_set_vsb(struct lgdt3306a_state *state)
 355 {
 356         u8 val;
 357         int ret;
 358
 359         lg_dbg("\n");
 360
 361         /* 0. Spectrum inversion detection manual; spectrum inverted */
 362         ret = lgdt3306a_read_reg(state, 0x0002, &val);
 363         val &= 0xf7; /* SPECINVAUTO Off */
 364         val |= 0x04; /* SPECINV On */
 365         ret = lgdt3306a_write_reg(state, 0x0002, val);
 366         if (lg_chkerr(ret))
 367                 goto fail;
 368
 369         /* 1. Selection of standard mode(0x08=QAM, 0x80=VSB) */
 370         ret = lgdt3306a_write_reg(state, 0x0008, 0x80);
 371         if (lg_chkerr(ret))
 372                 goto fail;
 373
 374         /* 2. Bandwidth mode for VSB(6MHz) */
 375         ret = lgdt3306a_read_reg(state, 0x0009, &val);
 376         val &= 0xe3;
 377         val |= 0x0c; /* STDOPDETTMODE[2:0]=3 */
 378         ret = lgdt3306a_write_reg(state, 0x0009, val);
 379         if (lg_chkerr(ret))
 380                 goto fail;
 381
 382         /* 3. QAM mode detection mode(None) */
 383         ret = lgdt3306a_read_reg(state, 0x0009, &val);
 384         val &= 0xfc; /* STDOPDETCMODE[1:0]=0 */
 385         ret = lgdt3306a_write_reg(state, 0x0009, val);
 386         if (lg_chkerr(ret))
 387                 goto fail;
 388
 389         /* 4. ADC sampling frequency rate(2x sampling) */
 390         ret = lgdt3306a_read_reg(state, 0x000d, &val);
 391         val &= 0xbf; /* SAMPLING4XFEN=0 */
 392         ret = lgdt3306a_write_reg(state, 0x000d, val);
 393         if (lg_chkerr(ret))
 394                 goto fail;
 395
 396 #if 0
 397         /* FGR - disable any AICC filtering, testing only */
 398
 399         ret = lgdt3306a_write_reg(state, 0x0024, 0x00);
 400         if (lg_chkerr(ret))
 401                 goto fail;
 402
 403         /* AICCFIXFREQ0 NT N-1(Video rejection) */
 404         ret = lgdt3306a_write_reg(state, 0x002e, 0x00);
 405         ret = lgdt3306a_write_reg(state, 0x002f, 0x00);
 406         ret = lgdt3306a_write_reg(state, 0x0030, 0x00);
 407
 408         /* AICCFIXFREQ1 NT N-1(Audio rejection) */
 409         ret = lgdt3306a_write_reg(state, 0x002b, 0x00);
 410         ret = lgdt3306a_write_reg(state, 0x002c, 0x00);
 411         ret = lgdt3306a_write_reg(state, 0x002d, 0x00);
 412
 413         /* AICCFIXFREQ2 NT Co-Channel(Video rejection) */
 414         ret = lgdt3306a_write_reg(state, 0x0028, 0x00);
 415         ret = lgdt3306a_write_reg(state, 0x0029, 0x00);
 416         ret = lgdt3306a_write_reg(state, 0x002a, 0x00);
 417
 418         /* AICCFIXFREQ3 NT Co-Channel(Audio rejection) */
 419         ret = lgdt3306a_write_reg(state, 0x0025, 0x00);
 420         ret = lgdt3306a_write_reg(state, 0x0026, 0x00);
 421         ret = lgdt3306a_write_reg(state, 0x0027, 0x00);
 422
 423 #else
 424         /* FGR - this works well for HVR-1955,1975 */
 425
 426         /* 5. AICCOPMODE  NT N-1 Adj. */
 427         ret = lgdt3306a_write_reg(state, 0x0024, 0x5A);
 428         if (lg_chkerr(ret))
 429                 goto fail;
 430
 431         /* AICCFIXFREQ0 NT N-1(Video rejection) */
 432         ret = lgdt3306a_write_reg(state, 0x002e, 0x5A);
 433         ret = lgdt3306a_write_reg(state, 0x002f, 0x00);
 434         ret = lgdt3306a_write_reg(state, 0x0030, 0x00);
 435
 436         /* AICCFIXFREQ1 NT N-1(Audio rejection) */
 437         ret = lgdt3306a_write_reg(state, 0x002b, 0x36);
 438         ret = lgdt3306a_write_reg(state, 0x002c, 0x00);
 439         ret = lgdt3306a_write_reg(state, 0x002d, 0x00);
 440
 441         /* AICCFIXFREQ2 NT Co-Channel(Video rejection) */
 442         ret = lgdt3306a_write_reg(state, 0x0028, 0x2A);
 443         ret = lgdt3306a_write_reg(state, 0x0029, 0x00);
 444         ret = lgdt3306a_write_reg(state, 0x002a, 0x00);
 445
 446         /* AICCFIXFREQ3 NT Co-Channel(Audio rejection) */
 447         ret = lgdt3306a_write_reg(state, 0x0025, 0x06);
 448         ret = lgdt3306a_write_reg(state, 0x0026, 0x00);
 449         ret = lgdt3306a_write_reg(state, 0x0027, 0x00);
 450 #endif
 451
 452         ret = lgdt3306a_read_reg(state, 0x001e, &val);
 453         val &= 0x0f;
 454         val |= 0xa0;
 455         ret = lgdt3306a_write_reg(state, 0x001e, val);
 456
 457         ret = lgdt3306a_write_reg(state, 0x0022, 0x08);
 458
 459         ret = lgdt3306a_write_reg(state, 0x0023, 0xFF);
 460
 461         ret = lgdt3306a_read_reg(state, 0x211f, &val);
 462         val &= 0xef;
 463         ret = lgdt3306a_write_reg(state, 0x211f, val);
 464
 465         ret = lgdt3306a_write_reg(state, 0x2173, 0x01);
 466
 467         ret = lgdt3306a_read_reg(state, 0x1061, &val);
 468         val &= 0xf8;
 469         val |= 0x04;
 470         ret = lgdt3306a_write_reg(state, 0x1061, val);
 471
 472         ret = lgdt3306a_read_reg(state, 0x103d, &val);
 473         val &= 0xcf;
 474         ret = lgdt3306a_write_reg(state, 0x103d, val);
 475
 476         ret = lgdt3306a_write_reg(state, 0x2122, 0x40);
 477
 478         ret = lgdt3306a_read_reg(state, 0x2141, &val);
 479         val &= 0x3f;
 480         ret = lgdt3306a_write_reg(state, 0x2141, val);
 481
 482         ret = lgdt3306a_read_reg(state, 0x2135, &val);
 483         val &= 0x0f;
 484         val |= 0x70;
 485         ret = lgdt3306a_write_reg(state, 0x2135, val);
 486
 487         ret = lgdt3306a_read_reg(state, 0x0003, &val);
 488         val &= 0xf7;
 489         ret = lgdt3306a_write_reg(state, 0x0003, val);
 490
 491         ret = lgdt3306a_read_reg(state, 0x001c, &val);
 492         val &= 0x7f;
 493         ret = lgdt3306a_write_reg(state, 0x001c, val);
 494
 495         /* 6. EQ step size */
 496         ret = lgdt3306a_read_reg(state, 0x2179, &val);
 497         val &= 0xf8;
 498         ret = lgdt3306a_write_reg(state, 0x2179, val);
 499
 500         ret = lgdt3306a_read_reg(state, 0x217a, &val);
 501         val &= 0xf8;
 502         ret = lgdt3306a_write_reg(state, 0x217a, val);
 503
 504         /* 7. Reset */
 505         ret = lgdt3306a_soft_reset(state);
 506         if (lg_chkerr(ret))
 507                 goto fail;
 508
 509         lg_dbg("complete\n");
 510 fail:
 511         return ret;
 512 }
 513
 514 static int lgdt3306a_set_qam(struct lgdt3306a_state *state, int modulation)
 515 {
 516         u8 val;
 517         int ret;
 518
 519         lg_dbg("modulation=%d\n", modulation);
 520
 521         /* 1. Selection of standard mode(0x08=QAM, 0x80=VSB) */
 522         ret = lgdt3306a_write_reg(state, 0x0008, 0x08);
 523         if (lg_chkerr(ret))
 524                 goto fail;
 525
 526         /* 1a. Spectrum inversion detection to Auto */
 527         ret = lgdt3306a_read_reg(state, 0x0002, &val);
 528         val &= 0xfb; /* SPECINV Off */
 529         val |= 0x08; /* SPECINVAUTO On */
 530         ret = lgdt3306a_write_reg(state, 0x0002, val);
 531         if (lg_chkerr(ret))
 532                 goto fail;
 533
 534         /* 2. Bandwidth mode for QAM */
 535         ret = lgdt3306a_read_reg(state, 0x0009, &val);
 536         val &= 0xe3; /* STDOPDETTMODE[2:0]=0 VSB Off */
 537         ret = lgdt3306a_write_reg(state, 0x0009, val);
 538         if (lg_chkerr(ret))
 539                 goto fail;
 540
 541         /* 3. : 64QAM/256QAM detection(manual, auto) */
 542         ret = lgdt3306a_read_reg(state, 0x0009, &val);
 543         val &= 0xfc;
 544         val |= 0x02; /* STDOPDETCMODE[1:0]=1=Manual 2=Auto */
 545         ret = lgdt3306a_write_reg(state, 0x0009, val);
 546         if (lg_chkerr(ret))
 547                 goto fail;
 548
 549         /* 3a. : 64QAM/256QAM selection for manual */
 550         ret = lgdt3306a_read_reg(state, 0x101a, &val);
 551         val &= 0xf8;
 552         if (modulation == QAM_64)
 553                 val |= 0x02; /* QMDQMODE[2:0]=2=QAM64 */
 554         else
 555                 val |= 0x04; /* QMDQMODE[2:0]=4=QAM256 */
 556
 557         ret = lgdt3306a_write_reg(state, 0x101a, val);
 558         if (lg_chkerr(ret))
 559                 goto fail;
 560
 561         /* 4. ADC sampling frequency rate(4x sampling) */
 562         ret = lgdt3306a_read_reg(state, 0x000d, &val);
 563         val &= 0xbf;
 564         val |= 0x40; /* SAMPLING4XFEN=1 */
 565         ret = lgdt3306a_write_reg(state, 0x000d, val);
 566         if (lg_chkerr(ret))
 567                 goto fail;
 568
 569         /* 5. No AICC operation in QAM mode */
 570         ret = lgdt3306a_read_reg(state, 0x0024, &val);
 571         val &= 0x00;
 572         ret = lgdt3306a_write_reg(state, 0x0024, val);
 573         if (lg_chkerr(ret))
 574                 goto fail;
 575
 576         /* 6. Reset */
 577         ret = lgdt3306a_soft_reset(state);
 578         if (lg_chkerr(ret))
 579                 goto fail;
 580
 581         lg_dbg("complete\n");
 582 fail:
 583         return ret;
 584 }
 585
 586 static int lgdt3306a_set_modulation(struct lgdt3306a_state *state,
 587                                    struct dtv_frontend_properties *p)
 588 {
 589         int ret;
 590
 591         lg_dbg("\n");
 592
 593         switch (p->modulation) {
 594         case VSB_8:
 595                 ret = lgdt3306a_set_vsb(state);
 596                 break;
 597         case QAM_64:
 598                 ret = lgdt3306a_set_qam(state, QAM_64);
 599                 break;
 600         case QAM_256:
 601                 ret = lgdt3306a_set_qam(state, QAM_256);
 602                 break;
 603         default:
 604                 return -EINVAL;
 605         }
 606         if (lg_chkerr(ret))
 607                 goto fail;
 608
 609         state->current_modulation = p->modulation;
 610
 611 fail:
 612         return ret;
 613 }
 614
 615 /* ------------------------------------------------------------------------ */
 616
 617 static int lgdt3306a_agc_setup(struct lgdt3306a_state *state,
 618                               struct dtv_frontend_properties *p)
 619 {
 620         /* TODO: anything we want to do here??? */
 621         lg_dbg("\n");
 622
 623         switch (p->modulation) {
 624         case VSB_8:
 625                 break;
 626         case QAM_64:
 627         case QAM_256:
 628                 break;
 629         default:
 630                 return -EINVAL;
 631         }
 632         return 0;
 633 }
 634
 635 /* ------------------------------------------------------------------------ */
 636
 637 static int lgdt3306a_set_inversion(struct lgdt3306a_state *state,
 638                                        int inversion)
 639 {
 640         int ret;
 641
 642         lg_dbg("(%d)\n", inversion);
 643
 644         ret = lgdt3306a_set_reg_bit(state, 0x0002, 2, inversion ? 1 : 0);
 645         return ret;
 646 }
 647
 648 static int lgdt3306a_set_inversion_auto(struct lgdt3306a_state *state,
 649                                        int enabled)
 650 {
 651         int ret;
 652
 653         lg_dbg("(%d)\n", enabled);
 654
 655         /* 0=Manual 1=Auto(QAM only) */
 656         ret = lgdt3306a_set_reg_bit(state, 0x0002, 3, enabled);/* SPECINVAUTO=0x04 */
 657         return ret;
 658 }
 659
 660 static int lgdt3306a_spectral_inversion(struct lgdt3306a_state *state,
 661                                        struct dtv_frontend_properties *p,
 662                                        int inversion)
 663 {
 664         int ret = 0;
 665
 666         lg_dbg("(%d)\n", inversion);
 667 #if 0
 668 /* FGR - spectral_inversion defaults already set for VSB and QAM; can enable later if desired */
 669
 670         ret = lgdt3306a_set_inversion(state, inversion);
 671
 672         switch (p->modulation) {
 673         case VSB_8:
 674                 ret = lgdt3306a_set_inversion_auto(state, 0); /* Manual only for VSB */
 675                 break;
 676         case QAM_64:
 677         case QAM_256:
 678                 ret = lgdt3306a_set_inversion_auto(state, 1); /* Auto ok for QAM */
 679                 break;
 680         default:
 681                 ret = -EINVAL;
 682         }
 683 #endif
 684         return ret;
 685 }
 686
 687 static int lgdt3306a_set_if(struct lgdt3306a_state *state,
 688                            struct dtv_frontend_properties *p)
 689 {
 690         int ret;
 691         u16 if_freq_khz;
 692         u8 nco1, nco2;
 693
 694         switch (p->modulation) {
 695         case VSB_8:
 696                 if_freq_khz = state->cfg->vsb_if_khz;
 697                 break;
 698         case QAM_64:
 699         case QAM_256:
 700                 if_freq_khz = state->cfg->qam_if_khz;
 701                 break;
 702         default:
 703                 return -EINVAL;
 704         }
 705
 706         switch (if_freq_khz) {
 707         default:
 708             lg_warn("IF=%d KHz is not supportted, 3250 assumed\n", if_freq_khz);
 709                 /* fallthrough */
 710         case 3250: /* 3.25Mhz */
 711                 nco1 = 0x34;
 712                 nco2 = 0x00;
 713                 break;
 714         case 3500: /* 3.50Mhz */
 715                 nco1 = 0x38;
 716                 nco2 = 0x00;
 717                 break;
 718         case 4000: /* 4.00Mhz */
 719                 nco1 = 0x40;
 720                 nco2 = 0x00;
 721                 break;
 722         case 5000: /* 5.00Mhz */
 723                 nco1 = 0x50;
 724                 nco2 = 0x00;
 725                 break;
 726         case 5380: /* 5.38Mhz */
 727                 nco1 = 0x56;
 728                 nco2 = 0x14;
 729                 break;
 730         }
 731         ret = lgdt3306a_write_reg(state, 0x0010, nco1);
 732         if (ret)
 733                 return ret;
 734         ret = lgdt3306a_write_reg(state, 0x0011, nco2);
 735         if (ret)
 736                 return ret;
 737
 738         lg_dbg("if_freq=%d KHz->[%04x]\n", if_freq_khz, nco1<<8 | nco2);
 739
 740         return 0;
 741 }
 742
 743 /* ------------------------------------------------------------------------ */
 744
 745 static int lgdt3306a_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
 746 {
 747         struct lgdt3306a_state *state = fe->demodulator_priv;
 748
 749         if (state->cfg->deny_i2c_rptr) {
 750                 lg_dbg("deny_i2c_rptr=%d\n", state->cfg->deny_i2c_rptr);
 751                 return 0;
 752         }
 753         lg_dbg("(%d)\n", enable);
 754
 755         return lgdt3306a_set_reg_bit(state, 0x0002, 7, enable ? 0 : 1); /* NI2CRPTEN=0x80 */
 756 }
 757
 758 static int lgdt3306a_sleep(struct lgdt3306a_state *state)
 759 {
 760         int ret;
 761
 762         lg_dbg("\n");
 763         state->current_frequency = -1; /* force re-tune, when we wake */
 764
 765         ret = lgdt3306a_mpeg_tristate(state, 1); /* disable data bus */
 766         if (lg_chkerr(ret))
 767                 goto fail;
 768
 769         ret = lgdt3306a_power(state, 0); /* power down */
 770         lg_chkerr(ret);
 771
 772 fail:
 773         return 0;
 774 }
 775
 776 static int lgdt3306a_fe_sleep(struct dvb_frontend *fe)
 777 {
 778         struct lgdt3306a_state *state = fe->demodulator_priv;
 779
 780         return lgdt3306a_sleep(state);
 781 }
 782
 783 static int lgdt3306a_init(struct dvb_frontend *fe)
 784 {
 785         struct lgdt3306a_state *state = fe->demodulator_priv;
 786         u8 val;
 787         int ret;
 788
 789         lg_dbg("\n");
 790
 791         /* 1. Normal operation mode */
 792         ret = lgdt3306a_set_reg_bit(state, 0x0001, 0, 1); /* SIMFASTENB=0x01 */
 793         if (lg_chkerr(ret))
 794                 goto fail;
 795
 796         /* 2. Spectrum inversion auto detection (Not valid for VSB) */
 797         ret = lgdt3306a_set_inversion_auto(state, 0);
 798         if (lg_chkerr(ret))
 799                 goto fail;
 800
 801         /* 3. Spectrum inversion(According to the tuner configuration) */
 802         ret = lgdt3306a_set_inversion(state, 1);
 803         if (lg_chkerr(ret))
 804                 goto fail;
 805
 806         /* 4. Peak-to-peak voltage of ADC input signal */
 807         ret = lgdt3306a_set_reg_bit(state, 0x0004, 7, 1); /* ADCSEL1V=0x80=1Vpp; 0x00=2Vpp */
 808         if (lg_chkerr(ret))
 809                 goto fail;
 810
 811         /* 5. ADC output data capture clock phase */
 812         ret = lgdt3306a_set_reg_bit(state, 0x0004, 2, 0); /* 0=same phase as ADC clock */
 813         if (lg_chkerr(ret))
 814                 goto fail;
 815
 816         /* 5a. ADC sampling clock source */
 817         ret = lgdt3306a_set_reg_bit(state, 0x0004, 3, 0); /* ADCCLKPLLSEL=0x08; 0=use ext clock, not PLL */
 818         if (lg_chkerr(ret))
 819                 goto fail;
 820
 821         /* 6. Automatic PLL set */
 822         ret = lgdt3306a_set_reg_bit(state, 0x0005, 6, 0); /* PLLSETAUTO=0x40; 0=off */
 823         if (lg_chkerr(ret))
 824                 goto fail;
 825
 826         if (state->cfg->xtalMHz == 24) {        /* 24MHz */
 827                 /* 7. Frequency for PLL output(0x2564 for 192MHz for 24MHz) */
 828                 ret = lgdt3306a_read_reg(state, 0x0005, &val);
 829                 if (lg_chkerr(ret))
 830                         goto fail;
 831                 val &= 0xc0;
 832                 val |= 0x25;
 833                 ret = lgdt3306a_write_reg(state, 0x0005, val);
 834                 if (lg_chkerr(ret))
 835                         goto fail;
 836                 ret = lgdt3306a_write_reg(state, 0x0006, 0x64);
 837                 if (lg_chkerr(ret))
 838                         goto fail;
 839
 840                 /* 8. ADC sampling frequency(0x180000 for 24MHz sampling) */
 841                 ret = lgdt3306a_read_reg(state, 0x000d, &val);
 842                 if (lg_chkerr(ret))
 843                         goto fail;
 844                 val &= 0xc0;
 845                 val |= 0x18;
 846                 ret = lgdt3306a_write_reg(state, 0x000d, val);
 847                 if (lg_chkerr(ret))
 848                         goto fail;
 849
 850         } else if (state->cfg->xtalMHz == 25) { /* 25MHz */
 851                 /* 7. Frequency for PLL output */
 852                 ret = lgdt3306a_read_reg(state, 0x0005, &val);
 853                 if (lg_chkerr(ret))
 854                         goto fail;
 855                 val &= 0xc0;
 856                 val |= 0x25;
 857                 ret = lgdt3306a_write_reg(state, 0x0005, val);
 858                 if (lg_chkerr(ret))
 859                         goto fail;
 860                 ret = lgdt3306a_write_reg(state, 0x0006, 0x64);
 861                 if (lg_chkerr(ret))
 862                         goto fail;
 863
 864                 /* 8. ADC sampling frequency(0x190000 for 25MHz sampling) */
 865                 ret = lgdt3306a_read_reg(state, 0x000d, &val);
 866                 if (lg_chkerr(ret))
 867                         goto fail;
 868                 val &= 0xc0;
 869                 val |= 0x19;
 870                 ret = lgdt3306a_write_reg(state, 0x000d, val);
 871                 if (lg_chkerr(ret))
 872                         goto fail;
 873         } else {
 874                 lg_err("Bad xtalMHz=%d\n", state->cfg->xtalMHz);
 875         }
 876 #if 0
 877         ret = lgdt3306a_write_reg(state, 0x000e, 0x00);
 878         ret = lgdt3306a_write_reg(state, 0x000f, 0x00);
 879 #endif
 880
 881         /* 9. Center frequency of input signal of ADC */
 882         ret = lgdt3306a_write_reg(state, 0x0010, 0x34); /* 3.25MHz */
 883         ret = lgdt3306a_write_reg(state, 0x0011, 0x00);
 884
 885         /* 10. Fixed gain error value */
 886         ret = lgdt3306a_write_reg(state, 0x0014, 0); /* gain error=0 */
 887
 888         /* 10a. VSB TR BW gear shift initial step */
 889         ret = lgdt3306a_read_reg(state, 0x103c, &val);
 890         val &= 0x0f;
 891         val |= 0x20; /* SAMGSAUTOSTL_V[3:0] = 2 */
 892         ret = lgdt3306a_write_reg(state, 0x103c, val);
 893
 894         /* 10b. Timing offset calibration in low temperature for VSB */
 895         ret = lgdt3306a_read_reg(state, 0x103d, &val);
 896         val &= 0xfc;
 897         val |= 0x03;
 898         ret = lgdt3306a_write_reg(state, 0x103d, val);
 899
 900         /* 10c. Timing offset calibration in low temperature for QAM */
 901         ret = lgdt3306a_read_reg(state, 0x1036, &val);
 902         val &= 0xf0;
 903         val |= 0x0c;
 904         ret = lgdt3306a_write_reg(state, 0x1036, val);
 905
 906         /* 11. Using the imaginary part of CIR in CIR loading */
 907         ret = lgdt3306a_read_reg(state, 0x211f, &val);
 908         val &= 0xef; /* do not use imaginary of CIR */
 909         ret = lgdt3306a_write_reg(state, 0x211f, val);
 910
 911         /* 12. Control of no signal detector function */
 912         ret = lgdt3306a_read_reg(state, 0x2849, &val);
 913         val &= 0xef; /* NOUSENOSIGDET=0, enable no signal detector */
 914         ret = lgdt3306a_write_reg(state, 0x2849, val);
 915
 916         /* FGR - put demod in some known mode */
 917         ret = lgdt3306a_set_vsb(state);
 918
 919         /* 13. TP stream format */
 920         ret = lgdt3306a_mpeg_mode(state, state->cfg->mpeg_mode);
 921
 922         /* 14. disable output buses */
 923         ret = lgdt3306a_mpeg_tristate(state, 1);
 924
 925         /* 15. Sleep (in reset) */
 926         ret = lgdt3306a_sleep(state);
 927         lg_chkerr(ret);
 928
 929 fail:
 930         return ret;
 931 }
 932
 933 static int lgdt3306a_set_parameters(struct dvb_frontend *fe)
 934 {
 935         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
 936         struct lgdt3306a_state *state = fe->demodulator_priv;
 937         int ret;
 938
 939         lg_dbg("(%d, %d)\n", p->frequency, p->modulation);
 940
 941         if (state->current_frequency  == p->frequency &&
 942            state->current_modulation == p->modulation) {
 943                 lg_dbg(" (already set, skipping ...)\n");
 944                 return 0;
 945         }
 946         state->current_frequency = -1;
 947         state->current_modulation = -1;
 948
 949         ret = lgdt3306a_power(state, 1); /* power up */
 950         if (lg_chkerr(ret))
 951                 goto fail;
 952
 953         if (fe->ops.tuner_ops.set_params) {
 954                 ret = fe->ops.tuner_ops.set_params(fe);
 955                 if (fe->ops.i2c_gate_ctrl)
 956                         fe->ops.i2c_gate_ctrl(fe, 0);
 957 #if 0
 958                 if (lg_chkerr(ret))
 959                         goto fail;
 960                 state->current_frequency = p->frequency;
 961 #endif
 962         }
 963
 964         ret = lgdt3306a_set_modulation(state, p);
 965         if (lg_chkerr(ret))
 966                 goto fail;
 967
 968         ret = lgdt3306a_agc_setup(state, p);
 969         if (lg_chkerr(ret))
 970                 goto fail;
 971
 972         ret = lgdt3306a_set_if(state, p);
 973         if (lg_chkerr(ret))
 974                 goto fail;
 975
 976         ret = lgdt3306a_spectral_inversion(state, p,
 977                                           state->cfg->spectral_inversion ? 1 : 0);
 978         if (lg_chkerr(ret))
 979                 goto fail;
 980
 981         ret = lgdt3306a_mpeg_mode(state, state->cfg->mpeg_mode);
 982         if (lg_chkerr(ret))
 983                 goto fail;
 984
 985         ret = lgdt3306a_mpeg_mode_polarity(state,
 986                                           state->cfg->tpclk_edge,
 987                                           state->cfg->tpvalid_polarity);
 988         if (lg_chkerr(ret))
 989                 goto fail;
 990
 991         ret = lgdt3306a_mpeg_tristate(state, 0); /* enable data bus */
 992         if (lg_chkerr(ret))
 993                 goto fail;
 994
 995         ret = lgdt3306a_soft_reset(state);
 996         if (lg_chkerr(ret))
 997                 goto fail;
 998
 999 #ifdef DBG_DUMP
1000         lgdt3306a_DumpAllRegs(state);
1001 #endif
1002         state->current_frequency = p->frequency;
1003 fail:
1004         return ret;
1005 }
1006
1007 static int lgdt3306a_get_frontend(struct dvb_frontend *fe)
1008 {
1009         struct lgdt3306a_state *state = fe->demodulator_priv;
1010         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1011
1012         lg_dbg("(%u, %d)\n", state->current_frequency, state->current_modulation);
1013
1014         p->modulation = state->current_modulation;
1015         p->frequency = state->current_frequency;
1016         return 0;
1017 }
1018
1019 static enum dvbfe_algo lgdt3306a_get_frontend_algo(struct dvb_frontend *fe)
1020 {
1021 #if 1
1022         return DVBFE_ALGO_CUSTOM;
1023 #else
1024         return DVBFE_ALGO_HW;
1025 #endif
1026 }
1027
1028 /* ------------------------------------------------------------------------ */
1029 static int lgdt3306a_monitor_vsb(struct lgdt3306a_state *state)
1030 {
1031         u8 val;
1032         int ret;
1033         u8 snrRef, maxPowerMan, nCombDet;
1034         u16 fbDlyCir;
1035
1036         ret = lgdt3306a_read_reg(state, 0x21a1, &val);
1037         if (ret)
1038                 return ret;
1039         snrRef = val & 0x3f;
1040
1041         ret = lgdt3306a_read_reg(state, 0x2185, &maxPowerMan);
1042         if (ret)
1043                 return ret;
1044
1045         ret = lgdt3306a_read_reg(state, 0x2191, &val);
1046         if (ret)
1047                 return ret;
1048         nCombDet = (val & 0x80) >> 7;
1049
1050         ret = lgdt3306a_read_reg(state, 0x2180, &val);
1051         if (ret)
1052                 return ret;
1053         fbDlyCir = (val & 0x03) << 8;
1054
1055         ret = lgdt3306a_read_reg(state, 0x2181, &val);
1056         if (ret)
1057                 return ret;
1058         fbDlyCir |= val;
1059
1060         lg_dbg("snrRef=%d maxPowerMan=0x%x nCombDet=%d fbDlyCir=0x%x\n",
1061                 snrRef, maxPowerMan, nCombDet, fbDlyCir);
1062
1063         /* Carrier offset sub loop bandwidth */
1064         ret = lgdt3306a_read_reg(state, 0x1061, &val);
1065         if (ret)
1066                 return ret;
1067         val &= 0xf8;
1068         if ((snrRef > 18) && (maxPowerMan > 0x68) && (nCombDet == 0x01) && ((fbDlyCir == 0x03FF) || (fbDlyCir < 0x6C))) {
1069                 /* SNR is over 18dB and no ghosting */
1070                 val |= 0x00; /* final bandwidth = 0 */
1071         } else {
1072                 val |= 0x04; /* final bandwidth = 4 */
1073         }
1074         ret = lgdt3306a_write_reg(state, 0x1061, val);
1075         if (ret)
1076                 return ret;
1077
1078         /* Adjust Notch Filter */
1079         ret = lgdt3306a_read_reg(state, 0x0024, &val);
1080         if (ret)
1081                 return ret;
1082         val &= 0x0f;
1083         if (nCombDet == 0) { /* Turn on the Notch Filter */
1084                 val |= 0x50;
1085         }
1086         ret = lgdt3306a_write_reg(state, 0x0024, val);
1087         if (ret)
1088                 return ret;
1089
1090         /* VSB Timing Recovery output normalization */
1091         ret = lgdt3306a_read_reg(state, 0x103d, &val);
1092         if (ret)
1093                 return ret;
1094         val &= 0xcf;
1095         val |= 0x20;
1096         ret = lgdt3306a_write_reg(state, 0x103d, val);
1097
1098         return ret;
1099 }
1100
1101 static enum lgdt3306a_modulation lgdt3306a_check_oper_mode(struct lgdt3306a_state *state)
1102 {
1103         u8 val = 0;
1104         int ret;
1105
1106         ret = lgdt3306a_read_reg(state, 0x0081, &val);
1107         if (ret)
1108                 goto err;
1109
1110         if (val & 0x80) {
1111                 lg_dbg("VSB\n");
1112                 return LG3306_VSB;
1113         }
1114         if (val & 0x08) {
1115                 ret = lgdt3306a_read_reg(state, 0x00a6, &val);
1116                 if (ret)
1117                         goto err;
1118                 val = val >> 2;
1119                 if (val & 0x01) {
1120                         lg_dbg("QAM256\n");
1121                         return LG3306_QAM256;
1122                 } else {
1123                         lg_dbg("QAM64\n");
1124                         return LG3306_QAM64;
1125                 }
1126         }
1127 err:
1128         lg_warn("UNKNOWN\n");
1129         return LG3306_UNKNOWN_MODE;
1130 }
1131
1132 static enum lgdt3306a_lock_status lgdt3306a_check_lock_status(struct lgdt3306a_state *state,
1133                         enum lgdt3306a_lock_check whatLock)
1134 {
1135         u8 val = 0;
1136         int ret;
1137         enum lgdt3306a_modulation       modeOper;
1138         enum lgdt3306a_lock_status lockStatus;
1139
1140         modeOper = LG3306_UNKNOWN_MODE;
1141
1142         switch (whatLock) {
1143         case LG3306_SYNC_LOCK:
1144         {
1145                 ret = lgdt3306a_read_reg(state, 0x00a6, &val);
1146                 if (ret)
1147                         return ret;
1148
1149                 if ((val & 0x80) == 0x80)
1150                         lockStatus = LG3306_LOCK;
1151                 else
1152                         lockStatus = LG3306_UNLOCK;
1153
1154                 lg_dbg("SYNC_LOCK=%x\n", lockStatus);
1155                 break;
1156         }
1157         case LG3306_AGC_LOCK:
1158         {
1159                 ret = lgdt3306a_read_reg(state, 0x0080, &val);
1160                 if (ret)
1161                         return ret;
1162
1163                 if ((val & 0x40) == 0x40)
1164                         lockStatus = LG3306_LOCK;
1165                 else
1166                         lockStatus = LG3306_UNLOCK;
1167
1168                 lg_dbg("AGC_LOCK=%x\n", lockStatus);
1169                 break;
1170         }
1171         case LG3306_TR_LOCK:
1172         {
1173                 modeOper = lgdt3306a_check_oper_mode(state);
1174                 if ((modeOper == LG3306_QAM64) || (modeOper == LG3306_QAM256)) {
1175                         ret = lgdt3306a_read_reg(state, 0x1094, &val);
1176                         if (ret)
1177                                 return ret;
1178
1179                         if ((val & 0x80) == 0x80)
1180                                 lockStatus = LG3306_LOCK;
1181                         else
1182                                 lockStatus = LG3306_UNLOCK;
1183                 } else
1184                         lockStatus = LG3306_UNKNOWN_LOCK;
1185
1186                 lg_dbg("TR_LOCK=%x\n", lockStatus);
1187                 break;
1188         }
1189         case LG3306_FEC_LOCK:
1190         {
1191                 modeOper = lgdt3306a_check_oper_mode(state);
1192                 if ((modeOper == LG3306_QAM64) || (modeOper == LG3306_QAM256)) {
1193                         ret = lgdt3306a_read_reg(state, 0x0080, &val);
1194                         if (ret)
1195                                 return ret;
1196
1197                         if ((val & 0x10) == 0x10)
1198                                 lockStatus = LG3306_LOCK;
1199                         else
1200                                 lockStatus = LG3306_UNLOCK;
1201                 } else
1202                         lockStatus = LG3306_UNKNOWN_LOCK;
1203
1204                 lg_dbg("FEC_LOCK=%x\n", lockStatus);
1205                 break;
1206         }
1207
1208         default:
1209                 lockStatus = LG3306_UNKNOWN_LOCK;
1210                 lg_warn("UNKNOWN whatLock=%d\n", whatLock);
1211                 break;
1212         }
1213
1214         return lockStatus;
1215 }
1216
1217 static enum lgdt3306a_neverlock_status lgdt3306a_check_neverlock_status(struct lgdt3306a_state *state)
1218 {
1219         u8 val = 0;
1220         int ret;
1221         enum lgdt3306a_neverlock_status lockStatus;
1222
1223         ret = lgdt3306a_read_reg(state, 0x0080, &val);
1224         if (ret)
1225                 return ret;
1226         lockStatus = (enum lgdt3306a_neverlock_status)(val & 0x03);
1227
1228         lg_dbg("NeverLock=%d", lockStatus);
1229
1230         return lockStatus;
1231 }
1232
1233 static int lgdt3306a_pre_monitoring(struct lgdt3306a_state *state)
1234 {
1235         u8 val = 0;
1236         int ret;
1237         u8 currChDiffACQ, snrRef, mainStrong, aiccrejStatus;
1238
1239         /* Channel variation */
1240         ret = lgdt3306a_read_reg(state, 0x21bc, &currChDiffACQ);
1241         if (ret)
1242                 return ret;
1243
1244         /* SNR of Frame sync */
1245         ret = lgdt3306a_read_reg(state, 0x21a1, &val);
1246         if (ret)
1247                 return ret;
1248         snrRef = val & 0x3f;
1249
1250         /* Strong Main CIR */
1251         ret = lgdt3306a_read_reg(state, 0x2199, &val);
1252         if (ret)
1253                 return ret;
1254         mainStrong = (val & 0x40) >> 6;
1255
1256         ret = lgdt3306a_read_reg(state, 0x0090, &val);
1257         if (ret)
1258                 return ret;
1259         aiccrejStatus = (val & 0xf0) >> 4;
1260
1261         lg_dbg("snrRef=%d mainStrong=%d aiccrejStatus=%d currChDiffACQ=0x%x\n",
1262                 snrRef, mainStrong, aiccrejStatus, currChDiffACQ);
1263
1264 #if 0
1265         if ((mainStrong == 0) && (currChDiffACQ > 0x70)) /* Dynamic ghost exists */
1266 #endif
1267         if (mainStrong == 0) {
1268                 ret = lgdt3306a_read_reg(state, 0x2135, &val);
1269                 if (ret)
1270                         return ret;
1271                 val &= 0x0f;
1272                 val |= 0xa0;
1273                 ret = lgdt3306a_write_reg(state, 0x2135, val);
1274                 if (ret)
1275                         return ret;
1276
1277                 ret = lgdt3306a_read_reg(state, 0x2141, &val);
1278                 if (ret)
1279                         return ret;
1280                 val &= 0x3f;
1281                 val |= 0x80;
1282                 ret = lgdt3306a_write_reg(state, 0x2141, val);
1283                 if (ret)
1284                         return ret;
1285
1286                 ret = lgdt3306a_write_reg(state, 0x2122, 0x70);
1287                 if (ret)
1288                         return ret;
1289         } else { /* Weak ghost or static channel */
1290                 ret = lgdt3306a_read_reg(state, 0x2135, &val);
1291                 if (ret)
1292                         return ret;
1293                 val &= 0x0f;
1294                 val |= 0x70;
1295                 ret = lgdt3306a_write_reg(state, 0x2135, val);
1296                 if (ret)
1297                         return ret;
1298
1299                 ret = lgdt3306a_read_reg(state, 0x2141, &val);
1300                 if (ret)
1301                         return ret;
1302                 val &= 0x3f;
1303                 val |= 0x40;
1304                 ret = lgdt3306a_write_reg(state, 0x2141, val);
1305                 if (ret)
1306                         return ret;
1307
1308                 ret = lgdt3306a_write_reg(state, 0x2122, 0x40);
1309                 if (ret)
1310                         return ret;
1311         }
1312         return 0;
1313 }
1314
1315 static enum lgdt3306a_lock_status lgdt3306a_sync_lock_poll(struct lgdt3306a_state *state)
1316 {
1317         enum lgdt3306a_lock_status syncLockStatus = LG3306_UNLOCK;
1318         int     i;
1319
1320         for (i = 0; i < 2; i++) {
1321                 msleep(30);
1322
1323                 syncLockStatus = lgdt3306a_check_lock_status(state, LG3306_SYNC_LOCK);
1324
1325                 if (syncLockStatus == LG3306_LOCK) {
1326                         lg_dbg("locked(%d)\n", i);
1327                         return LG3306_LOCK;
1328                 }
1329         }
1330         lg_dbg("not locked\n");
1331         return LG3306_UNLOCK;
1332 }
1333
1334 static enum lgdt3306a_lock_status lgdt3306a_fec_lock_poll(struct lgdt3306a_state *state)
1335 {
1336         enum lgdt3306a_lock_status FECLockStatus = LG3306_UNLOCK;
1337         int     i;
1338
1339         for (i = 0; i < 2; i++) {
1340                 msleep(30);
1341
1342                 FECLockStatus = lgdt3306a_check_lock_status(state, LG3306_FEC_LOCK);
1343
1344                 if (FECLockStatus == LG3306_LOCK) {
1345                         lg_dbg("locked(%d)\n", i);
1346                         return FECLockStatus;
1347                 }
1348         }
1349         lg_dbg("not locked\n");
1350         return FECLockStatus;
1351 }
1352
1353 static enum lgdt3306a_neverlock_status lgdt3306a_neverlock_poll(struct lgdt3306a_state *state)
1354 {
1355         enum lgdt3306a_neverlock_status NLLockStatus = LG3306_NL_FAIL;
1356         int     i;
1357
1358         for (i = 0; i < 5; i++) {
1359                 msleep(30);
1360
1361                 NLLockStatus = lgdt3306a_check_neverlock_status(state);
1362
1363                 if (NLLockStatus == LG3306_NL_LOCK) {
1364                         lg_dbg("NL_LOCK(%d)\n", i);
1365                         return NLLockStatus;
1366                 }
1367         }
1368         lg_dbg("NLLockStatus=%d\n", NLLockStatus);
1369         return NLLockStatus;
1370 }
1371
1372 static u8 lgdt3306a_get_packet_error(struct lgdt3306a_state *state)
1373 {
1374         u8 val;
1375         int ret;
1376
1377         ret = lgdt3306a_read_reg(state, 0x00fa, &val);
1378         if (ret)
1379                 return ret;
1380
1381         return val;
1382 }
1383
1384 static u32 log10_x1000(u32 x)
1385 {
1386         static u32 valx_x10[]     = {  10,  11,  13,  15,  17,  20,  25,  33,  41,  50,  59,  73,  87,  100 };
1387         static u32 log10x_x1000[] = {   0,  41, 114, 176, 230, 301, 398, 518, 613, 699, 771, 863, 939, 1000 };
1388         static u32 nelems = sizeof(valx_x10)/sizeof(valx_x10[0]);
1389         u32 diff_val, step_val, step_log10;
1390         u32 log_val = 0;
1391         u32 i;
1392
1393         if (x <= 0)
1394                 return -1000000; /* signal error */
1395
1396         if (x < 10) {
1397                 while (x < 10) {
1398                         x = x * 10;
1399                         log_val--;
1400                 }
1401         } else if (x == 10) {
1402                 return 0; /* log(1)=0 */
1403         } else {
1404                 while (x >= 100) {
1405                         x = x / 10;
1406                         log_val++;
1407                 }
1408         }
1409         log_val *= 1000;
1410
1411         if (x == 10) /* was our input an exact multiple of 10 */
1412                 return log_val; /* don't need to interpolate */
1413
1414         /* find our place on the log curve */
1415         for (i = 1; i < nelems; i++) {
1416                 if (valx_x10[i] >= x)
1417                         break;
1418         }
1419         if (i == nelems)
1420                 return log_val + log10x_x1000[i - 1];
1421
1422         diff_val   = x - valx_x10[i-1];
1423         step_val   = valx_x10[i] - valx_x10[i - 1];
1424         step_log10 = log10x_x1000[i] - log10x_x1000[i - 1];
1425
1426         /* do a linear interpolation to get in-between values */
1427         return log_val + log10x_x1000[i - 1] +
1428                 ((diff_val*step_log10) / step_val);
1429 }
1430
1431 static u32 lgdt3306a_calculate_snr_x100(struct lgdt3306a_state *state)
1432 {
1433         u32 mse; /* Mean-Square Error */
1434         u32 pwr; /* Constelation power */
1435         u32 snr_x100;
1436
1437         mse = (read_reg(state, 0x00ec) << 8) |
1438               (read_reg(state, 0x00ed));
1439         pwr = (read_reg(state, 0x00e8) << 8) |
1440               (read_reg(state, 0x00e9));
1441
1442         if (mse == 0) /* no signal */
1443                 return 0;
1444
1445         snr_x100 = log10_x1000((pwr * 10000) / mse) - 3000;
1446         lg_dbg("mse=%u, pwr=%u, snr_x100=%d\n", mse, pwr, snr_x100);
1447
1448         return snr_x100;
1449 }
1450
1451 static enum lgdt3306a_lock_status lgdt3306a_vsb_lock_poll(struct lgdt3306a_state *state)
1452 {
1453         int ret;
1454         u8 cnt = 0;
1455         u8 packet_error;
1456         u32 snr;
1457
1458         while (1) {
1459                 if (lgdt3306a_sync_lock_poll(state) == LG3306_UNLOCK) {
1460                         lg_dbg("no sync lock!\n");
1461                         return LG3306_UNLOCK;
1462                 } else {
1463                         msleep(20);
1464                         ret = lgdt3306a_pre_monitoring(state);
1465                         if (ret)
1466                                 return LG3306_UNLOCK;
1467
1468                         packet_error = lgdt3306a_get_packet_error(state);
1469                         snr = lgdt3306a_calculate_snr_x100(state);
1470                         lg_dbg("cnt=%d errors=%d snr=%d\n",
1471                                cnt, packet_error, snr);
1472
1473                         if ((snr < 1500) || (packet_error >= 0xff))
1474                                 cnt++;
1475                         else
1476                                 return LG3306_LOCK;
1477
1478                         if (cnt >= 10) {
1479                                 lg_dbg("not locked!\n");
1480                                 return LG3306_UNLOCK;
1481                         }
1482                 }
1483         }
1484         return LG3306_UNLOCK;
1485 }
1486
1487 static enum lgdt3306a_lock_status lgdt3306a_qam_lock_poll(struct lgdt3306a_state *state)
1488 {
1489         u8 cnt = 0;
1490         u8 packet_error;
1491         u32     snr;
1492
1493         while (1) {
1494                 if (lgdt3306a_fec_lock_poll(state) == LG3306_UNLOCK) {
1495                         lg_dbg("no fec lock!\n");
1496                         return LG3306_UNLOCK;
1497                 } else {
1498                         msleep(20);
1499
1500                         packet_error = lgdt3306a_get_packet_error(state);
1501                         snr = lgdt3306a_calculate_snr_x100(state);
1502                         lg_dbg("cnt=%d errors=%d snr=%d\n",
1503                                cnt, packet_error, snr);
1504
1505                         if ((snr < 1500) || (packet_error >= 0xff))
1506                                 cnt++;
1507                         else
1508                                 return LG3306_LOCK;
1509
1510                         if (cnt >= 10) {
1511                                 lg_dbg("not locked!\n");
1512                                 return LG3306_UNLOCK;
1513                         }
1514                 }
1515         }
1516         return LG3306_UNLOCK;
1517 }
1518
1519 static int lgdt3306a_read_status(struct dvb_frontend *fe, fe_status_t *status)
1520 {
1521         struct lgdt3306a_state *state = fe->demodulator_priv;
1522         u16 strength = 0;
1523         int ret = 0;
1524
1525         if (fe->ops.tuner_ops.get_rf_strength) {
1526                 ret = fe->ops.tuner_ops.get_rf_strength(fe, &strength);
1527                 if (ret == 0) {
1528                         lg_dbg("strength=%d\n", strength);
1529                 } else {
1530                         lg_dbg("fe->ops.tuner_ops.get_rf_strength() failed\n");
1531                 }
1532         }
1533
1534         *status = 0;
1535         if (lgdt3306a_neverlock_poll(state) == LG3306_NL_LOCK) {
1536                 *status |= FE_HAS_SIGNAL;
1537                 *status |= FE_HAS_CARRIER;
1538
1539                 switch (state->current_modulation) {
1540                 case QAM_256:
1541                 case QAM_64:
1542                         if (lgdt3306a_qam_lock_poll(state) == LG3306_LOCK) {
1543                                 *status |= FE_HAS_VITERBI;
1544                                 *status |= FE_HAS_SYNC;
1545
1546                                 *status |= FE_HAS_LOCK;
1547                         }
1548                         break;
1549                 case VSB_8:
1550                         if (lgdt3306a_vsb_lock_poll(state) == LG3306_LOCK) {
1551                                 *status |= FE_HAS_VITERBI;
1552                                 *status |= FE_HAS_SYNC;
1553
1554                                 *status |= FE_HAS_LOCK;
1555
1556                                 ret = lgdt3306a_monitor_vsb(state);
1557                         }
1558                         break;
1559                 default:
1560                         ret = -EINVAL;
1561                 }
1562         }
1563         return ret;
1564 }
1565
1566
1567 static int lgdt3306a_read_snr(struct dvb_frontend *fe, u16 *snr)
1568 {
1569         struct lgdt3306a_state *state = fe->demodulator_priv;
1570
1571         state->snr = lgdt3306a_calculate_snr_x100(state);
1572         /* report SNR in dB * 10 */
1573         *snr = state->snr/10;
1574
1575         return 0;
1576 }
1577
1578 static int lgdt3306a_read_signal_strength(struct dvb_frontend *fe,
1579                                          u16 *strength)
1580 {
1581         /*
1582          * Calculate some sort of "strength" from SNR
1583          */
1584         struct lgdt3306a_state *state = fe->demodulator_priv;
1585         u16 snr; /* snr_x10 */
1586         int ret;
1587         u32 ref_snr; /* snr*100 */
1588         u32 str;
1589
1590         *strength = 0;
1591
1592         switch (state->current_modulation) {
1593         case VSB_8:
1594                  ref_snr = 1600; /* 16dB */
1595                  break;
1596         case QAM_64:
1597                  ref_snr = 2200; /* 22dB */
1598                  break;
1599         case QAM_256:
1600                  ref_snr = 2800; /* 28dB */
1601                  break;
1602         default:
1603                 return -EINVAL;
1604         }
1605
1606         ret = fe->ops.read_snr(fe, &snr);
1607         if (lg_chkerr(ret))
1608                 goto fail;
1609
1610         if (state->snr <= (ref_snr - 100))
1611                 str = 0;
1612         else if (state->snr <= ref_snr)
1613                 str = (0xffff * 65) / 100; /* 65% */
1614         else {
1615                 str = state->snr - ref_snr;
1616                 str /= 50;
1617                 str += 78; /* 78%-100% */
1618                 if (str > 100)
1619                         str = 100;
1620                 str = (0xffff * str) / 100;
1621         }
1622         *strength = (u16)str;
1623         lg_dbg("strength=%u\n", *strength);
1624
1625 fail:
1626         return ret;
1627 }
1628
1629 /* ------------------------------------------------------------------------ */
1630
1631 static int lgdt3306a_read_ber(struct dvb_frontend *fe, u32 *ber)
1632 {
1633         struct lgdt3306a_state *state = fe->demodulator_priv;
1634         u32 tmp;
1635
1636         *ber = 0;
1637 #if 1
1638         /* FGR - BUGBUG - I don't know what value is expected by dvb_core
1639          * what is the scale of the value?? */
1640         tmp =              read_reg(state, 0x00fc); /* NBERVALUE[24-31] */
1641         tmp = (tmp << 8) | read_reg(state, 0x00fd); /* NBERVALUE[16-23] */
1642         tmp = (tmp << 8) | read_reg(state, 0x00fe); /* NBERVALUE[8-15] */
1643         tmp = (tmp << 8) | read_reg(state, 0x00ff); /* NBERVALUE[0-7] */
1644         *ber = tmp;
1645         lg_dbg("ber=%u\n", tmp);
1646 #endif
1647         return 0;
1648 }
1649
1650 static int lgdt3306a_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
1651 {
1652         struct lgdt3306a_state *state = fe->demodulator_priv;
1653
1654         *ucblocks = 0;
1655 #if 1
1656         /* FGR - BUGBUG - I don't know what value is expected by dvb_core
1657          * what happens when value wraps? */
1658         *ucblocks = read_reg(state, 0x00f4); /* TPIFTPERRCNT[0-7] */
1659         lg_dbg("ucblocks=%u\n", *ucblocks);
1660 #endif
1661
1662         return 0;
1663 }
1664
1665 static int lgdt3306a_tune(struct dvb_frontend *fe, bool re_tune, unsigned int mode_flags, unsigned int *delay, fe_status_t *status)
1666 {
1667         int ret = 0;
1668         struct lgdt3306a_state *state = fe->demodulator_priv;
1669
1670         lg_dbg("re_tune=%u\n", re_tune);
1671
1672         if (re_tune) {
1673                 state->current_frequency = -1; /* force re-tune */
1674                 ret = lgdt3306a_set_parameters(fe);
1675                 if (ret != 0)
1676                         return ret;
1677         }
1678         *delay = 125;
1679         ret = lgdt3306a_read_status(fe, status);
1680
1681         return ret;
1682 }
1683
1684 static int lgdt3306a_get_tune_settings(struct dvb_frontend *fe,
1685                                        struct dvb_frontend_tune_settings
1686                                        *fe_tune_settings)
1687 {
1688         fe_tune_settings->min_delay_ms = 100;
1689         lg_dbg("\n");
1690         return 0;
1691 }
1692
1693 static int lgdt3306a_search(struct dvb_frontend *fe)
1694 {
1695         fe_status_t status = 0;
1696         int i, ret;
1697
1698         /* set frontend */
1699         ret = lgdt3306a_set_parameters(fe);
1700         if (ret)
1701                 goto error;
1702
1703         /* wait frontend lock */
1704         for (i = 20; i > 0; i--) {
1705                 lg_dbg(": loop=%d\n", i);
1706                 msleep(50);
1707                 ret = lgdt3306a_read_status(fe, &status);
1708                 if (ret)
1709                         goto error;
1710
1711                 if (status & FE_HAS_LOCK)
1712                         break;
1713         }
1714
1715         /* check if we have a valid signal */
1716         if (status & FE_HAS_LOCK)
1717                 return DVBFE_ALGO_SEARCH_SUCCESS;
1718         else
1719                 return DVBFE_ALGO_SEARCH_AGAIN;
1720
1721 error:
1722         lg_dbg("failed (%d)\n", ret);
1723         return DVBFE_ALGO_SEARCH_ERROR;
1724 }
1725
1726 static void lgdt3306a_release(struct dvb_frontend *fe)
1727 {
1728         struct lgdt3306a_state *state = fe->demodulator_priv;
1729
1730         lg_dbg("\n");
1731         kfree(state);
1732 }
1733
1734 static struct dvb_frontend_ops lgdt3306a_ops;
1735
1736 struct dvb_frontend *lgdt3306a_attach(const struct lgdt3306a_config *config,
1737                                       struct i2c_adapter *i2c_adap)
1738 {
1739         struct lgdt3306a_state *state = NULL;
1740         int ret;
1741         u8 val;
1742
1743         lg_dbg("(%d-%04x)\n",
1744                i2c_adap ? i2c_adapter_id(i2c_adap) : 0,
1745                config ? config->i2c_addr : 0);
1746
1747         state = kzalloc(sizeof(struct lgdt3306a_state), GFP_KERNEL);
1748         if (state == NULL)
1749                 goto fail;
1750
1751         state->cfg = config;
1752         state->i2c_adap = i2c_adap;
1753
1754         memcpy(&state->frontend.ops, &lgdt3306a_ops,
1755                sizeof(struct dvb_frontend_ops));
1756         state->frontend.demodulator_priv = state;
1757
1758         /* verify that we're talking to a lg3306a */
1759         /* FGR - NOTE - there is no obvious ChipId to check; we check
1760          * some "known" bits after reset, but it's still just a guess */
1761         ret = lgdt3306a_read_reg(state, 0x0000, &val);
1762         if (lg_chkerr(ret))
1763                 goto fail;
1764         if ((val & 0x74) != 0x74) {
1765                 lg_warn("expected 0x74, got 0x%x\n", (val & 0x74));
1766 #if 0
1767                 goto fail;      /* BUGBUG - re-enable when we know this is right */
1768 #endif
1769         }
1770         ret = lgdt3306a_read_reg(state, 0x0001, &val);
1771         if (lg_chkerr(ret))
1772                 goto fail;
1773         if ((val & 0xf6) != 0xc6) {
1774                 lg_warn("expected 0xc6, got 0x%x\n", (val & 0xf6));
1775 #if 0
1776                 goto fail;      /* BUGBUG - re-enable when we know this is right */
1777 #endif
1778         }
1779         ret = lgdt3306a_read_reg(state, 0x0002, &val);
1780         if (lg_chkerr(ret))
1781                 goto fail;
1782         if ((val & 0x73) != 0x03) {
1783                 lg_warn("expected 0x03, got 0x%x\n", (val & 0x73));
1784 #if 0
1785                 goto fail;      /* BUGBUG - re-enable when we know this is right */
1786 #endif
1787         }
1788
1789         state->current_frequency = -1;
1790         state->current_modulation = -1;
1791
1792         lgdt3306a_sleep(state);
1793
1794         return &state->frontend;
1795
1796 fail:
1797         lg_warn("unable to detect LGDT3306A hardware\n");
1798         kfree(state);
1799         return NULL;
1800 }
1801 EXPORT_SYMBOL(lgdt3306a_attach);
1802
1803 #ifdef DBG_DUMP
1804
1805 static const short regtab[] = {
1806         0x0000, /* SOFTRSTB 1'b1 1'b1 1'b1 ADCPDB 1'b1 PLLPDB GBBPDB 11111111 */
1807         0x0001, /* 1'b1 1'b1 1'b0 1'b0 AUTORPTRS */
1808         0x0002, /* NI2CRPTEN 1'b0 1'b0 1'b0 SPECINVAUT */
1809         0x0003, /* AGCRFOUT */
1810         0x0004, /* ADCSEL1V ADCCNT ADCCNF ADCCNS ADCCLKPLL */
1811         0x0005, /* PLLINDIVSE */
1812         0x0006, /* PLLCTRL[7:0] 11100001 */
1813         0x0007, /* SYSINITWAITTIME[7:0] (msec) 00001000 */
1814         0x0008, /* STDOPMODE[7:0] 10000000 */
1815         0x0009, /* 1'b0 1'b0 1'b0 STDOPDETTMODE[2:0] STDOPDETCMODE[1:0] 00011110 */
1816         0x000a, /* DAFTEN 1'b1 x x SCSYSLOCK */
1817         0x000b, /* SCSYSLOCKCHKTIME[7:0] (10msec) 01100100 */
1818         0x000d, /* x SAMPLING4 */
1819         0x000e, /* SAMFREQ[15:8] 00000000 */
1820         0x000f, /* SAMFREQ[7:0] 00000000 */
1821         0x0010, /* IFFREQ[15:8] 01100000 */
1822         0x0011, /* IFFREQ[7:0] 00000000 */
1823         0x0012, /* AGCEN AGCREFMO */
1824         0x0013, /* AGCRFFIXB AGCIFFIXB AGCLOCKDETRNGSEL[1:0] 1'b1 1'b0 1'b0 1'b0 11101000 */
1825         0x0014, /* AGCFIXVALUE[7:0] 01111111 */
1826         0x0015, /* AGCREF[15:8] 00001010 */
1827         0x0016, /* AGCREF[7:0] 11100100 */
1828         0x0017, /* AGCDELAY[7:0] 00100000 */
1829         0x0018, /* AGCRFBW[3:0] AGCIFBW[3:0] 10001000 */
1830         0x0019, /* AGCUDOUTMODE[1:0] AGCUDCTRLLEN[1:0] AGCUDCTRL */
1831         0x001c, /* 1'b1 PFEN MFEN AICCVSYNC */
1832         0x001d, /* 1'b0 1'b1 1'b0 1'b1 AICCVSYNC */
1833         0x001e, /* AICCALPHA[3:0] 1'b1 1'b0 1'b1 1'b0 01111010 */
1834         0x001f, /* AICCDETTH[19:16] AICCOFFTH[19:16] 00000000 */
1835         0x0020, /* AICCDETTH[15:8] 01111100 */
1836         0x0021, /* AICCDETTH[7:0] 00000000 */
1837         0x0022, /* AICCOFFTH[15:8] 00000101 */
1838         0x0023, /* AICCOFFTH[7:0] 11100000 */
1839         0x0024, /* AICCOPMODE3[1:0] AICCOPMODE2[1:0] AICCOPMODE1[1:0] AICCOPMODE0[1:0] 00000000 */
1840         0x0025, /* AICCFIXFREQ3[23:16] 00000000 */
1841         0x0026, /* AICCFIXFREQ3[15:8] 00000000 */
1842         0x0027, /* AICCFIXFREQ3[7:0] 00000000 */
1843         0x0028, /* AICCFIXFREQ2[23:16] 00000000 */
1844         0x0029, /* AICCFIXFREQ2[15:8] 00000000 */
1845         0x002a, /* AICCFIXFREQ2[7:0] 00000000 */
1846         0x002b, /* AICCFIXFREQ1[23:16] 00000000 */
1847         0x002c, /* AICCFIXFREQ1[15:8] 00000000 */
1848         0x002d, /* AICCFIXFREQ1[7:0] 00000000 */
1849         0x002e, /* AICCFIXFREQ0[23:16] 00000000 */
1850         0x002f, /* AICCFIXFREQ0[15:8] 00000000 */
1851         0x0030, /* AICCFIXFREQ0[7:0] 00000000 */
1852         0x0031, /* 1'b0 1'b1 1'b0 1'b0 x DAGC1STER */
1853         0x0032, /* DAGC1STEN DAGC1STER */
1854         0x0033, /* DAGC1STREF[15:8] 00001010 */
1855         0x0034, /* DAGC1STREF[7:0] 11100100 */
1856         0x0035, /* DAGC2NDE */
1857         0x0036, /* DAGC2NDREF[15:8] 00001010 */
1858         0x0037, /* DAGC2NDREF[7:0] 10000000 */
1859         0x0038, /* DAGC2NDLOCKDETRNGSEL[1:0] */
1860         0x003d, /* 1'b1 SAMGEARS */
1861         0x0040, /* SAMLFGMA */
1862         0x0041, /* SAMLFBWM */
1863         0x0044, /* 1'b1 CRGEARSHE */
1864         0x0045, /* CRLFGMAN */
1865         0x0046, /* CFLFBWMA */
1866         0x0047, /* CRLFGMAN */
1867         0x0048, /* x x x x CRLFGSTEP_VS[3:0] xxxx1001 */
1868         0x0049, /* CRLFBWMA */
1869         0x004a, /* CRLFBWMA */
1870         0x0050, /* 1'b0 1'b1 1'b1 1'b0 MSECALCDA */
1871         0x0070, /* TPOUTEN TPIFEN TPCLKOUTE */
1872         0x0071, /* TPSENB TPSSOPBITE */
1873         0x0073, /* TP47HINS x x CHBERINT PERMODE[1:0] PERINT[1:0] 1xx11100 */
1874         0x0075, /* x x x x x IQSWAPCTRL[2:0] xxxxx000 */
1875         0x0076, /* NBERCON NBERST NBERPOL NBERWSYN */
1876         0x0077, /* x NBERLOSTTH[2:0] NBERACQTH[3:0] x0000000 */
1877         0x0078, /* NBERPOLY[31:24] 00000000 */
1878         0x0079, /* NBERPOLY[23:16] 00000000 */
1879         0x007a, /* NBERPOLY[15:8] 00000000 */
1880         0x007b, /* NBERPOLY[7:0] 00000000 */
1881         0x007c, /* NBERPED[31:24] 00000000 */
1882         0x007d, /* NBERPED[23:16] 00000000 */
1883         0x007e, /* NBERPED[15:8] 00000000 */
1884         0x007f, /* NBERPED[7:0] 00000000 */
1885         0x0080, /* x AGCLOCK DAGCLOCK SYSLOCK x x NEVERLOCK[1:0] */
1886         0x0085, /* SPECINVST */
1887         0x0088, /* SYSLOCKTIME[15:8] */
1888         0x0089, /* SYSLOCKTIME[7:0] */
1889         0x008c, /* FECLOCKTIME[15:8] */
1890         0x008d, /* FECLOCKTIME[7:0] */
1891         0x008e, /* AGCACCOUT[15:8] */
1892         0x008f, /* AGCACCOUT[7:0] */
1893         0x0090, /* AICCREJSTATUS[3:0] AICCREJBUSY[3:0] */
1894         0x0091, /* AICCVSYNC */
1895         0x009c, /* CARRFREQOFFSET[15:8] */
1896         0x009d, /* CARRFREQOFFSET[7:0] */
1897         0x00a1, /* SAMFREQOFFSET[23:16] */
1898         0x00a2, /* SAMFREQOFFSET[15:8] */
1899         0x00a3, /* SAMFREQOFFSET[7:0] */
1900         0x00a6, /* SYNCLOCK SYNCLOCKH */
1901 #if 0 /* covered elsewhere */
1902         0x00e8, /* CONSTPWR[15:8] */
1903         0x00e9, /* CONSTPWR[7:0] */
1904         0x00ea, /* BMSE[15:8] */
1905         0x00eb, /* BMSE[7:0] */
1906         0x00ec, /* MSE[15:8] */
1907         0x00ed, /* MSE[7:0] */
1908         0x00ee, /* CONSTI[7:0] */
1909         0x00ef, /* CONSTQ[7:0] */
1910 #endif
1911         0x00f4, /* TPIFTPERRCNT[7:0] */
1912         0x00f5, /* TPCORREC */
1913         0x00f6, /* VBBER[15:8] */
1914         0x00f7, /* VBBER[7:0] */
1915         0x00f8, /* VABER[15:8] */
1916         0x00f9, /* VABER[7:0] */
1917         0x00fa, /* TPERRCNT[7:0] */
1918         0x00fb, /* NBERLOCK x x x x x x x */
1919         0x00fc, /* NBERVALUE[31:24] */
1920         0x00fd, /* NBERVALUE[23:16] */
1921         0x00fe, /* NBERVALUE[15:8] */
1922         0x00ff, /* NBERVALUE[7:0] */
1923         0x1000, /* 1'b0 WODAGCOU */
1924         0x1005, /* x x 1'b1 1'b1 x SRD_Q_QM */
1925         0x1009, /* SRDWAITTIME[7:0] (10msec) 00100011 */
1926         0x100a, /* SRDWAITTIME_CQS[7:0] (msec) 01100100 */
1927         0x101a, /* x 1'b1 1'b0 1'b0 x QMDQAMMODE[2:0] x100x010 */
1928         0x1036, /* 1'b0 1'b1 1'b0 1'b0 SAMGSEND_CQS[3:0] 01001110 */
1929         0x103c, /* SAMGSAUTOSTL_V[3:0] SAMGSAUTOEDL_V[3:0] 01000110 */
1930         0x103d, /* 1'b1 1'b1 SAMCNORMBP_V[1:0] 1'b0 1'b0 SAMMODESEL_V[1:0] 11100001 */
1931         0x103f, /* SAMZTEDSE */
1932         0x105d, /* EQSTATUSE */
1933         0x105f, /* x PMAPG2_V[2:0] x DMAPG2_V[2:0] x001x011 */
1934         0x1060, /* 1'b1 EQSTATUSE */
1935         0x1061, /* CRMAPBWSTL_V[3:0] CRMAPBWEDL_V[3:0] 00000100 */
1936         0x1065, /* 1'b0 x CRMODE_V[1:0] 1'b1 x 1'b1 x 0x111x1x */
1937         0x1066, /* 1'b0 1'b0 1'b1 1'b0 1'b1 PNBOOSTSE */
1938         0x1068, /* CREPHNGAIN2_V[3:0] CREPHNPBW_V[3:0] 10010001 */
1939         0x106e, /* x x x x x CREPHNEN_ */
1940         0x106f, /* CREPHNTH_V[7:0] 00010101 */
1941         0x1072, /* CRSWEEPN */
1942         0x1073, /* CRPGAIN_V[3:0] x x 1'b1 1'b1 1001xx11 */
1943         0x1074, /* CRPBW_V[3:0] x x 1'b1 1'b1 0001xx11 */
1944         0x1080, /* DAFTSTATUS[1:0] x x x x x x */
1945         0x1081, /* SRDSTATUS[1:0] x x x x x SRDLOCK */
1946         0x10a9, /* EQSTATUS_CQS[1:0] x x x x x x */
1947         0x10b7, /* EQSTATUS_V[1:0] x x x x x x */
1948 #if 0 /* SMART_ANT */
1949         0x1f00, /* MODEDETE */
1950         0x1f01, /* x x x x x x x SFNRST xxxxxxx0 */
1951         0x1f03, /* NUMOFANT[7:0] 10000000 */
1952         0x1f04, /* x SELMASK[6:0] x0000000 */
1953         0x1f05, /* x SETMASK[6:0] x0000000 */
1954         0x1f06, /* x TXDATA[6:0] x0000000 */
1955         0x1f07, /* x CHNUMBER[6:0] x0000000 */
1956         0x1f09, /* AGCTIME[23:16] 10011000 */
1957         0x1f0a, /* AGCTIME[15:8] 10010110 */
1958         0x1f0b, /* AGCTIME[7:0] 10000000 */
1959         0x1f0c, /* ANTTIME[31:24] 00000000 */
1960         0x1f0d, /* ANTTIME[23:16] 00000011 */
1961         0x1f0e, /* ANTTIME[15:8] 10010000 */
1962         0x1f0f, /* ANTTIME[7:0] 10010000 */
1963         0x1f11, /* SYNCTIME[23:16] 10011000 */
1964         0x1f12, /* SYNCTIME[15:8] 10010110 */
1965         0x1f13, /* SYNCTIME[7:0] 10000000 */
1966         0x1f14, /* SNRTIME[31:24] 00000001 */
1967         0x1f15, /* SNRTIME[23:16] 01111101 */
1968         0x1f16, /* SNRTIME[15:8] 01111000 */
1969         0x1f17, /* SNRTIME[7:0] 01000000 */
1970         0x1f19, /* FECTIME[23:16] 00000000 */
1971         0x1f1a, /* FECTIME[15:8] 01110010 */
1972         0x1f1b, /* FECTIME[7:0] 01110000 */
1973         0x1f1d, /* FECTHD[7:0] 00000011 */
1974         0x1f1f, /* SNRTHD[23:16] 00001000 */
1975         0x1f20, /* SNRTHD[15:8] 01111111 */
1976         0x1f21, /* SNRTHD[7:0] 10000101 */
1977         0x1f80, /* IRQFLG x x SFSDRFLG MODEBFLG SAVEFLG SCANFLG TRACKFLG */
1978         0x1f81, /* x SYNCCON SNRCON FECCON x STDBUSY SYNCRST AGCFZCO */
1979         0x1f82, /* x x x SCANOPCD[4:0] */
1980         0x1f83, /* x x x x MAINOPCD[3:0] */
1981         0x1f84, /* x x RXDATA[13:8] */
1982         0x1f85, /* RXDATA[7:0] */
1983         0x1f86, /* x x SDTDATA[13:8] */
1984         0x1f87, /* SDTDATA[7:0] */
1985         0x1f89, /* ANTSNR[23:16] */
1986         0x1f8a, /* ANTSNR[15:8] */
1987         0x1f8b, /* ANTSNR[7:0] */
1988         0x1f8c, /* x x x x ANTFEC[13:8] */
1989         0x1f8d, /* ANTFEC[7:0] */
1990         0x1f8e, /* MAXCNT[7:0] */
1991         0x1f8f, /* SCANCNT[7:0] */
1992         0x1f91, /* MAXPW[23:16] */
1993         0x1f92, /* MAXPW[15:8] */
1994         0x1f93, /* MAXPW[7:0] */
1995         0x1f95, /* CURPWMSE[23:16] */
1996         0x1f96, /* CURPWMSE[15:8] */
1997         0x1f97, /* CURPWMSE[7:0] */
1998 #endif /* SMART_ANT */
1999         0x211f, /* 1'b1 1'b1 1'b1 CIRQEN x x 1'b0 1'b0 1111xx00 */
2000         0x212a, /* EQAUTOST */
2001         0x2122, /* CHFAST[7:0] 01100000 */
2002         0x212b, /* FFFSTEP_V[3:0] x FBFSTEP_V[2:0] 0001x001 */
2003         0x212c, /* PHDEROTBWSEL[3:0] 1'b1 1'b1 1'b1 1'b0 10001110 */
2004         0x212d, /* 1'b1 1'b1 1'b1 1'b1 x x TPIFLOCKS */
2005         0x2135, /* DYNTRACKFDEQ[3:0] x 1'b0 1'b0 1'b0 1010x000 */
2006         0x2141, /* TRMODE[1:0] 1'b1 1'b1 1'b0 1'b1 1'b1 1'b1 01110111 */
2007         0x2162, /* AICCCTRLE */
2008         0x2173, /* PHNCNFCNT[7:0] 00000100 */
2009         0x2179, /* 1'b0 1'b0 1'b0 1'b1 x BADSINGLEDYNTRACKFBF[2:0] 0001x001 */
2010         0x217a, /* 1'b0 1'b0 1'b0 1'b1 x BADSLOWSINGLEDYNTRACKFBF[2:0] 0001x001 */
2011         0x217e, /* CNFCNTTPIF[7:0] 00001000 */
2012         0x217f, /* TPERRCNTTPIF[7:0] 00000001 */
2013         0x2180, /* x x x x x x FBDLYCIR[9:8] */
2014         0x2181, /* FBDLYCIR[7:0] */
2015         0x2185, /* MAXPWRMAIN[7:0] */
2016         0x2191, /* NCOMBDET x x x x x x x */
2017         0x2199, /* x MAINSTRON */
2018         0x219a, /* FFFEQSTEPOUT_V[3:0] FBFSTEPOUT_V[2:0] */
2019         0x21a1, /* x x SNRREF[5:0] */
2020         0x2845, /* 1'b0 1'b1 x x FFFSTEP_CQS[1:0] FFFCENTERTAP[1:0] 01xx1110 */
2021         0x2846, /* 1'b0 x 1'b0 1'b1 FBFSTEP_CQS[1:0] 1'b1 1'b0 0x011110 */
2022         0x2847, /* ENNOSIGDE */
2023         0x2849, /* 1'b1 1'b1 NOUSENOSI */
2024         0x284a, /* EQINITWAITTIME[7:0] 01100100 */
2025         0x3000, /* 1'b1 1'b1 1'b1 x x x 1'b0 RPTRSTM */
2026         0x3001, /* RPTRSTWAITTIME[7:0] (100msec) 00110010 */
2027         0x3031, /* FRAMELOC */
2028         0x3032, /* 1'b1 1'b0 1'b0 1'b0 x x FRAMELOCKMODE_CQS[1:0] 1000xx11 */
2029         0x30a9, /* VDLOCK_Q FRAMELOCK */
2030         0x30aa, /* MPEGLOCK */
2031 };
2032
2033 #define numDumpRegs (sizeof(regtab)/sizeof(regtab[0]))
2034 static u8 regval1[numDumpRegs] = {0, };
2035 static u8 regval2[numDumpRegs] = {0, };
2036
2037 static void lgdt3306a_DumpAllRegs(struct lgdt3306a_state *state)
2038 {
2039                 memset(regval2, 0xff, sizeof(regval2));
2040                 lgdt3306a_DumpRegs(state);
2041 }
2042
2043 static void lgdt3306a_DumpRegs(struct lgdt3306a_state *state)
2044 {
2045         int i;
2046         int sav_debug = debug;
2047
2048         if ((debug & DBG_DUMP) == 0)
2049                 return;
2050         debug &= ~DBG_REG; /* suppress DBG_REG during reg dump */
2051
2052         lg_info("\n");
2053
2054         for (i = 0; i < numDumpRegs; i++) {
2055                 lgdt3306a_read_reg(state, regtab[i], &regval1[i]);
2056                 if (regval1[i] != regval2[i]) {
2057                         lg_info(" %04X = %02X\n", regtab[i], regval1[i]);
2058                                 regval2[i] = regval1[i];
2059                 }
2060         }
2061         debug = sav_debug;
2062 }
2063 #endif /* DBG_DUMP */
2064
2065
2066
2067 static struct dvb_frontend_ops lgdt3306a_ops = {
2068         .delsys = { SYS_ATSC, SYS_DVBC_ANNEX_B },
2069         .info = {
2070                 .name = "LG Electronics LGDT3306A VSB/QAM Frontend",
2071 #if 0
2072                 .type               = FE_ATSC,
2073 #endif
2074                 .frequency_min      = 54000000,
2075                 .frequency_max      = 858000000,
2076                 .frequency_stepsize = 62500,
2077                 .caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB
2078         },
2079         .i2c_gate_ctrl        = lgdt3306a_i2c_gate_ctrl,
2080         .init                 = lgdt3306a_init,
2081         .sleep                = lgdt3306a_fe_sleep,
2082         /* if this is set, it overrides the default swzigzag */
2083         .tune                 = lgdt3306a_tune,
2084         .set_frontend         = lgdt3306a_set_parameters,
2085         .get_frontend         = lgdt3306a_get_frontend,
2086         .get_frontend_algo    = lgdt3306a_get_frontend_algo,
2087         .get_tune_settings    = lgdt3306a_get_tune_settings,
2088         .read_status          = lgdt3306a_read_status,
2089         .read_ber             = lgdt3306a_read_ber,
2090         .read_signal_strength = lgdt3306a_read_signal_strength,
2091         .read_snr             = lgdt3306a_read_snr,
2092         .read_ucblocks        = lgdt3306a_read_ucblocks,
2093         .release              = lgdt3306a_release,
2094         .ts_bus_ctrl          = lgdt3306a_ts_bus_ctrl,
2095         .search               = lgdt3306a_search,
2096 };
2097
2098 MODULE_DESCRIPTION("LG Electronics LGDT3306A ATSC/QAM-B Demodulator Driver");
2099 MODULE_AUTHOR("Fred Richter <frichter@hauppauge.com>");
2100 MODULE_LICENSE("GPL");
2101 MODULE_VERSION("0.2");
2102
2103 /*
2104  * Local variables:
2105  * c-basic-offset: 8
2106  * End:
2107  */