2 * Montage Technology M88DS3103/M88RS6000 demodulator driver
4 * Copyright (C) 2013 Antti Palosaari <crope@iki.fi>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #include "m88ds3103_priv.h"
19 static struct dvb_frontend_ops m88ds3103_ops;
21 /* write reg val table using reg addr auto increment */
22 static int m88ds3103_wr_reg_val_tab(struct m88ds3103_dev *dev,
23 const struct m88ds3103_reg_val *tab, int tab_len)
25 struct i2c_client *client = dev->client;
29 dev_dbg(&client->dev, "tab_len=%d\n", tab_len);
36 for (i = 0, j = 0; i < tab_len; i++, j++) {
39 if (i == tab_len - 1 || tab[i].reg != tab[i + 1].reg - 1 ||
40 !((j + 1) % (dev->cfg->i2c_wr_max - 1))) {
41 ret = regmap_bulk_write(dev->regmap, tab[i].reg - j, buf, j + 1);
51 dev_dbg(&client->dev, "failed=%d\n", ret);
56 * Get the demodulator AGC PWM voltage setting supplied to the tuner.
58 int m88ds3103_get_agc_pwm(struct dvb_frontend *fe, u8 *_agc_pwm)
60 struct m88ds3103_dev *dev = fe->demodulator_priv;
64 ret = regmap_read(dev->regmap, 0x3f, &tmp);
69 EXPORT_SYMBOL(m88ds3103_get_agc_pwm);
71 static int m88ds3103_read_status(struct dvb_frontend *fe,
72 enum fe_status *status)
74 struct m88ds3103_dev *dev = fe->demodulator_priv;
75 struct i2c_client *client = dev->client;
76 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
88 switch (c->delivery_system) {
90 ret = regmap_read(dev->regmap, 0xd1, &utmp);
94 if ((utmp & 0x07) == 0x07)
95 *status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
96 FE_HAS_VITERBI | FE_HAS_SYNC |
100 ret = regmap_read(dev->regmap, 0x0d, &utmp);
104 if ((utmp & 0x8f) == 0x8f)
105 *status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
106 FE_HAS_VITERBI | FE_HAS_SYNC |
110 dev_dbg(&client->dev, "invalid delivery_system\n");
115 dev->fe_status = *status;
116 dev_dbg(&client->dev, "lock=%02x status=%02x\n", utmp, *status);
119 if (dev->fe_status & FE_HAS_VITERBI) {
120 unsigned int cnr, noise, signal, noise_tot, signal_tot;
123 /* more iterations for more accurate estimation */
124 #define M88DS3103_SNR_ITERATIONS 3
126 switch (c->delivery_system) {
130 for (i = 0; i < M88DS3103_SNR_ITERATIONS; i++) {
131 ret = regmap_read(dev->regmap, 0xff, &utmp);
138 /* use of single register limits max value to 15 dB */
139 /* SNR(X) dB = 10 * ln(X) / ln(10) dB */
140 itmp = DIV_ROUND_CLOSEST(itmp, 8 * M88DS3103_SNR_ITERATIONS);
142 cnr = div_u64((u64) 10000 * intlog2(itmp), intlog2(10));
148 for (i = 0; i < M88DS3103_SNR_ITERATIONS; i++) {
149 ret = regmap_bulk_read(dev->regmap, 0x8c, buf, 3);
153 noise = buf[1] << 6; /* [13:6] */
154 noise |= buf[0] & 0x3f; /* [5:0] */
156 signal = buf[2] * buf[2];
160 signal_tot += signal;
163 noise = noise_tot / M88DS3103_SNR_ITERATIONS;
164 signal = signal_tot / M88DS3103_SNR_ITERATIONS;
166 /* SNR(X) dB = 10 * log10(X) dB */
167 if (signal > noise) {
168 itmp = signal / noise;
169 cnr = div_u64((u64) 10000 * intlog10(itmp), (1 << 24));
173 dev_dbg(&client->dev, "invalid delivery_system\n");
179 c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
180 c->cnr.stat[0].svalue = cnr;
182 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
185 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
189 if (dev->fe_status & FE_HAS_LOCK) {
190 unsigned int utmp, post_bit_error, post_bit_count;
192 switch (c->delivery_system) {
194 ret = regmap_write(dev->regmap, 0xf9, 0x04);
198 ret = regmap_read(dev->regmap, 0xf8, &utmp);
202 /* measurement ready? */
203 if (!(utmp & 0x10)) {
204 ret = regmap_bulk_read(dev->regmap, 0xf6, buf, 2);
208 post_bit_error = buf[1] << 8 | buf[0] << 0;
209 post_bit_count = 0x800000;
210 dev->post_bit_error += post_bit_error;
211 dev->post_bit_count += post_bit_count;
212 dev->dvbv3_ber = post_bit_error;
214 /* restart measurement */
216 ret = regmap_write(dev->regmap, 0xf8, utmp);
222 ret = regmap_bulk_read(dev->regmap, 0xd5, buf, 3);
226 utmp = buf[2] << 16 | buf[1] << 8 | buf[0] << 0;
230 ret = regmap_bulk_read(dev->regmap, 0xf7, buf, 2);
234 post_bit_error = buf[1] << 8 | buf[0] << 0;
235 post_bit_count = 32 * utmp; /* TODO: FEC */
236 dev->post_bit_error += post_bit_error;
237 dev->post_bit_count += post_bit_count;
238 dev->dvbv3_ber = post_bit_error;
240 /* restart measurement */
241 ret = regmap_write(dev->regmap, 0xd1, 0x01);
245 ret = regmap_write(dev->regmap, 0xf9, 0x01);
249 ret = regmap_write(dev->regmap, 0xf9, 0x00);
253 ret = regmap_write(dev->regmap, 0xd1, 0x00);
259 dev_dbg(&client->dev, "invalid delivery_system\n");
264 c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
265 c->post_bit_error.stat[0].uvalue = dev->post_bit_error;
266 c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
267 c->post_bit_count.stat[0].uvalue = dev->post_bit_count;
269 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
270 c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
275 dev_dbg(&client->dev, "failed=%d\n", ret);
279 static int m88ds3103_set_frontend(struct dvb_frontend *fe)
281 struct m88ds3103_dev *dev = fe->demodulator_priv;
282 struct i2c_client *client = dev->client;
283 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
285 const struct m88ds3103_reg_val *init;
286 u8 u8tmp, u8tmp1 = 0, u8tmp2 = 0; /* silence compiler warning */
288 u16 u16tmp, divide_ratio = 0;
289 u32 tuner_frequency, target_mclk;
292 dev_dbg(&client->dev,
293 "delivery_system=%d modulation=%d frequency=%u symbol_rate=%d inversion=%d pilot=%d rolloff=%d\n",
294 c->delivery_system, c->modulation, c->frequency, c->symbol_rate,
295 c->inversion, c->pilot, c->rolloff);
303 ret = regmap_write(dev->regmap, 0x07, 0x80);
307 ret = regmap_write(dev->regmap, 0x07, 0x00);
311 /* Disable demod clock path */
312 if (dev->chip_id == M88RS6000_CHIP_ID) {
313 ret = regmap_write(dev->regmap, 0x06, 0xe0);
319 if (fe->ops.tuner_ops.set_params) {
320 ret = fe->ops.tuner_ops.set_params(fe);
325 if (fe->ops.tuner_ops.get_frequency) {
326 ret = fe->ops.tuner_ops.get_frequency(fe, &tuner_frequency);
331 * Use nominal target frequency as tuner driver does not provide
332 * actual frequency used. Carrier offset calculation is not
335 tuner_frequency = c->frequency;
338 /* select M88RS6000 demod main mclk and ts mclk from tuner die. */
339 if (dev->chip_id == M88RS6000_CHIP_ID) {
340 if (c->symbol_rate > 45010000)
341 dev->mclk_khz = 110250;
343 dev->mclk_khz = 96000;
345 if (c->delivery_system == SYS_DVBS)
348 target_mclk = 144000;
350 /* Enable demod clock path */
351 ret = regmap_write(dev->regmap, 0x06, 0x00);
354 usleep_range(10000, 20000);
356 /* set M88DS3103 mclk and ts mclk. */
357 dev->mclk_khz = 96000;
359 switch (dev->cfg->ts_mode) {
360 case M88DS3103_TS_SERIAL:
361 case M88DS3103_TS_SERIAL_D7:
362 target_mclk = dev->cfg->ts_clk;
364 case M88DS3103_TS_PARALLEL:
365 case M88DS3103_TS_CI:
366 if (c->delivery_system == SYS_DVBS)
369 if (c->symbol_rate < 18000000)
371 else if (c->symbol_rate < 28000000)
372 target_mclk = 144000;
374 target_mclk = 192000;
378 dev_dbg(&client->dev, "invalid ts_mode\n");
383 switch (target_mclk) {
385 u8tmp1 = 0x02; /* 0b10 */
386 u8tmp2 = 0x01; /* 0b01 */
389 u8tmp1 = 0x00; /* 0b00 */
390 u8tmp2 = 0x01; /* 0b01 */
393 u8tmp1 = 0x03; /* 0b11 */
394 u8tmp2 = 0x00; /* 0b00 */
397 ret = regmap_update_bits(dev->regmap, 0x22, 0xc0, u8tmp1 << 6);
400 ret = regmap_update_bits(dev->regmap, 0x24, 0xc0, u8tmp2 << 6);
405 ret = regmap_write(dev->regmap, 0xb2, 0x01);
409 ret = regmap_write(dev->regmap, 0x00, 0x01);
413 switch (c->delivery_system) {
415 if (dev->chip_id == M88RS6000_CHIP_ID) {
416 len = ARRAY_SIZE(m88rs6000_dvbs_init_reg_vals);
417 init = m88rs6000_dvbs_init_reg_vals;
419 len = ARRAY_SIZE(m88ds3103_dvbs_init_reg_vals);
420 init = m88ds3103_dvbs_init_reg_vals;
424 if (dev->chip_id == M88RS6000_CHIP_ID) {
425 len = ARRAY_SIZE(m88rs6000_dvbs2_init_reg_vals);
426 init = m88rs6000_dvbs2_init_reg_vals;
428 len = ARRAY_SIZE(m88ds3103_dvbs2_init_reg_vals);
429 init = m88ds3103_dvbs2_init_reg_vals;
433 dev_dbg(&client->dev, "invalid delivery_system\n");
438 /* program init table */
439 if (c->delivery_system != dev->delivery_system) {
440 ret = m88ds3103_wr_reg_val_tab(dev, init, len);
445 if (dev->chip_id == M88RS6000_CHIP_ID) {
446 if ((c->delivery_system == SYS_DVBS2)
447 && ((c->symbol_rate / 1000) <= 5000)) {
448 ret = regmap_write(dev->regmap, 0xc0, 0x04);
454 ret = regmap_bulk_write(dev->regmap, 0x8a, buf, 3);
458 ret = regmap_update_bits(dev->regmap, 0x9d, 0x08, 0x08);
461 ret = regmap_write(dev->regmap, 0xf1, 0x01);
464 ret = regmap_update_bits(dev->regmap, 0x30, 0x80, 0x80);
469 switch (dev->cfg->ts_mode) {
470 case M88DS3103_TS_SERIAL:
474 case M88DS3103_TS_SERIAL_D7:
478 case M88DS3103_TS_PARALLEL:
481 case M88DS3103_TS_CI:
485 dev_dbg(&client->dev, "invalid ts_mode\n");
490 if (dev->cfg->ts_clk_pol)
494 ret = regmap_write(dev->regmap, 0xfd, u8tmp);
498 switch (dev->cfg->ts_mode) {
499 case M88DS3103_TS_SERIAL:
500 case M88DS3103_TS_SERIAL_D7:
501 ret = regmap_update_bits(dev->regmap, 0x29, 0x20, u8tmp1);
508 if (dev->cfg->ts_clk) {
509 divide_ratio = DIV_ROUND_UP(target_mclk, dev->cfg->ts_clk);
510 u8tmp1 = divide_ratio / 2;
511 u8tmp2 = DIV_ROUND_UP(divide_ratio, 2);
515 dev_dbg(&client->dev,
516 "target_mclk=%d ts_clk=%d divide_ratio=%d\n",
517 target_mclk, dev->cfg->ts_clk, divide_ratio);
521 /* u8tmp1[5:2] => fe[3:0], u8tmp1[1:0] => ea[7:6] */
523 /* u8tmp2[5:0] => ea[5:0] */
526 ret = regmap_bulk_read(dev->regmap, 0xfe, &u8tmp, 1);
530 u8tmp = ((u8tmp & 0xf0) << 0) | u8tmp1 >> 2;
531 ret = regmap_write(dev->regmap, 0xfe, u8tmp);
535 u8tmp = ((u8tmp1 & 0x03) << 6) | u8tmp2 >> 0;
536 ret = regmap_write(dev->regmap, 0xea, u8tmp);
540 if (c->symbol_rate <= 3000000)
542 else if (c->symbol_rate <= 10000000)
547 ret = regmap_write(dev->regmap, 0xc3, 0x08);
551 ret = regmap_write(dev->regmap, 0xc8, u8tmp);
555 ret = regmap_write(dev->regmap, 0xc4, 0x08);
559 ret = regmap_write(dev->regmap, 0xc7, 0x00);
563 u16tmp = DIV_ROUND_CLOSEST((c->symbol_rate / 1000) << 15, dev->mclk_khz / 2);
564 buf[0] = (u16tmp >> 0) & 0xff;
565 buf[1] = (u16tmp >> 8) & 0xff;
566 ret = regmap_bulk_write(dev->regmap, 0x61, buf, 2);
570 ret = regmap_update_bits(dev->regmap, 0x4d, 0x02, dev->cfg->spec_inv << 1);
574 ret = regmap_update_bits(dev->regmap, 0x30, 0x10, dev->cfg->agc_inv << 4);
578 ret = regmap_write(dev->regmap, 0x33, dev->cfg->agc);
582 dev_dbg(&client->dev, "carrier offset=%d\n",
583 (tuner_frequency - c->frequency));
585 s32tmp = 0x10000 * (tuner_frequency - c->frequency);
586 s32tmp = DIV_ROUND_CLOSEST(s32tmp, dev->mclk_khz);
590 buf[0] = (s32tmp >> 0) & 0xff;
591 buf[1] = (s32tmp >> 8) & 0xff;
592 ret = regmap_bulk_write(dev->regmap, 0x5e, buf, 2);
596 ret = regmap_write(dev->regmap, 0x00, 0x00);
600 ret = regmap_write(dev->regmap, 0xb2, 0x00);
604 dev->delivery_system = c->delivery_system;
608 dev_dbg(&client->dev, "failed=%d\n", ret);
612 static int m88ds3103_init(struct dvb_frontend *fe)
614 struct m88ds3103_dev *dev = fe->demodulator_priv;
615 struct i2c_client *client = dev->client;
616 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
617 int ret, len, remaining;
619 const struct firmware *fw = NULL;
622 dev_dbg(&client->dev, "\n");
624 /* set cold state by default */
627 /* wake up device from sleep */
628 ret = regmap_update_bits(dev->regmap, 0x08, 0x01, 0x01);
631 ret = regmap_update_bits(dev->regmap, 0x04, 0x01, 0x00);
634 ret = regmap_update_bits(dev->regmap, 0x23, 0x10, 0x00);
638 /* firmware status */
639 ret = regmap_read(dev->regmap, 0xb9, &utmp);
643 dev_dbg(&client->dev, "firmware=%02x\n", utmp);
646 goto skip_fw_download;
648 /* global reset, global diseqc reset, golbal fec reset */
649 ret = regmap_write(dev->regmap, 0x07, 0xe0);
652 ret = regmap_write(dev->regmap, 0x07, 0x00);
656 /* cold state - try to download firmware */
657 dev_info(&client->dev, "found a '%s' in cold state\n",
658 m88ds3103_ops.info.name);
660 if (dev->chip_id == M88RS6000_CHIP_ID)
661 fw_file = M88RS6000_FIRMWARE;
663 fw_file = M88DS3103_FIRMWARE;
664 /* request the firmware, this will block and timeout */
665 ret = request_firmware(&fw, fw_file, &client->dev);
667 dev_err(&client->dev, "firmare file '%s' not found\n", fw_file);
671 dev_info(&client->dev, "downloading firmware from file '%s'\n",
674 ret = regmap_write(dev->regmap, 0xb2, 0x01);
676 goto error_fw_release;
678 for (remaining = fw->size; remaining > 0;
679 remaining -= (dev->cfg->i2c_wr_max - 1)) {
681 if (len > (dev->cfg->i2c_wr_max - 1))
682 len = (dev->cfg->i2c_wr_max - 1);
684 ret = regmap_bulk_write(dev->regmap, 0xb0,
685 &fw->data[fw->size - remaining], len);
687 dev_err(&client->dev, "firmware download failed=%d\n",
689 goto error_fw_release;
693 ret = regmap_write(dev->regmap, 0xb2, 0x00);
695 goto error_fw_release;
697 release_firmware(fw);
700 ret = regmap_read(dev->regmap, 0xb9, &utmp);
705 dev_info(&client->dev, "firmware did not run\n");
710 dev_info(&client->dev, "found a '%s' in warm state\n",
711 m88ds3103_ops.info.name);
712 dev_info(&client->dev, "firmware version: %X.%X\n",
713 (utmp >> 4) & 0xf, (utmp >> 0 & 0xf));
719 /* init stats here in order signal app which stats are supported */
721 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
722 c->post_bit_error.len = 1;
723 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
724 c->post_bit_count.len = 1;
725 c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
729 release_firmware(fw);
731 dev_dbg(&client->dev, "failed=%d\n", ret);
735 static int m88ds3103_sleep(struct dvb_frontend *fe)
737 struct m88ds3103_dev *dev = fe->demodulator_priv;
738 struct i2c_client *client = dev->client;
742 dev_dbg(&client->dev, "\n");
745 dev->delivery_system = SYS_UNDEFINED;
748 if (dev->chip_id == M88RS6000_CHIP_ID)
752 ret = regmap_update_bits(dev->regmap, utmp, 0x01, 0x00);
757 ret = regmap_update_bits(dev->regmap, 0x08, 0x01, 0x00);
760 ret = regmap_update_bits(dev->regmap, 0x04, 0x01, 0x01);
763 ret = regmap_update_bits(dev->regmap, 0x23, 0x10, 0x10);
769 dev_dbg(&client->dev, "failed=%d\n", ret);
773 static int m88ds3103_get_frontend(struct dvb_frontend *fe)
775 struct m88ds3103_dev *dev = fe->demodulator_priv;
776 struct i2c_client *client = dev->client;
777 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
781 dev_dbg(&client->dev, "\n");
783 if (!dev->warm || !(dev->fe_status & FE_HAS_LOCK)) {
788 switch (c->delivery_system) {
790 ret = regmap_bulk_read(dev->regmap, 0xe0, &buf[0], 1);
794 ret = regmap_bulk_read(dev->regmap, 0xe6, &buf[1], 1);
798 switch ((buf[0] >> 2) & 0x01) {
800 c->inversion = INVERSION_OFF;
803 c->inversion = INVERSION_ON;
807 switch ((buf[1] >> 5) & 0x07) {
809 c->fec_inner = FEC_7_8;
812 c->fec_inner = FEC_5_6;
815 c->fec_inner = FEC_3_4;
818 c->fec_inner = FEC_2_3;
821 c->fec_inner = FEC_1_2;
824 dev_dbg(&client->dev, "invalid fec_inner\n");
827 c->modulation = QPSK;
831 ret = regmap_bulk_read(dev->regmap, 0x7e, &buf[0], 1);
835 ret = regmap_bulk_read(dev->regmap, 0x89, &buf[1], 1);
839 ret = regmap_bulk_read(dev->regmap, 0xf2, &buf[2], 1);
843 switch ((buf[0] >> 0) & 0x0f) {
845 c->fec_inner = FEC_2_5;
848 c->fec_inner = FEC_1_2;
851 c->fec_inner = FEC_3_5;
854 c->fec_inner = FEC_2_3;
857 c->fec_inner = FEC_3_4;
860 c->fec_inner = FEC_4_5;
863 c->fec_inner = FEC_5_6;
866 c->fec_inner = FEC_8_9;
869 c->fec_inner = FEC_9_10;
872 dev_dbg(&client->dev, "invalid fec_inner\n");
875 switch ((buf[0] >> 5) & 0x01) {
877 c->pilot = PILOT_OFF;
884 switch ((buf[0] >> 6) & 0x07) {
886 c->modulation = QPSK;
889 c->modulation = PSK_8;
892 c->modulation = APSK_16;
895 c->modulation = APSK_32;
898 dev_dbg(&client->dev, "invalid modulation\n");
901 switch ((buf[1] >> 7) & 0x01) {
903 c->inversion = INVERSION_OFF;
906 c->inversion = INVERSION_ON;
910 switch ((buf[2] >> 0) & 0x03) {
912 c->rolloff = ROLLOFF_35;
915 c->rolloff = ROLLOFF_25;
918 c->rolloff = ROLLOFF_20;
921 dev_dbg(&client->dev, "invalid rolloff\n");
925 dev_dbg(&client->dev, "invalid delivery_system\n");
930 ret = regmap_bulk_read(dev->regmap, 0x6d, buf, 2);
934 c->symbol_rate = 1ull * ((buf[1] << 8) | (buf[0] << 0)) *
935 dev->mclk_khz * 1000 / 0x10000;
939 dev_dbg(&client->dev, "failed=%d\n", ret);
943 static int m88ds3103_read_snr(struct dvb_frontend *fe, u16 *snr)
945 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
947 if (c->cnr.stat[0].scale == FE_SCALE_DECIBEL)
948 *snr = div_s64(c->cnr.stat[0].svalue, 100);
955 static int m88ds3103_read_ber(struct dvb_frontend *fe, u32 *ber)
957 struct m88ds3103_dev *dev = fe->demodulator_priv;
959 *ber = dev->dvbv3_ber;
964 static int m88ds3103_set_tone(struct dvb_frontend *fe,
965 enum fe_sec_tone_mode fe_sec_tone_mode)
967 struct m88ds3103_dev *dev = fe->demodulator_priv;
968 struct i2c_client *client = dev->client;
970 unsigned int utmp, tone, reg_a1_mask;
972 dev_dbg(&client->dev, "fe_sec_tone_mode=%d\n", fe_sec_tone_mode);
979 switch (fe_sec_tone_mode) {
989 dev_dbg(&client->dev, "invalid fe_sec_tone_mode\n");
994 utmp = tone << 7 | dev->cfg->envelope_mode << 5;
995 ret = regmap_update_bits(dev->regmap, 0xa2, 0xe0, utmp);
1000 ret = regmap_update_bits(dev->regmap, 0xa1, reg_a1_mask, utmp);
1006 dev_dbg(&client->dev, "failed=%d\n", ret);
1010 static int m88ds3103_set_voltage(struct dvb_frontend *fe,
1011 enum fe_sec_voltage fe_sec_voltage)
1013 struct m88ds3103_dev *dev = fe->demodulator_priv;
1014 struct i2c_client *client = dev->client;
1017 bool voltage_sel, voltage_dis;
1019 dev_dbg(&client->dev, "fe_sec_voltage=%d\n", fe_sec_voltage);
1026 switch (fe_sec_voltage) {
1027 case SEC_VOLTAGE_18:
1029 voltage_dis = false;
1031 case SEC_VOLTAGE_13:
1032 voltage_sel = false;
1033 voltage_dis = false;
1035 case SEC_VOLTAGE_OFF:
1036 voltage_sel = false;
1040 dev_dbg(&client->dev, "invalid fe_sec_voltage\n");
1045 /* output pin polarity */
1046 voltage_sel ^= dev->cfg->lnb_hv_pol;
1047 voltage_dis ^= dev->cfg->lnb_en_pol;
1049 utmp = voltage_dis << 1 | voltage_sel << 0;
1050 ret = regmap_update_bits(dev->regmap, 0xa2, 0x03, utmp);
1056 dev_dbg(&client->dev, "failed=%d\n", ret);
1060 static int m88ds3103_diseqc_send_master_cmd(struct dvb_frontend *fe,
1061 struct dvb_diseqc_master_cmd *diseqc_cmd)
1063 struct m88ds3103_dev *dev = fe->demodulator_priv;
1064 struct i2c_client *client = dev->client;
1067 unsigned long timeout;
1069 dev_dbg(&client->dev, "msg=%*ph\n",
1070 diseqc_cmd->msg_len, diseqc_cmd->msg);
1077 if (diseqc_cmd->msg_len < 3 || diseqc_cmd->msg_len > 6) {
1082 utmp = dev->cfg->envelope_mode << 5;
1083 ret = regmap_update_bits(dev->regmap, 0xa2, 0xe0, utmp);
1087 ret = regmap_bulk_write(dev->regmap, 0xa3, diseqc_cmd->msg,
1088 diseqc_cmd->msg_len);
1092 ret = regmap_write(dev->regmap, 0xa1,
1093 (diseqc_cmd->msg_len - 1) << 3 | 0x07);
1097 /* wait DiSEqC TX ready */
1098 #define SEND_MASTER_CMD_TIMEOUT 120
1099 timeout = jiffies + msecs_to_jiffies(SEND_MASTER_CMD_TIMEOUT);
1101 /* DiSEqC message typical period is 54 ms */
1102 usleep_range(50000, 54000);
1104 for (utmp = 1; !time_after(jiffies, timeout) && utmp;) {
1105 ret = regmap_read(dev->regmap, 0xa1, &utmp);
1108 utmp = (utmp >> 6) & 0x1;
1112 dev_dbg(&client->dev, "diseqc tx took %u ms\n",
1113 jiffies_to_msecs(jiffies) -
1114 (jiffies_to_msecs(timeout) - SEND_MASTER_CMD_TIMEOUT));
1116 dev_dbg(&client->dev, "diseqc tx timeout\n");
1118 ret = regmap_update_bits(dev->regmap, 0xa1, 0xc0, 0x40);
1123 ret = regmap_update_bits(dev->regmap, 0xa2, 0xc0, 0x80);
1134 dev_dbg(&client->dev, "failed=%d\n", ret);
1138 static int m88ds3103_diseqc_send_burst(struct dvb_frontend *fe,
1139 enum fe_sec_mini_cmd fe_sec_mini_cmd)
1141 struct m88ds3103_dev *dev = fe->demodulator_priv;
1142 struct i2c_client *client = dev->client;
1144 unsigned int utmp, burst;
1145 unsigned long timeout;
1147 dev_dbg(&client->dev, "fe_sec_mini_cmd=%d\n", fe_sec_mini_cmd);
1154 utmp = dev->cfg->envelope_mode << 5;
1155 ret = regmap_update_bits(dev->regmap, 0xa2, 0xe0, utmp);
1159 switch (fe_sec_mini_cmd) {
1167 dev_dbg(&client->dev, "invalid fe_sec_mini_cmd\n");
1172 ret = regmap_write(dev->regmap, 0xa1, burst);
1176 /* wait DiSEqC TX ready */
1177 #define SEND_BURST_TIMEOUT 40
1178 timeout = jiffies + msecs_to_jiffies(SEND_BURST_TIMEOUT);
1180 /* DiSEqC ToneBurst period is 12.5 ms */
1181 usleep_range(8500, 12500);
1183 for (utmp = 1; !time_after(jiffies, timeout) && utmp;) {
1184 ret = regmap_read(dev->regmap, 0xa1, &utmp);
1187 utmp = (utmp >> 6) & 0x1;
1191 dev_dbg(&client->dev, "diseqc tx took %u ms\n",
1192 jiffies_to_msecs(jiffies) -
1193 (jiffies_to_msecs(timeout) - SEND_BURST_TIMEOUT));
1195 dev_dbg(&client->dev, "diseqc tx timeout\n");
1197 ret = regmap_update_bits(dev->regmap, 0xa1, 0xc0, 0x40);
1202 ret = regmap_update_bits(dev->regmap, 0xa2, 0xc0, 0x80);
1213 dev_dbg(&client->dev, "failed=%d\n", ret);
1217 static int m88ds3103_get_tune_settings(struct dvb_frontend *fe,
1218 struct dvb_frontend_tune_settings *s)
1220 s->min_delay_ms = 3000;
1225 static void m88ds3103_release(struct dvb_frontend *fe)
1227 struct m88ds3103_dev *dev = fe->demodulator_priv;
1228 struct i2c_client *client = dev->client;
1230 i2c_unregister_device(client);
1233 static int m88ds3103_select(struct i2c_adapter *adap, void *mux_priv, u32 chan)
1235 struct m88ds3103_dev *dev = mux_priv;
1236 struct i2c_client *client = dev->client;
1238 struct i2c_msg msg = {
1239 .addr = client->addr,
1245 /* Open tuner I2C repeater for 1 xfer, closes automatically */
1246 ret = __i2c_transfer(client->adapter, &msg, 1);
1248 dev_warn(&client->dev, "i2c wr failed=%d\n", ret);
1258 * XXX: That is wrapper to m88ds3103_probe() via driver core in order to provide
1259 * proper I2C client for legacy media attach binding.
1260 * New users must use I2C client binding directly!
1262 struct dvb_frontend *m88ds3103_attach(const struct m88ds3103_config *cfg,
1263 struct i2c_adapter *i2c, struct i2c_adapter **tuner_i2c_adapter)
1265 struct i2c_client *client;
1266 struct i2c_board_info board_info;
1267 struct m88ds3103_platform_data pdata;
1269 pdata.clk = cfg->clock;
1270 pdata.i2c_wr_max = cfg->i2c_wr_max;
1271 pdata.ts_mode = cfg->ts_mode;
1272 pdata.ts_clk = cfg->ts_clk;
1273 pdata.ts_clk_pol = cfg->ts_clk_pol;
1274 pdata.spec_inv = cfg->spec_inv;
1275 pdata.agc = cfg->agc;
1276 pdata.agc_inv = cfg->agc_inv;
1277 pdata.clk_out = cfg->clock_out;
1278 pdata.envelope_mode = cfg->envelope_mode;
1279 pdata.lnb_hv_pol = cfg->lnb_hv_pol;
1280 pdata.lnb_en_pol = cfg->lnb_en_pol;
1281 pdata.attach_in_use = true;
1283 memset(&board_info, 0, sizeof(board_info));
1284 strlcpy(board_info.type, "m88ds3103", I2C_NAME_SIZE);
1285 board_info.addr = cfg->i2c_addr;
1286 board_info.platform_data = &pdata;
1287 client = i2c_new_device(i2c, &board_info);
1288 if (!client || !client->dev.driver)
1291 *tuner_i2c_adapter = pdata.get_i2c_adapter(client);
1292 return pdata.get_dvb_frontend(client);
1294 EXPORT_SYMBOL(m88ds3103_attach);
1296 static struct dvb_frontend_ops m88ds3103_ops = {
1297 .delsys = {SYS_DVBS, SYS_DVBS2},
1299 .name = "Montage Technology M88DS3103",
1300 .frequency_min = 950000,
1301 .frequency_max = 2150000,
1302 .frequency_tolerance = 5000,
1303 .symbol_rate_min = 1000000,
1304 .symbol_rate_max = 45000000,
1305 .caps = FE_CAN_INVERSION_AUTO |
1317 FE_CAN_2G_MODULATION
1320 .release = m88ds3103_release,
1322 .get_tune_settings = m88ds3103_get_tune_settings,
1324 .init = m88ds3103_init,
1325 .sleep = m88ds3103_sleep,
1327 .set_frontend = m88ds3103_set_frontend,
1328 .get_frontend = m88ds3103_get_frontend,
1330 .read_status = m88ds3103_read_status,
1331 .read_snr = m88ds3103_read_snr,
1332 .read_ber = m88ds3103_read_ber,
1334 .diseqc_send_master_cmd = m88ds3103_diseqc_send_master_cmd,
1335 .diseqc_send_burst = m88ds3103_diseqc_send_burst,
1337 .set_tone = m88ds3103_set_tone,
1338 .set_voltage = m88ds3103_set_voltage,
1341 static struct dvb_frontend *m88ds3103_get_dvb_frontend(struct i2c_client *client)
1343 struct m88ds3103_dev *dev = i2c_get_clientdata(client);
1345 dev_dbg(&client->dev, "\n");
1350 static struct i2c_adapter *m88ds3103_get_i2c_adapter(struct i2c_client *client)
1352 struct m88ds3103_dev *dev = i2c_get_clientdata(client);
1354 dev_dbg(&client->dev, "\n");
1356 return dev->i2c_adapter;
1359 static int m88ds3103_probe(struct i2c_client *client,
1360 const struct i2c_device_id *id)
1362 struct m88ds3103_dev *dev;
1363 struct m88ds3103_platform_data *pdata = client->dev.platform_data;
1367 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1373 dev->client = client;
1374 dev->config.clock = pdata->clk;
1375 dev->config.i2c_wr_max = pdata->i2c_wr_max;
1376 dev->config.ts_mode = pdata->ts_mode;
1377 dev->config.ts_clk = pdata->ts_clk;
1378 dev->config.ts_clk_pol = pdata->ts_clk_pol;
1379 dev->config.spec_inv = pdata->spec_inv;
1380 dev->config.agc_inv = pdata->agc_inv;
1381 dev->config.clock_out = pdata->clk_out;
1382 dev->config.envelope_mode = pdata->envelope_mode;
1383 dev->config.agc = pdata->agc;
1384 dev->config.lnb_hv_pol = pdata->lnb_hv_pol;
1385 dev->config.lnb_en_pol = pdata->lnb_en_pol;
1386 dev->cfg = &dev->config;
1388 dev->regmap_config.reg_bits = 8,
1389 dev->regmap_config.val_bits = 8,
1390 dev->regmap_config.lock_arg = dev,
1391 dev->regmap = devm_regmap_init_i2c(client, &dev->regmap_config);
1392 if (IS_ERR(dev->regmap)) {
1393 ret = PTR_ERR(dev->regmap);
1397 /* 0x00: chip id[6:0], 0x01: chip ver[7:0], 0x02: chip ver[15:8] */
1398 ret = regmap_read(dev->regmap, 0x00, &utmp);
1402 dev->chip_id = utmp >> 1;
1403 dev_dbg(&client->dev, "chip_id=%02x\n", dev->chip_id);
1405 switch (dev->chip_id) {
1406 case M88RS6000_CHIP_ID:
1407 case M88DS3103_CHIP_ID:
1413 switch (dev->cfg->clock_out) {
1414 case M88DS3103_CLOCK_OUT_DISABLED:
1417 case M88DS3103_CLOCK_OUT_ENABLED:
1420 case M88DS3103_CLOCK_OUT_ENABLED_DIV2:
1428 /* 0x29 register is defined differently for m88rs6000. */
1429 /* set internal tuner address to 0x21 */
1430 if (dev->chip_id == M88RS6000_CHIP_ID)
1433 ret = regmap_write(dev->regmap, 0x29, utmp);
1438 ret = regmap_update_bits(dev->regmap, 0x08, 0x01, 0x00);
1441 ret = regmap_update_bits(dev->regmap, 0x04, 0x01, 0x01);
1444 ret = regmap_update_bits(dev->regmap, 0x23, 0x10, 0x10);
1448 /* create mux i2c adapter for tuner */
1449 dev->i2c_adapter = i2c_add_mux_adapter(client->adapter, &client->dev,
1450 dev, 0, 0, 0, m88ds3103_select,
1452 if (dev->i2c_adapter == NULL) {
1457 /* create dvb_frontend */
1458 memcpy(&dev->fe.ops, &m88ds3103_ops, sizeof(struct dvb_frontend_ops));
1459 if (dev->chip_id == M88RS6000_CHIP_ID)
1460 strncpy(dev->fe.ops.info.name, "Montage Technology M88RS6000",
1461 sizeof(dev->fe.ops.info.name));
1462 if (!pdata->attach_in_use)
1463 dev->fe.ops.release = NULL;
1464 dev->fe.demodulator_priv = dev;
1465 i2c_set_clientdata(client, dev);
1467 /* setup callbacks */
1468 pdata->get_dvb_frontend = m88ds3103_get_dvb_frontend;
1469 pdata->get_i2c_adapter = m88ds3103_get_i2c_adapter;
1474 dev_dbg(&client->dev, "failed=%d\n", ret);
1478 static int m88ds3103_remove(struct i2c_client *client)
1480 struct m88ds3103_dev *dev = i2c_get_clientdata(client);
1482 dev_dbg(&client->dev, "\n");
1484 i2c_del_mux_adapter(dev->i2c_adapter);
1490 static const struct i2c_device_id m88ds3103_id_table[] = {
1494 MODULE_DEVICE_TABLE(i2c, m88ds3103_id_table);
1496 static struct i2c_driver m88ds3103_driver = {
1498 .name = "m88ds3103",
1499 .suppress_bind_attrs = true,
1501 .probe = m88ds3103_probe,
1502 .remove = m88ds3103_remove,
1503 .id_table = m88ds3103_id_table,
1506 module_i2c_driver(m88ds3103_driver);
1508 MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>");
1509 MODULE_DESCRIPTION("Montage Technology M88DS3103 DVB-S/S2 demodulator driver");
1510 MODULE_LICENSE("GPL");
1511 MODULE_FIRMWARE(M88DS3103_FIRMWARE);
1512 MODULE_FIRMWARE(M88RS6000_FIRMWARE);