drivers/media/dvb-frontends/m88rs2000.c

   1 /*
   2         Driver for M88RS2000 demodulator and tuner
   3
   4         Copyright (C) 2012 Malcolm Priestley (tvboxspy@gmail.com)
   5         Beta Driver
   6
   7         Include various calculation code from DS3000 driver.
   8         Copyright (C) 2009 Konstantin Dimitrov.
   9
  10         This program is free software; you can redistribute it and/or modify
  11         it under the terms of the GNU General Public License as published by
  12         the Free Software Foundation; either version 2 of the License, or
  13         (at your option) any later version.
  14
  15         This program is distributed in the hope that it will be useful,
  16         but WITHOUT ANY WARRANTY; without even the implied warranty of
  17         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18         GNU General Public License for more details.
  19
  20         You should have received a copy of the GNU General Public License
  21         along with this program; if not, write to the Free Software
  22         Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  23
  24 */
  25 #include <linux/init.h>
  26 #include <linux/module.h>
  27 #include <linux/device.h>
  28 #include <linux/jiffies.h>
  29 #include <linux/string.h>
  30 #include <linux/slab.h>
  31 #include <linux/types.h>
  32
  33
  34 #include "dvb_frontend.h"
  35 #include "m88rs2000.h"
  36
  37 struct m88rs2000_state {
  38         struct i2c_adapter *i2c;
  39         const struct m88rs2000_config *config;
  40         struct dvb_frontend frontend;
  41         u8 no_lock_count;
  42         u32 tuner_frequency;
  43         u32 symbol_rate;
  44         fe_code_rate_t fec_inner;
  45         u8 tuner_level;
  46         int errmode;
  47 };
  48
  49 static int m88rs2000_debug;
  50
  51 module_param_named(debug, m88rs2000_debug, int, 0644);
  52 MODULE_PARM_DESC(debug, "set debugging level (1=info (or-able)).");
  53
  54 #define dprintk(level, args...) do { \
  55         if (level & m88rs2000_debug) \
  56                 printk(KERN_DEBUG "m88rs2000-fe: " args); \
  57 } while (0)
  58
  59 #define deb_info(args...)  dprintk(0x01, args)
  60 #define info(format, arg...) \
  61         printk(KERN_INFO "m88rs2000-fe: " format "\n" , ## arg)
  62
  63 static int m88rs2000_writereg(struct m88rs2000_state *state,
  64         u8 reg, u8 data)
  65 {
  66         int ret;
  67         u8 buf[] = { reg, data };
  68         struct i2c_msg msg = {
  69                 .addr = state->config->demod_addr,
  70                 .flags = 0,
  71                 .buf = buf,
  72                 .len = 2
  73         };
  74
  75         ret = i2c_transfer(state->i2c, &msg, 1);
  76
  77         if (ret != 1)
  78                 deb_info("%s: writereg error (reg == 0x%02x, val == 0x%02x, "
  79                         "ret == %i)\n", __func__, reg, data, ret);
  80
  81         return (ret != 1) ? -EREMOTEIO : 0;
  82 }
  83
  84 static u8 m88rs2000_readreg(struct m88rs2000_state *state, u8 reg)
  85 {
  86         int ret;
  87         u8 b0[] = { reg };
  88         u8 b1[] = { 0 };
  89
  90         struct i2c_msg msg[] = {
  91                 {
  92                         .addr = state->config->demod_addr,
  93                         .flags = 0,
  94                         .buf = b0,
  95                         .len = 1
  96                 }, {
  97                         .addr = state->config->demod_addr,
  98                         .flags = I2C_M_RD,
  99                         .buf = b1,
 100                         .len = 1
 101                 }
 102         };
 103
 104         ret = i2c_transfer(state->i2c, msg, 2);
 105
 106         if (ret != 2)
 107                 deb_info("%s: readreg error (reg == 0x%02x, ret == %i)\n",
 108                                 __func__, reg, ret);
 109
 110         return b1[0];
 111 }
 112
 113 static u32 m88rs2000_get_mclk(struct dvb_frontend *fe)
 114 {
 115         struct m88rs2000_state *state = fe->demodulator_priv;
 116         u32 mclk;
 117         u8 reg;
 118         /* Must not be 0x00 or 0xff */
 119         reg = m88rs2000_readreg(state, 0x86);
 120         if (!reg || reg == 0xff)
 121                 return 0;
 122
 123         reg /= 2;
 124         reg += 1;
 125
 126         mclk = (u32)(reg * RS2000_FE_CRYSTAL_KHZ + 28 / 2) / 28;
 127
 128         return mclk;
 129 }
 130
 131 static int m88rs2000_set_carrieroffset(struct dvb_frontend *fe, s16 offset)
 132 {
 133         struct m88rs2000_state *state = fe->demodulator_priv;
 134         u32 mclk;
 135         s32 tmp;
 136         u8 reg;
 137         int ret;
 138
 139         mclk = m88rs2000_get_mclk(fe);
 140         if (!mclk)
 141                 return -EINVAL;
 142
 143         tmp = (offset * 4096 + (s32)mclk / 2) / (s32)mclk;
 144         if (tmp < 0)
 145                 tmp += 4096;
 146
 147         /* Carrier Offset */
 148         ret = m88rs2000_writereg(state, 0x9c, (u8)(tmp >> 4));
 149
 150         reg = m88rs2000_readreg(state, 0x9d);
 151         reg &= 0xf;
 152         reg |= (u8)(tmp & 0xf) << 4;
 153
 154         ret |= m88rs2000_writereg(state, 0x9d, reg);
 155
 156         return ret;
 157 }
 158
 159 static int m88rs2000_set_symbolrate(struct dvb_frontend *fe, u32 srate)
 160 {
 161         struct m88rs2000_state *state = fe->demodulator_priv;
 162         int ret;
 163         u32 temp;
 164         u8 b[3];
 165
 166         if ((srate < 1000000) || (srate > 45000000))
 167                 return -EINVAL;
 168
 169         temp = srate / 1000;
 170         temp *= 11831;
 171         temp /= 68;
 172         temp -= 3;
 173
 174         b[0] = (u8) (temp >> 16) & 0xff;
 175         b[1] = (u8) (temp >> 8) & 0xff;
 176         b[2] = (u8) temp & 0xff;
 177         ret = m88rs2000_writereg(state, 0x93, b[2]);
 178         ret |= m88rs2000_writereg(state, 0x94, b[1]);
 179         ret |= m88rs2000_writereg(state, 0x95, b[0]);
 180
 181         deb_info("m88rs2000: m88rs2000_set_symbolrate\n");
 182         return ret;
 183 }
 184
 185 static int m88rs2000_send_diseqc_msg(struct dvb_frontend *fe,
 186                                     struct dvb_diseqc_master_cmd *m)
 187 {
 188         struct m88rs2000_state *state = fe->demodulator_priv;
 189
 190         int i;
 191         u8 reg;
 192         deb_info("%s\n", __func__);
 193         m88rs2000_writereg(state, 0x9a, 0x30);
 194         reg = m88rs2000_readreg(state, 0xb2);
 195         reg &= 0x3f;
 196         m88rs2000_writereg(state, 0xb2, reg);
 197         for (i = 0; i <  m->msg_len; i++)
 198                 m88rs2000_writereg(state, 0xb3 + i, m->msg[i]);
 199
 200         reg = m88rs2000_readreg(state, 0xb1);
 201         reg &= 0x87;
 202         reg |= ((m->msg_len - 1) << 3) | 0x07;
 203         reg &= 0x7f;
 204         m88rs2000_writereg(state, 0xb1, reg);
 205
 206         for (i = 0; i < 15; i++) {
 207                 if ((m88rs2000_readreg(state, 0xb1) & 0x40) == 0x0)
 208                         break;
 209                 msleep(20);
 210         }
 211
 212         reg = m88rs2000_readreg(state, 0xb1);
 213         if ((reg & 0x40) > 0x0) {
 214                 reg &= 0x7f;
 215                 reg |= 0x40;
 216                 m88rs2000_writereg(state, 0xb1, reg);
 217         }
 218
 219         reg = m88rs2000_readreg(state, 0xb2);
 220         reg &= 0x3f;
 221         reg |= 0x80;
 222         m88rs2000_writereg(state, 0xb2, reg);
 223         m88rs2000_writereg(state, 0x9a, 0xb0);
 224
 225
 226         return 0;
 227 }
 228
 229 static int m88rs2000_send_diseqc_burst(struct dvb_frontend *fe,
 230                                                 fe_sec_mini_cmd_t burst)
 231 {
 232         struct m88rs2000_state *state = fe->demodulator_priv;
 233         u8 reg0, reg1;
 234         deb_info("%s\n", __func__);
 235         m88rs2000_writereg(state, 0x9a, 0x30);
 236         msleep(50);
 237         reg0 = m88rs2000_readreg(state, 0xb1);
 238         reg1 = m88rs2000_readreg(state, 0xb2);
 239         /* TODO complete this section */
 240         m88rs2000_writereg(state, 0xb2, reg1);
 241         m88rs2000_writereg(state, 0xb1, reg0);
 242         m88rs2000_writereg(state, 0x9a, 0xb0);
 243
 244         return 0;
 245 }
 246
 247 static int m88rs2000_set_tone(struct dvb_frontend *fe, fe_sec_tone_mode_t tone)
 248 {
 249         struct m88rs2000_state *state = fe->demodulator_priv;
 250         u8 reg0, reg1;
 251         m88rs2000_writereg(state, 0x9a, 0x30);
 252         reg0 = m88rs2000_readreg(state, 0xb1);
 253         reg1 = m88rs2000_readreg(state, 0xb2);
 254
 255         reg1 &= 0x3f;
 256
 257         switch (tone) {
 258         case SEC_TONE_ON:
 259                 reg0 |= 0x4;
 260                 reg0 &= 0xbc;
 261                 break;
 262         case SEC_TONE_OFF:
 263                 reg1 |= 0x80;
 264                 break;
 265         default:
 266                 break;
 267         }
 268         m88rs2000_writereg(state, 0xb2, reg1);
 269         m88rs2000_writereg(state, 0xb1, reg0);
 270         m88rs2000_writereg(state, 0x9a, 0xb0);
 271         return 0;
 272 }
 273
 274 struct inittab {
 275         u8 cmd;
 276         u8 reg;
 277         u8 val;
 278 };
 279
 280 struct inittab m88rs2000_setup[] = {
 281         {DEMOD_WRITE, 0x9a, 0x30},
 282         {DEMOD_WRITE, 0x00, 0x01},
 283         {WRITE_DELAY, 0x19, 0x00},
 284         {DEMOD_WRITE, 0x00, 0x00},
 285         {DEMOD_WRITE, 0x9a, 0xb0},
 286         {DEMOD_WRITE, 0x81, 0xc1},
 287         {DEMOD_WRITE, 0x81, 0x81},
 288         {DEMOD_WRITE, 0x86, 0xc6},
 289         {DEMOD_WRITE, 0x9a, 0x30},
 290         {DEMOD_WRITE, 0xf0, 0x22},
 291         {DEMOD_WRITE, 0xf1, 0xbf},
 292         {DEMOD_WRITE, 0xb0, 0x45},
 293         {DEMOD_WRITE, 0xb2, 0x01}, /* set voltage pin always set 1*/
 294         {DEMOD_WRITE, 0x9a, 0xb0},
 295         {0xff, 0xaa, 0xff}
 296 };
 297
 298 struct inittab m88rs2000_shutdown[] = {
 299         {DEMOD_WRITE, 0x9a, 0x30},
 300         {DEMOD_WRITE, 0xb0, 0x00},
 301         {DEMOD_WRITE, 0xf1, 0x89},
 302         {DEMOD_WRITE, 0x00, 0x01},
 303         {DEMOD_WRITE, 0x9a, 0xb0},
 304         {DEMOD_WRITE, 0x81, 0x81},
 305         {0xff, 0xaa, 0xff}
 306 };
 307
 308 struct inittab fe_reset[] = {
 309         {DEMOD_WRITE, 0x00, 0x01},
 310         {DEMOD_WRITE, 0xf1, 0xbf},
 311         {DEMOD_WRITE, 0x00, 0x01},
 312         {DEMOD_WRITE, 0x20, 0x81},
 313         {DEMOD_WRITE, 0x21, 0x80},
 314         {DEMOD_WRITE, 0x10, 0x33},
 315         {DEMOD_WRITE, 0x11, 0x44},
 316         {DEMOD_WRITE, 0x12, 0x07},
 317         {DEMOD_WRITE, 0x18, 0x20},
 318         {DEMOD_WRITE, 0x28, 0x04},
 319         {DEMOD_WRITE, 0x29, 0x8e},
 320         {DEMOD_WRITE, 0x3b, 0xff},
 321         {DEMOD_WRITE, 0x32, 0x10},
 322         {DEMOD_WRITE, 0x33, 0x02},
 323         {DEMOD_WRITE, 0x34, 0x30},
 324         {DEMOD_WRITE, 0x35, 0xff},
 325         {DEMOD_WRITE, 0x38, 0x50},
 326         {DEMOD_WRITE, 0x39, 0x68},
 327         {DEMOD_WRITE, 0x3c, 0x7f},
 328         {DEMOD_WRITE, 0x3d, 0x0f},
 329         {DEMOD_WRITE, 0x45, 0x20},
 330         {DEMOD_WRITE, 0x46, 0x24},
 331         {DEMOD_WRITE, 0x47, 0x7c},
 332         {DEMOD_WRITE, 0x48, 0x16},
 333         {DEMOD_WRITE, 0x49, 0x04},
 334         {DEMOD_WRITE, 0x4a, 0x01},
 335         {DEMOD_WRITE, 0x4b, 0x78},
 336         {DEMOD_WRITE, 0X4d, 0xd2},
 337         {DEMOD_WRITE, 0x4e, 0x6d},
 338         {DEMOD_WRITE, 0x50, 0x30},
 339         {DEMOD_WRITE, 0x51, 0x30},
 340         {DEMOD_WRITE, 0x54, 0x7b},
 341         {DEMOD_WRITE, 0x56, 0x09},
 342         {DEMOD_WRITE, 0x58, 0x59},
 343         {DEMOD_WRITE, 0x59, 0x37},
 344         {DEMOD_WRITE, 0x63, 0xfa},
 345         {0xff, 0xaa, 0xff}
 346 };
 347
 348 struct inittab fe_trigger[] = {
 349         {DEMOD_WRITE, 0x97, 0x04},
 350         {DEMOD_WRITE, 0x99, 0x77},
 351         {DEMOD_WRITE, 0x9b, 0x64},
 352         {DEMOD_WRITE, 0x9e, 0x00},
 353         {DEMOD_WRITE, 0x9f, 0xf8},
 354         {DEMOD_WRITE, 0xa0, 0x20},
 355         {DEMOD_WRITE, 0xa1, 0xe0},
 356         {DEMOD_WRITE, 0xa3, 0x38},
 357         {DEMOD_WRITE, 0x98, 0xff},
 358         {DEMOD_WRITE, 0xc0, 0x0f},
 359         {DEMOD_WRITE, 0x89, 0x01},
 360         {DEMOD_WRITE, 0x00, 0x00},
 361         {WRITE_DELAY, 0x0a, 0x00},
 362         {DEMOD_WRITE, 0x00, 0x01},
 363         {DEMOD_WRITE, 0x00, 0x00},
 364         {DEMOD_WRITE, 0x9a, 0xb0},
 365         {0xff, 0xaa, 0xff}
 366 };
 367
 368 static int m88rs2000_tab_set(struct m88rs2000_state *state,
 369                 struct inittab *tab)
 370 {
 371         int ret = 0;
 372         u8 i;
 373         if (tab == NULL)
 374                 return -EINVAL;
 375
 376         for (i = 0; i < 255; i++) {
 377                 switch (tab[i].cmd) {
 378                 case 0x01:
 379                         ret = m88rs2000_writereg(state, tab[i].reg,
 380                                 tab[i].val);
 381                         break;
 382                 case 0x10:
 383                         if (tab[i].reg > 0)
 384                                 mdelay(tab[i].reg);
 385                         break;
 386                 case 0xff:
 387                         if (tab[i].reg == 0xaa && tab[i].val == 0xff)
 388                                 return 0;
 389                 case 0x00:
 390                         break;
 391                 default:
 392                         return -EINVAL;
 393                 }
 394                 if (ret < 0)
 395                         return -ENODEV;
 396         }
 397         return 0;
 398 }
 399
 400 static int m88rs2000_set_voltage(struct dvb_frontend *fe, fe_sec_voltage_t volt)
 401 {
 402         struct m88rs2000_state *state = fe->demodulator_priv;
 403         u8 data;
 404
 405         data = m88rs2000_readreg(state, 0xb2);
 406         data |= 0x03; /* bit0 V/H, bit1 off/on */
 407
 408         switch (volt) {
 409         case SEC_VOLTAGE_18:
 410                 data &= ~0x03;
 411                 break;
 412         case SEC_VOLTAGE_13:
 413                 data &= ~0x03;
 414                 data |= 0x01;
 415                 break;
 416         case SEC_VOLTAGE_OFF:
 417                 break;
 418         }
 419
 420         m88rs2000_writereg(state, 0xb2, data);
 421
 422         return 0;
 423 }
 424
 425 static int m88rs2000_init(struct dvb_frontend *fe)
 426 {
 427         struct m88rs2000_state *state = fe->demodulator_priv;
 428         int ret;
 429
 430         deb_info("m88rs2000: init chip\n");
 431         /* Setup frontend from shutdown/cold */
 432         if (state->config->inittab)
 433                 ret = m88rs2000_tab_set(state,
 434                                 (struct inittab *)state->config->inittab);
 435         else
 436                 ret = m88rs2000_tab_set(state, m88rs2000_setup);
 437
 438         return ret;
 439 }
 440
 441 static int m88rs2000_sleep(struct dvb_frontend *fe)
 442 {
 443         struct m88rs2000_state *state = fe->demodulator_priv;
 444         int ret;
 445         /* Shutdown the frondend */
 446         ret = m88rs2000_tab_set(state, m88rs2000_shutdown);
 447         return ret;
 448 }
 449
 450 static int m88rs2000_read_status(struct dvb_frontend *fe, fe_status_t *status)
 451 {
 452         struct m88rs2000_state *state = fe->demodulator_priv;
 453         u8 reg = m88rs2000_readreg(state, 0x8c);
 454
 455         *status = 0;
 456
 457         if ((reg & 0x7) == 0x7) {
 458                 *status = FE_HAS_CARRIER | FE_HAS_SIGNAL | FE_HAS_VITERBI
 459                         | FE_HAS_SYNC | FE_HAS_LOCK;
 460                 if (state->config->set_ts_params)
 461                         state->config->set_ts_params(fe, CALL_IS_READ);
 462         }
 463         return 0;
 464 }
 465
 466 static int m88rs2000_read_ber(struct dvb_frontend *fe, u32 *ber)
 467 {
 468         struct m88rs2000_state *state = fe->demodulator_priv;
 469         u8 tmp0, tmp1;
 470
 471         m88rs2000_writereg(state, 0x9a, 0x30);
 472         tmp0 = m88rs2000_readreg(state, 0xd8);
 473         if ((tmp0 & 0x10) != 0) {
 474                 m88rs2000_writereg(state, 0x9a, 0xb0);
 475                 *ber = 0xffffffff;
 476                 return 0;
 477         }
 478
 479         *ber = (m88rs2000_readreg(state, 0xd7) << 8) |
 480                 m88rs2000_readreg(state, 0xd6);
 481
 482         tmp1 = m88rs2000_readreg(state, 0xd9);
 483         m88rs2000_writereg(state, 0xd9, (tmp1 & ~7) | 4);
 484         /* needs twice */
 485         m88rs2000_writereg(state, 0xd8, (tmp0 & ~8) | 0x30);
 486         m88rs2000_writereg(state, 0xd8, (tmp0 & ~8) | 0x30);
 487         m88rs2000_writereg(state, 0x9a, 0xb0);
 488
 489         return 0;
 490 }
 491
 492 static int m88rs2000_read_signal_strength(struct dvb_frontend *fe,
 493         u16 *strength)
 494 {
 495         if (fe->ops.tuner_ops.get_rf_strength)
 496                 fe->ops.tuner_ops.get_rf_strength(fe, strength);
 497
 498         return 0;
 499 }
 500
 501 static int m88rs2000_read_snr(struct dvb_frontend *fe, u16 *snr)
 502 {
 503         struct m88rs2000_state *state = fe->demodulator_priv;
 504
 505         *snr = 512 * m88rs2000_readreg(state, 0x65);
 506
 507         return 0;
 508 }
 509
 510 static int m88rs2000_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
 511 {
 512         struct m88rs2000_state *state = fe->demodulator_priv;
 513         u8 tmp;
 514
 515         *ucblocks = (m88rs2000_readreg(state, 0xd5) << 8) |
 516                         m88rs2000_readreg(state, 0xd4);
 517         tmp = m88rs2000_readreg(state, 0xd8);
 518         m88rs2000_writereg(state, 0xd8, tmp & ~0x20);
 519         /* needs two times */
 520         m88rs2000_writereg(state, 0xd8, tmp | 0x20);
 521         m88rs2000_writereg(state, 0xd8, tmp | 0x20);
 522
 523         return 0;
 524 }
 525
 526 static int m88rs2000_set_fec(struct m88rs2000_state *state,
 527                 fe_code_rate_t fec)
 528 {
 529         u16 fec_set;
 530         switch (fec) {
 531         /* This is not confirmed kept for reference */
 532 /*      case FEC_1_2:
 533                 fec_set = 0x88;
 534                 break;
 535         case FEC_2_3:
 536                 fec_set = 0x68;
 537                 break;
 538         case FEC_3_4:
 539                 fec_set = 0x48;
 540                 break;
 541         case FEC_5_6:
 542                 fec_set = 0x28;
 543                 break;
 544         case FEC_7_8:
 545                 fec_set = 0x18;
 546                 break; */
 547         case FEC_AUTO:
 548         default:
 549                 fec_set = 0x08;
 550         }
 551         m88rs2000_writereg(state, 0x76, fec_set);
 552
 553         return 0;
 554 }
 555
 556
 557 static fe_code_rate_t m88rs2000_get_fec(struct m88rs2000_state *state)
 558 {
 559         u8 reg;
 560         m88rs2000_writereg(state, 0x9a, 0x30);
 561         reg = m88rs2000_readreg(state, 0x76);
 562         m88rs2000_writereg(state, 0x9a, 0xb0);
 563
 564         switch (reg) {
 565         case 0x88:
 566                 return FEC_1_2;
 567         case 0x68:
 568                 return FEC_2_3;
 569         case 0x48:
 570                 return FEC_3_4;
 571         case 0x28:
 572                 return FEC_5_6;
 573         case 0x18:
 574                 return FEC_7_8;
 575         case 0x08:
 576         default:
 577                 break;
 578         }
 579
 580         return FEC_AUTO;
 581 }
 582
 583 static int m88rs2000_set_frontend(struct dvb_frontend *fe)
 584 {
 585         struct m88rs2000_state *state = fe->demodulator_priv;
 586         struct dtv_frontend_properties *c = &fe->dtv_property_cache;
 587         fe_status_t status;
 588         int i, ret = 0;
 589         u32 tuner_freq;
 590         s16 offset = 0;
 591         u8 reg;
 592
 593         state->no_lock_count = 0;
 594
 595         if (c->delivery_system != SYS_DVBS) {
 596                         deb_info("%s: unsupported delivery "
 597                                 "system selected (%d)\n",
 598                                 __func__, c->delivery_system);
 599                         return -EOPNOTSUPP;
 600         }
 601
 602         /* Set Tuner */
 603         if (fe->ops.tuner_ops.set_params)
 604                 ret = fe->ops.tuner_ops.set_params(fe);
 605
 606         if (ret < 0)
 607                 return -ENODEV;
 608
 609         if (fe->ops.tuner_ops.get_frequency)
 610                 ret = fe->ops.tuner_ops.get_frequency(fe, &tuner_freq);
 611
 612         if (ret < 0)
 613                 return -ENODEV;
 614
 615         offset = (s16)((s32)tuner_freq - c->frequency);
 616
 617         /* default mclk value 96.4285 * 2 * 1000 = 192857 */
 618         if (((c->frequency % 192857) >= (192857 - 3000)) ||
 619                                 (c->frequency % 192857) <= 3000)
 620                 ret = m88rs2000_writereg(state, 0x86, 0xc2);
 621         else
 622                 ret = m88rs2000_writereg(state, 0x86, 0xc6);
 623
 624         ret |= m88rs2000_set_carrieroffset(fe, offset);
 625         if (ret < 0)
 626                 return -ENODEV;
 627
 628         /* Reset Demod */
 629         ret = m88rs2000_tab_set(state, fe_reset);
 630         if (ret < 0)
 631                 return -ENODEV;
 632
 633         /* Unknown */
 634         reg = m88rs2000_readreg(state, 0x70);
 635         ret = m88rs2000_writereg(state, 0x70, reg);
 636
 637         /* Set FEC */
 638         ret |= m88rs2000_set_fec(state, c->fec_inner);
 639         ret |= m88rs2000_writereg(state, 0x85, 0x1);
 640         ret |= m88rs2000_writereg(state, 0x8a, 0xbf);
 641         ret |= m88rs2000_writereg(state, 0x8d, 0x1e);
 642         ret |= m88rs2000_writereg(state, 0x90, 0xf1);
 643         ret |= m88rs2000_writereg(state, 0x91, 0x08);
 644
 645         if (ret < 0)
 646                 return -ENODEV;
 647
 648         /* Set Symbol Rate */
 649         ret = m88rs2000_set_symbolrate(fe, c->symbol_rate);
 650         if (ret < 0)
 651                 return -ENODEV;
 652
 653         /* Set up Demod */
 654         ret = m88rs2000_tab_set(state, fe_trigger);
 655         if (ret < 0)
 656                 return -ENODEV;
 657
 658         for (i = 0; i < 25; i++) {
 659                 reg = m88rs2000_readreg(state, 0x8c);
 660                 if ((reg & 0x7) == 0x7) {
 661                         status = FE_HAS_LOCK;
 662                         break;
 663                 }
 664                 state->no_lock_count++;
 665                 if (state->no_lock_count == 15) {
 666                         reg = m88rs2000_readreg(state, 0x70);
 667                         reg ^= 0x4;
 668                         m88rs2000_writereg(state, 0x70, reg);
 669                         state->no_lock_count = 0;
 670                 }
 671                 msleep(20);
 672         }
 673
 674         if (status & FE_HAS_LOCK) {
 675                 state->fec_inner = m88rs2000_get_fec(state);
 676                 /* Uknown suspect SNR level */
 677                 reg = m88rs2000_readreg(state, 0x65);
 678         }
 679
 680         state->tuner_frequency = c->frequency;
 681         state->symbol_rate = c->symbol_rate;
 682         return 0;
 683 }
 684
 685 static int m88rs2000_get_frontend(struct dvb_frontend *fe)
 686 {
 687         struct dtv_frontend_properties *c = &fe->dtv_property_cache;
 688         struct m88rs2000_state *state = fe->demodulator_priv;
 689         c->fec_inner = state->fec_inner;
 690         c->frequency = state->tuner_frequency;
 691         c->symbol_rate = state->symbol_rate;
 692         return 0;
 693 }
 694
 695 static int m88rs2000_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
 696 {
 697         struct m88rs2000_state *state = fe->demodulator_priv;
 698
 699         if (enable)
 700                 m88rs2000_writereg(state, 0x81, 0x84);
 701         else
 702                 m88rs2000_writereg(state, 0x81, 0x81);
 703         udelay(10);
 704         return 0;
 705 }
 706
 707 static void m88rs2000_release(struct dvb_frontend *fe)
 708 {
 709         struct m88rs2000_state *state = fe->demodulator_priv;
 710         kfree(state);
 711 }
 712
 713 static struct dvb_frontend_ops m88rs2000_ops = {
 714         .delsys = { SYS_DVBS },
 715         .info = {
 716                 .name                   = "M88RS2000 DVB-S",
 717                 .frequency_min          = 950000,
 718                 .frequency_max          = 2150000,
 719                 .frequency_stepsize     = 1000,  /* kHz for QPSK frontends */
 720                 .frequency_tolerance    = 5000,
 721                 .symbol_rate_min        = 1000000,
 722                 .symbol_rate_max        = 45000000,
 723                 .symbol_rate_tolerance  = 500,  /* ppm */
 724                 .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
 725                       FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
 726                       FE_CAN_QPSK |
 727                       FE_CAN_FEC_AUTO
 728         },
 729
 730         .release = m88rs2000_release,
 731         .init = m88rs2000_init,
 732         .sleep = m88rs2000_sleep,
 733         .i2c_gate_ctrl = m88rs2000_i2c_gate_ctrl,
 734         .read_status = m88rs2000_read_status,
 735         .read_ber = m88rs2000_read_ber,
 736         .read_signal_strength = m88rs2000_read_signal_strength,
 737         .read_snr = m88rs2000_read_snr,
 738         .read_ucblocks = m88rs2000_read_ucblocks,
 739         .diseqc_send_master_cmd = m88rs2000_send_diseqc_msg,
 740         .diseqc_send_burst = m88rs2000_send_diseqc_burst,
 741         .set_tone = m88rs2000_set_tone,
 742         .set_voltage = m88rs2000_set_voltage,
 743
 744         .set_frontend = m88rs2000_set_frontend,
 745         .get_frontend = m88rs2000_get_frontend,
 746 };
 747
 748 struct dvb_frontend *m88rs2000_attach(const struct m88rs2000_config *config,
 749                                     struct i2c_adapter *i2c)
 750 {
 751         struct m88rs2000_state *state = NULL;
 752
 753         /* allocate memory for the internal state */
 754         state = kzalloc(sizeof(struct m88rs2000_state), GFP_KERNEL);
 755         if (state == NULL)
 756                 goto error;
 757
 758         /* setup the state */
 759         state->config = config;
 760         state->i2c = i2c;
 761         state->tuner_frequency = 0;
 762         state->symbol_rate = 0;
 763         state->fec_inner = 0;
 764
 765         /* create dvb_frontend */
 766         memcpy(&state->frontend.ops, &m88rs2000_ops,
 767                         sizeof(struct dvb_frontend_ops));
 768         state->frontend.demodulator_priv = state;
 769         return &state->frontend;
 770
 771 error:
 772         kfree(state);
 773
 774         return NULL;
 775 }
 776 EXPORT_SYMBOL(m88rs2000_attach);
 777
 778 MODULE_DESCRIPTION("M88RS2000 DVB-S Demodulator driver");
 779 MODULE_AUTHOR("Malcolm Priestley tvboxspy@gmail.com");
 780 MODULE_LICENSE("GPL");
 781 MODULE_VERSION("1.13");
 782