2 * Fujitu mb86a20s ISDB-T/ISDB-Tsb Module driver
4 * Copyright (C) 2010-2013 Mauro Carvalho Chehab <mchehab@redhat.com>
5 * Copyright (C) 2009-2010 Douglas Landgraf <dougsland@redhat.com>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation version 2.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
17 #include <linux/kernel.h>
18 #include <asm/div64.h>
20 #include "dvb_frontend.h"
24 module_param(debug, int, 0644);
25 MODULE_PARM_DESC(debug, "Activates frontend debugging (default:0)");
27 struct mb86a20s_state {
28 struct i2c_adapter *i2c;
29 const struct mb86a20s_config *config;
32 struct dvb_frontend frontend;
34 u32 estimated_rate[3];
44 #define BER_SAMPLING_RATE 1 /* Seconds */
47 * Initialization sequence: Use whatevere default values that PV SBTVD
48 * does on its initialisation, obtained via USB snoop
50 static struct regdata mb86a20s_init[] = {
55 { 0x50, 0xd1 }, { 0x51, 0x22 },
58 { 0x28, 0x2a }, { 0x29, 0x00 }, { 0x2a, 0xff }, { 0x2b, 0x80 },
59 { 0x28, 0x20 }, { 0x29, 0x33 }, { 0x2a, 0xdf }, { 0x2b, 0xa9 },
60 { 0x28, 0x22 }, { 0x29, 0x00 }, { 0x2a, 0x1f }, { 0x2b, 0xf0 },
64 { 0x04, 0x08 }, { 0x05, 0x05 },
65 { 0x04, 0x0e }, { 0x05, 0x00 },
66 { 0x04, 0x0f }, { 0x05, 0x14 },
67 { 0x04, 0x0b }, { 0x05, 0x8c },
68 { 0x04, 0x00 }, { 0x05, 0x00 },
69 { 0x04, 0x01 }, { 0x05, 0x07 },
70 { 0x04, 0x02 }, { 0x05, 0x0f },
71 { 0x04, 0x03 }, { 0x05, 0xa0 },
72 { 0x04, 0x09 }, { 0x05, 0x00 },
73 { 0x04, 0x0a }, { 0x05, 0xff },
74 { 0x04, 0x27 }, { 0x05, 0x64 },
75 { 0x04, 0x28 }, { 0x05, 0x00 },
76 { 0x04, 0x1e }, { 0x05, 0xff },
77 { 0x04, 0x29 }, { 0x05, 0x0a },
78 { 0x04, 0x32 }, { 0x05, 0x0a },
79 { 0x04, 0x14 }, { 0x05, 0x02 },
80 { 0x04, 0x04 }, { 0x05, 0x00 },
81 { 0x04, 0x05 }, { 0x05, 0x22 },
82 { 0x04, 0x06 }, { 0x05, 0x0e },
83 { 0x04, 0x07 }, { 0x05, 0xd8 },
84 { 0x04, 0x12 }, { 0x05, 0x00 },
85 { 0x04, 0x13 }, { 0x05, 0xff },
86 { 0x04, 0x15 }, { 0x05, 0x4e },
87 { 0x04, 0x16 }, { 0x05, 0x20 },
90 * On this demod, when the bit count reaches the count below,
91 * it collects the bit error count. The bit counters are initialized
92 * to 65535 here. This warrants that all of them will be quickly
93 * calculated when device gets locked. As TMCC is parsed, the values
94 * will be adjusted later in the driver's code.
96 { 0x52, 0x01 }, /* Turn on BER before Viterbi */
97 { 0x50, 0xa7 }, { 0x51, 0x00 },
98 { 0x50, 0xa8 }, { 0x51, 0xff },
99 { 0x50, 0xa9 }, { 0x51, 0xff },
100 { 0x50, 0xaa }, { 0x51, 0x00 },
101 { 0x50, 0xab }, { 0x51, 0xff },
102 { 0x50, 0xac }, { 0x51, 0xff },
103 { 0x50, 0xad }, { 0x51, 0x00 },
104 { 0x50, 0xae }, { 0x51, 0xff },
105 { 0x50, 0xaf }, { 0x51, 0xff },
108 * On this demod, post BER counts blocks. When the count reaches the
109 * value below, it collects the block error count. The block counters
110 * are initialized to 127 here. This warrants that all of them will be
111 * quickly calculated when device gets locked. As TMCC is parsed, the
112 * values will be adjusted later in the driver's code.
114 { 0x5e, 0x07 }, /* Turn on BER after Viterbi */
115 { 0x50, 0xdc }, { 0x51, 0x00 },
116 { 0x50, 0xdd }, { 0x51, 0x7f },
117 { 0x50, 0xde }, { 0x51, 0x00 },
118 { 0x50, 0xdf }, { 0x51, 0x7f },
119 { 0x50, 0xe0 }, { 0x51, 0x00 },
120 { 0x50, 0xe1 }, { 0x51, 0x7f },
123 * On this demod, when the block count reaches the count below,
124 * it collects the block error count. The block counters are initialized
125 * to 127 here. This warrants that all of them will be quickly
126 * calculated when device gets locked. As TMCC is parsed, the values
127 * will be adjusted later in the driver's code.
129 { 0x50, 0xb0 }, { 0x51, 0x07 }, /* Enable PER */
130 { 0x50, 0xb2 }, { 0x51, 0x00 },
131 { 0x50, 0xb3 }, { 0x51, 0x7f },
132 { 0x50, 0xb4 }, { 0x51, 0x00 },
133 { 0x50, 0xb5 }, { 0x51, 0x7f },
134 { 0x50, 0xb6 }, { 0x51, 0x00 },
135 { 0x50, 0xb7 }, { 0x51, 0x7f },
137 { 0x50, 0x50 }, { 0x51, 0x02 }, /* MER manual mode */
138 { 0x50, 0x51 }, { 0x51, 0x04 }, /* MER symbol 4 */
139 { 0x45, 0x04 }, /* CN symbol 4 */
140 { 0x48, 0x04 }, /* CN manual mode */
142 { 0x50, 0xd5 }, { 0x51, 0x01 }, /* Serial */
143 { 0x50, 0xd6 }, { 0x51, 0x1f },
144 { 0x50, 0xd2 }, { 0x51, 0x03 },
145 { 0x50, 0xd7 }, { 0x51, 0x3f },
146 { 0x28, 0x74 }, { 0x29, 0x00 }, { 0x28, 0x74 }, { 0x29, 0x40 },
147 { 0x28, 0x46 }, { 0x29, 0x2c }, { 0x28, 0x46 }, { 0x29, 0x0c },
149 { 0x04, 0x40 }, { 0x05, 0x00 },
150 { 0x28, 0x00 }, { 0x29, 0x10 },
151 { 0x28, 0x05 }, { 0x29, 0x02 },
153 { 0x28, 0x06 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x03 },
154 { 0x28, 0x07 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x0d },
155 { 0x28, 0x08 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x02 },
156 { 0x28, 0x09 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x01 },
157 { 0x28, 0x0a }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x21 },
158 { 0x28, 0x0b }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x29 },
159 { 0x28, 0x0c }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x16 },
160 { 0x28, 0x0d }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x31 },
161 { 0x28, 0x0e }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x0e },
162 { 0x28, 0x0f }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x4e },
163 { 0x28, 0x10 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x46 },
164 { 0x28, 0x11 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x0f },
165 { 0x28, 0x12 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x56 },
166 { 0x28, 0x13 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x35 },
167 { 0x28, 0x14 }, { 0x29, 0x00 }, { 0x2a, 0x01 }, { 0x2b, 0xbe },
168 { 0x28, 0x15 }, { 0x29, 0x00 }, { 0x2a, 0x01 }, { 0x2b, 0x84 },
169 { 0x28, 0x16 }, { 0x29, 0x00 }, { 0x2a, 0x03 }, { 0x2b, 0xee },
170 { 0x28, 0x17 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x98 },
171 { 0x28, 0x18 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x9f },
172 { 0x28, 0x19 }, { 0x29, 0x00 }, { 0x2a, 0x07 }, { 0x2b, 0xb2 },
173 { 0x28, 0x1a }, { 0x29, 0x00 }, { 0x2a, 0x06 }, { 0x2b, 0xc2 },
174 { 0x28, 0x1b }, { 0x29, 0x00 }, { 0x2a, 0x07 }, { 0x2b, 0x4a },
175 { 0x28, 0x1c }, { 0x29, 0x00 }, { 0x2a, 0x01 }, { 0x2b, 0xbc },
176 { 0x28, 0x1d }, { 0x29, 0x00 }, { 0x2a, 0x04 }, { 0x2b, 0xba },
177 { 0x28, 0x1e }, { 0x29, 0x00 }, { 0x2a, 0x06 }, { 0x2b, 0x14 },
178 { 0x50, 0x1e }, { 0x51, 0x5d },
179 { 0x50, 0x22 }, { 0x51, 0x00 },
180 { 0x50, 0x23 }, { 0x51, 0xc8 },
181 { 0x50, 0x24 }, { 0x51, 0x00 },
182 { 0x50, 0x25 }, { 0x51, 0xf0 },
183 { 0x50, 0x26 }, { 0x51, 0x00 },
184 { 0x50, 0x27 }, { 0x51, 0xc3 },
185 { 0x50, 0x39 }, { 0x51, 0x02 },
186 { 0x28, 0x6a }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x00 },
190 static struct regdata mb86a20s_reset_reception[] = {
197 static struct regdata mb86a20s_per_ber_reset[] = {
198 { 0x53, 0x00 }, /* pre BER Counter reset */
201 { 0x5f, 0x00 }, /* post BER Counter reset */
204 { 0x50, 0xb1 }, /* PER Counter reset */
210 * I2C read/write functions and macros
213 static int mb86a20s_i2c_writereg(struct mb86a20s_state *state,
214 u8 i2c_addr, u8 reg, u8 data)
216 u8 buf[] = { reg, data };
217 struct i2c_msg msg = {
218 .addr = i2c_addr, .flags = 0, .buf = buf, .len = 2
222 rc = i2c_transfer(state->i2c, &msg, 1);
224 dev_err(&state->i2c->dev,
225 "%s: writereg error (rc == %i, reg == 0x%02x, data == 0x%02x)\n",
226 __func__, rc, reg, data);
233 static int mb86a20s_i2c_writeregdata(struct mb86a20s_state *state,
234 u8 i2c_addr, struct regdata *rd, int size)
238 for (i = 0; i < size; i++) {
239 rc = mb86a20s_i2c_writereg(state, i2c_addr, rd[i].reg,
247 static int mb86a20s_i2c_readreg(struct mb86a20s_state *state,
252 struct i2c_msg msg[] = {
253 { .addr = i2c_addr, .flags = 0, .buf = ®, .len = 1 },
254 { .addr = i2c_addr, .flags = I2C_M_RD, .buf = &val, .len = 1 }
257 rc = i2c_transfer(state->i2c, msg, 2);
260 dev_err(&state->i2c->dev, "%s: reg=0x%x (error=%d)\n",
262 return (rc < 0) ? rc : -EIO;
268 #define mb86a20s_readreg(state, reg) \
269 mb86a20s_i2c_readreg(state, state->config->demod_address, reg)
270 #define mb86a20s_writereg(state, reg, val) \
271 mb86a20s_i2c_writereg(state, state->config->demod_address, reg, val)
272 #define mb86a20s_writeregdata(state, regdata) \
273 mb86a20s_i2c_writeregdata(state, state->config->demod_address, \
274 regdata, ARRAY_SIZE(regdata))
277 * Ancillary internal routines (likely compiled inlined)
279 * The functions below assume that gateway lock has already obtained
282 static int mb86a20s_read_status(struct dvb_frontend *fe, fe_status_t *status)
284 struct mb86a20s_state *state = fe->demodulator_priv;
289 val = mb86a20s_readreg(state, 0x0a) & 0xf;
294 *status |= FE_HAS_SIGNAL;
297 *status |= FE_HAS_CARRIER;
300 *status |= FE_HAS_VITERBI;
303 *status |= FE_HAS_SYNC;
305 if (val >= 8) /* Maybe 9? */
306 *status |= FE_HAS_LOCK;
308 dev_dbg(&state->i2c->dev, "%s: Status = 0x%02x (state = %d)\n",
309 __func__, *status, val);
314 static int mb86a20s_read_signal_strength(struct dvb_frontend *fe)
316 struct mb86a20s_state *state = fe->demodulator_priv;
318 unsigned rf_max, rf_min, rf;
320 /* Does a binary search to get RF strength */
324 rf = (rf_max + rf_min) / 2;
325 rc = mb86a20s_writereg(state, 0x04, 0x1f);
328 rc = mb86a20s_writereg(state, 0x05, rf >> 8);
331 rc = mb86a20s_writereg(state, 0x04, 0x20);
334 rc = mb86a20s_writereg(state, 0x04, rf);
338 rc = mb86a20s_readreg(state, 0x02);
342 rf_min = (rf_max + rf_min) / 2;
344 rf_max = (rf_max + rf_min) / 2;
345 if (rf_max - rf_min < 4) {
346 rf = (rf_max + rf_min) / 2;
348 /* Rescale it from 2^12 (4096) to 2^16 */
350 dev_dbg(&state->i2c->dev,
351 "%s: signal strength = %d (%d < RF=%d < %d)\n",
352 __func__, rf, rf_min, rf >> 4, rf_max);
360 static int mb86a20s_get_modulation(struct mb86a20s_state *state,
364 static unsigned char reg[] = {
365 [0] = 0x86, /* Layer A */
366 [1] = 0x8a, /* Layer B */
367 [2] = 0x8e, /* Layer C */
370 if (layer >= ARRAY_SIZE(reg))
372 rc = mb86a20s_writereg(state, 0x6d, reg[layer]);
375 rc = mb86a20s_readreg(state, 0x6e);
378 switch ((rc >> 4) & 0x07) {
392 static int mb86a20s_get_fec(struct mb86a20s_state *state,
397 static unsigned char reg[] = {
398 [0] = 0x87, /* Layer A */
399 [1] = 0x8b, /* Layer B */
400 [2] = 0x8f, /* Layer C */
403 if (layer >= ARRAY_SIZE(reg))
405 rc = mb86a20s_writereg(state, 0x6d, reg[layer]);
408 rc = mb86a20s_readreg(state, 0x6e);
411 switch ((rc >> 4) & 0x07) {
427 static int mb86a20s_get_interleaving(struct mb86a20s_state *state,
432 static unsigned char reg[] = {
433 [0] = 0x88, /* Layer A */
434 [1] = 0x8c, /* Layer B */
435 [2] = 0x90, /* Layer C */
438 if (layer >= ARRAY_SIZE(reg))
440 rc = mb86a20s_writereg(state, 0x6d, reg[layer]);
443 rc = mb86a20s_readreg(state, 0x6e);
447 switch ((rc >> 4) & 0x07) {
449 return GUARD_INTERVAL_1_4;
451 return GUARD_INTERVAL_1_8;
453 return GUARD_INTERVAL_1_16;
455 return GUARD_INTERVAL_1_32;
459 return GUARD_INTERVAL_AUTO;
463 static int mb86a20s_get_segment_count(struct mb86a20s_state *state,
467 static unsigned char reg[] = {
468 [0] = 0x89, /* Layer A */
469 [1] = 0x8d, /* Layer B */
470 [2] = 0x91, /* Layer C */
473 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
475 if (layer >= ARRAY_SIZE(reg))
478 rc = mb86a20s_writereg(state, 0x6d, reg[layer]);
481 rc = mb86a20s_readreg(state, 0x6e);
484 count = (rc >> 4) & 0x0f;
486 dev_dbg(&state->i2c->dev, "%s: segments: %d.\n", __func__, count);
491 static void mb86a20s_reset_frontend_cache(struct dvb_frontend *fe)
493 struct mb86a20s_state *state = fe->demodulator_priv;
494 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
496 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
498 /* Fixed parameters */
499 c->delivery_system = SYS_ISDBT;
500 c->bandwidth_hz = 6000000;
502 /* Initialize values that will be later autodetected */
503 c->isdbt_layer_enabled = 0;
504 c->transmission_mode = TRANSMISSION_MODE_AUTO;
505 c->guard_interval = GUARD_INTERVAL_AUTO;
506 c->isdbt_sb_mode = 0;
507 c->isdbt_sb_segment_count = 0;
511 * Estimates the bit rate using the per-segment bit rate given by
512 * ABNT/NBR 15601 spec (table 4).
514 static u32 isdbt_rate[3][5][4] = {
516 { 280850, 312060, 330420, 340430 }, /* 1/2 */
517 { 374470, 416080, 440560, 453910 }, /* 2/3 */
518 { 421280, 468090, 495630, 510650 }, /* 3/4 */
519 { 468090, 520100, 550700, 567390 }, /* 5/6 */
520 { 491500, 546110, 578230, 595760 }, /* 7/8 */
522 { 561710, 624130, 660840, 680870 }, /* 1/2 */
523 { 748950, 832170, 881120, 907820 }, /* 2/3 */
524 { 842570, 936190, 991260, 1021300 }, /* 3/4 */
525 { 936190, 1040210, 1101400, 1134780 }, /* 5/6 */
526 { 983000, 1092220, 1156470, 1191520 }, /* 7/8 */
528 { 842570, 936190, 991260, 1021300 }, /* 1/2 */
529 { 1123430, 1248260, 1321680, 1361740 }, /* 2/3 */
530 { 1263860, 1404290, 1486900, 1531950 }, /* 3/4 */
531 { 1404290, 1560320, 1652110, 1702170 }, /* 5/6 */
532 { 1474500, 1638340, 1734710, 1787280 }, /* 7/8 */
536 static void mb86a20s_layer_bitrate(struct dvb_frontend *fe, u32 layer,
537 u32 modulation, u32 fec, u32 interleaving,
540 struct mb86a20s_state *state = fe->demodulator_priv;
545 * If modulation/fec/interleaving is not detected, the default is
546 * to consider the lowest bit rate, to avoid taking too long time
549 switch (modulation) {
583 switch (interleaving) {
585 case GUARD_INTERVAL_1_4:
588 case GUARD_INTERVAL_1_8:
591 case GUARD_INTERVAL_1_16:
594 case GUARD_INTERVAL_1_32:
599 /* Samples BER at BER_SAMPLING_RATE seconds */
600 rate = isdbt_rate[m][f][i] * segment * BER_SAMPLING_RATE;
602 /* Avoids sampling too quickly or to overflow the register */
605 else if (rate > (1 << 24) - 1)
606 rate = (1 << 24) - 1;
608 dev_dbg(&state->i2c->dev,
609 "%s: layer %c bitrate: %d kbps; counter = %d (0x%06x)\n",
610 __func__, 'A' + layer, segment * isdbt_rate[m][f][i]/1000,
613 state->estimated_rate[layer] = rate;
617 static int mb86a20s_get_frontend(struct dvb_frontend *fe)
619 struct mb86a20s_state *state = fe->demodulator_priv;
620 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
623 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
625 /* Reset frontend cache to default values */
626 mb86a20s_reset_frontend_cache(fe);
628 /* Check for partial reception */
629 rc = mb86a20s_writereg(state, 0x6d, 0x85);
632 rc = mb86a20s_readreg(state, 0x6e);
635 c->isdbt_partial_reception = (rc & 0x10) ? 1 : 0;
637 /* Get per-layer data */
639 for (i = 0; i < 3; i++) {
640 dev_dbg(&state->i2c->dev, "%s: getting data for layer %c.\n",
643 rc = mb86a20s_get_segment_count(state, i);
645 goto noperlayer_error;
646 if (rc >= 0 && rc < 14) {
647 c->layer[i].segment_count = rc;
649 c->layer[i].segment_count = 0;
650 state->estimated_rate[i] = 0;
653 c->isdbt_layer_enabled |= 1 << i;
654 rc = mb86a20s_get_modulation(state, i);
656 goto noperlayer_error;
657 dev_dbg(&state->i2c->dev, "%s: modulation %d.\n",
659 c->layer[i].modulation = rc;
660 rc = mb86a20s_get_fec(state, i);
662 goto noperlayer_error;
663 dev_dbg(&state->i2c->dev, "%s: FEC %d.\n",
665 c->layer[i].fec = rc;
666 rc = mb86a20s_get_interleaving(state, i);
668 goto noperlayer_error;
669 dev_dbg(&state->i2c->dev, "%s: interleaving %d.\n",
671 c->layer[i].interleaving = rc;
672 mb86a20s_layer_bitrate(fe, i, c->layer[i].modulation,
674 c->layer[i].interleaving,
675 c->layer[i].segment_count);
678 rc = mb86a20s_writereg(state, 0x6d, 0x84);
681 if ((rc & 0x60) == 0x20) {
682 c->isdbt_sb_mode = 1;
683 /* At least, one segment should exist */
684 if (!c->isdbt_sb_segment_count)
685 c->isdbt_sb_segment_count = 1;
688 /* Get transmission mode and guard interval */
689 rc = mb86a20s_readreg(state, 0x07);
692 if ((rc & 0x60) == 0x20) {
693 switch (rc & 0x0c >> 2) {
695 c->transmission_mode = TRANSMISSION_MODE_2K;
698 c->transmission_mode = TRANSMISSION_MODE_4K;
701 c->transmission_mode = TRANSMISSION_MODE_8K;
708 c->guard_interval = GUARD_INTERVAL_1_4;
711 c->guard_interval = GUARD_INTERVAL_1_8;
714 c->guard_interval = GUARD_INTERVAL_1_16;
722 /* per-layer info is incomplete; discard all per-layer */
723 c->isdbt_layer_enabled = 0;
728 static int mb86a20s_reset_counters(struct dvb_frontend *fe)
730 struct mb86a20s_state *state = fe->demodulator_priv;
731 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
734 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
736 /* Reset the counters, if the channel changed */
737 if (state->last_frequency != c->frequency) {
738 memset(&c->strength, 0, sizeof(c->strength));
739 memset(&c->cnr, 0, sizeof(c->cnr));
740 memset(&c->pre_bit_error, 0, sizeof(c->pre_bit_error));
741 memset(&c->pre_bit_count, 0, sizeof(c->pre_bit_count));
742 memset(&c->post_bit_error, 0, sizeof(c->post_bit_error));
743 memset(&c->post_bit_count, 0, sizeof(c->post_bit_count));
744 memset(&c->block_error, 0, sizeof(c->block_error));
745 memset(&c->block_count, 0, sizeof(c->block_count));
747 state->last_frequency = c->frequency;
750 /* Clear status for most stats */
752 /* BER/PER counter reset */
753 rc = mb86a20s_writeregdata(state, mb86a20s_per_ber_reset);
757 /* CNR counter reset */
758 rc = mb86a20s_readreg(state, 0x45);
762 rc = mb86a20s_writereg(state, 0x45, val | 0x10);
765 rc = mb86a20s_writereg(state, 0x45, val & 0x6f);
769 /* MER counter reset */
770 rc = mb86a20s_writereg(state, 0x50, 0x50);
773 rc = mb86a20s_readreg(state, 0x51);
777 rc = mb86a20s_writereg(state, 0x51, val | 0x01);
780 rc = mb86a20s_writereg(state, 0x51, val & 0x06);
786 dev_err(&state->i2c->dev,
787 "%s: Can't reset FE statistics (error %d).\n",
793 static int mb86a20s_get_pre_ber(struct dvb_frontend *fe,
795 u32 *error, u32 *count)
797 struct mb86a20s_state *state = fe->demodulator_priv;
800 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
805 /* Check if the BER measures are already available */
806 rc = mb86a20s_readreg(state, 0x54);
810 /* Check if data is available for that layer */
811 if (!(rc & (1 << layer))) {
812 dev_dbg(&state->i2c->dev,
813 "%s: preBER for layer %c is not available yet.\n",
814 __func__, 'A' + layer);
818 /* Read Bit Error Count */
819 rc = mb86a20s_readreg(state, 0x55 + layer * 3);
823 rc = mb86a20s_readreg(state, 0x56 + layer * 3);
827 rc = mb86a20s_readreg(state, 0x57 + layer * 3);
832 dev_dbg(&state->i2c->dev,
833 "%s: bit error before Viterbi for layer %c: %d.\n",
834 __func__, 'A' + layer, *error);
837 rc = mb86a20s_writereg(state, 0x50, 0xa7 + layer * 3);
840 rc = mb86a20s_readreg(state, 0x51);
844 rc = mb86a20s_writereg(state, 0x50, 0xa8 + layer * 3);
847 rc = mb86a20s_readreg(state, 0x51);
851 rc = mb86a20s_writereg(state, 0x50, 0xa9 + layer * 3);
854 rc = mb86a20s_readreg(state, 0x51);
859 dev_dbg(&state->i2c->dev,
860 "%s: bit count before Viterbi for layer %c: %d.\n",
861 __func__, 'A' + layer, *count);
865 * As we get TMCC data from the frontend, we can better estimate the
866 * BER bit counters, in order to do the BER measure during a longer
867 * time. Use those data, if available, to update the bit count
871 if (state->estimated_rate[layer]
872 && state->estimated_rate[layer] != *count) {
873 dev_dbg(&state->i2c->dev,
874 "%s: updating layer %c preBER counter to %d.\n",
875 __func__, 'A' + layer, state->estimated_rate[layer]);
877 /* Turn off BER before Viterbi */
878 rc = mb86a20s_writereg(state, 0x52, 0x00);
880 /* Update counter for this layer */
881 rc = mb86a20s_writereg(state, 0x50, 0xa7 + layer * 3);
884 rc = mb86a20s_writereg(state, 0x51,
885 state->estimated_rate[layer] >> 16);
888 rc = mb86a20s_writereg(state, 0x50, 0xa8 + layer * 3);
891 rc = mb86a20s_writereg(state, 0x51,
892 state->estimated_rate[layer] >> 8);
895 rc = mb86a20s_writereg(state, 0x50, 0xa9 + layer * 3);
898 rc = mb86a20s_writereg(state, 0x51,
899 state->estimated_rate[layer]);
903 /* Turn on BER before Viterbi */
904 rc = mb86a20s_writereg(state, 0x52, 0x01);
906 /* Reset all preBER counters */
907 rc = mb86a20s_writereg(state, 0x53, 0x00);
910 rc = mb86a20s_writereg(state, 0x53, 0x07);
912 /* Reset counter to collect new data */
913 rc = mb86a20s_readreg(state, 0x53);
917 rc = mb86a20s_writereg(state, 0x53, val & ~(1 << layer));
920 rc = mb86a20s_writereg(state, 0x53, val | (1 << layer));
926 static int mb86a20s_get_post_ber(struct dvb_frontend *fe,
928 u32 *error, u32 *count)
930 struct mb86a20s_state *state = fe->demodulator_priv;
931 u32 counter, collect_rate;
934 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
939 /* Check if the BER measures are already available */
940 rc = mb86a20s_readreg(state, 0x60);
944 /* Check if data is available for that layer */
945 if (!(rc & (1 << layer))) {
946 dev_dbg(&state->i2c->dev,
947 "%s: post BER for layer %c is not available yet.\n",
948 __func__, 'A' + layer);
952 /* Read Bit Error Count */
953 rc = mb86a20s_readreg(state, 0x64 + layer * 3);
957 rc = mb86a20s_readreg(state, 0x65 + layer * 3);
961 rc = mb86a20s_readreg(state, 0x66 + layer * 3);
966 dev_dbg(&state->i2c->dev,
967 "%s: post bit error for layer %c: %d.\n",
968 __func__, 'A' + layer, *error);
971 rc = mb86a20s_writereg(state, 0x50, 0xdc + layer * 2);
974 rc = mb86a20s_readreg(state, 0x51);
978 rc = mb86a20s_writereg(state, 0x50, 0xdd + layer * 2);
981 rc = mb86a20s_readreg(state, 0x51);
985 *count = counter * 204 * 8;
987 dev_dbg(&state->i2c->dev,
988 "%s: post bit count for layer %c: %d.\n",
989 __func__, 'A' + layer, *count);
992 * As we get TMCC data from the frontend, we can better estimate the
993 * BER bit counters, in order to do the BER measure during a longer
994 * time. Use those data, if available, to update the bit count
998 if (!state->estimated_rate[layer])
999 goto reset_measurement;
1001 collect_rate = state->estimated_rate[layer] / 204 / 8;
1002 if (collect_rate < 32)
1004 if (collect_rate > 65535)
1005 collect_rate = 65535;
1006 if (collect_rate != counter) {
1007 dev_dbg(&state->i2c->dev,
1008 "%s: updating postBER counter on layer %c to %d.\n",
1009 __func__, 'A' + layer, collect_rate);
1011 /* Turn off BER after Viterbi */
1012 rc = mb86a20s_writereg(state, 0x5e, 0x00);
1014 /* Update counter for this layer */
1015 rc = mb86a20s_writereg(state, 0x50, 0xdc + layer * 2);
1018 rc = mb86a20s_writereg(state, 0x51, collect_rate >> 8);
1021 rc = mb86a20s_writereg(state, 0x50, 0xdd + layer * 2);
1024 rc = mb86a20s_writereg(state, 0x51, collect_rate & 0xff);
1028 /* Turn on BER after Viterbi */
1029 rc = mb86a20s_writereg(state, 0x5e, 0x07);
1031 /* Reset all preBER counters */
1032 rc = mb86a20s_writereg(state, 0x5f, 0x00);
1035 rc = mb86a20s_writereg(state, 0x5f, 0x07);
1041 /* Reset counter to collect new data */
1042 rc = mb86a20s_readreg(state, 0x5f);
1046 rc = mb86a20s_writereg(state, 0x5f, val & ~(1 << layer));
1049 rc = mb86a20s_writereg(state, 0x5f, val | (1 << layer));
1054 static int mb86a20s_get_blk_error(struct dvb_frontend *fe,
1056 u32 *error, u32 *count)
1058 struct mb86a20s_state *state = fe->demodulator_priv;
1061 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1066 /* Check if the PER measures are already available */
1067 rc = mb86a20s_writereg(state, 0x50, 0xb8);
1070 rc = mb86a20s_readreg(state, 0x51);
1074 /* Check if data is available for that layer */
1076 if (!(rc & (1 << layer))) {
1077 dev_dbg(&state->i2c->dev,
1078 "%s: block counts for layer %c aren't available yet.\n",
1079 __func__, 'A' + layer);
1083 /* Read Packet error Count */
1084 rc = mb86a20s_writereg(state, 0x50, 0xb9 + layer * 2);
1087 rc = mb86a20s_readreg(state, 0x51);
1091 rc = mb86a20s_writereg(state, 0x50, 0xba + layer * 2);
1094 rc = mb86a20s_readreg(state, 0x51);
1098 dev_err(&state->i2c->dev, "%s: block error for layer %c: %d.\n",
1099 __func__, 'A' + layer, *error);
1101 /* Read Bit Count */
1102 rc = mb86a20s_writereg(state, 0x50, 0xb2 + layer * 2);
1105 rc = mb86a20s_readreg(state, 0x51);
1109 rc = mb86a20s_writereg(state, 0x50, 0xb3 + layer * 2);
1112 rc = mb86a20s_readreg(state, 0x51);
1117 dev_dbg(&state->i2c->dev,
1118 "%s: block count for layer %c: %d.\n",
1119 __func__, 'A' + layer, *count);
1122 * As we get TMCC data from the frontend, we can better estimate the
1123 * BER bit counters, in order to do the BER measure during a longer
1124 * time. Use those data, if available, to update the bit count
1128 if (!state->estimated_rate[layer])
1129 goto reset_measurement;
1131 collect_rate = state->estimated_rate[layer] / 204 / 8;
1132 if (collect_rate < 32)
1134 if (collect_rate > 65535)
1135 collect_rate = 65535;
1137 if (collect_rate != *count) {
1138 dev_dbg(&state->i2c->dev,
1139 "%s: updating PER counter on layer %c to %d.\n",
1140 __func__, 'A' + layer, collect_rate);
1142 /* Stop PER measurement */
1143 rc = mb86a20s_writereg(state, 0x50, 0xb0);
1146 rc = mb86a20s_writereg(state, 0x51, 0x00);
1150 /* Update this layer's counter */
1151 rc = mb86a20s_writereg(state, 0x50, 0xb2 + layer * 2);
1154 rc = mb86a20s_writereg(state, 0x51, collect_rate >> 8);
1157 rc = mb86a20s_writereg(state, 0x50, 0xb3 + layer * 2);
1160 rc = mb86a20s_writereg(state, 0x51, collect_rate & 0xff);
1164 /* start PER measurement */
1165 rc = mb86a20s_writereg(state, 0x50, 0xb0);
1168 rc = mb86a20s_writereg(state, 0x51, 0x07);
1172 /* Reset all counters to collect new data */
1173 rc = mb86a20s_writereg(state, 0x50, 0xb1);
1176 rc = mb86a20s_writereg(state, 0x51, 0x07);
1179 rc = mb86a20s_writereg(state, 0x51, 0x00);
1185 /* Reset counter to collect new data */
1186 rc = mb86a20s_writereg(state, 0x50, 0xb1);
1189 rc = mb86a20s_readreg(state, 0x51);
1193 rc = mb86a20s_writereg(state, 0x51, val | (1 << layer));
1196 rc = mb86a20s_writereg(state, 0x51, val & ~(1 << layer));
1201 struct linear_segments {
1206 * All tables below return a dB/1000 measurement
1209 static struct linear_segments cnr_to_db_table[] = {
1243 static struct linear_segments cnr_64qam_table[] = {
1277 static struct linear_segments cnr_16qam_table[] = {
1311 struct linear_segments cnr_qpsk_table[] = {
1345 static u32 interpolate_value(u32 value, struct linear_segments *segments,
1352 if (value >= segments[0].x)
1353 return segments[0].y;
1354 if (value < segments[len-1].x)
1355 return segments[len-1].y;
1357 for (i = 1; i < len - 1; i++) {
1358 /* If value is identical, no need to interpolate */
1359 if (value == segments[i].x)
1360 return segments[i].y;
1361 if (value > segments[i].x)
1365 /* Linear interpolation between the two (x,y) points */
1366 dy = segments[i].y - segments[i - 1].y;
1367 dx = segments[i - 1].x - segments[i].x;
1368 tmp64 = value - segments[i].x;
1371 ret = segments[i].y - tmp64;
1376 static int mb86a20s_get_main_CNR(struct dvb_frontend *fe)
1378 struct mb86a20s_state *state = fe->demodulator_priv;
1379 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1380 u32 cnr_linear, cnr;
1383 /* Check if CNR is available */
1384 rc = mb86a20s_readreg(state, 0x45);
1389 dev_info(&state->i2c->dev, "%s: CNR is not available yet.\n",
1395 rc = mb86a20s_readreg(state, 0x46);
1398 cnr_linear = rc << 8;
1400 rc = mb86a20s_readreg(state, 0x46);
1405 cnr = interpolate_value(cnr_linear,
1406 cnr_to_db_table, ARRAY_SIZE(cnr_to_db_table));
1408 c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
1409 c->cnr.stat[0].svalue = cnr;
1411 dev_dbg(&state->i2c->dev, "%s: CNR is %d.%03d dB (%d)\n",
1412 __func__, cnr / 1000, cnr % 1000, cnr_linear);
1414 /* CNR counter reset */
1415 rc = mb86a20s_writereg(state, 0x45, val | 0x10);
1418 rc = mb86a20s_writereg(state, 0x45, val & 0x6f);
1423 static int mb86a20s_get_blk_error_layer_CNR(struct dvb_frontend *fe)
1425 struct mb86a20s_state *state = fe->demodulator_priv;
1426 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1429 struct linear_segments *segs;
1432 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1434 /* Check if the measures are already available */
1435 rc = mb86a20s_writereg(state, 0x50, 0x5b);
1438 rc = mb86a20s_readreg(state, 0x51);
1442 /* Check if data is available */
1444 dev_info(&state->i2c->dev,
1445 "%s: MER measures aren't available yet.\n", __func__);
1449 /* Read all layers */
1450 for (i = 0; i < 3; i++) {
1451 if (!(c->isdbt_layer_enabled & (1 << i))) {
1452 c->cnr.stat[1 + i].scale = FE_SCALE_NOT_AVAILABLE;
1456 rc = mb86a20s_writereg(state, 0x50, 0x52 + i * 3);
1459 rc = mb86a20s_readreg(state, 0x51);
1463 rc = mb86a20s_writereg(state, 0x50, 0x53 + i * 3);
1466 rc = mb86a20s_readreg(state, 0x51);
1470 rc = mb86a20s_writereg(state, 0x50, 0x54 + i * 3);
1473 rc = mb86a20s_readreg(state, 0x51);
1478 switch (c->layer[i].modulation) {
1481 segs = cnr_qpsk_table;
1482 segs_len = ARRAY_SIZE(cnr_qpsk_table);
1485 segs = cnr_16qam_table;
1486 segs_len = ARRAY_SIZE(cnr_16qam_table);
1490 segs = cnr_64qam_table;
1491 segs_len = ARRAY_SIZE(cnr_64qam_table);
1494 cnr = interpolate_value(mer, segs, segs_len);
1496 c->cnr.stat[1 + i].scale = FE_SCALE_DECIBEL;
1497 c->cnr.stat[1 + i].svalue = cnr;
1499 dev_dbg(&state->i2c->dev,
1500 "%s: CNR for layer %c is %d.%03d dB (MER = %d).\n",
1501 __func__, 'A' + i, cnr / 1000, cnr % 1000, mer);
1505 /* Start a new MER measurement */
1506 /* MER counter reset */
1507 rc = mb86a20s_writereg(state, 0x50, 0x50);
1510 rc = mb86a20s_readreg(state, 0x51);
1515 rc = mb86a20s_writereg(state, 0x51, val | 0x01);
1518 rc = mb86a20s_writereg(state, 0x51, val & 0x06);
1525 static void mb86a20s_stats_not_ready(struct dvb_frontend *fe)
1527 struct mb86a20s_state *state = fe->demodulator_priv;
1528 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1531 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1533 /* Fill the length of each status counter */
1535 /* Only global stats */
1536 c->strength.len = 1;
1538 /* Per-layer stats - 3 layers + global */
1540 c->pre_bit_error.len = 4;
1541 c->pre_bit_count.len = 4;
1542 c->post_bit_error.len = 4;
1543 c->post_bit_count.len = 4;
1544 c->block_error.len = 4;
1545 c->block_count.len = 4;
1547 /* Signal is always available */
1548 c->strength.stat[0].scale = FE_SCALE_RELATIVE;
1549 c->strength.stat[0].uvalue = 0;
1551 /* Put all of them at FE_SCALE_NOT_AVAILABLE */
1552 for (i = 0; i < 4; i++) {
1553 c->cnr.stat[i].scale = FE_SCALE_NOT_AVAILABLE;
1554 c->pre_bit_error.stat[i].scale = FE_SCALE_NOT_AVAILABLE;
1555 c->pre_bit_count.stat[i].scale = FE_SCALE_NOT_AVAILABLE;
1556 c->post_bit_error.stat[i].scale = FE_SCALE_NOT_AVAILABLE;
1557 c->post_bit_count.stat[i].scale = FE_SCALE_NOT_AVAILABLE;
1558 c->block_error.stat[i].scale = FE_SCALE_NOT_AVAILABLE;
1559 c->block_count.stat[i].scale = FE_SCALE_NOT_AVAILABLE;
1563 static int mb86a20s_get_stats(struct dvb_frontend *fe)
1565 struct mb86a20s_state *state = fe->demodulator_priv;
1566 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1568 u32 bit_error = 0, bit_count = 0;
1569 u32 t_pre_bit_error = 0, t_pre_bit_count = 0;
1570 u32 t_post_bit_error = 0, t_post_bit_count = 0;
1571 u32 block_error = 0, block_count = 0;
1572 u32 t_block_error = 0, t_block_count = 0;
1573 int active_layers = 0, pre_ber_layers = 0, post_ber_layers = 0;
1576 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1578 mb86a20s_get_main_CNR(fe);
1580 /* Get per-layer stats */
1581 mb86a20s_get_blk_error_layer_CNR(fe);
1583 for (i = 0; i < 3; i++) {
1584 if (c->isdbt_layer_enabled & (1 << i)) {
1585 /* Layer is active and has rc segments */
1588 /* Handle BER before vterbi */
1589 rc = mb86a20s_get_pre_ber(fe, i,
1590 &bit_error, &bit_count);
1592 c->pre_bit_error.stat[1 + i].scale = FE_SCALE_COUNTER;
1593 c->pre_bit_error.stat[1 + i].uvalue += bit_error;
1594 c->pre_bit_count.stat[1 + i].scale = FE_SCALE_COUNTER;
1595 c->pre_bit_count.stat[1 + i].uvalue += bit_count;
1596 } else if (rc != -EBUSY) {
1598 * If an I/O error happened,
1599 * measures are now unavailable
1601 c->pre_bit_error.stat[1 + i].scale = FE_SCALE_NOT_AVAILABLE;
1602 c->pre_bit_count.stat[1 + i].scale = FE_SCALE_NOT_AVAILABLE;
1603 dev_err(&state->i2c->dev,
1604 "%s: Can't get BER for layer %c (error %d).\n",
1605 __func__, 'A' + i, rc);
1607 if (c->block_error.stat[1 + i].scale != FE_SCALE_NOT_AVAILABLE)
1610 /* Handle BER post vterbi */
1611 rc = mb86a20s_get_post_ber(fe, i,
1612 &bit_error, &bit_count);
1614 c->post_bit_error.stat[1 + i].scale = FE_SCALE_COUNTER;
1615 c->post_bit_error.stat[1 + i].uvalue += bit_error;
1616 c->post_bit_count.stat[1 + i].scale = FE_SCALE_COUNTER;
1617 c->post_bit_count.stat[1 + i].uvalue += bit_count;
1618 } else if (rc != -EBUSY) {
1620 * If an I/O error happened,
1621 * measures are now unavailable
1623 c->post_bit_error.stat[1 + i].scale = FE_SCALE_NOT_AVAILABLE;
1624 c->post_bit_count.stat[1 + i].scale = FE_SCALE_NOT_AVAILABLE;
1625 dev_err(&state->i2c->dev,
1626 "%s: Can't get BER for layer %c (error %d).\n",
1627 __func__, 'A' + i, rc);
1629 if (c->block_error.stat[1 + i].scale != FE_SCALE_NOT_AVAILABLE)
1632 /* Handle Block errors for PER/UCB reports */
1633 rc = mb86a20s_get_blk_error(fe, i,
1637 c->block_error.stat[1 + i].scale = FE_SCALE_COUNTER;
1638 c->block_error.stat[1 + i].uvalue += block_error;
1639 c->block_count.stat[1 + i].scale = FE_SCALE_COUNTER;
1640 c->block_count.stat[1 + i].uvalue += block_count;
1641 } else if (rc != -EBUSY) {
1643 * If an I/O error happened,
1644 * measures are now unavailable
1646 c->block_error.stat[1 + i].scale = FE_SCALE_NOT_AVAILABLE;
1647 c->block_count.stat[1 + i].scale = FE_SCALE_NOT_AVAILABLE;
1648 dev_err(&state->i2c->dev,
1649 "%s: Can't get PER for layer %c (error %d).\n",
1650 __func__, 'A' + i, rc);
1653 if (c->block_error.stat[1 + i].scale != FE_SCALE_NOT_AVAILABLE)
1656 /* Update total preBER */
1657 t_pre_bit_error += c->pre_bit_error.stat[1 + i].uvalue;
1658 t_pre_bit_count += c->pre_bit_count.stat[1 + i].uvalue;
1660 /* Update total postBER */
1661 t_post_bit_error += c->post_bit_error.stat[1 + i].uvalue;
1662 t_post_bit_count += c->post_bit_count.stat[1 + i].uvalue;
1664 /* Update total PER */
1665 t_block_error += c->block_error.stat[1 + i].uvalue;
1666 t_block_count += c->block_count.stat[1 + i].uvalue;
1671 * Start showing global count if at least one error count is
1674 if (pre_ber_layers) {
1676 * At least one per-layer BER measure was read. We can now
1677 * calculate the total BER
1679 * Total Bit Error/Count is calculated as the sum of the
1680 * bit errors on all active layers.
1682 c->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER;
1683 c->pre_bit_error.stat[0].uvalue = t_pre_bit_error;
1684 c->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER;
1685 c->pre_bit_count.stat[0].uvalue = t_pre_bit_count;
1687 c->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1688 c->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER;
1692 * Start showing global count if at least one error count is
1695 if (post_ber_layers) {
1697 * At least one per-layer BER measure was read. We can now
1698 * calculate the total BER
1700 * Total Bit Error/Count is calculated as the sum of the
1701 * bit errors on all active layers.
1703 c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
1704 c->post_bit_error.stat[0].uvalue = t_post_bit_error;
1705 c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
1706 c->post_bit_count.stat[0].uvalue = t_post_bit_count;
1708 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1709 c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
1714 * At least one per-layer UCB measure was read. We can now
1715 * calculate the total UCB
1717 * Total block Error/Count is calculated as the sum of the
1718 * block errors on all active layers.
1720 c->block_error.stat[0].scale = FE_SCALE_COUNTER;
1721 c->block_error.stat[0].uvalue = t_block_error;
1722 c->block_count.stat[0].scale = FE_SCALE_COUNTER;
1723 c->block_count.stat[0].uvalue = t_block_count;
1725 c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1726 c->block_count.stat[0].scale = FE_SCALE_COUNTER;
1733 * The functions below are called via DVB callbacks, so they need to
1734 * properly use the I2C gate control
1737 static int mb86a20s_initfe(struct dvb_frontend *fe)
1739 struct mb86a20s_state *state = fe->demodulator_priv;
1743 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1745 if (fe->ops.i2c_gate_ctrl)
1746 fe->ops.i2c_gate_ctrl(fe, 0);
1748 /* Initialize the frontend */
1749 rc = mb86a20s_writeregdata(state, mb86a20s_init);
1753 if (!state->config->is_serial) {
1756 rc = mb86a20s_writereg(state, 0x50, 0xd5);
1759 rc = mb86a20s_writereg(state, 0x51, regD5);
1765 if (fe->ops.i2c_gate_ctrl)
1766 fe->ops.i2c_gate_ctrl(fe, 1);
1769 state->need_init = true;
1770 dev_info(&state->i2c->dev,
1771 "mb86a20s: Init failed. Will try again later\n");
1773 state->need_init = false;
1774 dev_dbg(&state->i2c->dev, "Initialization succeeded.\n");
1779 static int mb86a20s_set_frontend(struct dvb_frontend *fe)
1781 struct mb86a20s_state *state = fe->demodulator_priv;
1785 * FIXME: Properly implement the set frontend properties
1787 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1789 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1792 * Gate should already be opened, but it doesn't hurt to
1795 if (fe->ops.i2c_gate_ctrl)
1796 fe->ops.i2c_gate_ctrl(fe, 1);
1797 fe->ops.tuner_ops.set_params(fe);
1800 * Make it more reliable: if, for some reason, the initial
1801 * device initialization doesn't happen, initialize it when
1802 * a SBTVD parameters are adjusted.
1804 * Unfortunately, due to a hard to track bug at tda829x/tda18271,
1805 * the agc callback logic is not called during DVB attach time,
1806 * causing mb86a20s to not be initialized with Kworld SBTVD.
1807 * So, this hack is needed, in order to make Kworld SBTVD to work.
1809 if (state->need_init)
1810 mb86a20s_initfe(fe);
1812 if (fe->ops.i2c_gate_ctrl)
1813 fe->ops.i2c_gate_ctrl(fe, 0);
1815 rc = mb86a20s_writeregdata(state, mb86a20s_reset_reception);
1816 mb86a20s_reset_counters(fe);
1818 if (fe->ops.i2c_gate_ctrl)
1819 fe->ops.i2c_gate_ctrl(fe, 1);
1824 static int mb86a20s_read_status_and_stats(struct dvb_frontend *fe,
1825 fe_status_t *status)
1827 struct mb86a20s_state *state = fe->demodulator_priv;
1828 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1831 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1833 if (fe->ops.i2c_gate_ctrl)
1834 fe->ops.i2c_gate_ctrl(fe, 0);
1837 rc = mb86a20s_read_status(fe, status);
1838 if (!(*status & FE_HAS_LOCK)) {
1839 mb86a20s_stats_not_ready(fe);
1840 mb86a20s_reset_frontend_cache(fe);
1843 dev_err(&state->i2c->dev,
1844 "%s: Can't read frontend lock status\n", __func__);
1848 /* Get signal strength */
1849 rc = mb86a20s_read_signal_strength(fe);
1851 dev_err(&state->i2c->dev,
1852 "%s: Can't reset VBER registers.\n", __func__);
1853 mb86a20s_stats_not_ready(fe);
1854 mb86a20s_reset_frontend_cache(fe);
1856 rc = 0; /* Status is OK */
1859 /* Fill signal strength */
1860 c->strength.stat[0].uvalue = rc;
1862 if (*status & FE_HAS_LOCK) {
1864 rc = mb86a20s_get_frontend(fe);
1866 dev_err(&state->i2c->dev,
1867 "%s: Can't get FE TMCC data.\n", __func__);
1868 rc = 0; /* Status is OK */
1872 /* Get statistics */
1873 rc = mb86a20s_get_stats(fe);
1874 if (rc < 0 && rc != -EBUSY) {
1875 dev_err(&state->i2c->dev,
1876 "%s: Can't get FE statistics.\n", __func__);
1880 rc = 0; /* Don't return EBUSY to userspace */
1885 mb86a20s_stats_not_ready(fe);
1888 if (fe->ops.i2c_gate_ctrl)
1889 fe->ops.i2c_gate_ctrl(fe, 1);
1894 static int mb86a20s_read_signal_strength_from_cache(struct dvb_frontend *fe,
1897 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1900 *strength = c->strength.stat[0].uvalue;
1905 static int mb86a20s_get_frontend_dummy(struct dvb_frontend *fe)
1908 * get_frontend is now handled together with other stats
1909 * retrival, when read_status() is called, as some statistics
1910 * will depend on the layers detection.
1915 static int mb86a20s_tune(struct dvb_frontend *fe,
1917 unsigned int mode_flags,
1918 unsigned int *delay,
1919 fe_status_t *status)
1921 struct mb86a20s_state *state = fe->demodulator_priv;
1924 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1927 rc = mb86a20s_set_frontend(fe);
1929 if (!(mode_flags & FE_TUNE_MODE_ONESHOT))
1930 mb86a20s_read_status_and_stats(fe, status);
1935 static void mb86a20s_release(struct dvb_frontend *fe)
1937 struct mb86a20s_state *state = fe->demodulator_priv;
1939 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1944 static struct dvb_frontend_ops mb86a20s_ops;
1946 struct dvb_frontend *mb86a20s_attach(const struct mb86a20s_config *config,
1947 struct i2c_adapter *i2c)
1949 struct mb86a20s_state *state;
1952 dev_dbg(&i2c->dev, "%s called.\n", __func__);
1954 /* allocate memory for the internal state */
1955 state = kzalloc(sizeof(struct mb86a20s_state), GFP_KERNEL);
1956 if (state == NULL) {
1958 "%s: unable to allocate memory for state\n", __func__);
1962 /* setup the state */
1963 state->config = config;
1966 /* create dvb_frontend */
1967 memcpy(&state->frontend.ops, &mb86a20s_ops,
1968 sizeof(struct dvb_frontend_ops));
1969 state->frontend.demodulator_priv = state;
1971 /* Check if it is a mb86a20s frontend */
1972 rev = mb86a20s_readreg(state, 0);
1976 "Detected a Fujitsu mb86a20s frontend\n");
1979 "Frontend revision %d is unknown - aborting.\n",
1984 return &state->frontend;
1990 EXPORT_SYMBOL(mb86a20s_attach);
1992 static struct dvb_frontend_ops mb86a20s_ops = {
1993 .delsys = { SYS_ISDBT },
1994 /* Use dib8000 values per default */
1996 .name = "Fujitsu mb86A20s",
1997 .caps = FE_CAN_INVERSION_AUTO | FE_CAN_RECOVER |
1998 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
1999 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
2000 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 |
2001 FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_QAM_AUTO |
2002 FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_HIERARCHY_AUTO,
2003 /* Actually, those values depend on the used tuner */
2004 .frequency_min = 45000000,
2005 .frequency_max = 864000000,
2006 .frequency_stepsize = 62500,
2009 .release = mb86a20s_release,
2011 .init = mb86a20s_initfe,
2012 .set_frontend = mb86a20s_set_frontend,
2013 .get_frontend = mb86a20s_get_frontend_dummy,
2014 .read_status = mb86a20s_read_status_and_stats,
2015 .read_signal_strength = mb86a20s_read_signal_strength_from_cache,
2016 .tune = mb86a20s_tune,
2019 MODULE_DESCRIPTION("DVB Frontend module for Fujitsu mb86A20s hardware");
2020 MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>");
2021 MODULE_LICENSE("GPL");