2 * Fujitu mb86a20s ISDB-T/ISDB-Tsb Module driver
4 * Copyright (C) 2010-2013 Mauro Carvalho Chehab
5 * Copyright (C) 2009-2010 Douglas Landgraf <dougsland@redhat.com>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation version 2.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
17 #include <linux/kernel.h>
18 #include <asm/div64.h>
20 #include "dvb_frontend.h"
25 enum mb86a20s_bandwidth {
27 MB86A20S_13SEG_PARTIAL = 1,
32 static u8 mb86a20s_subchannel[] = {
33 0xb0, 0xc0, 0xd0, 0xe0,
34 0xf0, 0x00, 0x10, 0x20,
37 struct mb86a20s_state {
38 struct i2c_adapter *i2c;
39 const struct mb86a20s_config *config;
42 struct dvb_frontend frontend;
45 enum mb86a20s_bandwidth bw;
49 u32 estimated_rate[NUM_LAYERS];
50 unsigned long get_strength_time;
60 #define BER_SAMPLING_RATE 1 /* Seconds */
63 * Initialization sequence: Use whatevere default values that PV SBTVD
64 * does on its initialisation, obtained via USB snoop
66 static struct regdata mb86a20s_init1[] = {
70 { 0x50, 0xd1 }, { 0x51, 0x20 },
73 static struct regdata mb86a20s_init2[] = {
74 { 0x50, 0xd1 }, { 0x51, 0x22 },
80 { 0x04, 0x08 }, { 0x05, 0x05 },
81 { 0x04, 0x0e }, { 0x05, 0x00 },
82 { 0x04, 0x0f }, { 0x05, 0x14 },
83 { 0x04, 0x0b }, { 0x05, 0x8c },
84 { 0x04, 0x00 }, { 0x05, 0x00 },
85 { 0x04, 0x01 }, { 0x05, 0x07 },
86 { 0x04, 0x02 }, { 0x05, 0x0f },
87 { 0x04, 0x03 }, { 0x05, 0xa0 },
88 { 0x04, 0x09 }, { 0x05, 0x00 },
89 { 0x04, 0x0a }, { 0x05, 0xff },
90 { 0x04, 0x27 }, { 0x05, 0x64 },
91 { 0x04, 0x28 }, { 0x05, 0x00 },
92 { 0x04, 0x1e }, { 0x05, 0xff },
93 { 0x04, 0x29 }, { 0x05, 0x0a },
94 { 0x04, 0x32 }, { 0x05, 0x0a },
95 { 0x04, 0x14 }, { 0x05, 0x02 },
96 { 0x04, 0x04 }, { 0x05, 0x00 },
97 { 0x04, 0x05 }, { 0x05, 0x22 },
98 { 0x04, 0x06 }, { 0x05, 0x0e },
99 { 0x04, 0x07 }, { 0x05, 0xd8 },
100 { 0x04, 0x12 }, { 0x05, 0x00 },
101 { 0x04, 0x13 }, { 0x05, 0xff },
104 * On this demod, when the bit count reaches the count below,
105 * it collects the bit error count. The bit counters are initialized
106 * to 65535 here. This warrants that all of them will be quickly
107 * calculated when device gets locked. As TMCC is parsed, the values
108 * will be adjusted later in the driver's code.
110 { 0x52, 0x01 }, /* Turn on BER before Viterbi */
111 { 0x50, 0xa7 }, { 0x51, 0x00 },
112 { 0x50, 0xa8 }, { 0x51, 0xff },
113 { 0x50, 0xa9 }, { 0x51, 0xff },
114 { 0x50, 0xaa }, { 0x51, 0x00 },
115 { 0x50, 0xab }, { 0x51, 0xff },
116 { 0x50, 0xac }, { 0x51, 0xff },
117 { 0x50, 0xad }, { 0x51, 0x00 },
118 { 0x50, 0xae }, { 0x51, 0xff },
119 { 0x50, 0xaf }, { 0x51, 0xff },
122 * On this demod, post BER counts blocks. When the count reaches the
123 * value below, it collects the block error count. The block counters
124 * are initialized to 127 here. This warrants that all of them will be
125 * quickly calculated when device gets locked. As TMCC is parsed, the
126 * values will be adjusted later in the driver's code.
128 { 0x5e, 0x07 }, /* Turn on BER after Viterbi */
129 { 0x50, 0xdc }, { 0x51, 0x00 },
130 { 0x50, 0xdd }, { 0x51, 0x7f },
131 { 0x50, 0xde }, { 0x51, 0x00 },
132 { 0x50, 0xdf }, { 0x51, 0x7f },
133 { 0x50, 0xe0 }, { 0x51, 0x00 },
134 { 0x50, 0xe1 }, { 0x51, 0x7f },
137 * On this demod, when the block count reaches the count below,
138 * it collects the block error count. The block counters are initialized
139 * to 127 here. This warrants that all of them will be quickly
140 * calculated when device gets locked. As TMCC is parsed, the values
141 * will be adjusted later in the driver's code.
143 { 0x50, 0xb0 }, { 0x51, 0x07 }, /* Enable PER */
144 { 0x50, 0xb2 }, { 0x51, 0x00 },
145 { 0x50, 0xb3 }, { 0x51, 0x7f },
146 { 0x50, 0xb4 }, { 0x51, 0x00 },
147 { 0x50, 0xb5 }, { 0x51, 0x7f },
148 { 0x50, 0xb6 }, { 0x51, 0x00 },
149 { 0x50, 0xb7 }, { 0x51, 0x7f },
151 { 0x50, 0x50 }, { 0x51, 0x02 }, /* MER manual mode */
152 { 0x50, 0x51 }, { 0x51, 0x04 }, /* MER symbol 4 */
153 { 0x45, 0x04 }, /* CN symbol 4 */
154 { 0x48, 0x04 }, /* CN manual mode */
155 { 0x50, 0xd5 }, { 0x51, 0x01 },
156 { 0x50, 0xd6 }, { 0x51, 0x1f },
157 { 0x50, 0xd2 }, { 0x51, 0x03 },
158 { 0x50, 0xd7 }, { 0x51, 0x3f },
160 { 0x28, 0x06 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x03 },
161 { 0x28, 0x07 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x0d },
162 { 0x28, 0x08 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x02 },
163 { 0x28, 0x09 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x01 },
164 { 0x28, 0x0a }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x21 },
165 { 0x28, 0x0b }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x29 },
166 { 0x28, 0x0c }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x16 },
167 { 0x28, 0x0d }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x31 },
168 { 0x28, 0x0e }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x0e },
169 { 0x28, 0x0f }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x4e },
170 { 0x28, 0x10 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x46 },
171 { 0x28, 0x11 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x0f },
172 { 0x28, 0x12 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x56 },
173 { 0x28, 0x13 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x35 },
174 { 0x28, 0x14 }, { 0x29, 0x00 }, { 0x2a, 0x01 }, { 0x2b, 0xbe },
175 { 0x28, 0x15 }, { 0x29, 0x00 }, { 0x2a, 0x01 }, { 0x2b, 0x84 },
176 { 0x28, 0x16 }, { 0x29, 0x00 }, { 0x2a, 0x03 }, { 0x2b, 0xee },
177 { 0x28, 0x17 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x98 },
178 { 0x28, 0x18 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x9f },
179 { 0x28, 0x19 }, { 0x29, 0x00 }, { 0x2a, 0x07 }, { 0x2b, 0xb2 },
180 { 0x28, 0x1a }, { 0x29, 0x00 }, { 0x2a, 0x06 }, { 0x2b, 0xc2 },
181 { 0x28, 0x1b }, { 0x29, 0x00 }, { 0x2a, 0x07 }, { 0x2b, 0x4a },
182 { 0x28, 0x1c }, { 0x29, 0x00 }, { 0x2a, 0x01 }, { 0x2b, 0xbc },
183 { 0x28, 0x1d }, { 0x29, 0x00 }, { 0x2a, 0x04 }, { 0x2b, 0xba },
184 { 0x28, 0x1e }, { 0x29, 0x00 }, { 0x2a, 0x06 }, { 0x2b, 0x14 },
185 { 0x50, 0x1e }, { 0x51, 0x5d },
186 { 0x50, 0x22 }, { 0x51, 0x00 },
187 { 0x50, 0x23 }, { 0x51, 0xc8 },
188 { 0x50, 0x24 }, { 0x51, 0x00 },
189 { 0x50, 0x25 }, { 0x51, 0xf0 },
190 { 0x50, 0x26 }, { 0x51, 0x00 },
191 { 0x50, 0x27 }, { 0x51, 0xc3 },
192 { 0x50, 0x39 }, { 0x51, 0x02 },
193 { 0x50, 0xd5 }, { 0x51, 0x01 },
197 static struct regdata mb86a20s_reset_reception[] = {
204 static struct regdata mb86a20s_per_ber_reset[] = {
205 { 0x53, 0x00 }, /* pre BER Counter reset */
208 { 0x5f, 0x00 }, /* post BER Counter reset */
211 { 0x50, 0xb1 }, /* PER Counter reset */
217 * I2C read/write functions and macros
220 static int mb86a20s_i2c_writereg(struct mb86a20s_state *state,
221 u8 i2c_addr, u8 reg, u8 data)
223 u8 buf[] = { reg, data };
224 struct i2c_msg msg = {
225 .addr = i2c_addr, .flags = 0, .buf = buf, .len = 2
229 rc = i2c_transfer(state->i2c, &msg, 1);
231 dev_err(&state->i2c->dev,
232 "%s: writereg error (rc == %i, reg == 0x%02x, data == 0x%02x)\n",
233 __func__, rc, reg, data);
240 static int mb86a20s_i2c_writeregdata(struct mb86a20s_state *state,
241 u8 i2c_addr, struct regdata *rd, int size)
245 for (i = 0; i < size; i++) {
246 rc = mb86a20s_i2c_writereg(state, i2c_addr, rd[i].reg,
254 static int mb86a20s_i2c_readreg(struct mb86a20s_state *state,
259 struct i2c_msg msg[] = {
260 { .addr = i2c_addr, .flags = 0, .buf = ®, .len = 1 },
261 { .addr = i2c_addr, .flags = I2C_M_RD, .buf = &val, .len = 1 }
264 rc = i2c_transfer(state->i2c, msg, 2);
267 dev_err(&state->i2c->dev, "%s: reg=0x%x (error=%d)\n",
269 return (rc < 0) ? rc : -EIO;
275 #define mb86a20s_readreg(state, reg) \
276 mb86a20s_i2c_readreg(state, state->config->demod_address, reg)
277 #define mb86a20s_writereg(state, reg, val) \
278 mb86a20s_i2c_writereg(state, state->config->demod_address, reg, val)
279 #define mb86a20s_writeregdata(state, regdata) \
280 mb86a20s_i2c_writeregdata(state, state->config->demod_address, \
281 regdata, ARRAY_SIZE(regdata))
284 * Ancillary internal routines (likely compiled inlined)
286 * The functions below assume that gateway lock has already obtained
289 static int mb86a20s_read_status(struct dvb_frontend *fe, enum fe_status *status)
291 struct mb86a20s_state *state = fe->demodulator_priv;
296 val = mb86a20s_readreg(state, 0x0a) & 0xf;
301 *status |= FE_HAS_SIGNAL;
304 *status |= FE_HAS_CARRIER;
307 *status |= FE_HAS_VITERBI;
310 *status |= FE_HAS_SYNC;
313 * Actually, on state S8, it starts receiving TS, but the TS
314 * output is only on normal state after the transition to S9.
317 *status |= FE_HAS_LOCK;
319 dev_dbg(&state->i2c->dev, "%s: Status = 0x%02x (state = %d)\n",
320 __func__, *status, val);
325 static int mb86a20s_read_signal_strength(struct dvb_frontend *fe)
327 struct mb86a20s_state *state = fe->demodulator_priv;
328 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
330 unsigned rf_max, rf_min, rf;
332 if (state->get_strength_time &&
333 (!time_after(jiffies, state->get_strength_time)))
334 return c->strength.stat[0].uvalue;
336 /* Reset its value if an error happen */
337 c->strength.stat[0].uvalue = 0;
339 /* Does a binary search to get RF strength */
343 rf = (rf_max + rf_min) / 2;
344 rc = mb86a20s_writereg(state, 0x04, 0x1f);
347 rc = mb86a20s_writereg(state, 0x05, rf >> 8);
350 rc = mb86a20s_writereg(state, 0x04, 0x20);
353 rc = mb86a20s_writereg(state, 0x05, rf);
357 rc = mb86a20s_readreg(state, 0x02);
361 rf_min = (rf_max + rf_min) / 2;
363 rf_max = (rf_max + rf_min) / 2;
364 if (rf_max - rf_min < 4) {
365 rf = (rf_max + rf_min) / 2;
367 /* Rescale it from 2^12 (4096) to 2^16 */
368 rf = rf << (16 - 12);
372 dev_dbg(&state->i2c->dev,
373 "%s: signal strength = %d (%d < RF=%d < %d)\n",
374 __func__, rf, rf_min, rf >> 4, rf_max);
375 c->strength.stat[0].uvalue = rf;
376 state->get_strength_time = jiffies +
377 msecs_to_jiffies(1000);
383 static int mb86a20s_get_modulation(struct mb86a20s_state *state,
387 static unsigned char reg[] = {
388 [0] = 0x86, /* Layer A */
389 [1] = 0x8a, /* Layer B */
390 [2] = 0x8e, /* Layer C */
393 if (layer >= ARRAY_SIZE(reg))
395 rc = mb86a20s_writereg(state, 0x6d, reg[layer]);
398 rc = mb86a20s_readreg(state, 0x6e);
401 switch ((rc >> 4) & 0x07) {
415 static int mb86a20s_get_fec(struct mb86a20s_state *state,
420 static unsigned char reg[] = {
421 [0] = 0x87, /* Layer A */
422 [1] = 0x8b, /* Layer B */
423 [2] = 0x8f, /* Layer C */
426 if (layer >= ARRAY_SIZE(reg))
428 rc = mb86a20s_writereg(state, 0x6d, reg[layer]);
431 rc = mb86a20s_readreg(state, 0x6e);
434 switch ((rc >> 4) & 0x07) {
450 static int mb86a20s_get_interleaving(struct mb86a20s_state *state,
454 int interleaving[] = {
458 static unsigned char reg[] = {
459 [0] = 0x88, /* Layer A */
460 [1] = 0x8c, /* Layer B */
461 [2] = 0x90, /* Layer C */
464 if (layer >= ARRAY_SIZE(reg))
466 rc = mb86a20s_writereg(state, 0x6d, reg[layer]);
469 rc = mb86a20s_readreg(state, 0x6e);
473 return interleaving[(rc >> 4) & 0x07];
476 static int mb86a20s_get_segment_count(struct mb86a20s_state *state,
480 static unsigned char reg[] = {
481 [0] = 0x89, /* Layer A */
482 [1] = 0x8d, /* Layer B */
483 [2] = 0x91, /* Layer C */
486 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
488 if (layer >= ARRAY_SIZE(reg))
491 rc = mb86a20s_writereg(state, 0x6d, reg[layer]);
494 rc = mb86a20s_readreg(state, 0x6e);
497 count = (rc >> 4) & 0x0f;
499 dev_dbg(&state->i2c->dev, "%s: segments: %d.\n", __func__, count);
504 static void mb86a20s_reset_frontend_cache(struct dvb_frontend *fe)
506 struct mb86a20s_state *state = fe->demodulator_priv;
507 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
509 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
511 /* Fixed parameters */
512 c->delivery_system = SYS_ISDBT;
513 c->bandwidth_hz = 6000000;
515 /* Initialize values that will be later autodetected */
516 c->isdbt_layer_enabled = 0;
517 c->transmission_mode = TRANSMISSION_MODE_AUTO;
518 c->guard_interval = GUARD_INTERVAL_AUTO;
519 c->isdbt_sb_mode = 0;
520 c->isdbt_sb_segment_count = 0;
524 * Estimates the bit rate using the per-segment bit rate given by
525 * ABNT/NBR 15601 spec (table 4).
527 static u32 isdbt_rate[3][5][4] = {
529 { 280850, 312060, 330420, 340430 }, /* 1/2 */
530 { 374470, 416080, 440560, 453910 }, /* 2/3 */
531 { 421280, 468090, 495630, 510650 }, /* 3/4 */
532 { 468090, 520100, 550700, 567390 }, /* 5/6 */
533 { 491500, 546110, 578230, 595760 }, /* 7/8 */
535 { 561710, 624130, 660840, 680870 }, /* 1/2 */
536 { 748950, 832170, 881120, 907820 }, /* 2/3 */
537 { 842570, 936190, 991260, 1021300 }, /* 3/4 */
538 { 936190, 1040210, 1101400, 1134780 }, /* 5/6 */
539 { 983000, 1092220, 1156470, 1191520 }, /* 7/8 */
541 { 842570, 936190, 991260, 1021300 }, /* 1/2 */
542 { 1123430, 1248260, 1321680, 1361740 }, /* 2/3 */
543 { 1263860, 1404290, 1486900, 1531950 }, /* 3/4 */
544 { 1404290, 1560320, 1652110, 1702170 }, /* 5/6 */
545 { 1474500, 1638340, 1734710, 1787280 }, /* 7/8 */
549 static void mb86a20s_layer_bitrate(struct dvb_frontend *fe, u32 layer,
550 u32 modulation, u32 forward_error_correction,
554 struct mb86a20s_state *state = fe->demodulator_priv;
559 * If modulation/fec/guard is not detected, the default is
560 * to consider the lowest bit rate, to avoid taking too long time
563 switch (modulation) {
577 switch (forward_error_correction) {
597 switch (guard_interval) {
599 case GUARD_INTERVAL_1_4:
602 case GUARD_INTERVAL_1_8:
605 case GUARD_INTERVAL_1_16:
608 case GUARD_INTERVAL_1_32:
613 /* Samples BER at BER_SAMPLING_RATE seconds */
614 rate = isdbt_rate[mod][fec][guard] * segment * BER_SAMPLING_RATE;
616 /* Avoids sampling too quickly or to overflow the register */
619 else if (rate > (1 << 24) - 1)
620 rate = (1 << 24) - 1;
622 dev_dbg(&state->i2c->dev,
623 "%s: layer %c bitrate: %d kbps; counter = %d (0x%06x)\n",
624 __func__, 'A' + layer,
625 segment * isdbt_rate[mod][fec][guard]/1000,
628 state->estimated_rate[layer] = rate;
631 static int mb86a20s_get_frontend(struct dvb_frontend *fe)
633 struct mb86a20s_state *state = fe->demodulator_priv;
634 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
637 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
639 /* Reset frontend cache to default values */
640 mb86a20s_reset_frontend_cache(fe);
642 /* Check for partial reception */
643 rc = mb86a20s_writereg(state, 0x6d, 0x85);
646 rc = mb86a20s_readreg(state, 0x6e);
649 c->isdbt_partial_reception = (rc & 0x10) ? 1 : 0;
651 /* Get per-layer data */
653 for (layer = 0; layer < NUM_LAYERS; layer++) {
654 dev_dbg(&state->i2c->dev, "%s: getting data for layer %c.\n",
655 __func__, 'A' + layer);
657 rc = mb86a20s_get_segment_count(state, layer);
659 goto noperlayer_error;
660 if (rc >= 0 && rc < 14) {
661 c->layer[layer].segment_count = rc;
663 c->layer[layer].segment_count = 0;
664 state->estimated_rate[layer] = 0;
667 c->isdbt_layer_enabled |= 1 << layer;
668 rc = mb86a20s_get_modulation(state, layer);
670 goto noperlayer_error;
671 dev_dbg(&state->i2c->dev, "%s: modulation %d.\n",
673 c->layer[layer].modulation = rc;
674 rc = mb86a20s_get_fec(state, layer);
676 goto noperlayer_error;
677 dev_dbg(&state->i2c->dev, "%s: FEC %d.\n",
679 c->layer[layer].fec = rc;
680 rc = mb86a20s_get_interleaving(state, layer);
682 goto noperlayer_error;
683 dev_dbg(&state->i2c->dev, "%s: interleaving %d.\n",
685 c->layer[layer].interleaving = rc;
686 mb86a20s_layer_bitrate(fe, layer, c->layer[layer].modulation,
689 c->layer[layer].segment_count);
692 rc = mb86a20s_writereg(state, 0x6d, 0x84);
695 if ((rc & 0x60) == 0x20) {
696 c->isdbt_sb_mode = 1;
697 /* At least, one segment should exist */
698 if (!c->isdbt_sb_segment_count)
699 c->isdbt_sb_segment_count = 1;
702 /* Get transmission mode and guard interval */
703 rc = mb86a20s_readreg(state, 0x07);
706 c->transmission_mode = TRANSMISSION_MODE_AUTO;
707 if ((rc & 0x60) == 0x20) {
708 /* Only modes 2 and 3 are supported */
709 switch ((rc >> 2) & 0x03) {
711 c->transmission_mode = TRANSMISSION_MODE_4K;
714 c->transmission_mode = TRANSMISSION_MODE_8K;
718 c->guard_interval = GUARD_INTERVAL_AUTO;
720 /* Guard interval 1/32 is not supported */
723 c->guard_interval = GUARD_INTERVAL_1_4;
726 c->guard_interval = GUARD_INTERVAL_1_8;
729 c->guard_interval = GUARD_INTERVAL_1_16;
737 /* per-layer info is incomplete; discard all per-layer */
738 c->isdbt_layer_enabled = 0;
743 static int mb86a20s_reset_counters(struct dvb_frontend *fe)
745 struct mb86a20s_state *state = fe->demodulator_priv;
746 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
749 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
751 /* Reset the counters, if the channel changed */
752 if (state->last_frequency != c->frequency) {
753 memset(&c->cnr, 0, sizeof(c->cnr));
754 memset(&c->pre_bit_error, 0, sizeof(c->pre_bit_error));
755 memset(&c->pre_bit_count, 0, sizeof(c->pre_bit_count));
756 memset(&c->post_bit_error, 0, sizeof(c->post_bit_error));
757 memset(&c->post_bit_count, 0, sizeof(c->post_bit_count));
758 memset(&c->block_error, 0, sizeof(c->block_error));
759 memset(&c->block_count, 0, sizeof(c->block_count));
761 state->last_frequency = c->frequency;
764 /* Clear status for most stats */
766 /* BER/PER counter reset */
767 rc = mb86a20s_writeregdata(state, mb86a20s_per_ber_reset);
771 /* CNR counter reset */
772 rc = mb86a20s_readreg(state, 0x45);
776 rc = mb86a20s_writereg(state, 0x45, val | 0x10);
779 rc = mb86a20s_writereg(state, 0x45, val & 0x6f);
783 /* MER counter reset */
784 rc = mb86a20s_writereg(state, 0x50, 0x50);
787 rc = mb86a20s_readreg(state, 0x51);
791 rc = mb86a20s_writereg(state, 0x51, val | 0x01);
794 rc = mb86a20s_writereg(state, 0x51, val & 0x06);
800 dev_err(&state->i2c->dev,
801 "%s: Can't reset FE statistics (error %d).\n",
807 static int mb86a20s_get_pre_ber(struct dvb_frontend *fe,
809 u32 *error, u32 *count)
811 struct mb86a20s_state *state = fe->demodulator_priv;
814 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
816 if (layer >= NUM_LAYERS)
819 /* Check if the BER measures are already available */
820 rc = mb86a20s_readreg(state, 0x54);
824 /* Check if data is available for that layer */
825 if (!(rc & (1 << layer))) {
826 dev_dbg(&state->i2c->dev,
827 "%s: preBER for layer %c is not available yet.\n",
828 __func__, 'A' + layer);
832 /* Read Bit Error Count */
833 rc = mb86a20s_readreg(state, 0x55 + layer * 3);
837 rc = mb86a20s_readreg(state, 0x56 + layer * 3);
841 rc = mb86a20s_readreg(state, 0x57 + layer * 3);
846 dev_dbg(&state->i2c->dev,
847 "%s: bit error before Viterbi for layer %c: %d.\n",
848 __func__, 'A' + layer, *error);
851 rc = mb86a20s_writereg(state, 0x50, 0xa7 + layer * 3);
854 rc = mb86a20s_readreg(state, 0x51);
858 rc = mb86a20s_writereg(state, 0x50, 0xa8 + layer * 3);
861 rc = mb86a20s_readreg(state, 0x51);
865 rc = mb86a20s_writereg(state, 0x50, 0xa9 + layer * 3);
868 rc = mb86a20s_readreg(state, 0x51);
873 dev_dbg(&state->i2c->dev,
874 "%s: bit count before Viterbi for layer %c: %d.\n",
875 __func__, 'A' + layer, *count);
879 * As we get TMCC data from the frontend, we can better estimate the
880 * BER bit counters, in order to do the BER measure during a longer
881 * time. Use those data, if available, to update the bit count
885 if (state->estimated_rate[layer]
886 && state->estimated_rate[layer] != *count) {
887 dev_dbg(&state->i2c->dev,
888 "%s: updating layer %c preBER counter to %d.\n",
889 __func__, 'A' + layer, state->estimated_rate[layer]);
891 /* Turn off BER before Viterbi */
892 rc = mb86a20s_writereg(state, 0x52, 0x00);
894 /* Update counter for this layer */
895 rc = mb86a20s_writereg(state, 0x50, 0xa7 + layer * 3);
898 rc = mb86a20s_writereg(state, 0x51,
899 state->estimated_rate[layer] >> 16);
902 rc = mb86a20s_writereg(state, 0x50, 0xa8 + layer * 3);
905 rc = mb86a20s_writereg(state, 0x51,
906 state->estimated_rate[layer] >> 8);
909 rc = mb86a20s_writereg(state, 0x50, 0xa9 + layer * 3);
912 rc = mb86a20s_writereg(state, 0x51,
913 state->estimated_rate[layer]);
917 /* Turn on BER before Viterbi */
918 rc = mb86a20s_writereg(state, 0x52, 0x01);
920 /* Reset all preBER counters */
921 rc = mb86a20s_writereg(state, 0x53, 0x00);
924 rc = mb86a20s_writereg(state, 0x53, 0x07);
926 /* Reset counter to collect new data */
927 rc = mb86a20s_readreg(state, 0x53);
931 rc = mb86a20s_writereg(state, 0x53, val & ~(1 << layer));
934 rc = mb86a20s_writereg(state, 0x53, val | (1 << layer));
940 static int mb86a20s_get_post_ber(struct dvb_frontend *fe,
942 u32 *error, u32 *count)
944 struct mb86a20s_state *state = fe->demodulator_priv;
945 u32 counter, collect_rate;
948 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
950 if (layer >= NUM_LAYERS)
953 /* Check if the BER measures are already available */
954 rc = mb86a20s_readreg(state, 0x60);
958 /* Check if data is available for that layer */
959 if (!(rc & (1 << layer))) {
960 dev_dbg(&state->i2c->dev,
961 "%s: post BER for layer %c is not available yet.\n",
962 __func__, 'A' + layer);
966 /* Read Bit Error Count */
967 rc = mb86a20s_readreg(state, 0x64 + layer * 3);
971 rc = mb86a20s_readreg(state, 0x65 + layer * 3);
975 rc = mb86a20s_readreg(state, 0x66 + layer * 3);
980 dev_dbg(&state->i2c->dev,
981 "%s: post bit error for layer %c: %d.\n",
982 __func__, 'A' + layer, *error);
985 rc = mb86a20s_writereg(state, 0x50, 0xdc + layer * 2);
988 rc = mb86a20s_readreg(state, 0x51);
992 rc = mb86a20s_writereg(state, 0x50, 0xdd + layer * 2);
995 rc = mb86a20s_readreg(state, 0x51);
999 *count = counter * 204 * 8;
1001 dev_dbg(&state->i2c->dev,
1002 "%s: post bit count for layer %c: %d.\n",
1003 __func__, 'A' + layer, *count);
1006 * As we get TMCC data from the frontend, we can better estimate the
1007 * BER bit counters, in order to do the BER measure during a longer
1008 * time. Use those data, if available, to update the bit count
1012 if (!state->estimated_rate[layer])
1013 goto reset_measurement;
1015 collect_rate = state->estimated_rate[layer] / 204 / 8;
1016 if (collect_rate < 32)
1018 if (collect_rate > 65535)
1019 collect_rate = 65535;
1020 if (collect_rate != counter) {
1021 dev_dbg(&state->i2c->dev,
1022 "%s: updating postBER counter on layer %c to %d.\n",
1023 __func__, 'A' + layer, collect_rate);
1025 /* Turn off BER after Viterbi */
1026 rc = mb86a20s_writereg(state, 0x5e, 0x00);
1028 /* Update counter for this layer */
1029 rc = mb86a20s_writereg(state, 0x50, 0xdc + layer * 2);
1032 rc = mb86a20s_writereg(state, 0x51, collect_rate >> 8);
1035 rc = mb86a20s_writereg(state, 0x50, 0xdd + layer * 2);
1038 rc = mb86a20s_writereg(state, 0x51, collect_rate & 0xff);
1042 /* Turn on BER after Viterbi */
1043 rc = mb86a20s_writereg(state, 0x5e, 0x07);
1045 /* Reset all preBER counters */
1046 rc = mb86a20s_writereg(state, 0x5f, 0x00);
1049 rc = mb86a20s_writereg(state, 0x5f, 0x07);
1055 /* Reset counter to collect new data */
1056 rc = mb86a20s_readreg(state, 0x5f);
1060 rc = mb86a20s_writereg(state, 0x5f, val & ~(1 << layer));
1063 rc = mb86a20s_writereg(state, 0x5f, val | (1 << layer));
1068 static int mb86a20s_get_blk_error(struct dvb_frontend *fe,
1070 u32 *error, u32 *count)
1072 struct mb86a20s_state *state = fe->demodulator_priv;
1075 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1077 if (layer >= NUM_LAYERS)
1080 /* Check if the PER measures are already available */
1081 rc = mb86a20s_writereg(state, 0x50, 0xb8);
1084 rc = mb86a20s_readreg(state, 0x51);
1088 /* Check if data is available for that layer */
1090 if (!(rc & (1 << layer))) {
1091 dev_dbg(&state->i2c->dev,
1092 "%s: block counts for layer %c aren't available yet.\n",
1093 __func__, 'A' + layer);
1097 /* Read Packet error Count */
1098 rc = mb86a20s_writereg(state, 0x50, 0xb9 + layer * 2);
1101 rc = mb86a20s_readreg(state, 0x51);
1105 rc = mb86a20s_writereg(state, 0x50, 0xba + layer * 2);
1108 rc = mb86a20s_readreg(state, 0x51);
1112 dev_dbg(&state->i2c->dev, "%s: block error for layer %c: %d.\n",
1113 __func__, 'A' + layer, *error);
1115 /* Read Bit Count */
1116 rc = mb86a20s_writereg(state, 0x50, 0xb2 + layer * 2);
1119 rc = mb86a20s_readreg(state, 0x51);
1123 rc = mb86a20s_writereg(state, 0x50, 0xb3 + layer * 2);
1126 rc = mb86a20s_readreg(state, 0x51);
1131 dev_dbg(&state->i2c->dev,
1132 "%s: block count for layer %c: %d.\n",
1133 __func__, 'A' + layer, *count);
1136 * As we get TMCC data from the frontend, we can better estimate the
1137 * BER bit counters, in order to do the BER measure during a longer
1138 * time. Use those data, if available, to update the bit count
1142 if (!state->estimated_rate[layer])
1143 goto reset_measurement;
1145 collect_rate = state->estimated_rate[layer] / 204 / 8;
1146 if (collect_rate < 32)
1148 if (collect_rate > 65535)
1149 collect_rate = 65535;
1151 if (collect_rate != *count) {
1152 dev_dbg(&state->i2c->dev,
1153 "%s: updating PER counter on layer %c to %d.\n",
1154 __func__, 'A' + layer, collect_rate);
1156 /* Stop PER measurement */
1157 rc = mb86a20s_writereg(state, 0x50, 0xb0);
1160 rc = mb86a20s_writereg(state, 0x51, 0x00);
1164 /* Update this layer's counter */
1165 rc = mb86a20s_writereg(state, 0x50, 0xb2 + layer * 2);
1168 rc = mb86a20s_writereg(state, 0x51, collect_rate >> 8);
1171 rc = mb86a20s_writereg(state, 0x50, 0xb3 + layer * 2);
1174 rc = mb86a20s_writereg(state, 0x51, collect_rate & 0xff);
1178 /* start PER measurement */
1179 rc = mb86a20s_writereg(state, 0x50, 0xb0);
1182 rc = mb86a20s_writereg(state, 0x51, 0x07);
1186 /* Reset all counters to collect new data */
1187 rc = mb86a20s_writereg(state, 0x50, 0xb1);
1190 rc = mb86a20s_writereg(state, 0x51, 0x07);
1193 rc = mb86a20s_writereg(state, 0x51, 0x00);
1199 /* Reset counter to collect new data */
1200 rc = mb86a20s_writereg(state, 0x50, 0xb1);
1203 rc = mb86a20s_readreg(state, 0x51);
1207 rc = mb86a20s_writereg(state, 0x51, val | (1 << layer));
1210 rc = mb86a20s_writereg(state, 0x51, val & ~(1 << layer));
1215 struct linear_segments {
1220 * All tables below return a dB/1000 measurement
1223 static const struct linear_segments cnr_to_db_table[] = {
1257 static const struct linear_segments cnr_64qam_table[] = {
1291 static const struct linear_segments cnr_16qam_table[] = {
1325 static const struct linear_segments cnr_qpsk_table[] = {
1359 static u32 interpolate_value(u32 value, const struct linear_segments *segments,
1366 if (value >= segments[0].x)
1367 return segments[0].y;
1368 if (value < segments[len-1].x)
1369 return segments[len-1].y;
1371 for (i = 1; i < len - 1; i++) {
1372 /* If value is identical, no need to interpolate */
1373 if (value == segments[i].x)
1374 return segments[i].y;
1375 if (value > segments[i].x)
1379 /* Linear interpolation between the two (x,y) points */
1380 dy = segments[i].y - segments[i - 1].y;
1381 dx = segments[i - 1].x - segments[i].x;
1382 tmp64 = value - segments[i].x;
1385 ret = segments[i].y - tmp64;
1390 static int mb86a20s_get_main_CNR(struct dvb_frontend *fe)
1392 struct mb86a20s_state *state = fe->demodulator_priv;
1393 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1394 u32 cnr_linear, cnr;
1397 /* Check if CNR is available */
1398 rc = mb86a20s_readreg(state, 0x45);
1403 dev_dbg(&state->i2c->dev, "%s: CNR is not available yet.\n",
1409 rc = mb86a20s_readreg(state, 0x46);
1412 cnr_linear = rc << 8;
1414 rc = mb86a20s_readreg(state, 0x46);
1419 cnr = interpolate_value(cnr_linear,
1420 cnr_to_db_table, ARRAY_SIZE(cnr_to_db_table));
1422 c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
1423 c->cnr.stat[0].svalue = cnr;
1425 dev_dbg(&state->i2c->dev, "%s: CNR is %d.%03d dB (%d)\n",
1426 __func__, cnr / 1000, cnr % 1000, cnr_linear);
1428 /* CNR counter reset */
1429 rc = mb86a20s_writereg(state, 0x45, val | 0x10);
1432 rc = mb86a20s_writereg(state, 0x45, val & 0x6f);
1437 static int mb86a20s_get_blk_error_layer_CNR(struct dvb_frontend *fe)
1439 struct mb86a20s_state *state = fe->demodulator_priv;
1440 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1443 const struct linear_segments *segs;
1446 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1448 /* Check if the measures are already available */
1449 rc = mb86a20s_writereg(state, 0x50, 0x5b);
1452 rc = mb86a20s_readreg(state, 0x51);
1456 /* Check if data is available */
1458 dev_dbg(&state->i2c->dev,
1459 "%s: MER measures aren't available yet.\n", __func__);
1463 /* Read all layers */
1464 for (layer = 0; layer < NUM_LAYERS; layer++) {
1465 if (!(c->isdbt_layer_enabled & (1 << layer))) {
1466 c->cnr.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
1470 rc = mb86a20s_writereg(state, 0x50, 0x52 + layer * 3);
1473 rc = mb86a20s_readreg(state, 0x51);
1477 rc = mb86a20s_writereg(state, 0x50, 0x53 + layer * 3);
1480 rc = mb86a20s_readreg(state, 0x51);
1484 rc = mb86a20s_writereg(state, 0x50, 0x54 + layer * 3);
1487 rc = mb86a20s_readreg(state, 0x51);
1492 switch (c->layer[layer].modulation) {
1495 segs = cnr_qpsk_table;
1496 segs_len = ARRAY_SIZE(cnr_qpsk_table);
1499 segs = cnr_16qam_table;
1500 segs_len = ARRAY_SIZE(cnr_16qam_table);
1504 segs = cnr_64qam_table;
1505 segs_len = ARRAY_SIZE(cnr_64qam_table);
1508 cnr = interpolate_value(mer, segs, segs_len);
1510 c->cnr.stat[1 + layer].scale = FE_SCALE_DECIBEL;
1511 c->cnr.stat[1 + layer].svalue = cnr;
1513 dev_dbg(&state->i2c->dev,
1514 "%s: CNR for layer %c is %d.%03d dB (MER = %d).\n",
1515 __func__, 'A' + layer, cnr / 1000, cnr % 1000, mer);
1519 /* Start a new MER measurement */
1520 /* MER counter reset */
1521 rc = mb86a20s_writereg(state, 0x50, 0x50);
1524 rc = mb86a20s_readreg(state, 0x51);
1529 rc = mb86a20s_writereg(state, 0x51, val | 0x01);
1532 rc = mb86a20s_writereg(state, 0x51, val & 0x06);
1539 static void mb86a20s_stats_not_ready(struct dvb_frontend *fe)
1541 struct mb86a20s_state *state = fe->demodulator_priv;
1542 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1545 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1547 /* Fill the length of each status counter */
1549 /* Only global stats */
1550 c->strength.len = 1;
1552 /* Per-layer stats - 3 layers + global */
1553 c->cnr.len = NUM_LAYERS + 1;
1554 c->pre_bit_error.len = NUM_LAYERS + 1;
1555 c->pre_bit_count.len = NUM_LAYERS + 1;
1556 c->post_bit_error.len = NUM_LAYERS + 1;
1557 c->post_bit_count.len = NUM_LAYERS + 1;
1558 c->block_error.len = NUM_LAYERS + 1;
1559 c->block_count.len = NUM_LAYERS + 1;
1561 /* Signal is always available */
1562 c->strength.stat[0].scale = FE_SCALE_RELATIVE;
1563 c->strength.stat[0].uvalue = 0;
1565 /* Put all of them at FE_SCALE_NOT_AVAILABLE */
1566 for (layer = 0; layer < NUM_LAYERS + 1; layer++) {
1567 c->cnr.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
1568 c->pre_bit_error.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
1569 c->pre_bit_count.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
1570 c->post_bit_error.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
1571 c->post_bit_count.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
1572 c->block_error.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
1573 c->block_count.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
1577 static int mb86a20s_get_stats(struct dvb_frontend *fe, int status_nr)
1579 struct mb86a20s_state *state = fe->demodulator_priv;
1580 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1582 u32 bit_error = 0, bit_count = 0;
1583 u32 t_pre_bit_error = 0, t_pre_bit_count = 0;
1584 u32 t_post_bit_error = 0, t_post_bit_count = 0;
1585 u32 block_error = 0, block_count = 0;
1586 u32 t_block_error = 0, t_block_count = 0;
1587 int active_layers = 0, pre_ber_layers = 0, post_ber_layers = 0;
1590 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1592 mb86a20s_get_main_CNR(fe);
1594 /* Get per-layer stats */
1595 mb86a20s_get_blk_error_layer_CNR(fe);
1598 * At state 7, only CNR is available
1599 * For BER measures, state=9 is required
1600 * FIXME: we may get MER measures with state=8
1605 for (layer = 0; layer < NUM_LAYERS; layer++) {
1606 if (c->isdbt_layer_enabled & (1 << layer)) {
1607 /* Layer is active and has rc segments */
1610 /* Handle BER before vterbi */
1611 rc = mb86a20s_get_pre_ber(fe, layer,
1612 &bit_error, &bit_count);
1614 c->pre_bit_error.stat[1 + layer].scale = FE_SCALE_COUNTER;
1615 c->pre_bit_error.stat[1 + layer].uvalue += bit_error;
1616 c->pre_bit_count.stat[1 + layer].scale = FE_SCALE_COUNTER;
1617 c->pre_bit_count.stat[1 + layer].uvalue += bit_count;
1618 } else if (rc != -EBUSY) {
1620 * If an I/O error happened,
1621 * measures are now unavailable
1623 c->pre_bit_error.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
1624 c->pre_bit_count.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
1625 dev_err(&state->i2c->dev,
1626 "%s: Can't get BER for layer %c (error %d).\n",
1627 __func__, 'A' + layer, rc);
1629 if (c->block_error.stat[1 + layer].scale != FE_SCALE_NOT_AVAILABLE)
1632 /* Handle BER post vterbi */
1633 rc = mb86a20s_get_post_ber(fe, layer,
1634 &bit_error, &bit_count);
1636 c->post_bit_error.stat[1 + layer].scale = FE_SCALE_COUNTER;
1637 c->post_bit_error.stat[1 + layer].uvalue += bit_error;
1638 c->post_bit_count.stat[1 + layer].scale = FE_SCALE_COUNTER;
1639 c->post_bit_count.stat[1 + layer].uvalue += bit_count;
1640 } else if (rc != -EBUSY) {
1642 * If an I/O error happened,
1643 * measures are now unavailable
1645 c->post_bit_error.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
1646 c->post_bit_count.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
1647 dev_err(&state->i2c->dev,
1648 "%s: Can't get BER for layer %c (error %d).\n",
1649 __func__, 'A' + layer, rc);
1651 if (c->block_error.stat[1 + layer].scale != FE_SCALE_NOT_AVAILABLE)
1654 /* Handle Block errors for PER/UCB reports */
1655 rc = mb86a20s_get_blk_error(fe, layer,
1659 c->block_error.stat[1 + layer].scale = FE_SCALE_COUNTER;
1660 c->block_error.stat[1 + layer].uvalue += block_error;
1661 c->block_count.stat[1 + layer].scale = FE_SCALE_COUNTER;
1662 c->block_count.stat[1 + layer].uvalue += block_count;
1663 } else if (rc != -EBUSY) {
1665 * If an I/O error happened,
1666 * measures are now unavailable
1668 c->block_error.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
1669 c->block_count.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
1670 dev_err(&state->i2c->dev,
1671 "%s: Can't get PER for layer %c (error %d).\n",
1672 __func__, 'A' + layer, rc);
1675 if (c->block_error.stat[1 + layer].scale != FE_SCALE_NOT_AVAILABLE)
1678 /* Update total preBER */
1679 t_pre_bit_error += c->pre_bit_error.stat[1 + layer].uvalue;
1680 t_pre_bit_count += c->pre_bit_count.stat[1 + layer].uvalue;
1682 /* Update total postBER */
1683 t_post_bit_error += c->post_bit_error.stat[1 + layer].uvalue;
1684 t_post_bit_count += c->post_bit_count.stat[1 + layer].uvalue;
1686 /* Update total PER */
1687 t_block_error += c->block_error.stat[1 + layer].uvalue;
1688 t_block_count += c->block_count.stat[1 + layer].uvalue;
1693 * Start showing global count if at least one error count is
1696 if (pre_ber_layers) {
1698 * At least one per-layer BER measure was read. We can now
1699 * calculate the total BER
1701 * Total Bit Error/Count is calculated as the sum of the
1702 * bit errors on all active layers.
1704 c->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER;
1705 c->pre_bit_error.stat[0].uvalue = t_pre_bit_error;
1706 c->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER;
1707 c->pre_bit_count.stat[0].uvalue = t_pre_bit_count;
1709 c->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1710 c->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER;
1714 * Start showing global count if at least one error count is
1717 if (post_ber_layers) {
1719 * At least one per-layer BER measure was read. We can now
1720 * calculate the total BER
1722 * Total Bit Error/Count is calculated as the sum of the
1723 * bit errors on all active layers.
1725 c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
1726 c->post_bit_error.stat[0].uvalue = t_post_bit_error;
1727 c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
1728 c->post_bit_count.stat[0].uvalue = t_post_bit_count;
1730 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1731 c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
1736 * At least one per-layer UCB measure was read. We can now
1737 * calculate the total UCB
1739 * Total block Error/Count is calculated as the sum of the
1740 * block errors on all active layers.
1742 c->block_error.stat[0].scale = FE_SCALE_COUNTER;
1743 c->block_error.stat[0].uvalue = t_block_error;
1744 c->block_count.stat[0].scale = FE_SCALE_COUNTER;
1745 c->block_count.stat[0].uvalue = t_block_count;
1747 c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1748 c->block_count.stat[0].scale = FE_SCALE_COUNTER;
1755 * The functions below are called via DVB callbacks, so they need to
1756 * properly use the I2C gate control
1759 static int mb86a20s_initfe(struct dvb_frontend *fe)
1761 struct mb86a20s_state *state = fe->demodulator_priv;
1765 u8 regD5 = 1, reg71, reg09 = 0x3a;
1767 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1769 if (fe->ops.i2c_gate_ctrl)
1770 fe->ops.i2c_gate_ctrl(fe, 0);
1772 /* Initialize the frontend */
1773 rc = mb86a20s_writeregdata(state, mb86a20s_init1);
1777 if (!state->inversion)
1779 rc = mb86a20s_writereg(state, 0x09, reg09);
1786 rc = mb86a20s_writereg(state, 0x39, reg71);
1789 rc = mb86a20s_writereg(state, 0x71, state->bw);
1792 if (state->subchannel) {
1793 rc = mb86a20s_writereg(state, 0x44, state->subchannel);
1798 fclk = state->config->fclk;
1802 /* Adjust IF frequency to match tuner */
1803 if (fe->ops.tuner_ops.get_if_frequency)
1804 fe->ops.tuner_ops.get_if_frequency(fe, &state->if_freq);
1806 if (!state->if_freq)
1807 state->if_freq = 3300000;
1809 pll = (((u64)1) << 34) * state->if_freq;
1810 do_div(pll, 63 * fclk);
1811 pll = (1 << 25) - pll;
1812 rc = mb86a20s_writereg(state, 0x28, 0x2a);
1815 rc = mb86a20s_writereg(state, 0x29, (pll >> 16) & 0xff);
1818 rc = mb86a20s_writereg(state, 0x2a, (pll >> 8) & 0xff);
1821 rc = mb86a20s_writereg(state, 0x2b, pll & 0xff);
1824 dev_dbg(&state->i2c->dev, "%s: fclk=%d, IF=%d, clock reg=0x%06llx\n",
1825 __func__, fclk, state->if_freq, (long long)pll);
1827 /* pll = freq[Hz] * 2^24/10^6 / 16.285714286 */
1828 pll = state->if_freq * 1677721600L;
1829 do_div(pll, 1628571429L);
1830 rc = mb86a20s_writereg(state, 0x28, 0x20);
1833 rc = mb86a20s_writereg(state, 0x29, (pll >> 16) & 0xff);
1836 rc = mb86a20s_writereg(state, 0x2a, (pll >> 8) & 0xff);
1839 rc = mb86a20s_writereg(state, 0x2b, pll & 0xff);
1842 dev_dbg(&state->i2c->dev, "%s: IF=%d, IF reg=0x%06llx\n",
1843 __func__, state->if_freq, (long long)pll);
1845 if (!state->config->is_serial)
1848 rc = mb86a20s_writereg(state, 0x50, 0xd5);
1851 rc = mb86a20s_writereg(state, 0x51, regD5);
1855 rc = mb86a20s_writeregdata(state, mb86a20s_init2);
1861 if (fe->ops.i2c_gate_ctrl)
1862 fe->ops.i2c_gate_ctrl(fe, 1);
1865 state->need_init = true;
1866 dev_info(&state->i2c->dev,
1867 "mb86a20s: Init failed. Will try again later\n");
1869 state->need_init = false;
1870 dev_dbg(&state->i2c->dev, "Initialization succeeded.\n");
1875 static int mb86a20s_set_frontend(struct dvb_frontend *fe)
1877 struct mb86a20s_state *state = fe->demodulator_priv;
1878 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1880 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1882 if (!c->isdbt_layer_enabled)
1883 c->isdbt_layer_enabled = 7;
1885 if (c->isdbt_layer_enabled == 1)
1886 state->bw = MB86A20S_1SEG;
1887 else if (c->isdbt_partial_reception)
1888 state->bw = MB86A20S_13SEG_PARTIAL;
1890 state->bw = MB86A20S_13SEG;
1892 if (c->inversion == INVERSION_ON)
1893 state->inversion = true;
1895 state->inversion = false;
1897 if (!c->isdbt_sb_mode) {
1898 state->subchannel = 0;
1900 if (c->isdbt_sb_subchannel >= ARRAY_SIZE(mb86a20s_subchannel))
1901 c->isdbt_sb_subchannel = 0;
1903 state->subchannel = mb86a20s_subchannel[c->isdbt_sb_subchannel];
1907 * Gate should already be opened, but it doesn't hurt to
1910 if (fe->ops.i2c_gate_ctrl)
1911 fe->ops.i2c_gate_ctrl(fe, 1);
1912 fe->ops.tuner_ops.set_params(fe);
1914 if (fe->ops.tuner_ops.get_if_frequency)
1915 fe->ops.tuner_ops.get_if_frequency(fe, &if_freq);
1918 * Make it more reliable: if, for some reason, the initial
1919 * device initialization doesn't happen, initialize it when
1920 * a SBTVD parameters are adjusted.
1922 * Unfortunately, due to a hard to track bug at tda829x/tda18271,
1923 * the agc callback logic is not called during DVB attach time,
1924 * causing mb86a20s to not be initialized with Kworld SBTVD.
1925 * So, this hack is needed, in order to make Kworld SBTVD to work.
1927 * It is also needed to change the IF after the initial init.
1929 * HACK: Always init the frontend when set_frontend is called:
1930 * it was noticed that, on some devices, it fails to lock on a
1931 * different channel. So, it is better to reset everything, even
1932 * wasting some time, than to loose channel lock.
1934 mb86a20s_initfe(fe);
1936 if (fe->ops.i2c_gate_ctrl)
1937 fe->ops.i2c_gate_ctrl(fe, 0);
1939 rc = mb86a20s_writeregdata(state, mb86a20s_reset_reception);
1940 mb86a20s_reset_counters(fe);
1941 mb86a20s_stats_not_ready(fe);
1943 if (fe->ops.i2c_gate_ctrl)
1944 fe->ops.i2c_gate_ctrl(fe, 1);
1949 static int mb86a20s_read_status_and_stats(struct dvb_frontend *fe,
1950 enum fe_status *status)
1952 struct mb86a20s_state *state = fe->demodulator_priv;
1955 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1957 if (fe->ops.i2c_gate_ctrl)
1958 fe->ops.i2c_gate_ctrl(fe, 0);
1961 status_nr = mb86a20s_read_status(fe, status);
1962 if (status_nr < 7) {
1963 mb86a20s_stats_not_ready(fe);
1964 mb86a20s_reset_frontend_cache(fe);
1966 if (status_nr < 0) {
1967 dev_err(&state->i2c->dev,
1968 "%s: Can't read frontend lock status\n", __func__);
1972 /* Get signal strength */
1973 rc = mb86a20s_read_signal_strength(fe);
1975 dev_err(&state->i2c->dev,
1976 "%s: Can't reset VBER registers.\n", __func__);
1977 mb86a20s_stats_not_ready(fe);
1978 mb86a20s_reset_frontend_cache(fe);
1980 rc = 0; /* Status is OK */
1984 if (status_nr >= 7) {
1986 rc = mb86a20s_get_frontend(fe);
1988 dev_err(&state->i2c->dev,
1989 "%s: Can't get FE TMCC data.\n", __func__);
1990 rc = 0; /* Status is OK */
1994 /* Get statistics */
1995 rc = mb86a20s_get_stats(fe, status_nr);
1996 if (rc < 0 && rc != -EBUSY) {
1997 dev_err(&state->i2c->dev,
1998 "%s: Can't get FE statistics.\n", __func__);
2002 rc = 0; /* Don't return EBUSY to userspace */
2007 mb86a20s_stats_not_ready(fe);
2010 if (fe->ops.i2c_gate_ctrl)
2011 fe->ops.i2c_gate_ctrl(fe, 1);
2016 static int mb86a20s_read_signal_strength_from_cache(struct dvb_frontend *fe,
2019 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
2022 *strength = c->strength.stat[0].uvalue;
2027 static int mb86a20s_get_frontend_dummy(struct dvb_frontend *fe)
2030 * get_frontend is now handled together with other stats
2031 * retrival, when read_status() is called, as some statistics
2032 * will depend on the layers detection.
2037 static int mb86a20s_tune(struct dvb_frontend *fe,
2039 unsigned int mode_flags,
2040 unsigned int *delay,
2041 enum fe_status *status)
2043 struct mb86a20s_state *state = fe->demodulator_priv;
2046 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
2049 rc = mb86a20s_set_frontend(fe);
2051 if (!(mode_flags & FE_TUNE_MODE_ONESHOT))
2052 mb86a20s_read_status_and_stats(fe, status);
2057 static void mb86a20s_release(struct dvb_frontend *fe)
2059 struct mb86a20s_state *state = fe->demodulator_priv;
2061 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
2066 static int mb86a20s_get_frontend_algo(struct dvb_frontend *fe)
2068 return DVBFE_ALGO_HW;
2071 static struct dvb_frontend_ops mb86a20s_ops;
2073 struct dvb_frontend *mb86a20s_attach(const struct mb86a20s_config *config,
2074 struct i2c_adapter *i2c)
2076 struct mb86a20s_state *state;
2079 dev_dbg(&i2c->dev, "%s called.\n", __func__);
2081 /* allocate memory for the internal state */
2082 state = kzalloc(sizeof(struct mb86a20s_state), GFP_KERNEL);
2083 if (state == NULL) {
2085 "%s: unable to allocate memory for state\n", __func__);
2089 /* setup the state */
2090 state->config = config;
2093 /* create dvb_frontend */
2094 memcpy(&state->frontend.ops, &mb86a20s_ops,
2095 sizeof(struct dvb_frontend_ops));
2096 state->frontend.demodulator_priv = state;
2098 /* Check if it is a mb86a20s frontend */
2099 rev = mb86a20s_readreg(state, 0);
2103 "Detected a Fujitsu mb86a20s frontend\n");
2106 "Frontend revision %d is unknown - aborting.\n",
2111 return &state->frontend;
2117 EXPORT_SYMBOL(mb86a20s_attach);
2119 static struct dvb_frontend_ops mb86a20s_ops = {
2120 .delsys = { SYS_ISDBT },
2121 /* Use dib8000 values per default */
2123 .name = "Fujitsu mb86A20s",
2124 .caps = FE_CAN_RECOVER |
2125 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
2126 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
2127 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 |
2128 FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_QAM_AUTO |
2129 FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_HIERARCHY_AUTO,
2130 /* Actually, those values depend on the used tuner */
2131 .frequency_min = 45000000,
2132 .frequency_max = 864000000,
2133 .frequency_stepsize = 62500,
2136 .release = mb86a20s_release,
2138 .init = mb86a20s_initfe,
2139 .set_frontend = mb86a20s_set_frontend,
2140 .get_frontend = mb86a20s_get_frontend_dummy,
2141 .read_status = mb86a20s_read_status_and_stats,
2142 .read_signal_strength = mb86a20s_read_signal_strength_from_cache,
2143 .tune = mb86a20s_tune,
2144 .get_frontend_algo = mb86a20s_get_frontend_algo,
2147 MODULE_DESCRIPTION("DVB Frontend module for Fujitsu mb86A20s hardware");
2148 MODULE_AUTHOR("Mauro Carvalho Chehab");
2149 MODULE_LICENSE("GPL");