2 * Realtek RTL2832 DVB-T demodulator driver
4 * Copyright (C) 2012 Thomas Mair <thomas.mair86@gmail.com>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
21 #include "rtl2832_priv.h"
23 #include <linux/bitops.h>
25 #define REG_MASK(b) (BIT(b + 1) - 1)
27 static const struct rtl2832_reg_entry registers[] = {
28 [DVBT_SOFT_RST] = {0x101, 2, 2},
29 [DVBT_IIC_REPEAT] = {0x101, 3, 3},
30 [DVBT_TR_WAIT_MIN_8K] = {0x188, 11, 2},
31 [DVBT_RSD_BER_FAIL_VAL] = {0x18f, 15, 0},
32 [DVBT_EN_BK_TRK] = {0x1a6, 7, 7},
33 [DVBT_AD_EN_REG] = {0x008, 7, 7},
34 [DVBT_AD_EN_REG1] = {0x008, 6, 6},
35 [DVBT_EN_BBIN] = {0x1b1, 0, 0},
36 [DVBT_MGD_THD0] = {0x195, 7, 0},
37 [DVBT_MGD_THD1] = {0x196, 7, 0},
38 [DVBT_MGD_THD2] = {0x197, 7, 0},
39 [DVBT_MGD_THD3] = {0x198, 7, 0},
40 [DVBT_MGD_THD4] = {0x199, 7, 0},
41 [DVBT_MGD_THD5] = {0x19a, 7, 0},
42 [DVBT_MGD_THD6] = {0x19b, 7, 0},
43 [DVBT_MGD_THD7] = {0x19c, 7, 0},
44 [DVBT_EN_CACQ_NOTCH] = {0x161, 4, 4},
45 [DVBT_AD_AV_REF] = {0x009, 6, 0},
46 [DVBT_REG_PI] = {0x00a, 2, 0},
47 [DVBT_PIP_ON] = {0x021, 3, 3},
48 [DVBT_SCALE1_B92] = {0x292, 7, 0},
49 [DVBT_SCALE1_B93] = {0x293, 7, 0},
50 [DVBT_SCALE1_BA7] = {0x2a7, 7, 0},
51 [DVBT_SCALE1_BA9] = {0x2a9, 7, 0},
52 [DVBT_SCALE1_BAA] = {0x2aa, 7, 0},
53 [DVBT_SCALE1_BAB] = {0x2ab, 7, 0},
54 [DVBT_SCALE1_BAC] = {0x2ac, 7, 0},
55 [DVBT_SCALE1_BB0] = {0x2b0, 7, 0},
56 [DVBT_SCALE1_BB1] = {0x2b1, 7, 0},
57 [DVBT_KB_P1] = {0x164, 3, 1},
58 [DVBT_KB_P2] = {0x164, 6, 4},
59 [DVBT_KB_P3] = {0x165, 2, 0},
60 [DVBT_OPT_ADC_IQ] = {0x006, 5, 4},
61 [DVBT_AD_AVI] = {0x009, 1, 0},
62 [DVBT_AD_AVQ] = {0x009, 3, 2},
63 [DVBT_K1_CR_STEP12] = {0x2ad, 9, 4},
64 [DVBT_TRK_KS_P2] = {0x16f, 2, 0},
65 [DVBT_TRK_KS_I2] = {0x170, 5, 3},
66 [DVBT_TR_THD_SET2] = {0x172, 3, 0},
67 [DVBT_TRK_KC_P2] = {0x173, 5, 3},
68 [DVBT_TRK_KC_I2] = {0x175, 2, 0},
69 [DVBT_CR_THD_SET2] = {0x176, 7, 6},
70 [DVBT_PSET_IFFREQ] = {0x119, 21, 0},
71 [DVBT_SPEC_INV] = {0x115, 0, 0},
72 [DVBT_RSAMP_RATIO] = {0x19f, 27, 2},
73 [DVBT_CFREQ_OFF_RATIO] = {0x19d, 23, 4},
74 [DVBT_FSM_STAGE] = {0x351, 6, 3},
75 [DVBT_RX_CONSTEL] = {0x33c, 3, 2},
76 [DVBT_RX_HIER] = {0x33c, 6, 4},
77 [DVBT_RX_C_RATE_LP] = {0x33d, 2, 0},
78 [DVBT_RX_C_RATE_HP] = {0x33d, 5, 3},
79 [DVBT_GI_IDX] = {0x351, 1, 0},
80 [DVBT_FFT_MODE_IDX] = {0x351, 2, 2},
81 [DVBT_RSD_BER_EST] = {0x34e, 15, 0},
82 [DVBT_CE_EST_EVM] = {0x40c, 15, 0},
83 [DVBT_RF_AGC_VAL] = {0x35b, 13, 0},
84 [DVBT_IF_AGC_VAL] = {0x359, 13, 0},
85 [DVBT_DAGC_VAL] = {0x305, 7, 0},
86 [DVBT_SFREQ_OFF] = {0x318, 13, 0},
87 [DVBT_CFREQ_OFF] = {0x35f, 17, 0},
88 [DVBT_POLAR_RF_AGC] = {0x00e, 1, 1},
89 [DVBT_POLAR_IF_AGC] = {0x00e, 0, 0},
90 [DVBT_AAGC_HOLD] = {0x104, 5, 5},
91 [DVBT_EN_RF_AGC] = {0x104, 6, 6},
92 [DVBT_EN_IF_AGC] = {0x104, 7, 7},
93 [DVBT_IF_AGC_MIN] = {0x108, 7, 0},
94 [DVBT_IF_AGC_MAX] = {0x109, 7, 0},
95 [DVBT_RF_AGC_MIN] = {0x10a, 7, 0},
96 [DVBT_RF_AGC_MAX] = {0x10b, 7, 0},
97 [DVBT_IF_AGC_MAN] = {0x10c, 6, 6},
98 [DVBT_IF_AGC_MAN_VAL] = {0x10c, 13, 0},
99 [DVBT_RF_AGC_MAN] = {0x10e, 6, 6},
100 [DVBT_RF_AGC_MAN_VAL] = {0x10e, 13, 0},
101 [DVBT_DAGC_TRG_VAL] = {0x112, 7, 0},
102 [DVBT_AGC_TARG_VAL_0] = {0x102, 0, 0},
103 [DVBT_AGC_TARG_VAL_8_1] = {0x103, 7, 0},
104 [DVBT_AAGC_LOOP_GAIN] = {0x1c7, 5, 1},
105 [DVBT_LOOP_GAIN2_3_0] = {0x104, 4, 1},
106 [DVBT_LOOP_GAIN2_4] = {0x105, 7, 7},
107 [DVBT_LOOP_GAIN3] = {0x1c8, 4, 0},
108 [DVBT_VTOP1] = {0x106, 5, 0},
109 [DVBT_VTOP2] = {0x1c9, 5, 0},
110 [DVBT_VTOP3] = {0x1ca, 5, 0},
111 [DVBT_KRF1] = {0x1cb, 7, 0},
112 [DVBT_KRF2] = {0x107, 7, 0},
113 [DVBT_KRF3] = {0x1cd, 7, 0},
114 [DVBT_KRF4] = {0x1ce, 7, 0},
115 [DVBT_EN_GI_PGA] = {0x1e5, 0, 0},
116 [DVBT_THD_LOCK_UP] = {0x1d9, 8, 0},
117 [DVBT_THD_LOCK_DW] = {0x1db, 8, 0},
118 [DVBT_THD_UP1] = {0x1dd, 7, 0},
119 [DVBT_THD_DW1] = {0x1de, 7, 0},
120 [DVBT_INTER_CNT_LEN] = {0x1d8, 3, 0},
121 [DVBT_GI_PGA_STATE] = {0x1e6, 3, 3},
122 [DVBT_EN_AGC_PGA] = {0x1d7, 0, 0},
123 [DVBT_CKOUTPAR] = {0x17b, 5, 5},
124 [DVBT_CKOUT_PWR] = {0x17b, 6, 6},
125 [DVBT_SYNC_DUR] = {0x17b, 7, 7},
126 [DVBT_ERR_DUR] = {0x17c, 0, 0},
127 [DVBT_SYNC_LVL] = {0x17c, 1, 1},
128 [DVBT_ERR_LVL] = {0x17c, 2, 2},
129 [DVBT_VAL_LVL] = {0x17c, 3, 3},
130 [DVBT_SERIAL] = {0x17c, 4, 4},
131 [DVBT_SER_LSB] = {0x17c, 5, 5},
132 [DVBT_CDIV_PH0] = {0x17d, 3, 0},
133 [DVBT_CDIV_PH1] = {0x17d, 7, 4},
134 [DVBT_MPEG_IO_OPT_2_2] = {0x006, 7, 7},
135 [DVBT_MPEG_IO_OPT_1_0] = {0x007, 7, 6},
136 [DVBT_CKOUTPAR_PIP] = {0x0b7, 4, 4},
137 [DVBT_CKOUT_PWR_PIP] = {0x0b7, 3, 3},
138 [DVBT_SYNC_LVL_PIP] = {0x0b7, 2, 2},
139 [DVBT_ERR_LVL_PIP] = {0x0b7, 1, 1},
140 [DVBT_VAL_LVL_PIP] = {0x0b7, 0, 0},
141 [DVBT_CKOUTPAR_PID] = {0x0b9, 4, 4},
142 [DVBT_CKOUT_PWR_PID] = {0x0b9, 3, 3},
143 [DVBT_SYNC_LVL_PID] = {0x0b9, 2, 2},
144 [DVBT_ERR_LVL_PID] = {0x0b9, 1, 1},
145 [DVBT_VAL_LVL_PID] = {0x0b9, 0, 0},
146 [DVBT_SM_PASS] = {0x193, 11, 0},
147 [DVBT_AD7_SETTING] = {0x011, 15, 0},
148 [DVBT_RSSI_R] = {0x301, 6, 0},
149 [DVBT_ACI_DET_IND] = {0x312, 0, 0},
150 [DVBT_REG_MON] = {0x00d, 1, 0},
151 [DVBT_REG_MONSEL] = {0x00d, 2, 2},
152 [DVBT_REG_GPE] = {0x00d, 7, 7},
153 [DVBT_REG_GPO] = {0x010, 0, 0},
154 [DVBT_REG_4MSEL] = {0x013, 0, 0},
157 /* Our regmap is bypassing I2C adapter lock, thus we do it! */
158 int rtl2832_bulk_write(struct i2c_client *client, unsigned int reg,
159 const void *val, size_t val_count)
161 struct rtl2832_dev *dev = i2c_get_clientdata(client);
164 i2c_lock_adapter(client->adapter);
165 ret = regmap_bulk_write(dev->regmap, reg, val, val_count);
166 i2c_unlock_adapter(client->adapter);
170 int rtl2832_update_bits(struct i2c_client *client, unsigned int reg,
171 unsigned int mask, unsigned int val)
173 struct rtl2832_dev *dev = i2c_get_clientdata(client);
176 i2c_lock_adapter(client->adapter);
177 ret = regmap_update_bits(dev->regmap, reg, mask, val);
178 i2c_unlock_adapter(client->adapter);
182 int rtl2832_bulk_read(struct i2c_client *client, unsigned int reg, void *val,
185 struct rtl2832_dev *dev = i2c_get_clientdata(client);
188 i2c_lock_adapter(client->adapter);
189 ret = regmap_bulk_read(dev->regmap, reg, val, val_count);
190 i2c_unlock_adapter(client->adapter);
194 static int rtl2832_rd_demod_reg(struct rtl2832_dev *dev, int reg, u32 *val)
196 struct i2c_client *client = dev->client;
208 reg_start_addr = registers[reg].start_address;
209 msb = registers[reg].msb;
210 lsb = registers[reg].lsb;
212 len = (msb >> 3) + 1;
213 mask = REG_MASK(msb - lsb);
215 ret = rtl2832_bulk_read(client, reg_start_addr, reading, len);
220 for (i = 0; i < len; i++)
221 reading_tmp |= reading[i] << ((len - 1 - i) * 8);
223 *val = (reading_tmp >> lsb) & mask;
228 dev_dbg(&client->dev, "failed=%d\n", ret);
233 static int rtl2832_wr_demod_reg(struct rtl2832_dev *dev, int reg, u32 val)
235 struct i2c_client *client = dev->client;
249 reg_start_addr = registers[reg].start_address;
250 msb = registers[reg].msb;
251 lsb = registers[reg].lsb;
253 len = (msb >> 3) + 1;
254 mask = REG_MASK(msb - lsb);
257 ret = rtl2832_bulk_read(client, reg_start_addr, reading, len);
262 for (i = 0; i < len; i++)
263 reading_tmp |= reading[i] << ((len - 1 - i) * 8);
265 writing_tmp = reading_tmp & ~(mask << lsb);
266 writing_tmp |= ((val & mask) << lsb);
269 for (i = 0; i < len; i++)
270 writing[i] = (writing_tmp >> ((len - 1 - i) * 8)) & 0xff;
272 ret = rtl2832_bulk_write(client, reg_start_addr, writing, len);
279 dev_dbg(&client->dev, "failed=%d\n", ret);
284 static int rtl2832_set_if(struct dvb_frontend *fe, u32 if_freq)
286 struct rtl2832_dev *dev = fe->demodulator_priv;
287 struct i2c_client *client = dev->client;
290 u8 en_bbin = (if_freq == 0 ? 0x1 : 0x0);
293 * PSET_IFFREQ = - floor((IfFreqHz % CrystalFreqHz) * pow(2, 22)
297 pset_iffreq = if_freq % dev->pdata->clk;
298 pset_iffreq *= 0x400000;
299 pset_iffreq = div_u64(pset_iffreq, dev->pdata->clk);
300 pset_iffreq = -pset_iffreq;
301 pset_iffreq = pset_iffreq & 0x3fffff;
302 dev_dbg(&client->dev, "if_frequency=%d pset_iffreq=%08x\n",
303 if_freq, (unsigned)pset_iffreq);
305 ret = rtl2832_wr_demod_reg(dev, DVBT_EN_BBIN, en_bbin);
309 ret = rtl2832_wr_demod_reg(dev, DVBT_PSET_IFFREQ, pset_iffreq);
314 static int rtl2832_init(struct dvb_frontend *fe)
316 struct rtl2832_dev *dev = fe->demodulator_priv;
317 struct i2c_client *client = dev->client;
318 struct dtv_frontend_properties *c = &dev->fe.dtv_property_cache;
319 const struct rtl2832_reg_value *init;
321 /* initialization values for the demodulator registers */
322 struct rtl2832_reg_value rtl2832_initial_regs[] = {
323 {DVBT_AD_EN_REG, 0x1},
324 {DVBT_AD_EN_REG1, 0x1},
325 {DVBT_RSD_BER_FAIL_VAL, 0x2800},
326 {DVBT_MGD_THD0, 0x10},
327 {DVBT_MGD_THD1, 0x20},
328 {DVBT_MGD_THD2, 0x20},
329 {DVBT_MGD_THD3, 0x40},
330 {DVBT_MGD_THD4, 0x22},
331 {DVBT_MGD_THD5, 0x32},
332 {DVBT_MGD_THD6, 0x37},
333 {DVBT_MGD_THD7, 0x39},
334 {DVBT_EN_BK_TRK, 0x0},
335 {DVBT_EN_CACQ_NOTCH, 0x0},
336 {DVBT_AD_AV_REF, 0x2a},
339 {DVBT_CDIV_PH0, 0x8},
340 {DVBT_CDIV_PH1, 0x8},
341 {DVBT_SCALE1_B92, 0x4},
342 {DVBT_SCALE1_B93, 0xb0},
343 {DVBT_SCALE1_BA7, 0x78},
344 {DVBT_SCALE1_BA9, 0x28},
345 {DVBT_SCALE1_BAA, 0x59},
346 {DVBT_SCALE1_BAB, 0x83},
347 {DVBT_SCALE1_BAC, 0xd4},
348 {DVBT_SCALE1_BB0, 0x65},
349 {DVBT_SCALE1_BB1, 0x43},
353 {DVBT_K1_CR_STEP12, 0xa},
356 {DVBT_CDIV_PH0, 0x9},
357 {DVBT_CDIV_PH1, 0x9},
358 {DVBT_MPEG_IO_OPT_2_2, 0x0},
359 {DVBT_MPEG_IO_OPT_1_0, 0x0},
360 {DVBT_TRK_KS_P2, 0x4},
361 {DVBT_TRK_KS_I2, 0x7},
362 {DVBT_TR_THD_SET2, 0x6},
363 {DVBT_TRK_KC_I2, 0x5},
364 {DVBT_CR_THD_SET2, 0x1},
367 dev_dbg(&client->dev, "\n");
369 for (i = 0; i < ARRAY_SIZE(rtl2832_initial_regs); i++) {
370 ret = rtl2832_wr_demod_reg(dev, rtl2832_initial_regs[i].reg,
371 rtl2832_initial_regs[i].value);
376 /* load tuner specific settings */
377 dev_dbg(&client->dev, "load settings for tuner=%02x\n",
379 switch (dev->pdata->tuner) {
380 case RTL2832_TUNER_FC0012:
381 case RTL2832_TUNER_FC0013:
382 len = ARRAY_SIZE(rtl2832_tuner_init_fc0012);
383 init = rtl2832_tuner_init_fc0012;
385 case RTL2832_TUNER_TUA9001:
386 len = ARRAY_SIZE(rtl2832_tuner_init_tua9001);
387 init = rtl2832_tuner_init_tua9001;
389 case RTL2832_TUNER_E4000:
390 len = ARRAY_SIZE(rtl2832_tuner_init_e4000);
391 init = rtl2832_tuner_init_e4000;
393 case RTL2832_TUNER_R820T:
394 case RTL2832_TUNER_R828D:
395 len = ARRAY_SIZE(rtl2832_tuner_init_r820t);
396 init = rtl2832_tuner_init_r820t;
403 for (i = 0; i < len; i++) {
404 ret = rtl2832_wr_demod_reg(dev, init[i].reg, init[i].value);
409 /* init stats here in order signal app which stats are supported */
411 c->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
413 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
414 c->post_bit_error.len = 1;
415 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
416 c->post_bit_count.len = 1;
417 c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
418 /* start statistics polling */
419 schedule_delayed_work(&dev->stat_work, msecs_to_jiffies(2000));
420 dev->sleeping = false;
424 dev_dbg(&client->dev, "failed=%d\n", ret);
428 static int rtl2832_sleep(struct dvb_frontend *fe)
430 struct rtl2832_dev *dev = fe->demodulator_priv;
431 struct i2c_client *client = dev->client;
433 dev_dbg(&client->dev, "\n");
434 dev->sleeping = true;
435 /* stop statistics polling */
436 cancel_delayed_work_sync(&dev->stat_work);
441 static int rtl2832_get_tune_settings(struct dvb_frontend *fe,
442 struct dvb_frontend_tune_settings *s)
444 struct rtl2832_dev *dev = fe->demodulator_priv;
445 struct i2c_client *client = dev->client;
447 dev_dbg(&client->dev, "\n");
448 s->min_delay_ms = 1000;
449 s->step_size = fe->ops.info.frequency_stepsize * 2;
450 s->max_drift = (fe->ops.info.frequency_stepsize * 2) + 1;
454 static int rtl2832_set_frontend(struct dvb_frontend *fe)
456 struct rtl2832_dev *dev = fe->demodulator_priv;
457 struct i2c_client *client = dev->client;
458 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
460 u64 bw_mode, num, num2;
461 u32 resamp_ratio, cfreq_off_ratio;
462 static u8 bw_params[3][32] = {
463 /* 6 MHz bandwidth */
465 0xf5, 0xff, 0x15, 0x38, 0x5d, 0x6d, 0x52, 0x07, 0xfa, 0x2f,
466 0x53, 0xf5, 0x3f, 0xca, 0x0b, 0x91, 0xea, 0x30, 0x63, 0xb2,
467 0x13, 0xda, 0x0b, 0xc4, 0x18, 0x7e, 0x16, 0x66, 0x08, 0x67,
471 /* 7 MHz bandwidth */
473 0xe7, 0xcc, 0xb5, 0xba, 0xe8, 0x2f, 0x67, 0x61, 0x00, 0xaf,
474 0x86, 0xf2, 0xbf, 0x59, 0x04, 0x11, 0xb6, 0x33, 0xa4, 0x30,
475 0x15, 0x10, 0x0a, 0x42, 0x18, 0xf8, 0x17, 0xd9, 0x07, 0x22,
479 /* 8 MHz bandwidth */
481 0x09, 0xf6, 0xd2, 0xa7, 0x9a, 0xc9, 0x27, 0x77, 0x06, 0xbf,
482 0xec, 0xf4, 0x4f, 0x0b, 0xfc, 0x01, 0x63, 0x35, 0x54, 0xa7,
483 0x16, 0x66, 0x08, 0xb4, 0x19, 0x6e, 0x19, 0x65, 0x05, 0xc8,
489 dev_dbg(&client->dev, "frequency=%u bandwidth_hz=%u inversion=%u\n",
490 c->frequency, c->bandwidth_hz, c->inversion);
493 if (fe->ops.tuner_ops.set_params)
494 fe->ops.tuner_ops.set_params(fe);
496 /* PIP mode related */
497 ret = rtl2832_bulk_write(client, 0x192, "\x00\x0f\xff", 3);
501 /* If the frontend has get_if_frequency(), use it */
502 if (fe->ops.tuner_ops.get_if_frequency) {
505 ret = fe->ops.tuner_ops.get_if_frequency(fe, &if_freq);
509 ret = rtl2832_set_if(fe, if_freq);
514 switch (c->bandwidth_hz) {
528 dev_err(&client->dev, "invalid bandwidth_hz %u\n",
534 for (j = 0; j < sizeof(bw_params[0]); j++) {
535 ret = rtl2832_bulk_write(client, 0x11c + j, &bw_params[i][j], 1);
540 /* calculate and set resample ratio
541 * RSAMP_RATIO = floor(CrystalFreqHz * 7 * pow(2, 22)
542 * / ConstWithBandwidthMode)
544 num = dev->pdata->clk * 7;
546 num = div_u64(num, bw_mode);
547 resamp_ratio = num & 0x3ffffff;
548 ret = rtl2832_wr_demod_reg(dev, DVBT_RSAMP_RATIO, resamp_ratio);
552 /* calculate and set cfreq off ratio
553 * CFREQ_OFF_RATIO = - floor(ConstWithBandwidthMode * pow(2, 20)
554 * / (CrystalFreqHz * 7))
557 num2 = dev->pdata->clk * 7;
558 num = div_u64(num, num2);
560 cfreq_off_ratio = num & 0xfffff;
561 ret = rtl2832_wr_demod_reg(dev, DVBT_CFREQ_OFF_RATIO, cfreq_off_ratio);
566 ret = rtl2832_wr_demod_reg(dev, DVBT_SOFT_RST, 0x1);
570 ret = rtl2832_wr_demod_reg(dev, DVBT_SOFT_RST, 0x0);
576 dev_dbg(&client->dev, "failed=%d\n", ret);
580 static int rtl2832_get_frontend(struct dvb_frontend *fe)
582 struct rtl2832_dev *dev = fe->demodulator_priv;
583 struct i2c_client *client = dev->client;
584 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
591 ret = rtl2832_bulk_read(client, 0x33c, buf, 2);
595 ret = rtl2832_bulk_read(client, 0x351, &buf[2], 1);
599 dev_dbg(&client->dev, "TPS=%*ph\n", 3, buf);
601 switch ((buf[0] >> 2) & 3) {
603 c->modulation = QPSK;
606 c->modulation = QAM_16;
609 c->modulation = QAM_64;
613 switch ((buf[2] >> 2) & 1) {
615 c->transmission_mode = TRANSMISSION_MODE_2K;
618 c->transmission_mode = TRANSMISSION_MODE_8K;
621 switch ((buf[2] >> 0) & 3) {
623 c->guard_interval = GUARD_INTERVAL_1_32;
626 c->guard_interval = GUARD_INTERVAL_1_16;
629 c->guard_interval = GUARD_INTERVAL_1_8;
632 c->guard_interval = GUARD_INTERVAL_1_4;
636 switch ((buf[0] >> 4) & 7) {
638 c->hierarchy = HIERARCHY_NONE;
641 c->hierarchy = HIERARCHY_1;
644 c->hierarchy = HIERARCHY_2;
647 c->hierarchy = HIERARCHY_4;
651 switch ((buf[1] >> 3) & 7) {
653 c->code_rate_HP = FEC_1_2;
656 c->code_rate_HP = FEC_2_3;
659 c->code_rate_HP = FEC_3_4;
662 c->code_rate_HP = FEC_5_6;
665 c->code_rate_HP = FEC_7_8;
669 switch ((buf[1] >> 0) & 7) {
671 c->code_rate_LP = FEC_1_2;
674 c->code_rate_LP = FEC_2_3;
677 c->code_rate_LP = FEC_3_4;
680 c->code_rate_LP = FEC_5_6;
683 c->code_rate_LP = FEC_7_8;
689 dev_dbg(&client->dev, "failed=%d\n", ret);
693 static int rtl2832_read_status(struct dvb_frontend *fe, fe_status_t *status)
695 struct rtl2832_dev *dev = fe->demodulator_priv;
696 struct i2c_client *client = dev->client;
700 dev_dbg(&client->dev, "\n");
706 ret = rtl2832_rd_demod_reg(dev, DVBT_FSM_STAGE, &tmp);
711 *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
712 FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
713 } else if (tmp == 10) {
714 *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
718 dev->fe_status = *status;
721 dev_dbg(&client->dev, "failed=%d\n", ret);
725 static int rtl2832_read_snr(struct dvb_frontend *fe, u16 *snr)
727 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
729 /* report SNR in resolution of 0.1 dB */
730 if (c->cnr.stat[0].scale == FE_SCALE_DECIBEL)
731 *snr = div_s64(c->cnr.stat[0].svalue, 100);
738 static int rtl2832_read_ber(struct dvb_frontend *fe, u32 *ber)
740 struct rtl2832_dev *dev = fe->demodulator_priv;
742 *ber = (dev->post_bit_error - dev->post_bit_error_prev);
743 dev->post_bit_error_prev = dev->post_bit_error;
748 static void rtl2832_stat_work(struct work_struct *work)
750 struct rtl2832_dev *dev = container_of(work, struct rtl2832_dev, stat_work.work);
751 struct i2c_client *client = dev->client;
752 struct dtv_frontend_properties *c = &dev->fe.dtv_property_cache;
757 dev_dbg(&client->dev, "\n");
759 /* signal strength */
760 if (dev->fe_status & FE_HAS_SIGNAL) {
761 /* read digital AGC */
762 ret = rtl2832_bulk_read(client, 0x305, &u8tmp, 1);
766 dev_dbg(&client->dev, "digital agc=%02x", u8tmp);
769 u16tmp = u8tmp << 8 | u8tmp << 0;
771 c->strength.stat[0].scale = FE_SCALE_RELATIVE;
772 c->strength.stat[0].uvalue = u16tmp;
774 c->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
778 if (dev->fe_status & FE_HAS_VITERBI) {
779 unsigned hierarchy, constellation;
780 #define CONSTELLATION_NUM 3
781 #define HIERARCHY_NUM 4
782 static const u32 constant[CONSTELLATION_NUM][HIERARCHY_NUM] = {
783 {85387325, 85387325, 85387325, 85387325},
784 {86676178, 86676178, 87167949, 87795660},
785 {87659938, 87659938, 87885178, 88241743},
788 ret = rtl2832_bulk_read(client, 0x33c, &u8tmp, 1);
792 constellation = (u8tmp >> 2) & 0x03; /* [3:2] */
793 if (constellation > CONSTELLATION_NUM - 1)
794 goto err_schedule_delayed_work;
796 hierarchy = (u8tmp >> 4) & 0x07; /* [6:4] */
797 if (hierarchy > HIERARCHY_NUM - 1)
798 goto err_schedule_delayed_work;
800 ret = rtl2832_bulk_read(client, 0x40c, buf, 2);
804 u16tmp = buf[0] << 8 | buf[1] << 0;
806 tmp = (constant[constellation][hierarchy] -
807 intlog10(u16tmp)) / ((1 << 24) / 10000);
811 dev_dbg(&client->dev, "cnr raw=%u\n", u16tmp);
813 c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
814 c->cnr.stat[0].svalue = tmp;
816 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
820 if (dev->fe_status & FE_HAS_LOCK) {
821 ret = rtl2832_bulk_read(client, 0x34e, buf, 2);
825 u16tmp = buf[0] << 8 | buf[1] << 0;
826 dev->post_bit_error += u16tmp;
827 dev->post_bit_count += 1000000;
829 dev_dbg(&client->dev, "ber errors=%u total=1000000\n", u16tmp);
831 c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
832 c->post_bit_error.stat[0].uvalue = dev->post_bit_error;
833 c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
834 c->post_bit_count.stat[0].uvalue = dev->post_bit_count;
836 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
837 c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
840 err_schedule_delayed_work:
841 schedule_delayed_work(&dev->stat_work, msecs_to_jiffies(2000));
844 dev_dbg(&client->dev, "failed=%d\n", ret);
848 * I2C gate/mux/repeater logic
849 * We must use unlocked __i2c_transfer() here (through regmap) because of I2C
850 * adapter lock is already taken by tuner driver.
851 * There is delay mechanism to avoid unneeded I2C gate open / close. Gate close
852 * is delayed here a little bit in order to see if there is sequence of I2C
853 * messages sent to same I2C bus.
855 static void rtl2832_i2c_gate_work(struct work_struct *work)
857 struct rtl2832_dev *dev = container_of(work, struct rtl2832_dev, i2c_gate_work.work);
858 struct i2c_client *client = dev->client;
862 ret = rtl2832_update_bits(dev->client, 0x101, 0x08, 0x00);
868 dev_dbg(&client->dev, "failed=%d\n", ret);
872 static int rtl2832_select(struct i2c_adapter *adap, void *mux_priv, u32 chan_id)
874 struct rtl2832_dev *dev = mux_priv;
875 struct i2c_client *client = dev->client;
878 /* terminate possible gate closing */
879 cancel_delayed_work(&dev->i2c_gate_work);
882 * chan_id 1 is muxed adapter demod provides and chan_id 0 is demod
883 * itself. We need open gate when request is for chan_id 1. On that case
884 * I2C adapter lock is already taken and due to that we will use
885 * regmap_update_bits() which does not lock again I2C adapter.
888 ret = regmap_update_bits(dev->regmap, 0x101, 0x08, 0x08);
890 ret = rtl2832_update_bits(dev->client, 0x101, 0x08, 0x00);
896 dev_dbg(&client->dev, "failed=%d\n", ret);
900 static int rtl2832_deselect(struct i2c_adapter *adap, void *mux_priv,
903 struct rtl2832_dev *dev = mux_priv;
905 schedule_delayed_work(&dev->i2c_gate_work, usecs_to_jiffies(100));
909 static struct dvb_frontend_ops rtl2832_ops = {
910 .delsys = { SYS_DVBT },
912 .name = "Realtek RTL2832 (DVB-T)",
913 .frequency_min = 174000000,
914 .frequency_max = 862000000,
915 .frequency_stepsize = 166667,
916 .caps = FE_CAN_FEC_1_2 |
926 FE_CAN_TRANSMISSION_MODE_AUTO |
927 FE_CAN_GUARD_INTERVAL_AUTO |
928 FE_CAN_HIERARCHY_AUTO |
933 .init = rtl2832_init,
934 .sleep = rtl2832_sleep,
936 .get_tune_settings = rtl2832_get_tune_settings,
938 .set_frontend = rtl2832_set_frontend,
939 .get_frontend = rtl2832_get_frontend,
941 .read_status = rtl2832_read_status,
942 .read_snr = rtl2832_read_snr,
943 .read_ber = rtl2832_read_ber,
946 static bool rtl2832_volatile_reg(struct device *dev, unsigned int reg)
953 case 0x40c ... 0x40d:
963 * We implement own I2C access routines for regmap in order to get manual access
964 * to I2C adapter lock, which is needed for I2C mux adapter.
966 static int rtl2832_regmap_read(void *context, const void *reg_buf,
967 size_t reg_size, void *val_buf, size_t val_size)
969 struct i2c_client *client = context;
971 struct i2c_msg msg[2] = {
973 .addr = client->addr,
976 .buf = (u8 *)reg_buf,
978 .addr = client->addr,
985 ret = __i2c_transfer(client->adapter, msg, 2);
987 dev_warn(&client->dev, "i2c reg read failed %d\n", ret);
995 static int rtl2832_regmap_write(void *context, const void *data, size_t count)
997 struct i2c_client *client = context;
999 struct i2c_msg msg[1] = {
1001 .addr = client->addr,
1008 ret = __i2c_transfer(client->adapter, msg, 1);
1010 dev_warn(&client->dev, "i2c reg write failed %d\n", ret);
1018 static int rtl2832_regmap_gather_write(void *context, const void *reg,
1019 size_t reg_len, const void *val,
1022 struct i2c_client *client = context;
1025 struct i2c_msg msg[1] = {
1027 .addr = client->addr,
1034 buf[0] = *(u8 const *)reg;
1035 memcpy(&buf[1], val, val_len);
1037 ret = __i2c_transfer(client->adapter, msg, 1);
1039 dev_warn(&client->dev, "i2c reg write failed %d\n", ret);
1047 static struct dvb_frontend *rtl2832_get_dvb_frontend(struct i2c_client *client)
1049 struct rtl2832_dev *dev = i2c_get_clientdata(client);
1051 dev_dbg(&client->dev, "\n");
1055 static struct i2c_adapter *rtl2832_get_i2c_adapter_(struct i2c_client *client)
1057 struct rtl2832_dev *dev = i2c_get_clientdata(client);
1059 dev_dbg(&client->dev, "\n");
1060 return dev->i2c_adapter_tuner;
1063 static struct i2c_adapter *rtl2832_get_private_i2c_adapter_(struct i2c_client *client)
1065 struct rtl2832_dev *dev = i2c_get_clientdata(client);
1067 dev_dbg(&client->dev, "\n");
1068 return dev->i2c_adapter;
1071 static int rtl2832_enable_slave_ts(struct i2c_client *client)
1073 struct rtl2832_dev *dev = i2c_get_clientdata(client);
1076 dev_dbg(&client->dev, "\n");
1078 ret = rtl2832_bulk_write(client, 0x10c, "\x5f\xff", 2);
1082 ret = rtl2832_wr_demod_reg(dev, DVBT_PIP_ON, 0x1);
1086 ret = rtl2832_bulk_write(client, 0x0bc, "\x18", 1);
1090 ret = rtl2832_bulk_write(client, 0x022, "\x01", 1);
1094 ret = rtl2832_bulk_write(client, 0x026, "\x1f", 1);
1098 ret = rtl2832_bulk_write(client, 0x027, "\xff", 1);
1102 ret = rtl2832_bulk_write(client, 0x192, "\x7f\xf7\xff", 3);
1107 ret = rtl2832_wr_demod_reg(dev, DVBT_SOFT_RST, 0x1);
1111 ret = rtl2832_wr_demod_reg(dev, DVBT_SOFT_RST, 0x0);
1117 dev_dbg(&client->dev, "failed=%d\n", ret);
1121 static int rtl2832_pid_filter_ctrl(struct dvb_frontend *fe, int onoff)
1123 struct rtl2832_dev *dev = fe->demodulator_priv;
1124 struct i2c_client *client = dev->client;
1128 dev_dbg(&client->dev, "onoff=%d\n", onoff);
1130 /* enable / disable PID filter */
1136 ret = rtl2832_update_bits(client, 0x061, 0xc0, u8tmp);
1142 dev_dbg(&client->dev, "failed=%d\n", ret);
1146 static int rtl2832_pid_filter(struct dvb_frontend *fe, u8 index, u16 pid,
1149 struct rtl2832_dev *dev = fe->demodulator_priv;
1150 struct i2c_client *client = dev->client;
1154 dev_dbg(&client->dev, "index=%d pid=%04x onoff=%d\n",
1157 /* skip invalid PIDs (0x2000) */
1158 if (pid > 0x1fff || index > 32)
1162 set_bit(index, &dev->filters);
1164 clear_bit(index, &dev->filters);
1166 /* enable / disable PIDs */
1167 buf[0] = (dev->filters >> 0) & 0xff;
1168 buf[1] = (dev->filters >> 8) & 0xff;
1169 buf[2] = (dev->filters >> 16) & 0xff;
1170 buf[3] = (dev->filters >> 24) & 0xff;
1171 ret = rtl2832_bulk_write(client, 0x062, buf, 4);
1176 buf[0] = (pid >> 8) & 0xff;
1177 buf[1] = (pid >> 0) & 0xff;
1178 ret = rtl2832_bulk_write(client, 0x066 + 2 * index, buf, 2);
1184 dev_dbg(&client->dev, "failed=%d\n", ret);
1188 static int rtl2832_probe(struct i2c_client *client,
1189 const struct i2c_device_id *id)
1191 struct rtl2832_platform_data *pdata = client->dev.platform_data;
1192 struct i2c_adapter *i2c = client->adapter;
1193 struct rtl2832_dev *dev;
1196 static const struct regmap_bus regmap_bus = {
1197 .read = rtl2832_regmap_read,
1198 .write = rtl2832_regmap_write,
1199 .gather_write = rtl2832_regmap_gather_write,
1200 .val_format_endian_default = REGMAP_ENDIAN_NATIVE,
1202 static const struct regmap_range_cfg regmap_range_cfg[] = {
1204 .selector_reg = 0x00,
1205 .selector_mask = 0xff,
1206 .selector_shift = 0,
1208 .window_len = 0x100,
1209 .range_min = 0 * 0x100,
1210 .range_max = 5 * 0x100,
1213 static const struct regmap_config regmap_config = {
1216 .volatile_reg = rtl2832_volatile_reg,
1217 .max_register = 5 * 0x100,
1218 .ranges = regmap_range_cfg,
1219 .num_ranges = ARRAY_SIZE(regmap_range_cfg),
1220 .cache_type = REGCACHE_RBTREE,
1223 dev_dbg(&client->dev, "\n");
1225 /* allocate memory for the internal state */
1226 dev = kzalloc(sizeof(struct rtl2832_dev), GFP_KERNEL);
1232 /* setup the state */
1233 i2c_set_clientdata(client, dev);
1234 dev->client = client;
1235 dev->pdata = client->dev.platform_data;
1236 if (pdata->config) {
1237 dev->pdata->clk = pdata->config->xtal;
1238 dev->pdata->tuner = pdata->config->tuner;
1240 dev->sleeping = true;
1241 INIT_DELAYED_WORK(&dev->i2c_gate_work, rtl2832_i2c_gate_work);
1242 INIT_DELAYED_WORK(&dev->stat_work, rtl2832_stat_work);
1244 dev->regmap = regmap_init(&client->dev, ®map_bus, client,
1246 if (IS_ERR(dev->regmap)) {
1247 ret = PTR_ERR(dev->regmap);
1250 /* create muxed i2c adapter for demod itself */
1251 dev->i2c_adapter = i2c_add_mux_adapter(i2c, &i2c->dev, dev, 0, 0, 0,
1252 rtl2832_select, NULL);
1253 if (dev->i2c_adapter == NULL) {
1255 goto err_regmap_exit;
1258 /* check if the demod is there */
1259 ret = rtl2832_bulk_read(client, 0x000, &tmp, 1);
1261 goto err_i2c_del_mux_adapter;
1263 /* create muxed i2c adapter for demod tuner bus */
1264 dev->i2c_adapter_tuner = i2c_add_mux_adapter(i2c, &i2c->dev, dev,
1265 0, 1, 0, rtl2832_select, rtl2832_deselect);
1266 if (dev->i2c_adapter_tuner == NULL) {
1268 goto err_i2c_del_mux_adapter;
1271 /* create dvb_frontend */
1272 memcpy(&dev->fe.ops, &rtl2832_ops, sizeof(struct dvb_frontend_ops));
1273 dev->fe.demodulator_priv = dev;
1275 /* setup callbacks */
1276 pdata->get_dvb_frontend = rtl2832_get_dvb_frontend;
1277 pdata->get_i2c_adapter = rtl2832_get_i2c_adapter_;
1278 pdata->get_private_i2c_adapter = rtl2832_get_private_i2c_adapter_;
1279 pdata->enable_slave_ts = rtl2832_enable_slave_ts;
1280 pdata->pid_filter = rtl2832_pid_filter;
1281 pdata->pid_filter_ctrl = rtl2832_pid_filter_ctrl;
1282 pdata->bulk_read = rtl2832_bulk_read;
1283 pdata->bulk_write = rtl2832_bulk_write;
1284 pdata->update_bits = rtl2832_update_bits;
1286 dev_info(&client->dev, "Realtek RTL2832 successfully attached\n");
1288 err_i2c_del_mux_adapter:
1289 i2c_del_mux_adapter(dev->i2c_adapter);
1291 regmap_exit(dev->regmap);
1295 dev_dbg(&client->dev, "failed=%d\n", ret);
1299 static int rtl2832_remove(struct i2c_client *client)
1301 struct rtl2832_dev *dev = i2c_get_clientdata(client);
1303 dev_dbg(&client->dev, "\n");
1305 cancel_delayed_work_sync(&dev->i2c_gate_work);
1307 i2c_del_mux_adapter(dev->i2c_adapter_tuner);
1309 i2c_del_mux_adapter(dev->i2c_adapter);
1311 regmap_exit(dev->regmap);
1318 static const struct i2c_device_id rtl2832_id_table[] = {
1322 MODULE_DEVICE_TABLE(i2c, rtl2832_id_table);
1324 static struct i2c_driver rtl2832_driver = {
1326 .owner = THIS_MODULE,
1329 .probe = rtl2832_probe,
1330 .remove = rtl2832_remove,
1331 .id_table = rtl2832_id_table,
1334 module_i2c_driver(rtl2832_driver);
1336 MODULE_AUTHOR("Thomas Mair <mair.thomas86@gmail.com>");
1337 MODULE_DESCRIPTION("Realtek RTL2832 DVB-T demodulator driver");
1338 MODULE_LICENSE("GPL");
1339 MODULE_VERSION("0.5");