2 * Realtek RTL2832 DVB-T demodulator driver
4 * Copyright (C) 2012 Thomas Mair <thomas.mair86@gmail.com>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
21 #include "rtl2832_priv.h"
23 #include <linux/bitops.h>
25 /* Max transfer size done by I2C transfer functions */
26 #define MAX_XFER_SIZE 64
27 #define REG_MASK(b) (BIT(b + 1) - 1)
29 static const struct rtl2832_reg_entry registers[] = {
30 [DVBT_SOFT_RST] = {0x1, 0x1, 2, 2},
31 [DVBT_IIC_REPEAT] = {0x1, 0x1, 3, 3},
32 [DVBT_TR_WAIT_MIN_8K] = {0x1, 0x88, 11, 2},
33 [DVBT_RSD_BER_FAIL_VAL] = {0x1, 0x8f, 15, 0},
34 [DVBT_EN_BK_TRK] = {0x1, 0xa6, 7, 7},
35 [DVBT_AD_EN_REG] = {0x0, 0x8, 7, 7},
36 [DVBT_AD_EN_REG1] = {0x0, 0x8, 6, 6},
37 [DVBT_EN_BBIN] = {0x1, 0xb1, 0, 0},
38 [DVBT_MGD_THD0] = {0x1, 0x95, 7, 0},
39 [DVBT_MGD_THD1] = {0x1, 0x96, 7, 0},
40 [DVBT_MGD_THD2] = {0x1, 0x97, 7, 0},
41 [DVBT_MGD_THD3] = {0x1, 0x98, 7, 0},
42 [DVBT_MGD_THD4] = {0x1, 0x99, 7, 0},
43 [DVBT_MGD_THD5] = {0x1, 0x9a, 7, 0},
44 [DVBT_MGD_THD6] = {0x1, 0x9b, 7, 0},
45 [DVBT_MGD_THD7] = {0x1, 0x9c, 7, 0},
46 [DVBT_EN_CACQ_NOTCH] = {0x1, 0x61, 4, 4},
47 [DVBT_AD_AV_REF] = {0x0, 0x9, 6, 0},
48 [DVBT_REG_PI] = {0x0, 0xa, 2, 0},
49 [DVBT_PIP_ON] = {0x0, 0x21, 3, 3},
50 [DVBT_SCALE1_B92] = {0x2, 0x92, 7, 0},
51 [DVBT_SCALE1_B93] = {0x2, 0x93, 7, 0},
52 [DVBT_SCALE1_BA7] = {0x2, 0xa7, 7, 0},
53 [DVBT_SCALE1_BA9] = {0x2, 0xa9, 7, 0},
54 [DVBT_SCALE1_BAA] = {0x2, 0xaa, 7, 0},
55 [DVBT_SCALE1_BAB] = {0x2, 0xab, 7, 0},
56 [DVBT_SCALE1_BAC] = {0x2, 0xac, 7, 0},
57 [DVBT_SCALE1_BB0] = {0x2, 0xb0, 7, 0},
58 [DVBT_SCALE1_BB1] = {0x2, 0xb1, 7, 0},
59 [DVBT_KB_P1] = {0x1, 0x64, 3, 1},
60 [DVBT_KB_P2] = {0x1, 0x64, 6, 4},
61 [DVBT_KB_P3] = {0x1, 0x65, 2, 0},
62 [DVBT_OPT_ADC_IQ] = {0x0, 0x6, 5, 4},
63 [DVBT_AD_AVI] = {0x0, 0x9, 1, 0},
64 [DVBT_AD_AVQ] = {0x0, 0x9, 3, 2},
65 [DVBT_K1_CR_STEP12] = {0x2, 0xad, 9, 4},
66 [DVBT_TRK_KS_P2] = {0x1, 0x6f, 2, 0},
67 [DVBT_TRK_KS_I2] = {0x1, 0x70, 5, 3},
68 [DVBT_TR_THD_SET2] = {0x1, 0x72, 3, 0},
69 [DVBT_TRK_KC_P2] = {0x1, 0x73, 5, 3},
70 [DVBT_TRK_KC_I2] = {0x1, 0x75, 2, 0},
71 [DVBT_CR_THD_SET2] = {0x1, 0x76, 7, 6},
72 [DVBT_PSET_IFFREQ] = {0x1, 0x19, 21, 0},
73 [DVBT_SPEC_INV] = {0x1, 0x15, 0, 0},
74 [DVBT_RSAMP_RATIO] = {0x1, 0x9f, 27, 2},
75 [DVBT_CFREQ_OFF_RATIO] = {0x1, 0x9d, 23, 4},
76 [DVBT_FSM_STAGE] = {0x3, 0x51, 6, 3},
77 [DVBT_RX_CONSTEL] = {0x3, 0x3c, 3, 2},
78 [DVBT_RX_HIER] = {0x3, 0x3c, 6, 4},
79 [DVBT_RX_C_RATE_LP] = {0x3, 0x3d, 2, 0},
80 [DVBT_RX_C_RATE_HP] = {0x3, 0x3d, 5, 3},
81 [DVBT_GI_IDX] = {0x3, 0x51, 1, 0},
82 [DVBT_FFT_MODE_IDX] = {0x3, 0x51, 2, 2},
83 [DVBT_RSD_BER_EST] = {0x3, 0x4e, 15, 0},
84 [DVBT_CE_EST_EVM] = {0x4, 0xc, 15, 0},
85 [DVBT_RF_AGC_VAL] = {0x3, 0x5b, 13, 0},
86 [DVBT_IF_AGC_VAL] = {0x3, 0x59, 13, 0},
87 [DVBT_DAGC_VAL] = {0x3, 0x5, 7, 0},
88 [DVBT_SFREQ_OFF] = {0x3, 0x18, 13, 0},
89 [DVBT_CFREQ_OFF] = {0x3, 0x5f, 17, 0},
90 [DVBT_POLAR_RF_AGC] = {0x0, 0xe, 1, 1},
91 [DVBT_POLAR_IF_AGC] = {0x0, 0xe, 0, 0},
92 [DVBT_AAGC_HOLD] = {0x1, 0x4, 5, 5},
93 [DVBT_EN_RF_AGC] = {0x1, 0x4, 6, 6},
94 [DVBT_EN_IF_AGC] = {0x1, 0x4, 7, 7},
95 [DVBT_IF_AGC_MIN] = {0x1, 0x8, 7, 0},
96 [DVBT_IF_AGC_MAX] = {0x1, 0x9, 7, 0},
97 [DVBT_RF_AGC_MIN] = {0x1, 0xa, 7, 0},
98 [DVBT_RF_AGC_MAX] = {0x1, 0xb, 7, 0},
99 [DVBT_IF_AGC_MAN] = {0x1, 0xc, 6, 6},
100 [DVBT_IF_AGC_MAN_VAL] = {0x1, 0xc, 13, 0},
101 [DVBT_RF_AGC_MAN] = {0x1, 0xe, 6, 6},
102 [DVBT_RF_AGC_MAN_VAL] = {0x1, 0xe, 13, 0},
103 [DVBT_DAGC_TRG_VAL] = {0x1, 0x12, 7, 0},
104 [DVBT_AGC_TARG_VAL_0] = {0x1, 0x2, 0, 0},
105 [DVBT_AGC_TARG_VAL_8_1] = {0x1, 0x3, 7, 0},
106 [DVBT_AAGC_LOOP_GAIN] = {0x1, 0xc7, 5, 1},
107 [DVBT_LOOP_GAIN2_3_0] = {0x1, 0x4, 4, 1},
108 [DVBT_LOOP_GAIN2_4] = {0x1, 0x5, 7, 7},
109 [DVBT_LOOP_GAIN3] = {0x1, 0xc8, 4, 0},
110 [DVBT_VTOP1] = {0x1, 0x6, 5, 0},
111 [DVBT_VTOP2] = {0x1, 0xc9, 5, 0},
112 [DVBT_VTOP3] = {0x1, 0xca, 5, 0},
113 [DVBT_KRF1] = {0x1, 0xcb, 7, 0},
114 [DVBT_KRF2] = {0x1, 0x7, 7, 0},
115 [DVBT_KRF3] = {0x1, 0xcd, 7, 0},
116 [DVBT_KRF4] = {0x1, 0xce, 7, 0},
117 [DVBT_EN_GI_PGA] = {0x1, 0xe5, 0, 0},
118 [DVBT_THD_LOCK_UP] = {0x1, 0xd9, 8, 0},
119 [DVBT_THD_LOCK_DW] = {0x1, 0xdb, 8, 0},
120 [DVBT_THD_UP1] = {0x1, 0xdd, 7, 0},
121 [DVBT_THD_DW1] = {0x1, 0xde, 7, 0},
122 [DVBT_INTER_CNT_LEN] = {0x1, 0xd8, 3, 0},
123 [DVBT_GI_PGA_STATE] = {0x1, 0xe6, 3, 3},
124 [DVBT_EN_AGC_PGA] = {0x1, 0xd7, 0, 0},
125 [DVBT_CKOUTPAR] = {0x1, 0x7b, 5, 5},
126 [DVBT_CKOUT_PWR] = {0x1, 0x7b, 6, 6},
127 [DVBT_SYNC_DUR] = {0x1, 0x7b, 7, 7},
128 [DVBT_ERR_DUR] = {0x1, 0x7c, 0, 0},
129 [DVBT_SYNC_LVL] = {0x1, 0x7c, 1, 1},
130 [DVBT_ERR_LVL] = {0x1, 0x7c, 2, 2},
131 [DVBT_VAL_LVL] = {0x1, 0x7c, 3, 3},
132 [DVBT_SERIAL] = {0x1, 0x7c, 4, 4},
133 [DVBT_SER_LSB] = {0x1, 0x7c, 5, 5},
134 [DVBT_CDIV_PH0] = {0x1, 0x7d, 3, 0},
135 [DVBT_CDIV_PH1] = {0x1, 0x7d, 7, 4},
136 [DVBT_MPEG_IO_OPT_2_2] = {0x0, 0x6, 7, 7},
137 [DVBT_MPEG_IO_OPT_1_0] = {0x0, 0x7, 7, 6},
138 [DVBT_CKOUTPAR_PIP] = {0x0, 0xb7, 4, 4},
139 [DVBT_CKOUT_PWR_PIP] = {0x0, 0xb7, 3, 3},
140 [DVBT_SYNC_LVL_PIP] = {0x0, 0xb7, 2, 2},
141 [DVBT_ERR_LVL_PIP] = {0x0, 0xb7, 1, 1},
142 [DVBT_VAL_LVL_PIP] = {0x0, 0xb7, 0, 0},
143 [DVBT_CKOUTPAR_PID] = {0x0, 0xb9, 4, 4},
144 [DVBT_CKOUT_PWR_PID] = {0x0, 0xb9, 3, 3},
145 [DVBT_SYNC_LVL_PID] = {0x0, 0xb9, 2, 2},
146 [DVBT_ERR_LVL_PID] = {0x0, 0xb9, 1, 1},
147 [DVBT_VAL_LVL_PID] = {0x0, 0xb9, 0, 0},
148 [DVBT_SM_PASS] = {0x1, 0x93, 11, 0},
149 [DVBT_AD7_SETTING] = {0x0, 0x11, 15, 0},
150 [DVBT_RSSI_R] = {0x3, 0x1, 6, 0},
151 [DVBT_ACI_DET_IND] = {0x3, 0x12, 0, 0},
152 [DVBT_REG_MON] = {0x0, 0xd, 1, 0},
153 [DVBT_REG_MONSEL] = {0x0, 0xd, 2, 2},
154 [DVBT_REG_GPE] = {0x0, 0xd, 7, 7},
155 [DVBT_REG_GPO] = {0x0, 0x10, 0, 0},
156 [DVBT_REG_4MSEL] = {0x0, 0x13, 0, 0},
159 /* write multiple hardware registers */
160 static int rtl2832_wr(struct rtl2832_priv *priv, u8 reg, u8 *val, int len)
163 u8 buf[MAX_XFER_SIZE];
164 struct i2c_msg msg[1] = {
166 .addr = priv->cfg.i2c_addr,
173 if (1 + len > sizeof(buf)) {
174 dev_warn(&priv->i2c->dev,
175 "%s: i2c wr reg=%04x: len=%d is too big!\n",
176 KBUILD_MODNAME, reg, len);
181 memcpy(&buf[1], val, len);
183 ret = i2c_transfer(priv->i2c_adapter, msg, 1);
187 dev_warn(&priv->i2c->dev,
188 "%s: i2c wr failed=%d reg=%02x len=%d\n",
189 KBUILD_MODNAME, ret, reg, len);
195 /* read multiple hardware registers */
196 static int rtl2832_rd(struct rtl2832_priv *priv, u8 reg, u8 *val, int len)
199 struct i2c_msg msg[2] = {
201 .addr = priv->cfg.i2c_addr,
206 .addr = priv->cfg.i2c_addr,
213 ret = i2c_transfer(priv->i2c_adapter, msg, 2);
217 dev_warn(&priv->i2c->dev,
218 "%s: i2c rd failed=%d reg=%02x len=%d\n",
219 KBUILD_MODNAME, ret, reg, len);
225 /* write multiple registers */
226 static int rtl2832_wr_regs(struct rtl2832_priv *priv, u8 reg, u8 page, u8 *val,
231 /* switch bank if needed */
232 if (page != priv->page) {
233 ret = rtl2832_wr(priv, 0x00, &page, 1);
240 return rtl2832_wr(priv, reg, val, len);
243 /* read multiple registers */
244 static int rtl2832_rd_regs(struct rtl2832_priv *priv, u8 reg, u8 page, u8 *val,
249 /* switch bank if needed */
250 if (page != priv->page) {
251 ret = rtl2832_wr(priv, 0x00, &page, 1);
258 return rtl2832_rd(priv, reg, val, len);
261 /* write single register */
262 static int rtl2832_wr_reg(struct rtl2832_priv *priv, u8 reg, u8 page, u8 val)
264 return rtl2832_wr_regs(priv, reg, page, &val, 1);
267 /* read single register */
268 static int rtl2832_rd_reg(struct rtl2832_priv *priv, u8 reg, u8 page, u8 *val)
270 return rtl2832_rd_regs(priv, reg, page, val, 1);
273 static int rtl2832_rd_demod_reg(struct rtl2832_priv *priv, int reg, u32 *val)
287 reg_start_addr = registers[reg].start_address;
288 msb = registers[reg].msb;
289 lsb = registers[reg].lsb;
290 page = registers[reg].page;
292 len = (msb >> 3) + 1;
293 mask = REG_MASK(msb - lsb);
295 ret = rtl2832_rd_regs(priv, reg_start_addr, page, &reading[0], len);
300 for (i = 0; i < len; i++)
301 reading_tmp |= reading[i] << ((len - 1 - i) * 8);
303 *val = (reading_tmp >> lsb) & mask;
308 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
313 static int rtl2832_wr_demod_reg(struct rtl2832_priv *priv, int reg, u32 val)
329 reg_start_addr = registers[reg].start_address;
330 msb = registers[reg].msb;
331 lsb = registers[reg].lsb;
332 page = registers[reg].page;
334 len = (msb >> 3) + 1;
335 mask = REG_MASK(msb - lsb);
338 ret = rtl2832_rd_regs(priv, reg_start_addr, page, &reading[0], len);
343 for (i = 0; i < len; i++)
344 reading_tmp |= reading[i] << ((len - 1 - i) * 8);
346 writing_tmp = reading_tmp & ~(mask << lsb);
347 writing_tmp |= ((val & mask) << lsb);
350 for (i = 0; i < len; i++)
351 writing[i] = (writing_tmp >> ((len - 1 - i) * 8)) & 0xff;
353 ret = rtl2832_wr_regs(priv, reg_start_addr, page, &writing[0], len);
360 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
365 static int rtl2832_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
368 struct rtl2832_priv *priv = fe->demodulator_priv;
370 dev_dbg(&priv->i2c->dev, "%s: enable=%d\n", __func__, enable);
372 /* gate already open or close */
373 if (priv->i2c_gate_state == enable)
376 ret = rtl2832_wr_demod_reg(priv, DVBT_IIC_REPEAT, (enable ? 0x1 : 0x0));
380 priv->i2c_gate_state = enable;
384 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
389 static int rtl2832_set_if(struct dvb_frontend *fe, u32 if_freq)
391 struct rtl2832_priv *priv = fe->demodulator_priv;
394 u8 en_bbin = (if_freq == 0 ? 0x1 : 0x0);
397 * PSET_IFFREQ = - floor((IfFreqHz % CrystalFreqHz) * pow(2, 22)
401 pset_iffreq = if_freq % priv->cfg.xtal;
402 pset_iffreq *= 0x400000;
403 pset_iffreq = div_u64(pset_iffreq, priv->cfg.xtal);
404 pset_iffreq = -pset_iffreq;
405 pset_iffreq = pset_iffreq & 0x3fffff;
406 dev_dbg(&priv->i2c->dev, "%s: if_frequency=%d pset_iffreq=%08x\n",
407 __func__, if_freq, (unsigned)pset_iffreq);
409 ret = rtl2832_wr_demod_reg(priv, DVBT_EN_BBIN, en_bbin);
413 ret = rtl2832_wr_demod_reg(priv, DVBT_PSET_IFFREQ, pset_iffreq);
418 static int rtl2832_init(struct dvb_frontend *fe)
420 struct rtl2832_priv *priv = fe->demodulator_priv;
421 const struct rtl2832_reg_value *init;
424 /* initialization values for the demodulator registers */
425 struct rtl2832_reg_value rtl2832_initial_regs[] = {
426 {DVBT_AD_EN_REG, 0x1},
427 {DVBT_AD_EN_REG1, 0x1},
428 {DVBT_RSD_BER_FAIL_VAL, 0x2800},
429 {DVBT_MGD_THD0, 0x10},
430 {DVBT_MGD_THD1, 0x20},
431 {DVBT_MGD_THD2, 0x20},
432 {DVBT_MGD_THD3, 0x40},
433 {DVBT_MGD_THD4, 0x22},
434 {DVBT_MGD_THD5, 0x32},
435 {DVBT_MGD_THD6, 0x37},
436 {DVBT_MGD_THD7, 0x39},
437 {DVBT_EN_BK_TRK, 0x0},
438 {DVBT_EN_CACQ_NOTCH, 0x0},
439 {DVBT_AD_AV_REF, 0x2a},
442 {DVBT_CDIV_PH0, 0x8},
443 {DVBT_CDIV_PH1, 0x8},
444 {DVBT_SCALE1_B92, 0x4},
445 {DVBT_SCALE1_B93, 0xb0},
446 {DVBT_SCALE1_BA7, 0x78},
447 {DVBT_SCALE1_BA9, 0x28},
448 {DVBT_SCALE1_BAA, 0x59},
449 {DVBT_SCALE1_BAB, 0x83},
450 {DVBT_SCALE1_BAC, 0xd4},
451 {DVBT_SCALE1_BB0, 0x65},
452 {DVBT_SCALE1_BB1, 0x43},
456 {DVBT_K1_CR_STEP12, 0xa},
459 {DVBT_CDIV_PH0, 0x9},
460 {DVBT_CDIV_PH1, 0x9},
461 {DVBT_MPEG_IO_OPT_2_2, 0x0},
462 {DVBT_MPEG_IO_OPT_1_0, 0x0},
463 {DVBT_TRK_KS_P2, 0x4},
464 {DVBT_TRK_KS_I2, 0x7},
465 {DVBT_TR_THD_SET2, 0x6},
466 {DVBT_TRK_KC_I2, 0x5},
467 {DVBT_CR_THD_SET2, 0x1},
470 dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
472 for (i = 0; i < ARRAY_SIZE(rtl2832_initial_regs); i++) {
473 ret = rtl2832_wr_demod_reg(priv, rtl2832_initial_regs[i].reg,
474 rtl2832_initial_regs[i].value);
479 /* load tuner specific settings */
480 dev_dbg(&priv->i2c->dev, "%s: load settings for tuner=%02x\n",
481 __func__, priv->cfg.tuner);
482 switch (priv->cfg.tuner) {
483 case RTL2832_TUNER_FC0012:
484 case RTL2832_TUNER_FC0013:
485 len = ARRAY_SIZE(rtl2832_tuner_init_fc0012);
486 init = rtl2832_tuner_init_fc0012;
488 case RTL2832_TUNER_TUA9001:
489 len = ARRAY_SIZE(rtl2832_tuner_init_tua9001);
490 init = rtl2832_tuner_init_tua9001;
492 case RTL2832_TUNER_E4000:
493 len = ARRAY_SIZE(rtl2832_tuner_init_e4000);
494 init = rtl2832_tuner_init_e4000;
496 case RTL2832_TUNER_R820T:
497 case RTL2832_TUNER_R828D:
498 len = ARRAY_SIZE(rtl2832_tuner_init_r820t);
499 init = rtl2832_tuner_init_r820t;
506 for (i = 0; i < len; i++) {
507 ret = rtl2832_wr_demod_reg(priv, init[i].reg, init[i].value);
513 * r820t NIM code does a software reset here at the demod -
514 * may not be needed, as there's already a software reset at
519 ret = rtl2832_wr_demod_reg(priv, DVBT_SOFT_RST, 0x1);
523 ret = rtl2832_wr_demod_reg(priv, DVBT_SOFT_RST, 0x0);
528 priv->sleeping = false;
533 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
537 static int rtl2832_sleep(struct dvb_frontend *fe)
539 struct rtl2832_priv *priv = fe->demodulator_priv;
541 dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
542 priv->sleeping = true;
546 static int rtl2832_get_tune_settings(struct dvb_frontend *fe,
547 struct dvb_frontend_tune_settings *s)
549 struct rtl2832_priv *priv = fe->demodulator_priv;
551 dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
552 s->min_delay_ms = 1000;
553 s->step_size = fe->ops.info.frequency_stepsize * 2;
554 s->max_drift = (fe->ops.info.frequency_stepsize * 2) + 1;
558 static int rtl2832_set_frontend(struct dvb_frontend *fe)
560 struct rtl2832_priv *priv = fe->demodulator_priv;
561 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
563 u64 bw_mode, num, num2;
564 u32 resamp_ratio, cfreq_off_ratio;
565 static u8 bw_params[3][32] = {
566 /* 6 MHz bandwidth */
568 0xf5, 0xff, 0x15, 0x38, 0x5d, 0x6d, 0x52, 0x07, 0xfa, 0x2f,
569 0x53, 0xf5, 0x3f, 0xca, 0x0b, 0x91, 0xea, 0x30, 0x63, 0xb2,
570 0x13, 0xda, 0x0b, 0xc4, 0x18, 0x7e, 0x16, 0x66, 0x08, 0x67,
574 /* 7 MHz bandwidth */
576 0xe7, 0xcc, 0xb5, 0xba, 0xe8, 0x2f, 0x67, 0x61, 0x00, 0xaf,
577 0x86, 0xf2, 0xbf, 0x59, 0x04, 0x11, 0xb6, 0x33, 0xa4, 0x30,
578 0x15, 0x10, 0x0a, 0x42, 0x18, 0xf8, 0x17, 0xd9, 0x07, 0x22,
582 /* 8 MHz bandwidth */
584 0x09, 0xf6, 0xd2, 0xa7, 0x9a, 0xc9, 0x27, 0x77, 0x06, 0xbf,
585 0xec, 0xf4, 0x4f, 0x0b, 0xfc, 0x01, 0x63, 0x35, 0x54, 0xa7,
586 0x16, 0x66, 0x08, 0xb4, 0x19, 0x6e, 0x19, 0x65, 0x05, 0xc8,
592 dev_dbg(&priv->i2c->dev,
593 "%s: frequency=%d bandwidth_hz=%d inversion=%d\n",
594 __func__, c->frequency, c->bandwidth_hz, c->inversion);
597 if (fe->ops.tuner_ops.set_params)
598 fe->ops.tuner_ops.set_params(fe);
600 /* PIP mode related */
601 ret = rtl2832_wr_regs(priv, 0x92, 1, "\x00\x0f\xff", 3);
605 /* If the frontend has get_if_frequency(), use it */
606 if (fe->ops.tuner_ops.get_if_frequency) {
609 ret = fe->ops.tuner_ops.get_if_frequency(fe, &if_freq);
613 ret = rtl2832_set_if(fe, if_freq);
618 switch (c->bandwidth_hz) {
632 dev_dbg(&priv->i2c->dev, "%s: invalid bandwidth\n", __func__);
636 for (j = 0; j < sizeof(bw_params[0]); j++) {
637 ret = rtl2832_wr_regs(priv, 0x1c+j, 1, &bw_params[i][j], 1);
642 /* calculate and set resample ratio
643 * RSAMP_RATIO = floor(CrystalFreqHz * 7 * pow(2, 22)
644 * / ConstWithBandwidthMode)
646 num = priv->cfg.xtal * 7;
648 num = div_u64(num, bw_mode);
649 resamp_ratio = num & 0x3ffffff;
650 ret = rtl2832_wr_demod_reg(priv, DVBT_RSAMP_RATIO, resamp_ratio);
654 /* calculate and set cfreq off ratio
655 * CFREQ_OFF_RATIO = - floor(ConstWithBandwidthMode * pow(2, 20)
656 * / (CrystalFreqHz * 7))
659 num2 = priv->cfg.xtal * 7;
660 num = div_u64(num, num2);
662 cfreq_off_ratio = num & 0xfffff;
663 ret = rtl2832_wr_demod_reg(priv, DVBT_CFREQ_OFF_RATIO, cfreq_off_ratio);
668 ret = rtl2832_wr_demod_reg(priv, DVBT_SOFT_RST, 0x1);
672 ret = rtl2832_wr_demod_reg(priv, DVBT_SOFT_RST, 0x0);
678 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
682 static int rtl2832_get_frontend(struct dvb_frontend *fe)
684 struct rtl2832_priv *priv = fe->demodulator_priv;
685 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
692 ret = rtl2832_rd_regs(priv, 0x3c, 3, buf, 2);
696 ret = rtl2832_rd_reg(priv, 0x51, 3, &buf[2]);
700 dev_dbg(&priv->i2c->dev, "%s: TPS=%*ph\n", __func__, 3, buf);
702 switch ((buf[0] >> 2) & 3) {
704 c->modulation = QPSK;
707 c->modulation = QAM_16;
710 c->modulation = QAM_64;
714 switch ((buf[2] >> 2) & 1) {
716 c->transmission_mode = TRANSMISSION_MODE_2K;
719 c->transmission_mode = TRANSMISSION_MODE_8K;
722 switch ((buf[2] >> 0) & 3) {
724 c->guard_interval = GUARD_INTERVAL_1_32;
727 c->guard_interval = GUARD_INTERVAL_1_16;
730 c->guard_interval = GUARD_INTERVAL_1_8;
733 c->guard_interval = GUARD_INTERVAL_1_4;
737 switch ((buf[0] >> 4) & 7) {
739 c->hierarchy = HIERARCHY_NONE;
742 c->hierarchy = HIERARCHY_1;
745 c->hierarchy = HIERARCHY_2;
748 c->hierarchy = HIERARCHY_4;
752 switch ((buf[1] >> 3) & 7) {
754 c->code_rate_HP = FEC_1_2;
757 c->code_rate_HP = FEC_2_3;
760 c->code_rate_HP = FEC_3_4;
763 c->code_rate_HP = FEC_5_6;
766 c->code_rate_HP = FEC_7_8;
770 switch ((buf[1] >> 0) & 7) {
772 c->code_rate_LP = FEC_1_2;
775 c->code_rate_LP = FEC_2_3;
778 c->code_rate_LP = FEC_3_4;
781 c->code_rate_LP = FEC_5_6;
784 c->code_rate_LP = FEC_7_8;
790 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
794 static int rtl2832_read_status(struct dvb_frontend *fe, fe_status_t *status)
796 struct rtl2832_priv *priv = fe->demodulator_priv;
801 dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
805 ret = rtl2832_rd_demod_reg(priv, DVBT_FSM_STAGE, &tmp);
810 *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
811 FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
813 /* TODO find out if this is also true for rtl2832? */
814 /*else if (tmp == 10) {
815 *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
821 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
825 static int rtl2832_read_snr(struct dvb_frontend *fe, u16 *snr)
827 struct rtl2832_priv *priv = fe->demodulator_priv;
828 int ret, hierarchy, constellation;
831 #define CONSTELLATION_NUM 3
832 #define HIERARCHY_NUM 4
833 static const u32 snr_constant[CONSTELLATION_NUM][HIERARCHY_NUM] = {
834 { 85387325, 85387325, 85387325, 85387325 },
835 { 86676178, 86676178, 87167949, 87795660 },
836 { 87659938, 87659938, 87885178, 88241743 },
839 /* reports SNR in resolution of 0.1 dB */
841 ret = rtl2832_rd_reg(priv, 0x3c, 3, &tmp);
845 constellation = (tmp >> 2) & 0x03; /* [3:2] */
846 if (constellation > CONSTELLATION_NUM - 1)
849 hierarchy = (tmp >> 4) & 0x07; /* [6:4] */
850 if (hierarchy > HIERARCHY_NUM - 1)
853 ret = rtl2832_rd_regs(priv, 0x0c, 4, buf, 2);
857 tmp16 = buf[0] << 8 | buf[1];
860 *snr = (snr_constant[constellation][hierarchy] -
861 intlog10(tmp16)) / ((1 << 24) / 100);
867 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
871 static int rtl2832_read_ber(struct dvb_frontend *fe, u32 *ber)
873 struct rtl2832_priv *priv = fe->demodulator_priv;
877 ret = rtl2832_rd_regs(priv, 0x4e, 3, buf, 2);
881 *ber = buf[0] << 8 | buf[1];
885 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
889 static struct dvb_frontend_ops rtl2832_ops;
891 static void rtl2832_release(struct dvb_frontend *fe)
893 struct rtl2832_priv *priv = fe->demodulator_priv;
895 dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
896 cancel_delayed_work_sync(&priv->i2c_gate_work);
897 i2c_del_mux_adapter(priv->i2c_adapter_tuner);
898 i2c_del_mux_adapter(priv->i2c_adapter);
903 * Delay mechanism to avoid unneeded I2C gate open / close. Gate close is
904 * delayed here a little bit in order to see if there is sequence of I2C
905 * messages sent to same I2C bus.
906 * We must use unlocked version of __i2c_transfer() in order to avoid deadlock
907 * as lock is already taken by calling muxed i2c_transfer().
909 static void rtl2832_i2c_gate_work(struct work_struct *work)
911 struct rtl2832_priv *priv = container_of(work,
912 struct rtl2832_priv, i2c_gate_work.work);
913 struct i2c_adapter *adap = priv->i2c;
916 struct i2c_msg msg[1] = {
918 .addr = priv->cfg.i2c_addr,
925 /* select reg bank 1 */
928 ret = __i2c_transfer(adap, msg, 1);
934 /* close I2C repeater gate */
937 ret = __i2c_transfer(adap, msg, 1);
941 priv->i2c_gate_state = false;
945 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
950 static int rtl2832_select(struct i2c_adapter *adap, void *mux_priv, u32 chan_id)
952 struct rtl2832_priv *priv = mux_priv;
955 struct i2c_msg msg[1] = {
957 .addr = priv->cfg.i2c_addr,
963 struct i2c_msg msg_rd[2] = {
965 .addr = priv->cfg.i2c_addr,
970 .addr = priv->cfg.i2c_addr,
977 /* terminate possible gate closing */
978 cancel_delayed_work_sync(&priv->i2c_gate_work);
980 if (priv->i2c_gate_state == chan_id)
983 /* select reg bank 1 */
986 ret = __i2c_transfer(adap, msg, 1);
992 /* we must read that register, otherwise there will be errors */
993 ret = __i2c_transfer(adap, msg_rd, 2);
997 /* open or close I2C repeater gate */
1000 buf[1] = 0x18; /* open */
1002 buf[1] = 0x10; /* close */
1004 ret = __i2c_transfer(adap, msg, 1);
1008 priv->i2c_gate_state = chan_id;
1012 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
1017 static int rtl2832_deselect(struct i2c_adapter *adap, void *mux_priv,
1020 struct rtl2832_priv *priv = mux_priv;
1021 schedule_delayed_work(&priv->i2c_gate_work, usecs_to_jiffies(100));
1025 int rtl2832_enable_external_ts_if(struct dvb_frontend *fe)
1027 struct rtl2832_priv *priv = fe->demodulator_priv;
1030 dev_dbg(&priv->i2c->dev, "%s: setting PIP mode\n", __func__);
1032 ret = rtl2832_wr_regs(priv, 0x0c, 1, "\x5f\xff", 2);
1036 ret = rtl2832_wr_demod_reg(priv, DVBT_PIP_ON, 0x1);
1040 ret = rtl2832_wr_reg(priv, 0xbc, 0, 0x18);
1044 ret = rtl2832_wr_reg(priv, 0x22, 0, 0x01);
1048 ret = rtl2832_wr_reg(priv, 0x26, 0, 0x1f);
1052 ret = rtl2832_wr_reg(priv, 0x27, 0, 0xff);
1056 ret = rtl2832_wr_regs(priv, 0x92, 1, "\x7f\xf7\xff", 3);
1061 ret = rtl2832_wr_demod_reg(priv, DVBT_SOFT_RST, 0x1);
1065 ret = rtl2832_wr_demod_reg(priv, DVBT_SOFT_RST, 0x0);
1071 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
1075 EXPORT_SYMBOL(rtl2832_enable_external_ts_if);
1077 struct i2c_adapter *rtl2832_get_i2c_adapter(struct dvb_frontend *fe)
1079 struct rtl2832_priv *priv = fe->demodulator_priv;
1080 return priv->i2c_adapter_tuner;
1082 EXPORT_SYMBOL(rtl2832_get_i2c_adapter);
1084 struct i2c_adapter *rtl2832_get_private_i2c_adapter(struct dvb_frontend *fe)
1086 struct rtl2832_priv *priv = fe->demodulator_priv;
1087 return priv->i2c_adapter;
1089 EXPORT_SYMBOL(rtl2832_get_private_i2c_adapter);
1091 struct dvb_frontend *rtl2832_attach(const struct rtl2832_config *cfg,
1092 struct i2c_adapter *i2c)
1094 struct rtl2832_priv *priv = NULL;
1098 dev_dbg(&i2c->dev, "%s:\n", __func__);
1100 /* allocate memory for the internal state */
1101 priv = kzalloc(sizeof(struct rtl2832_priv), GFP_KERNEL);
1105 /* setup the priv */
1107 priv->tuner = cfg->tuner;
1108 memcpy(&priv->cfg, cfg, sizeof(struct rtl2832_config));
1109 INIT_DELAYED_WORK(&priv->i2c_gate_work, rtl2832_i2c_gate_work);
1111 /* create muxed i2c adapter for demod itself */
1112 priv->i2c_adapter = i2c_add_mux_adapter(i2c, &i2c->dev, priv, 0, 0, 0,
1113 rtl2832_select, NULL);
1114 if (priv->i2c_adapter == NULL)
1117 /* check if the demod is there */
1118 ret = rtl2832_rd_reg(priv, 0x00, 0x0, &tmp);
1122 /* create muxed i2c adapter for demod tuner bus */
1123 priv->i2c_adapter_tuner = i2c_add_mux_adapter(i2c, &i2c->dev, priv,
1124 0, 1, 0, rtl2832_select, rtl2832_deselect);
1125 if (priv->i2c_adapter_tuner == NULL)
1128 /* create dvb_frontend */
1129 memcpy(&priv->fe.ops, &rtl2832_ops, sizeof(struct dvb_frontend_ops));
1130 priv->fe.demodulator_priv = priv;
1132 /* TODO implement sleep mode */
1133 priv->sleeping = true;
1137 dev_dbg(&i2c->dev, "%s: failed=%d\n", __func__, ret);
1138 if (priv && priv->i2c_adapter)
1139 i2c_del_mux_adapter(priv->i2c_adapter);
1143 EXPORT_SYMBOL(rtl2832_attach);
1145 static struct dvb_frontend_ops rtl2832_ops = {
1146 .delsys = { SYS_DVBT },
1148 .name = "Realtek RTL2832 (DVB-T)",
1149 .frequency_min = 174000000,
1150 .frequency_max = 862000000,
1151 .frequency_stepsize = 166667,
1152 .caps = FE_CAN_FEC_1_2 |
1162 FE_CAN_TRANSMISSION_MODE_AUTO |
1163 FE_CAN_GUARD_INTERVAL_AUTO |
1164 FE_CAN_HIERARCHY_AUTO |
1169 .release = rtl2832_release,
1171 .init = rtl2832_init,
1172 .sleep = rtl2832_sleep,
1174 .get_tune_settings = rtl2832_get_tune_settings,
1176 .set_frontend = rtl2832_set_frontend,
1177 .get_frontend = rtl2832_get_frontend,
1179 .read_status = rtl2832_read_status,
1180 .read_snr = rtl2832_read_snr,
1181 .read_ber = rtl2832_read_ber,
1183 .i2c_gate_ctrl = rtl2832_i2c_gate_ctrl,
1186 MODULE_AUTHOR("Thomas Mair <mair.thomas86@gmail.com>");
1187 MODULE_DESCRIPTION("Realtek RTL2832 DVB-T demodulator driver");
1188 MODULE_LICENSE("GPL");
1189 MODULE_VERSION("0.5");