2 * Realtek RTL2832 DVB-T demodulator driver
4 * Copyright (C) 2012 Thomas Mair <thomas.mair86@gmail.com>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
21 #ifndef RTL2832_PRIV_H
22 #define RTL2832_PRIV_H
24 #include "dvb_frontend.h"
26 #include <linux/i2c-mux.h>
27 #include <linux/regmap.h>
28 #include <linux/math64.h>
31 struct rtl2832_platform_data *pdata;
32 struct i2c_client *client;
33 struct regmap *regmap;
34 struct i2c_adapter *i2c_adapter;
35 struct i2c_adapter *i2c_adapter_tuner;
36 struct dvb_frontend fe;
37 struct delayed_work stat_work;
38 fe_status_t fe_status;
39 u64 post_bit_error_prev; /* for old DVBv3 read_ber() calculation */
43 struct delayed_work i2c_gate_work;
44 unsigned long filters; /* PID filter */
47 struct rtl2832_reg_entry {
53 struct rtl2832_reg_value {
59 /* Demod register bit names */
60 enum DVBT_REG_BIT_NAME {
64 DVBT_RSD_BER_FAIL_VAL,
125 DVBT_CFREQ_OFF_RATIO,
160 DVBT_AGC_TARG_VAL_8_1,
191 DVBT_MPEG_IO_OPT_2_2,
192 DVBT_MPEG_IO_OPT_1_0,
249 DVBT_REG_BIT_NAME_ITEM_TERMINATOR,
252 static const struct rtl2832_reg_value rtl2832_tuner_init_tua9001[] = {
253 {DVBT_DAGC_TRG_VAL, 0x39},
254 {DVBT_AGC_TARG_VAL_0, 0x0},
255 {DVBT_AGC_TARG_VAL_8_1, 0x5a},
256 {DVBT_AAGC_LOOP_GAIN, 0x16},
257 {DVBT_LOOP_GAIN2_3_0, 0x6},
258 {DVBT_LOOP_GAIN2_4, 0x1},
259 {DVBT_LOOP_GAIN3, 0x16},
267 {DVBT_IF_AGC_MIN, 0x80},
268 {DVBT_IF_AGC_MAX, 0x7f},
269 {DVBT_RF_AGC_MIN, 0x9c},
270 {DVBT_RF_AGC_MAX, 0x7f},
271 {DVBT_POLAR_RF_AGC, 0x0},
272 {DVBT_POLAR_IF_AGC, 0x0},
273 {DVBT_AD7_SETTING, 0xe9f4},
274 {DVBT_OPT_ADC_IQ, 0x1},
277 {DVBT_SPEC_INV, 0x0},
280 static const struct rtl2832_reg_value rtl2832_tuner_init_fc0012[] = {
281 {DVBT_DAGC_TRG_VAL, 0x5a},
282 {DVBT_AGC_TARG_VAL_0, 0x0},
283 {DVBT_AGC_TARG_VAL_8_1, 0x5a},
284 {DVBT_AAGC_LOOP_GAIN, 0x16},
285 {DVBT_LOOP_GAIN2_3_0, 0x6},
286 {DVBT_LOOP_GAIN2_4, 0x1},
287 {DVBT_LOOP_GAIN3, 0x16},
295 {DVBT_IF_AGC_MIN, 0x80},
296 {DVBT_IF_AGC_MAX, 0x7f},
297 {DVBT_RF_AGC_MIN, 0x80},
298 {DVBT_RF_AGC_MAX, 0x7f},
299 {DVBT_POLAR_RF_AGC, 0x0},
300 {DVBT_POLAR_IF_AGC, 0x0},
301 {DVBT_AD7_SETTING, 0xe9bf},
302 {DVBT_EN_GI_PGA, 0x0},
303 {DVBT_THD_LOCK_UP, 0x0},
304 {DVBT_THD_LOCK_DW, 0x0},
305 {DVBT_THD_UP1, 0x11},
306 {DVBT_THD_DW1, 0xef},
307 {DVBT_INTER_CNT_LEN, 0xc},
308 {DVBT_GI_PGA_STATE, 0x0},
309 {DVBT_EN_AGC_PGA, 0x1},
310 {DVBT_IF_AGC_MAN, 0x0},
311 {DVBT_SPEC_INV, 0x0},
314 static const struct rtl2832_reg_value rtl2832_tuner_init_e4000[] = {
315 {DVBT_DAGC_TRG_VAL, 0x5a},
316 {DVBT_AGC_TARG_VAL_0, 0x0},
317 {DVBT_AGC_TARG_VAL_8_1, 0x5a},
318 {DVBT_AAGC_LOOP_GAIN, 0x18},
319 {DVBT_LOOP_GAIN2_3_0, 0x8},
320 {DVBT_LOOP_GAIN2_4, 0x1},
321 {DVBT_LOOP_GAIN3, 0x18},
329 {DVBT_IF_AGC_MIN, 0x80},
330 {DVBT_IF_AGC_MAX, 0x7f},
331 {DVBT_RF_AGC_MIN, 0x80},
332 {DVBT_RF_AGC_MAX, 0x7f},
333 {DVBT_POLAR_RF_AGC, 0x0},
334 {DVBT_POLAR_IF_AGC, 0x0},
335 {DVBT_AD7_SETTING, 0xe9d4},
336 {DVBT_EN_GI_PGA, 0x0},
337 {DVBT_THD_LOCK_UP, 0x0},
338 {DVBT_THD_LOCK_DW, 0x0},
339 {DVBT_THD_UP1, 0x14},
340 {DVBT_THD_DW1, 0xec},
341 {DVBT_INTER_CNT_LEN, 0xc},
342 {DVBT_GI_PGA_STATE, 0x0},
343 {DVBT_EN_AGC_PGA, 0x1},
346 {DVBT_REG_MONSEL, 0x1},
348 {DVBT_REG_4MSEL, 0x0},
349 {DVBT_SPEC_INV, 0x0},
352 static const struct rtl2832_reg_value rtl2832_tuner_init_r820t[] = {
353 {DVBT_DAGC_TRG_VAL, 0x39},
354 {DVBT_AGC_TARG_VAL_0, 0x0},
355 {DVBT_AGC_TARG_VAL_8_1, 0x40},
356 {DVBT_AAGC_LOOP_GAIN, 0x16},
357 {DVBT_LOOP_GAIN2_3_0, 0x8},
358 {DVBT_LOOP_GAIN2_4, 0x1},
359 {DVBT_LOOP_GAIN3, 0x18},
367 {DVBT_IF_AGC_MIN, 0x80},
368 {DVBT_IF_AGC_MAX, 0x7f},
369 {DVBT_RF_AGC_MIN, 0x80},
370 {DVBT_RF_AGC_MAX, 0x7f},
371 {DVBT_POLAR_RF_AGC, 0x0},
372 {DVBT_POLAR_IF_AGC, 0x0},
373 {DVBT_AD7_SETTING, 0xe9f4},
374 {DVBT_SPEC_INV, 0x1},
377 #endif /* RTL2832_PRIV_H */