2 Montage Technology TS2020 - Silicon Tuner driver
3 Copyright (C) 2009-2012 Konstantin Dimitrov <kosio.dimitrov@gmail.com>
5 Copyright (C) 2009-2012 TurboSight.com
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 #include "dvb_frontend.h"
25 #define TS2020_XTAL_FREQ 27000 /* in kHz */
26 #define FREQ_OFFSET_LOW_SYM_RATE 3000
29 struct dvb_frontend *fe;
32 struct i2c_adapter *i2c;
35 u32 frequency_div; /* LO output divider switch frequency */
36 u32 frequency_khz; /* actual used LO frequency */
37 #define TS2020_M88TS2020 0
38 #define TS2020_M88TS2022 1
43 struct ts2020_reg_val {
48 static int ts2020_release(struct dvb_frontend *fe)
50 kfree(fe->tuner_priv);
51 fe->tuner_priv = NULL;
55 static int ts2020_writereg(struct dvb_frontend *fe, int reg, int data)
57 struct ts2020_priv *priv = fe->tuner_priv;
58 u8 buf[] = { reg, data };
59 struct i2c_msg msg[] = {
61 .addr = priv->i2c_address,
69 if (fe->ops.i2c_gate_ctrl)
70 fe->ops.i2c_gate_ctrl(fe, 1);
72 err = i2c_transfer(priv->i2c, msg, 1);
75 "%s: writereg error(err == %i, reg == 0x%02x, value == 0x%02x)\n",
76 __func__, err, reg, data);
80 if (fe->ops.i2c_gate_ctrl)
81 fe->ops.i2c_gate_ctrl(fe, 0);
86 static int ts2020_readreg(struct dvb_frontend *fe, u8 reg)
88 struct ts2020_priv *priv = fe->tuner_priv;
92 struct i2c_msg msg[] = {
94 .addr = priv->i2c_address,
99 .addr = priv->i2c_address,
106 if (fe->ops.i2c_gate_ctrl)
107 fe->ops.i2c_gate_ctrl(fe, 1);
109 ret = i2c_transfer(priv->i2c, msg, 2);
112 printk(KERN_ERR "%s: reg=0x%x(error=%d)\n",
117 if (fe->ops.i2c_gate_ctrl)
118 fe->ops.i2c_gate_ctrl(fe, 0);
123 static int ts2020_sleep(struct dvb_frontend *fe)
125 struct ts2020_priv *priv = fe->tuner_priv;
128 if (priv->tuner == TS2020_M88TS2020)
129 u8tmp = 0x0a; /* XXX: probably wrong */
133 return ts2020_writereg(fe, u8tmp, 0x00);
136 static int ts2020_init(struct dvb_frontend *fe)
138 struct ts2020_priv *priv = fe->tuner_priv;
142 if (priv->tuner == TS2020_M88TS2020) {
143 ts2020_writereg(fe, 0x42, 0x73);
144 ts2020_writereg(fe, 0x05, priv->clk_out_div);
145 ts2020_writereg(fe, 0x20, 0x27);
146 ts2020_writereg(fe, 0x07, 0x02);
147 ts2020_writereg(fe, 0x11, 0xff);
148 ts2020_writereg(fe, 0x60, 0xf9);
149 ts2020_writereg(fe, 0x08, 0x01);
150 ts2020_writereg(fe, 0x00, 0x41);
152 static const struct ts2020_reg_val reg_vals[] = {
166 ts2020_writereg(fe, 0x00, 0x01);
167 ts2020_writereg(fe, 0x00, 0x03);
169 switch (priv->clk_out) {
170 case TS2020_CLK_OUT_DISABLED:
173 case TS2020_CLK_OUT_ENABLED:
175 ts2020_writereg(fe, 0x05, priv->clk_out_div);
177 case TS2020_CLK_OUT_ENABLED_XTALOUT:
185 ts2020_writereg(fe, 0x42, u8tmp);
187 if (priv->loop_through)
192 ts2020_writereg(fe, 0x62, u8tmp);
194 for (i = 0; i < ARRAY_SIZE(reg_vals); i++)
195 ts2020_writereg(fe, reg_vals[i].reg, reg_vals[i].val);
201 static int ts2020_tuner_gate_ctrl(struct dvb_frontend *fe, u8 offset)
204 ret = ts2020_writereg(fe, 0x51, 0x1f - offset);
205 ret |= ts2020_writereg(fe, 0x51, 0x1f);
206 ret |= ts2020_writereg(fe, 0x50, offset);
207 ret |= ts2020_writereg(fe, 0x50, 0x00);
212 static int ts2020_set_tuner_rf(struct dvb_frontend *fe)
216 reg = ts2020_readreg(fe, 0x3d);
220 else if (reg == 0x16)
225 ts2020_writereg(fe, 0x60, reg);
226 reg = ts2020_tuner_gate_ctrl(fe, 0x08);
231 static int ts2020_set_params(struct dvb_frontend *fe)
233 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
234 struct ts2020_priv *priv = fe->tuner_priv;
236 u32 symbol_rate = (c->symbol_rate / 1000);
238 u16 u16tmp, value, lpf_coeff;
239 u8 buf[3], reg10, lpf_mxdiv, mlpf_max, mlpf_min, nlpf;
240 unsigned int f_ref_khz, f_vco_khz, div_ref, div_out, pll_n;
241 unsigned int frequency_khz = c->frequency;
244 * Integer-N PLL synthesizer
245 * kHz is used for all calculations to keep calculations within 32-bit
247 f_ref_khz = TS2020_XTAL_FREQ;
248 div_ref = DIV_ROUND_CLOSEST(f_ref_khz, 2000);
250 /* select LO output divider */
251 if (frequency_khz < priv->frequency_div) {
259 f_vco_khz = frequency_khz * div_out;
260 pll_n = f_vco_khz * div_ref / f_ref_khz;
262 priv->frequency_khz = pll_n * f_ref_khz / div_ref / div_out;
264 pr_debug("frequency=%u offset=%d f_vco_khz=%u pll_n=%u div_ref=%u div_out=%u\n",
265 priv->frequency_khz, priv->frequency_khz - c->frequency,
266 f_vco_khz, pll_n, div_ref, div_out);
268 if (priv->tuner == TS2020_M88TS2020) {
271 ret = ts2020_writereg(fe, 0x10, reg10);
275 ret = ts2020_writereg(fe, 0x10, reg10);
276 ret |= ts2020_writereg(fe, 0x11, 0x40);
279 u16tmp = pll_n - 1024;
280 buf[0] = (u16tmp >> 8) & 0xff;
281 buf[1] = (u16tmp >> 0) & 0xff;
282 buf[2] = div_ref - 8;
284 ret |= ts2020_writereg(fe, 0x01, buf[0]);
285 ret |= ts2020_writereg(fe, 0x02, buf[1]);
286 ret |= ts2020_writereg(fe, 0x03, buf[2]);
288 ret |= ts2020_tuner_gate_ctrl(fe, 0x10);
292 ret |= ts2020_tuner_gate_ctrl(fe, 0x08);
295 if (priv->tuner == TS2020_M88TS2020)
296 ret |= ts2020_set_tuner_rf(fe);
298 gdiv28 = (TS2020_XTAL_FREQ / 1000 * 1694 + 500) / 1000;
299 ret |= ts2020_writereg(fe, 0x04, gdiv28 & 0xff);
300 ret |= ts2020_tuner_gate_ctrl(fe, 0x04);
304 if (priv->tuner == TS2020_M88TS2022) {
305 ret = ts2020_writereg(fe, 0x25, 0x00);
306 ret |= ts2020_writereg(fe, 0x27, 0x70);
307 ret |= ts2020_writereg(fe, 0x41, 0x09);
308 ret |= ts2020_writereg(fe, 0x08, 0x0b);
313 value = ts2020_readreg(fe, 0x26);
315 f3db = (symbol_rate * 135) / 200 + 2000;
316 f3db += FREQ_OFFSET_LOW_SYM_RATE;
322 gdiv28 = gdiv28 * 207 / (value * 2 + 151);
323 mlpf_max = gdiv28 * 135 / 100;
324 mlpf_min = gdiv28 * 78 / 100;
328 nlpf = (f3db * gdiv28 * 2 / lpf_coeff /
329 (TS2020_XTAL_FREQ / 1000) + 1) / 2;
335 lpf_mxdiv = (nlpf * (TS2020_XTAL_FREQ / 1000)
336 * lpf_coeff * 2 / f3db + 1) / 2;
338 if (lpf_mxdiv < mlpf_min) {
340 lpf_mxdiv = (nlpf * (TS2020_XTAL_FREQ / 1000)
341 * lpf_coeff * 2 / f3db + 1) / 2;
344 if (lpf_mxdiv > mlpf_max)
345 lpf_mxdiv = mlpf_max;
347 ret = ts2020_writereg(fe, 0x04, lpf_mxdiv);
348 ret |= ts2020_writereg(fe, 0x06, nlpf);
350 ret |= ts2020_tuner_gate_ctrl(fe, 0x04);
352 ret |= ts2020_tuner_gate_ctrl(fe, 0x01);
356 return (ret < 0) ? -EINVAL : 0;
359 static int ts2020_get_frequency(struct dvb_frontend *fe, u32 *frequency)
361 struct ts2020_priv *priv = fe->tuner_priv;
363 *frequency = priv->frequency_khz;
367 static int ts2020_get_if_frequency(struct dvb_frontend *fe, u32 *frequency)
369 *frequency = 0; /* Zero-IF */
373 /* read TS2020 signal strength */
374 static int ts2020_read_signal_strength(struct dvb_frontend *fe,
375 u16 *signal_strength)
377 u16 sig_reading, sig_strength;
380 rfgain = ts2020_readreg(fe, 0x3d) & 0x1f;
381 bbgain = ts2020_readreg(fe, 0x21) & 0x1f;
388 sig_reading = rfgain * 2 + bbgain * 3;
390 sig_strength = 40 + (64 - sig_reading) * 50 / 64 ;
392 /* cook the value to be suitable for szap-s2 human readable output */
393 *signal_strength = sig_strength * 1000;
398 static struct dvb_tuner_ops ts2020_tuner_ops = {
401 .frequency_min = 950000,
402 .frequency_max = 2150000
405 .release = ts2020_release,
406 .sleep = ts2020_sleep,
407 .set_params = ts2020_set_params,
408 .get_frequency = ts2020_get_frequency,
409 .get_if_frequency = ts2020_get_if_frequency,
410 .get_rf_strength = ts2020_read_signal_strength,
413 struct dvb_frontend *ts2020_attach(struct dvb_frontend *fe,
414 const struct ts2020_config *config,
415 struct i2c_adapter *i2c)
417 struct ts2020_priv *priv = NULL;
420 priv = kzalloc(sizeof(struct ts2020_priv), GFP_KERNEL);
424 priv->i2c_address = config->tuner_address;
426 priv->clk_out = config->clk_out;
427 priv->clk_out_div = config->clk_out_div;
428 priv->frequency_div = config->frequency_div;
430 fe->tuner_priv = priv;
432 if (!priv->frequency_div)
433 priv->frequency_div = 1060000;
435 /* Wake Up the tuner */
436 if ((0x03 & ts2020_readreg(fe, 0x00)) == 0x00) {
437 ts2020_writereg(fe, 0x00, 0x01);
441 ts2020_writereg(fe, 0x00, 0x03);
444 /* Check the tuner version */
445 buf = ts2020_readreg(fe, 0x00);
446 if ((buf == 0x01) || (buf == 0x41) || (buf == 0x81)) {
447 printk(KERN_INFO "%s: Find tuner TS2020!\n", __func__);
448 priv->tuner = TS2020_M88TS2020;
449 } else if ((buf == 0x83) || (buf == 0xc3)) {
450 printk(KERN_INFO "%s: Find tuner TS2022!\n", __func__);
451 priv->tuner = TS2020_M88TS2022;
453 printk(KERN_ERR "%s: Read tuner reg[0] = %d\n", __func__, buf);
458 memcpy(&fe->ops.tuner_ops, &ts2020_tuner_ops,
459 sizeof(struct dvb_tuner_ops));
463 EXPORT_SYMBOL(ts2020_attach);
465 static int ts2020_probe(struct i2c_client *client,
466 const struct i2c_device_id *id)
468 struct ts2020_config *pdata = client->dev.platform_data;
469 struct dvb_frontend *fe = pdata->fe;
470 struct ts2020_priv *dev;
476 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
482 dev->i2c = client->adapter;
483 dev->i2c_address = client->addr;
484 dev->clk_out = pdata->clk_out;
485 dev->clk_out_div = pdata->clk_out_div;
486 dev->frequency_div = pdata->frequency_div;
488 fe->tuner_priv = dev;
490 /* check if the tuner is there */
491 ret = ts2020_readreg(fe, 0x00);
496 if ((utmp & 0x03) == 0x00) {
497 ret = ts2020_writereg(fe, 0x00, 0x01);
501 usleep_range(2000, 50000);
504 ret = ts2020_writereg(fe, 0x00, 0x03);
508 usleep_range(2000, 50000);
510 ret = ts2020_readreg(fe, 0x00);
515 dev_dbg(&client->dev, "chip_id=%02x\n", utmp);
521 dev->tuner = TS2020_M88TS2020;
523 if (!dev->frequency_div)
524 dev->frequency_div = 1060000;
528 dev->tuner = TS2020_M88TS2022;
530 if (!dev->frequency_div)
531 dev->frequency_div = 1103000;
538 if (dev->tuner == TS2020_M88TS2022) {
539 switch (dev->clk_out) {
540 case TS2020_CLK_OUT_DISABLED:
543 case TS2020_CLK_OUT_ENABLED:
545 ret = ts2020_writereg(fe, 0x05, dev->clk_out_div);
549 case TS2020_CLK_OUT_ENABLED_XTALOUT:
557 ret = ts2020_writereg(fe, 0x42, u8tmp);
561 if (dev->loop_through)
566 ret = ts2020_writereg(fe, 0x62, u8tmp);
572 ret = ts2020_writereg(fe, 0x00, 0x00);
576 dev_info(&client->dev,
577 "Montage Technology %s successfully identified\n", chip_str);
579 memcpy(&fe->ops.tuner_ops, &ts2020_tuner_ops,
580 sizeof(struct dvb_tuner_ops));
581 fe->ops.tuner_ops.release = NULL;
583 i2c_set_clientdata(client, dev);
586 dev_dbg(&client->dev, "failed=%d\n", ret);
591 static int ts2020_remove(struct i2c_client *client)
593 struct ts2020_priv *dev = i2c_get_clientdata(client);
594 struct dvb_frontend *fe = dev->fe;
596 dev_dbg(&client->dev, "\n");
598 memset(&fe->ops.tuner_ops, 0, sizeof(struct dvb_tuner_ops));
599 fe->tuner_priv = NULL;
605 static const struct i2c_device_id ts2020_id_table[] = {
610 MODULE_DEVICE_TABLE(i2c, ts2020_id_table);
612 static struct i2c_driver ts2020_driver = {
614 .owner = THIS_MODULE,
617 .probe = ts2020_probe,
618 .remove = ts2020_remove,
619 .id_table = ts2020_id_table,
622 module_i2c_driver(ts2020_driver);
624 MODULE_AUTHOR("Konstantin Dimitrov <kosio.dimitrov@gmail.com>");
625 MODULE_DESCRIPTION("Montage Technology TS2020 - Silicon tuner driver module");
626 MODULE_LICENSE("GPL");