drivers/media/i2c/adv7604.c

   1 /*
   2  * adv7604 - Analog Devices ADV7604 video decoder driver
   3  *
   4  * Copyright 2012 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
   5  *
   6  * This program is free software; you may redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  11  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  12  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  13  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  14  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  15  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  16  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  17  * SOFTWARE.
  18  *
  19  */
  20
  21 /*
  22  * References (c = chapter, p = page):
  23  * REF_01 - Analog devices, ADV7604, Register Settings Recommendations,
  24  *              Revision 2.5, June 2010
  25  * REF_02 - Analog devices, Register map documentation, Documentation of
  26  *              the register maps, Software manual, Rev. F, June 2010
  27  * REF_03 - Analog devices, ADV7604, Hardware Manual, Rev. F, August 2010
  28  */
  29
  30 #include <linux/delay.h>
  31 #include <linux/gpio/consumer.h>
  32 #include <linux/i2c.h>
  33 #include <linux/kernel.h>
  34 #include <linux/module.h>
  35 #include <linux/slab.h>
  36 #include <linux/v4l2-dv-timings.h>
  37 #include <linux/videodev2.h>
  38 #include <linux/workqueue.h>
  39
  40 #include <media/adv7604.h>
  41 #include <media/v4l2-ctrls.h>
  42 #include <media/v4l2-device.h>
  43 #include <media/v4l2-dv-timings.h>
  44 #include <media/v4l2-of.h>
  45
  46 static int debug;
  47 module_param(debug, int, 0644);
  48 MODULE_PARM_DESC(debug, "debug level (0-2)");
  49
  50 MODULE_DESCRIPTION("Analog Devices ADV7604 video decoder driver");
  51 MODULE_AUTHOR("Hans Verkuil <hans.verkuil@cisco.com>");
  52 MODULE_AUTHOR("Mats Randgaard <mats.randgaard@cisco.com>");
  53 MODULE_LICENSE("GPL");
  54
  55 /* ADV7604 system clock frequency */
  56 #define ADV7604_fsc (28636360)
  57
  58 #define ADV7604_RGB_OUT                                 (1 << 1)
  59
  60 #define ADV7604_OP_FORMAT_SEL_8BIT                      (0 << 0)
  61 #define ADV7604_OP_FORMAT_SEL_10BIT                     (1 << 0)
  62 #define ADV7604_OP_FORMAT_SEL_12BIT                     (2 << 0)
  63
  64 #define ADV7604_OP_MODE_SEL_SDR_422                     (0 << 5)
  65 #define ADV7604_OP_MODE_SEL_DDR_422                     (1 << 5)
  66 #define ADV7604_OP_MODE_SEL_SDR_444                     (2 << 5)
  67 #define ADV7604_OP_MODE_SEL_DDR_444                     (3 << 5)
  68 #define ADV7604_OP_MODE_SEL_SDR_422_2X                  (4 << 5)
  69 #define ADV7604_OP_MODE_SEL_ADI_CM                      (5 << 5)
  70
  71 #define ADV7604_OP_CH_SEL_GBR                           (0 << 5)
  72 #define ADV7604_OP_CH_SEL_GRB                           (1 << 5)
  73 #define ADV7604_OP_CH_SEL_BGR                           (2 << 5)
  74 #define ADV7604_OP_CH_SEL_RGB                           (3 << 5)
  75 #define ADV7604_OP_CH_SEL_BRG                           (4 << 5)
  76 #define ADV7604_OP_CH_SEL_RBG                           (5 << 5)
  77
  78 #define ADV7604_OP_SWAP_CB_CR                           (1 << 0)
  79
  80 enum adv7604_type {
  81         ADV7604,
  82         ADV7611,
  83 };
  84
  85 struct adv7604_reg_seq {
  86         unsigned int reg;
  87         u8 val;
  88 };
  89
  90 struct adv7604_format_info {
  91         u32 code;
  92         u8 op_ch_sel;
  93         bool rgb_out;
  94         bool swap_cb_cr;
  95         u8 op_format_sel;
  96 };
  97
  98 struct adv7604_chip_info {
  99         enum adv7604_type type;
 100
 101         bool has_afe;
 102         unsigned int max_port;
 103         unsigned int num_dv_ports;
 104
 105         unsigned int edid_enable_reg;
 106         unsigned int edid_status_reg;
 107         unsigned int lcf_reg;
 108
 109         unsigned int cable_det_mask;
 110         unsigned int tdms_lock_mask;
 111         unsigned int fmt_change_digital_mask;
 112
 113         const struct adv7604_format_info *formats;
 114         unsigned int nformats;
 115
 116         void (*set_termination)(struct v4l2_subdev *sd, bool enable);
 117         void (*setup_irqs)(struct v4l2_subdev *sd);
 118         unsigned int (*read_hdmi_pixelclock)(struct v4l2_subdev *sd);
 119         unsigned int (*read_cable_det)(struct v4l2_subdev *sd);
 120
 121         /* 0 = AFE, 1 = HDMI */
 122         const struct adv7604_reg_seq *recommended_settings[2];
 123         unsigned int num_recommended_settings[2];
 124
 125         unsigned long page_mask;
 126 };
 127
 128 /*
 129  **********************************************************************
 130  *
 131  *  Arrays with configuration parameters for the ADV7604
 132  *
 133  **********************************************************************
 134  */
 135
 136 struct adv7604_state {
 137         const struct adv7604_chip_info *info;
 138         struct adv7604_platform_data pdata;
 139
 140         struct gpio_desc *hpd_gpio[4];
 141
 142         struct v4l2_subdev sd;
 143         struct media_pad pads[ADV7604_PAD_MAX];
 144         unsigned int source_pad;
 145
 146         struct v4l2_ctrl_handler hdl;
 147
 148         enum adv7604_pad selected_input;
 149
 150         struct v4l2_dv_timings timings;
 151         const struct adv7604_format_info *format;
 152
 153         struct {
 154                 u8 edid[256];
 155                 u32 present;
 156                 unsigned blocks;
 157         } edid;
 158         u16 spa_port_a[2];
 159         struct v4l2_fract aspect_ratio;
 160         u32 rgb_quantization_range;
 161         struct workqueue_struct *work_queues;
 162         struct delayed_work delayed_work_enable_hotplug;
 163         bool restart_stdi_once;
 164
 165         /* i2c clients */
 166         struct i2c_client *i2c_clients[ADV7604_PAGE_MAX];
 167
 168         /* controls */
 169         struct v4l2_ctrl *detect_tx_5v_ctrl;
 170         struct v4l2_ctrl *analog_sampling_phase_ctrl;
 171         struct v4l2_ctrl *free_run_color_manual_ctrl;
 172         struct v4l2_ctrl *free_run_color_ctrl;
 173         struct v4l2_ctrl *rgb_quantization_range_ctrl;
 174 };
 175
 176 static bool adv7604_has_afe(struct adv7604_state *state)
 177 {
 178         return state->info->has_afe;
 179 }
 180
 181 /* Supported CEA and DMT timings */
 182 static const struct v4l2_dv_timings adv7604_timings[] = {
 183         V4L2_DV_BT_CEA_720X480P59_94,
 184         V4L2_DV_BT_CEA_720X576P50,
 185         V4L2_DV_BT_CEA_1280X720P24,
 186         V4L2_DV_BT_CEA_1280X720P25,
 187         V4L2_DV_BT_CEA_1280X720P50,
 188         V4L2_DV_BT_CEA_1280X720P60,
 189         V4L2_DV_BT_CEA_1920X1080P24,
 190         V4L2_DV_BT_CEA_1920X1080P25,
 191         V4L2_DV_BT_CEA_1920X1080P30,
 192         V4L2_DV_BT_CEA_1920X1080P50,
 193         V4L2_DV_BT_CEA_1920X1080P60,
 194
 195         /* sorted by DMT ID */
 196         V4L2_DV_BT_DMT_640X350P85,
 197         V4L2_DV_BT_DMT_640X400P85,
 198         V4L2_DV_BT_DMT_720X400P85,
 199         V4L2_DV_BT_DMT_640X480P60,
 200         V4L2_DV_BT_DMT_640X480P72,
 201         V4L2_DV_BT_DMT_640X480P75,
 202         V4L2_DV_BT_DMT_640X480P85,
 203         V4L2_DV_BT_DMT_800X600P56,
 204         V4L2_DV_BT_DMT_800X600P60,
 205         V4L2_DV_BT_DMT_800X600P72,
 206         V4L2_DV_BT_DMT_800X600P75,
 207         V4L2_DV_BT_DMT_800X600P85,
 208         V4L2_DV_BT_DMT_848X480P60,
 209         V4L2_DV_BT_DMT_1024X768P60,
 210         V4L2_DV_BT_DMT_1024X768P70,
 211         V4L2_DV_BT_DMT_1024X768P75,
 212         V4L2_DV_BT_DMT_1024X768P85,
 213         V4L2_DV_BT_DMT_1152X864P75,
 214         V4L2_DV_BT_DMT_1280X768P60_RB,
 215         V4L2_DV_BT_DMT_1280X768P60,
 216         V4L2_DV_BT_DMT_1280X768P75,
 217         V4L2_DV_BT_DMT_1280X768P85,
 218         V4L2_DV_BT_DMT_1280X800P60_RB,
 219         V4L2_DV_BT_DMT_1280X800P60,
 220         V4L2_DV_BT_DMT_1280X800P75,
 221         V4L2_DV_BT_DMT_1280X800P85,
 222         V4L2_DV_BT_DMT_1280X960P60,
 223         V4L2_DV_BT_DMT_1280X960P85,
 224         V4L2_DV_BT_DMT_1280X1024P60,
 225         V4L2_DV_BT_DMT_1280X1024P75,
 226         V4L2_DV_BT_DMT_1280X1024P85,
 227         V4L2_DV_BT_DMT_1360X768P60,
 228         V4L2_DV_BT_DMT_1400X1050P60_RB,
 229         V4L2_DV_BT_DMT_1400X1050P60,
 230         V4L2_DV_BT_DMT_1400X1050P75,
 231         V4L2_DV_BT_DMT_1400X1050P85,
 232         V4L2_DV_BT_DMT_1440X900P60_RB,
 233         V4L2_DV_BT_DMT_1440X900P60,
 234         V4L2_DV_BT_DMT_1600X1200P60,
 235         V4L2_DV_BT_DMT_1680X1050P60_RB,
 236         V4L2_DV_BT_DMT_1680X1050P60,
 237         V4L2_DV_BT_DMT_1792X1344P60,
 238         V4L2_DV_BT_DMT_1856X1392P60,
 239         V4L2_DV_BT_DMT_1920X1200P60_RB,
 240         V4L2_DV_BT_DMT_1366X768P60_RB,
 241         V4L2_DV_BT_DMT_1366X768P60,
 242         V4L2_DV_BT_DMT_1920X1080P60,
 243         { },
 244 };
 245
 246 struct adv7604_video_standards {
 247         struct v4l2_dv_timings timings;
 248         u8 vid_std;
 249         u8 v_freq;
 250 };
 251
 252 /* sorted by number of lines */
 253 static const struct adv7604_video_standards adv7604_prim_mode_comp[] = {
 254         /* { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, TODO flickering */
 255         { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
 256         { V4L2_DV_BT_CEA_1280X720P50, 0x19, 0x01 },
 257         { V4L2_DV_BT_CEA_1280X720P60, 0x19, 0x00 },
 258         { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
 259         { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
 260         { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
 261         { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
 262         { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
 263         /* TODO add 1920x1080P60_RB (CVT timing) */
 264         { },
 265 };
 266
 267 /* sorted by number of lines */
 268 static const struct adv7604_video_standards adv7604_prim_mode_gr[] = {
 269         { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
 270         { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
 271         { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
 272         { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
 273         { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
 274         { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
 275         { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
 276         { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
 277         { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
 278         { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
 279         { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
 280         { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
 281         { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
 282         { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
 283         { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
 284         { V4L2_DV_BT_DMT_1360X768P60, 0x12, 0x00 },
 285         { V4L2_DV_BT_DMT_1366X768P60, 0x13, 0x00 },
 286         { V4L2_DV_BT_DMT_1400X1050P60, 0x14, 0x00 },
 287         { V4L2_DV_BT_DMT_1400X1050P75, 0x15, 0x00 },
 288         { V4L2_DV_BT_DMT_1600X1200P60, 0x16, 0x00 }, /* TODO not tested */
 289         /* TODO add 1600X1200P60_RB (not a DMT timing) */
 290         { V4L2_DV_BT_DMT_1680X1050P60, 0x18, 0x00 },
 291         { V4L2_DV_BT_DMT_1920X1200P60_RB, 0x19, 0x00 }, /* TODO not tested */
 292         { },
 293 };
 294
 295 /* sorted by number of lines */
 296 static const struct adv7604_video_standards adv7604_prim_mode_hdmi_comp[] = {
 297         { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 },
 298         { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
 299         { V4L2_DV_BT_CEA_1280X720P50, 0x13, 0x01 },
 300         { V4L2_DV_BT_CEA_1280X720P60, 0x13, 0x00 },
 301         { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
 302         { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
 303         { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
 304         { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
 305         { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
 306         { },
 307 };
 308
 309 /* sorted by number of lines */
 310 static const struct adv7604_video_standards adv7604_prim_mode_hdmi_gr[] = {
 311         { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
 312         { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
 313         { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
 314         { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
 315         { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
 316         { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
 317         { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
 318         { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
 319         { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
 320         { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
 321         { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
 322         { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
 323         { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
 324         { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
 325         { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
 326         { },
 327 };
 328
 329 /* ----------------------------------------------------------------------- */
 330
 331 static inline struct adv7604_state *to_state(struct v4l2_subdev *sd)
 332 {
 333         return container_of(sd, struct adv7604_state, sd);
 334 }
 335
 336 static inline unsigned htotal(const struct v4l2_bt_timings *t)
 337 {
 338         return V4L2_DV_BT_FRAME_WIDTH(t);
 339 }
 340
 341 static inline unsigned vtotal(const struct v4l2_bt_timings *t)
 342 {
 343         return V4L2_DV_BT_FRAME_HEIGHT(t);
 344 }
 345
 346 /* ----------------------------------------------------------------------- */
 347
 348 static s32 adv_smbus_read_byte_data_check(struct i2c_client *client,
 349                 u8 command, bool check)
 350 {
 351         union i2c_smbus_data data;
 352
 353         if (!i2c_smbus_xfer(client->adapter, client->addr, client->flags,
 354                         I2C_SMBUS_READ, command,
 355                         I2C_SMBUS_BYTE_DATA, &data))
 356                 return data.byte;
 357         if (check)
 358                 v4l_err(client, "error reading %02x, %02x\n",
 359                                 client->addr, command);
 360         return -EIO;
 361 }
 362
 363 static s32 adv_smbus_read_byte_data(struct adv7604_state *state,
 364                                     enum adv7604_page page, u8 command)
 365 {
 366         return adv_smbus_read_byte_data_check(state->i2c_clients[page],
 367                                               command, true);
 368 }
 369
 370 static s32 adv_smbus_write_byte_data(struct adv7604_state *state,
 371                                      enum adv7604_page page, u8 command,
 372                                      u8 value)
 373 {
 374         struct i2c_client *client = state->i2c_clients[page];
 375         union i2c_smbus_data data;
 376         int err;
 377         int i;
 378
 379         data.byte = value;
 380         for (i = 0; i < 3; i++) {
 381                 err = i2c_smbus_xfer(client->adapter, client->addr,
 382                                 client->flags,
 383                                 I2C_SMBUS_WRITE, command,
 384                                 I2C_SMBUS_BYTE_DATA, &data);
 385                 if (!err)
 386                         break;
 387         }
 388         if (err < 0)
 389                 v4l_err(client, "error writing %02x, %02x, %02x\n",
 390                                 client->addr, command, value);
 391         return err;
 392 }
 393
 394 static s32 adv_smbus_write_i2c_block_data(struct adv7604_state *state,
 395                                           enum adv7604_page page, u8 command,
 396                                           unsigned length, const u8 *values)
 397 {
 398         struct i2c_client *client = state->i2c_clients[page];
 399         union i2c_smbus_data data;
 400
 401         if (length > I2C_SMBUS_BLOCK_MAX)
 402                 length = I2C_SMBUS_BLOCK_MAX;
 403         data.block[0] = length;
 404         memcpy(data.block + 1, values, length);
 405         return i2c_smbus_xfer(client->adapter, client->addr, client->flags,
 406                               I2C_SMBUS_WRITE, command,
 407                               I2C_SMBUS_I2C_BLOCK_DATA, &data);
 408 }
 409
 410 /* ----------------------------------------------------------------------- */
 411
 412 static inline int io_read(struct v4l2_subdev *sd, u8 reg)
 413 {
 414         struct adv7604_state *state = to_state(sd);
 415
 416         return adv_smbus_read_byte_data(state, ADV7604_PAGE_IO, reg);
 417 }
 418
 419 static inline int io_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 420 {
 421         struct adv7604_state *state = to_state(sd);
 422
 423         return adv_smbus_write_byte_data(state, ADV7604_PAGE_IO, reg, val);
 424 }
 425
 426 static inline int io_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
 427 {
 428         return io_write(sd, reg, (io_read(sd, reg) & ~mask) | val);
 429 }
 430
 431 static inline int avlink_read(struct v4l2_subdev *sd, u8 reg)
 432 {
 433         struct adv7604_state *state = to_state(sd);
 434
 435         return adv_smbus_read_byte_data(state, ADV7604_PAGE_AVLINK, reg);
 436 }
 437
 438 static inline int avlink_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 439 {
 440         struct adv7604_state *state = to_state(sd);
 441
 442         return adv_smbus_write_byte_data(state, ADV7604_PAGE_AVLINK, reg, val);
 443 }
 444
 445 static inline int cec_read(struct v4l2_subdev *sd, u8 reg)
 446 {
 447         struct adv7604_state *state = to_state(sd);
 448
 449         return adv_smbus_read_byte_data(state, ADV7604_PAGE_CEC, reg);
 450 }
 451
 452 static inline int cec_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 453 {
 454         struct adv7604_state *state = to_state(sd);
 455
 456         return adv_smbus_write_byte_data(state, ADV7604_PAGE_CEC, reg, val);
 457 }
 458
 459 static inline int infoframe_read(struct v4l2_subdev *sd, u8 reg)
 460 {
 461         struct adv7604_state *state = to_state(sd);
 462
 463         return adv_smbus_read_byte_data(state, ADV7604_PAGE_INFOFRAME, reg);
 464 }
 465
 466 static inline int infoframe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 467 {
 468         struct adv7604_state *state = to_state(sd);
 469
 470         return adv_smbus_write_byte_data(state, ADV7604_PAGE_INFOFRAME,
 471                                          reg, val);
 472 }
 473
 474 static inline int afe_read(struct v4l2_subdev *sd, u8 reg)
 475 {
 476         struct adv7604_state *state = to_state(sd);
 477
 478         return adv_smbus_read_byte_data(state, ADV7604_PAGE_AFE, reg);
 479 }
 480
 481 static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 482 {
 483         struct adv7604_state *state = to_state(sd);
 484
 485         return adv_smbus_write_byte_data(state, ADV7604_PAGE_AFE, reg, val);
 486 }
 487
 488 static inline int rep_read(struct v4l2_subdev *sd, u8 reg)
 489 {
 490         struct adv7604_state *state = to_state(sd);
 491
 492         return adv_smbus_read_byte_data(state, ADV7604_PAGE_REP, reg);
 493 }
 494
 495 static inline int rep_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 496 {
 497         struct adv7604_state *state = to_state(sd);
 498
 499         return adv_smbus_write_byte_data(state, ADV7604_PAGE_REP, reg, val);
 500 }
 501
 502 static inline int rep_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
 503 {
 504         return rep_write(sd, reg, (rep_read(sd, reg) & ~mask) | val);
 505 }
 506
 507 static inline int edid_read(struct v4l2_subdev *sd, u8 reg)
 508 {
 509         struct adv7604_state *state = to_state(sd);
 510
 511         return adv_smbus_read_byte_data(state, ADV7604_PAGE_EDID, reg);
 512 }
 513
 514 static inline int edid_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 515 {
 516         struct adv7604_state *state = to_state(sd);
 517
 518         return adv_smbus_write_byte_data(state, ADV7604_PAGE_EDID, reg, val);
 519 }
 520
 521 static inline int edid_write_block(struct v4l2_subdev *sd,
 522                                         unsigned len, const u8 *val)
 523 {
 524         struct adv7604_state *state = to_state(sd);
 525         int err = 0;
 526         int i;
 527
 528         v4l2_dbg(2, debug, sd, "%s: write EDID block (%d byte)\n", __func__, len);
 529
 530         for (i = 0; !err && i < len; i += I2C_SMBUS_BLOCK_MAX)
 531                 err = adv_smbus_write_i2c_block_data(state, ADV7604_PAGE_EDID,
 532                                 i, I2C_SMBUS_BLOCK_MAX, val + i);
 533         return err;
 534 }
 535
 536 static void adv7604_set_hpd(struct adv7604_state *state, unsigned int hpd)
 537 {
 538         unsigned int i;
 539
 540         for (i = 0; i < state->info->num_dv_ports; ++i) {
 541                 if (IS_ERR(state->hpd_gpio[i]))
 542                         continue;
 543
 544                 gpiod_set_value_cansleep(state->hpd_gpio[i], hpd & BIT(i));
 545         }
 546
 547         v4l2_subdev_notify(&state->sd, ADV7604_HOTPLUG, &hpd);
 548 }
 549
 550 static void adv7604_delayed_work_enable_hotplug(struct work_struct *work)
 551 {
 552         struct delayed_work *dwork = to_delayed_work(work);
 553         struct adv7604_state *state = container_of(dwork, struct adv7604_state,
 554                                                 delayed_work_enable_hotplug);
 555         struct v4l2_subdev *sd = &state->sd;
 556
 557         v4l2_dbg(2, debug, sd, "%s: enable hotplug\n", __func__);
 558
 559         adv7604_set_hpd(state, state->edid.present);
 560 }
 561
 562 static inline int hdmi_read(struct v4l2_subdev *sd, u8 reg)
 563 {
 564         struct adv7604_state *state = to_state(sd);
 565
 566         return adv_smbus_read_byte_data(state, ADV7604_PAGE_HDMI, reg);
 567 }
 568
 569 static u16 hdmi_read16(struct v4l2_subdev *sd, u8 reg, u16 mask)
 570 {
 571         return ((hdmi_read(sd, reg) << 8) | hdmi_read(sd, reg + 1)) & mask;
 572 }
 573
 574 static inline int hdmi_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 575 {
 576         struct adv7604_state *state = to_state(sd);
 577
 578         return adv_smbus_write_byte_data(state, ADV7604_PAGE_HDMI, reg, val);
 579 }
 580
 581 static inline int hdmi_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
 582 {
 583         return hdmi_write(sd, reg, (hdmi_read(sd, reg) & ~mask) | val);
 584 }
 585
 586 static inline int test_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 587 {
 588         struct adv7604_state *state = to_state(sd);
 589
 590         return adv_smbus_write_byte_data(state, ADV7604_PAGE_TEST, reg, val);
 591 }
 592
 593 static inline int cp_read(struct v4l2_subdev *sd, u8 reg)
 594 {
 595         struct adv7604_state *state = to_state(sd);
 596
 597         return adv_smbus_read_byte_data(state, ADV7604_PAGE_CP, reg);
 598 }
 599
 600 static u16 cp_read16(struct v4l2_subdev *sd, u8 reg, u16 mask)
 601 {
 602         return ((cp_read(sd, reg) << 8) | cp_read(sd, reg + 1)) & mask;
 603 }
 604
 605 static inline int cp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 606 {
 607         struct adv7604_state *state = to_state(sd);
 608
 609         return adv_smbus_write_byte_data(state, ADV7604_PAGE_CP, reg, val);
 610 }
 611
 612 static inline int cp_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
 613 {
 614         return cp_write(sd, reg, (cp_read(sd, reg) & ~mask) | val);
 615 }
 616
 617 static inline int vdp_read(struct v4l2_subdev *sd, u8 reg)
 618 {
 619         struct adv7604_state *state = to_state(sd);
 620
 621         return adv_smbus_read_byte_data(state, ADV7604_PAGE_VDP, reg);
 622 }
 623
 624 static inline int vdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 625 {
 626         struct adv7604_state *state = to_state(sd);
 627
 628         return adv_smbus_write_byte_data(state, ADV7604_PAGE_VDP, reg, val);
 629 }
 630
 631 #define ADV7604_REG(page, offset)       (((page) << 8) | (offset))
 632 #define ADV7604_REG_SEQ_TERM            0xffff
 633
 634 #ifdef CONFIG_VIDEO_ADV_DEBUG
 635 static int adv7604_read_reg(struct v4l2_subdev *sd, unsigned int reg)
 636 {
 637         struct adv7604_state *state = to_state(sd);
 638         unsigned int page = reg >> 8;
 639
 640         if (!(BIT(page) & state->info->page_mask))
 641                 return -EINVAL;
 642
 643         reg &= 0xff;
 644
 645         return adv_smbus_read_byte_data(state, page, reg);
 646 }
 647 #endif
 648
 649 static int adv7604_write_reg(struct v4l2_subdev *sd, unsigned int reg, u8 val)
 650 {
 651         struct adv7604_state *state = to_state(sd);
 652         unsigned int page = reg >> 8;
 653
 654         if (!(BIT(page) & state->info->page_mask))
 655                 return -EINVAL;
 656
 657         reg &= 0xff;
 658
 659         return adv_smbus_write_byte_data(state, page, reg, val);
 660 }
 661
 662 static void adv7604_write_reg_seq(struct v4l2_subdev *sd,
 663                                   const struct adv7604_reg_seq *reg_seq)
 664 {
 665         unsigned int i;
 666
 667         for (i = 0; reg_seq[i].reg != ADV7604_REG_SEQ_TERM; i++)
 668                 adv7604_write_reg(sd, reg_seq[i].reg, reg_seq[i].val);
 669 }
 670
 671 /* -----------------------------------------------------------------------------
 672  * Format helpers
 673  */
 674
 675 static const struct adv7604_format_info adv7604_formats[] = {
 676         { MEDIA_BUS_FMT_RGB888_1X24, ADV7604_OP_CH_SEL_RGB, true, false,
 677           ADV7604_OP_MODE_SEL_SDR_444 | ADV7604_OP_FORMAT_SEL_8BIT },
 678         { MEDIA_BUS_FMT_YUYV8_2X8, ADV7604_OP_CH_SEL_RGB, false, false,
 679           ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_8BIT },
 680         { MEDIA_BUS_FMT_YVYU8_2X8, ADV7604_OP_CH_SEL_RGB, false, true,
 681           ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_8BIT },
 682         { MEDIA_BUS_FMT_YUYV10_2X10, ADV7604_OP_CH_SEL_RGB, false, false,
 683           ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_10BIT },
 684         { MEDIA_BUS_FMT_YVYU10_2X10, ADV7604_OP_CH_SEL_RGB, false, true,
 685           ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_10BIT },
 686         { MEDIA_BUS_FMT_YUYV12_2X12, ADV7604_OP_CH_SEL_RGB, false, false,
 687           ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_12BIT },
 688         { MEDIA_BUS_FMT_YVYU12_2X12, ADV7604_OP_CH_SEL_RGB, false, true,
 689           ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_12BIT },
 690         { MEDIA_BUS_FMT_UYVY8_1X16, ADV7604_OP_CH_SEL_RBG, false, false,
 691           ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT },
 692         { MEDIA_BUS_FMT_VYUY8_1X16, ADV7604_OP_CH_SEL_RBG, false, true,
 693           ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT },
 694         { MEDIA_BUS_FMT_YUYV8_1X16, ADV7604_OP_CH_SEL_RGB, false, false,
 695           ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT },
 696         { MEDIA_BUS_FMT_YVYU8_1X16, ADV7604_OP_CH_SEL_RGB, false, true,
 697           ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT },
 698         { MEDIA_BUS_FMT_UYVY10_1X20, ADV7604_OP_CH_SEL_RBG, false, false,
 699           ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
 700         { MEDIA_BUS_FMT_VYUY10_1X20, ADV7604_OP_CH_SEL_RBG, false, true,
 701           ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
 702         { MEDIA_BUS_FMT_YUYV10_1X20, ADV7604_OP_CH_SEL_RGB, false, false,
 703           ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
 704         { MEDIA_BUS_FMT_YVYU10_1X20, ADV7604_OP_CH_SEL_RGB, false, true,
 705           ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
 706         { MEDIA_BUS_FMT_UYVY12_1X24, ADV7604_OP_CH_SEL_RBG, false, false,
 707           ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT },
 708         { MEDIA_BUS_FMT_VYUY12_1X24, ADV7604_OP_CH_SEL_RBG, false, true,
 709           ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT },
 710         { MEDIA_BUS_FMT_YUYV12_1X24, ADV7604_OP_CH_SEL_RGB, false, false,
 711           ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT },
 712         { MEDIA_BUS_FMT_YVYU12_1X24, ADV7604_OP_CH_SEL_RGB, false, true,
 713           ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT },
 714 };
 715
 716 static const struct adv7604_format_info adv7611_formats[] = {
 717         { MEDIA_BUS_FMT_RGB888_1X24, ADV7604_OP_CH_SEL_RGB, true, false,
 718           ADV7604_OP_MODE_SEL_SDR_444 | ADV7604_OP_FORMAT_SEL_8BIT },
 719         { MEDIA_BUS_FMT_YUYV8_2X8, ADV7604_OP_CH_SEL_RGB, false, false,
 720           ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_8BIT },
 721         { MEDIA_BUS_FMT_YVYU8_2X8, ADV7604_OP_CH_SEL_RGB, false, true,
 722           ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_8BIT },
 723         { MEDIA_BUS_FMT_YUYV12_2X12, ADV7604_OP_CH_SEL_RGB, false, false,
 724           ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_12BIT },
 725         { MEDIA_BUS_FMT_YVYU12_2X12, ADV7604_OP_CH_SEL_RGB, false, true,
 726           ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_12BIT },
 727         { MEDIA_BUS_FMT_UYVY8_1X16, ADV7604_OP_CH_SEL_RBG, false, false,
 728           ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT },
 729         { MEDIA_BUS_FMT_VYUY8_1X16, ADV7604_OP_CH_SEL_RBG, false, true,
 730           ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT },
 731         { MEDIA_BUS_FMT_YUYV8_1X16, ADV7604_OP_CH_SEL_RGB, false, false,
 732           ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT },
 733         { MEDIA_BUS_FMT_YVYU8_1X16, ADV7604_OP_CH_SEL_RGB, false, true,
 734           ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT },
 735         { MEDIA_BUS_FMT_UYVY12_1X24, ADV7604_OP_CH_SEL_RBG, false, false,
 736           ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT },
 737         { MEDIA_BUS_FMT_VYUY12_1X24, ADV7604_OP_CH_SEL_RBG, false, true,
 738           ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT },
 739         { MEDIA_BUS_FMT_YUYV12_1X24, ADV7604_OP_CH_SEL_RGB, false, false,
 740           ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT },
 741         { MEDIA_BUS_FMT_YVYU12_1X24, ADV7604_OP_CH_SEL_RGB, false, true,
 742           ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT },
 743 };
 744
 745 static const struct adv7604_format_info *
 746 adv7604_format_info(struct adv7604_state *state, u32 code)
 747 {
 748         unsigned int i;
 749
 750         for (i = 0; i < state->info->nformats; ++i) {
 751                 if (state->info->formats[i].code == code)
 752                         return &state->info->formats[i];
 753         }
 754
 755         return NULL;
 756 }
 757
 758 /* ----------------------------------------------------------------------- */
 759
 760 static inline bool is_analog_input(struct v4l2_subdev *sd)
 761 {
 762         struct adv7604_state *state = to_state(sd);
 763
 764         return state->selected_input == ADV7604_PAD_VGA_RGB ||
 765                state->selected_input == ADV7604_PAD_VGA_COMP;
 766 }
 767
 768 static inline bool is_digital_input(struct v4l2_subdev *sd)
 769 {
 770         struct adv7604_state *state = to_state(sd);
 771
 772         return state->selected_input == ADV7604_PAD_HDMI_PORT_A ||
 773                state->selected_input == ADV7604_PAD_HDMI_PORT_B ||
 774                state->selected_input == ADV7604_PAD_HDMI_PORT_C ||
 775                state->selected_input == ADV7604_PAD_HDMI_PORT_D;
 776 }
 777
 778 /* ----------------------------------------------------------------------- */
 779
 780 #ifdef CONFIG_VIDEO_ADV_DEBUG
 781 static void adv7604_inv_register(struct v4l2_subdev *sd)
 782 {
 783         v4l2_info(sd, "0x000-0x0ff: IO Map\n");
 784         v4l2_info(sd, "0x100-0x1ff: AVLink Map\n");
 785         v4l2_info(sd, "0x200-0x2ff: CEC Map\n");
 786         v4l2_info(sd, "0x300-0x3ff: InfoFrame Map\n");
 787         v4l2_info(sd, "0x400-0x4ff: ESDP Map\n");
 788         v4l2_info(sd, "0x500-0x5ff: DPP Map\n");
 789         v4l2_info(sd, "0x600-0x6ff: AFE Map\n");
 790         v4l2_info(sd, "0x700-0x7ff: Repeater Map\n");
 791         v4l2_info(sd, "0x800-0x8ff: EDID Map\n");
 792         v4l2_info(sd, "0x900-0x9ff: HDMI Map\n");
 793         v4l2_info(sd, "0xa00-0xaff: Test Map\n");
 794         v4l2_info(sd, "0xb00-0xbff: CP Map\n");
 795         v4l2_info(sd, "0xc00-0xcff: VDP Map\n");
 796 }
 797
 798 static int adv7604_g_register(struct v4l2_subdev *sd,
 799                                         struct v4l2_dbg_register *reg)
 800 {
 801         int ret;
 802
 803         ret = adv7604_read_reg(sd, reg->reg);
 804         if (ret < 0) {
 805                 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
 806                 adv7604_inv_register(sd);
 807                 return ret;
 808         }
 809
 810         reg->size = 1;
 811         reg->val = ret;
 812
 813         return 0;
 814 }
 815
 816 static int adv7604_s_register(struct v4l2_subdev *sd,
 817                                         const struct v4l2_dbg_register *reg)
 818 {
 819         int ret;
 820
 821         ret = adv7604_write_reg(sd, reg->reg, reg->val);
 822         if (ret < 0) {
 823                 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
 824                 adv7604_inv_register(sd);
 825                 return ret;
 826         }
 827
 828         return 0;
 829 }
 830 #endif
 831
 832 static unsigned int adv7604_read_cable_det(struct v4l2_subdev *sd)
 833 {
 834         u8 value = io_read(sd, 0x6f);
 835
 836         return ((value & 0x10) >> 4)
 837              | ((value & 0x08) >> 2)
 838              | ((value & 0x04) << 0)
 839              | ((value & 0x02) << 2);
 840 }
 841
 842 static unsigned int adv7611_read_cable_det(struct v4l2_subdev *sd)
 843 {
 844         u8 value = io_read(sd, 0x6f);
 845
 846         return value & 1;
 847 }
 848
 849 static int adv7604_s_detect_tx_5v_ctrl(struct v4l2_subdev *sd)
 850 {
 851         struct adv7604_state *state = to_state(sd);
 852         const struct adv7604_chip_info *info = state->info;
 853
 854         return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl,
 855                                 info->read_cable_det(sd));
 856 }
 857
 858 static int find_and_set_predefined_video_timings(struct v4l2_subdev *sd,
 859                 u8 prim_mode,
 860                 const struct adv7604_video_standards *predef_vid_timings,
 861                 const struct v4l2_dv_timings *timings)
 862 {
 863         int i;
 864
 865         for (i = 0; predef_vid_timings[i].timings.bt.width; i++) {
 866                 if (!v4l2_match_dv_timings(timings, &predef_vid_timings[i].timings,
 867                                         is_digital_input(sd) ? 250000 : 1000000))
 868                         continue;
 869                 io_write(sd, 0x00, predef_vid_timings[i].vid_std); /* video std */
 870                 io_write(sd, 0x01, (predef_vid_timings[i].v_freq << 4) +
 871                                 prim_mode); /* v_freq and prim mode */
 872                 return 0;
 873         }
 874
 875         return -1;
 876 }
 877
 878 static int configure_predefined_video_timings(struct v4l2_subdev *sd,
 879                 struct v4l2_dv_timings *timings)
 880 {
 881         struct adv7604_state *state = to_state(sd);
 882         int err;
 883
 884         v4l2_dbg(1, debug, sd, "%s", __func__);
 885
 886         if (adv7604_has_afe(state)) {
 887                 /* reset to default values */
 888                 io_write(sd, 0x16, 0x43);
 889                 io_write(sd, 0x17, 0x5a);
 890         }
 891         /* disable embedded syncs for auto graphics mode */
 892         cp_write_clr_set(sd, 0x81, 0x10, 0x00);
 893         cp_write(sd, 0x8f, 0x00);
 894         cp_write(sd, 0x90, 0x00);
 895         cp_write(sd, 0xa2, 0x00);
 896         cp_write(sd, 0xa3, 0x00);
 897         cp_write(sd, 0xa4, 0x00);
 898         cp_write(sd, 0xa5, 0x00);
 899         cp_write(sd, 0xa6, 0x00);
 900         cp_write(sd, 0xa7, 0x00);
 901         cp_write(sd, 0xab, 0x00);
 902         cp_write(sd, 0xac, 0x00);
 903
 904         if (is_analog_input(sd)) {
 905                 err = find_and_set_predefined_video_timings(sd,
 906                                 0x01, adv7604_prim_mode_comp, timings);
 907                 if (err)
 908                         err = find_and_set_predefined_video_timings(sd,
 909                                         0x02, adv7604_prim_mode_gr, timings);
 910         } else if (is_digital_input(sd)) {
 911                 err = find_and_set_predefined_video_timings(sd,
 912                                 0x05, adv7604_prim_mode_hdmi_comp, timings);
 913                 if (err)
 914                         err = find_and_set_predefined_video_timings(sd,
 915                                         0x06, adv7604_prim_mode_hdmi_gr, timings);
 916         } else {
 917                 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
 918                                 __func__, state->selected_input);
 919                 err = -1;
 920         }
 921
 922
 923         return err;
 924 }
 925
 926 static void configure_custom_video_timings(struct v4l2_subdev *sd,
 927                 const struct v4l2_bt_timings *bt)
 928 {
 929         struct adv7604_state *state = to_state(sd);
 930         u32 width = htotal(bt);
 931         u32 height = vtotal(bt);
 932         u16 cp_start_sav = bt->hsync + bt->hbackporch - 4;
 933         u16 cp_start_eav = width - bt->hfrontporch;
 934         u16 cp_start_vbi = height - bt->vfrontporch;
 935         u16 cp_end_vbi = bt->vsync + bt->vbackporch;
 936         u16 ch1_fr_ll = (((u32)bt->pixelclock / 100) > 0) ?
 937                 ((width * (ADV7604_fsc / 100)) / ((u32)bt->pixelclock / 100)) : 0;
 938         const u8 pll[2] = {
 939                 0xc0 | ((width >> 8) & 0x1f),
 940                 width & 0xff
 941         };
 942
 943         v4l2_dbg(2, debug, sd, "%s\n", __func__);
 944
 945         if (is_analog_input(sd)) {
 946                 /* auto graphics */
 947                 io_write(sd, 0x00, 0x07); /* video std */
 948                 io_write(sd, 0x01, 0x02); /* prim mode */
 949                 /* enable embedded syncs for auto graphics mode */
 950                 cp_write_clr_set(sd, 0x81, 0x10, 0x10);
 951
 952                 /* Should only be set in auto-graphics mode [REF_02, p. 91-92] */
 953                 /* setup PLL_DIV_MAN_EN and PLL_DIV_RATIO */
 954                 /* IO-map reg. 0x16 and 0x17 should be written in sequence */
 955                 if (adv_smbus_write_i2c_block_data(state, ADV7604_PAGE_IO,
 956                                                    0x16, 2, pll))
 957                         v4l2_err(sd, "writing to reg 0x16 and 0x17 failed\n");
 958
 959                 /* active video - horizontal timing */
 960                 cp_write(sd, 0xa2, (cp_start_sav >> 4) & 0xff);
 961                 cp_write(sd, 0xa3, ((cp_start_sav & 0x0f) << 4) |
 962                                    ((cp_start_eav >> 8) & 0x0f));
 963                 cp_write(sd, 0xa4, cp_start_eav & 0xff);
 964
 965                 /* active video - vertical timing */
 966                 cp_write(sd, 0xa5, (cp_start_vbi >> 4) & 0xff);
 967                 cp_write(sd, 0xa6, ((cp_start_vbi & 0xf) << 4) |
 968                                    ((cp_end_vbi >> 8) & 0xf));
 969                 cp_write(sd, 0xa7, cp_end_vbi & 0xff);
 970         } else if (is_digital_input(sd)) {
 971                 /* set default prim_mode/vid_std for HDMI
 972                    according to [REF_03, c. 4.2] */
 973                 io_write(sd, 0x00, 0x02); /* video std */
 974                 io_write(sd, 0x01, 0x06); /* prim mode */
 975         } else {
 976                 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
 977                                 __func__, state->selected_input);
 978         }
 979
 980         cp_write(sd, 0x8f, (ch1_fr_ll >> 8) & 0x7);
 981         cp_write(sd, 0x90, ch1_fr_ll & 0xff);
 982         cp_write(sd, 0xab, (height >> 4) & 0xff);
 983         cp_write(sd, 0xac, (height & 0x0f) << 4);
 984 }
 985
 986 static void adv7604_set_offset(struct v4l2_subdev *sd, bool auto_offset, u16 offset_a, u16 offset_b, u16 offset_c)
 987 {
 988         struct adv7604_state *state = to_state(sd);
 989         u8 offset_buf[4];
 990
 991         if (auto_offset) {
 992                 offset_a = 0x3ff;
 993                 offset_b = 0x3ff;
 994                 offset_c = 0x3ff;
 995         }
 996
 997         v4l2_dbg(2, debug, sd, "%s: %s offset: a = 0x%x, b = 0x%x, c = 0x%x\n",
 998                         __func__, auto_offset ? "Auto" : "Manual",
 999                         offset_a, offset_b, offset_c);
1000
1001         offset_buf[0] = (cp_read(sd, 0x77) & 0xc0) | ((offset_a & 0x3f0) >> 4);
1002         offset_buf[1] = ((offset_a & 0x00f) << 4) | ((offset_b & 0x3c0) >> 6);
1003         offset_buf[2] = ((offset_b & 0x03f) << 2) | ((offset_c & 0x300) >> 8);
1004         offset_buf[3] = offset_c & 0x0ff;
1005
1006         /* Registers must be written in this order with no i2c access in between */
1007         if (adv_smbus_write_i2c_block_data(state, ADV7604_PAGE_CP,
1008                                            0x77, 4, offset_buf))
1009                 v4l2_err(sd, "%s: i2c error writing to CP reg 0x77, 0x78, 0x79, 0x7a\n", __func__);
1010 }
1011
1012 static void adv7604_set_gain(struct v4l2_subdev *sd, bool auto_gain, u16 gain_a, u16 gain_b, u16 gain_c)
1013 {
1014         struct adv7604_state *state = to_state(sd);
1015         u8 gain_buf[4];
1016         u8 gain_man = 1;
1017         u8 agc_mode_man = 1;
1018
1019         if (auto_gain) {
1020                 gain_man = 0;
1021                 agc_mode_man = 0;
1022                 gain_a = 0x100;
1023                 gain_b = 0x100;
1024                 gain_c = 0x100;
1025         }
1026
1027         v4l2_dbg(2, debug, sd, "%s: %s gain: a = 0x%x, b = 0x%x, c = 0x%x\n",
1028                         __func__, auto_gain ? "Auto" : "Manual",
1029                         gain_a, gain_b, gain_c);
1030
1031         gain_buf[0] = ((gain_man << 7) | (agc_mode_man << 6) | ((gain_a & 0x3f0) >> 4));
1032         gain_buf[1] = (((gain_a & 0x00f) << 4) | ((gain_b & 0x3c0) >> 6));
1033         gain_buf[2] = (((gain_b & 0x03f) << 2) | ((gain_c & 0x300) >> 8));
1034         gain_buf[3] = ((gain_c & 0x0ff));
1035
1036         /* Registers must be written in this order with no i2c access in between */
1037         if (adv_smbus_write_i2c_block_data(state, ADV7604_PAGE_CP,
1038                                            0x73, 4, gain_buf))
1039                 v4l2_err(sd, "%s: i2c error writing to CP reg 0x73, 0x74, 0x75, 0x76\n", __func__);
1040 }
1041
1042 static void set_rgb_quantization_range(struct v4l2_subdev *sd)
1043 {
1044         struct adv7604_state *state = to_state(sd);
1045         bool rgb_output = io_read(sd, 0x02) & 0x02;
1046         bool hdmi_signal = hdmi_read(sd, 0x05) & 0x80;
1047
1048         v4l2_dbg(2, debug, sd, "%s: RGB quantization range: %d, RGB out: %d, HDMI: %d\n",
1049                         __func__, state->rgb_quantization_range,
1050                         rgb_output, hdmi_signal);
1051
1052         adv7604_set_gain(sd, true, 0x0, 0x0, 0x0);
1053         adv7604_set_offset(sd, true, 0x0, 0x0, 0x0);
1054
1055         switch (state->rgb_quantization_range) {
1056         case V4L2_DV_RGB_RANGE_AUTO:
1057                 if (state->selected_input == ADV7604_PAD_VGA_RGB) {
1058                         /* Receiving analog RGB signal
1059                          * Set RGB full range (0-255) */
1060                         io_write_clr_set(sd, 0x02, 0xf0, 0x10);
1061                         break;
1062                 }
1063
1064                 if (state->selected_input == ADV7604_PAD_VGA_COMP) {
1065                         /* Receiving analog YPbPr signal
1066                          * Set automode */
1067                         io_write_clr_set(sd, 0x02, 0xf0, 0xf0);
1068                         break;
1069                 }
1070
1071                 if (hdmi_signal) {
1072                         /* Receiving HDMI signal
1073                          * Set automode */
1074                         io_write_clr_set(sd, 0x02, 0xf0, 0xf0);
1075                         break;
1076                 }
1077
1078                 /* Receiving DVI-D signal
1079                  * ADV7604 selects RGB limited range regardless of
1080                  * input format (CE/IT) in automatic mode */
1081                 if (state->timings.bt.standards & V4L2_DV_BT_STD_CEA861) {
1082                         /* RGB limited range (16-235) */
1083                         io_write_clr_set(sd, 0x02, 0xf0, 0x00);
1084                 } else {
1085                         /* RGB full range (0-255) */
1086                         io_write_clr_set(sd, 0x02, 0xf0, 0x10);
1087
1088                         if (is_digital_input(sd) && rgb_output) {
1089                                 adv7604_set_offset(sd, false, 0x40, 0x40, 0x40);
1090                         } else {
1091                                 adv7604_set_gain(sd, false, 0xe0, 0xe0, 0xe0);
1092                                 adv7604_set_offset(sd, false, 0x70, 0x70, 0x70);
1093                         }
1094                 }
1095                 break;
1096         case V4L2_DV_RGB_RANGE_LIMITED:
1097                 if (state->selected_input == ADV7604_PAD_VGA_COMP) {
1098                         /* YCrCb limited range (16-235) */
1099                         io_write_clr_set(sd, 0x02, 0xf0, 0x20);
1100                         break;
1101                 }
1102
1103                 /* RGB limited range (16-235) */
1104                 io_write_clr_set(sd, 0x02, 0xf0, 0x00);
1105
1106                 break;
1107         case V4L2_DV_RGB_RANGE_FULL:
1108                 if (state->selected_input == ADV7604_PAD_VGA_COMP) {
1109                         /* YCrCb full range (0-255) */
1110                         io_write_clr_set(sd, 0x02, 0xf0, 0x60);
1111                         break;
1112                 }
1113
1114                 /* RGB full range (0-255) */
1115                 io_write_clr_set(sd, 0x02, 0xf0, 0x10);
1116
1117                 if (is_analog_input(sd) || hdmi_signal)
1118                         break;
1119
1120                 /* Adjust gain/offset for DVI-D signals only */
1121                 if (rgb_output) {
1122                         adv7604_set_offset(sd, false, 0x40, 0x40, 0x40);
1123                 } else {
1124                         adv7604_set_gain(sd, false, 0xe0, 0xe0, 0xe0);
1125                         adv7604_set_offset(sd, false, 0x70, 0x70, 0x70);
1126                 }
1127                 break;
1128         }
1129 }
1130
1131 static int adv7604_s_ctrl(struct v4l2_ctrl *ctrl)
1132 {
1133         struct v4l2_subdev *sd =
1134                 &container_of(ctrl->handler, struct adv7604_state, hdl)->sd;
1135
1136         struct adv7604_state *state = to_state(sd);
1137
1138         switch (ctrl->id) {
1139         case V4L2_CID_BRIGHTNESS:
1140                 cp_write(sd, 0x3c, ctrl->val);
1141                 return 0;
1142         case V4L2_CID_CONTRAST:
1143                 cp_write(sd, 0x3a, ctrl->val);
1144                 return 0;
1145         case V4L2_CID_SATURATION:
1146                 cp_write(sd, 0x3b, ctrl->val);
1147                 return 0;
1148         case V4L2_CID_HUE:
1149                 cp_write(sd, 0x3d, ctrl->val);
1150                 return 0;
1151         case  V4L2_CID_DV_RX_RGB_RANGE:
1152                 state->rgb_quantization_range = ctrl->val;
1153                 set_rgb_quantization_range(sd);
1154                 return 0;
1155         case V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE:
1156                 if (!adv7604_has_afe(state))
1157                         return -EINVAL;
1158                 /* Set the analog sampling phase. This is needed to find the
1159                    best sampling phase for analog video: an application or
1160                    driver has to try a number of phases and analyze the picture
1161                    quality before settling on the best performing phase. */
1162                 afe_write(sd, 0xc8, ctrl->val);
1163                 return 0;
1164         case V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL:
1165                 /* Use the default blue color for free running mode,
1166                    or supply your own. */
1167                 cp_write_clr_set(sd, 0xbf, 0x04, ctrl->val << 2);
1168                 return 0;
1169         case V4L2_CID_ADV_RX_FREE_RUN_COLOR:
1170                 cp_write(sd, 0xc0, (ctrl->val & 0xff0000) >> 16);
1171                 cp_write(sd, 0xc1, (ctrl->val & 0x00ff00) >> 8);
1172                 cp_write(sd, 0xc2, (u8)(ctrl->val & 0x0000ff));
1173                 return 0;
1174         }
1175         return -EINVAL;
1176 }
1177
1178 /* ----------------------------------------------------------------------- */
1179
1180 static inline bool no_power(struct v4l2_subdev *sd)
1181 {
1182         /* Entire chip or CP powered off */
1183         return io_read(sd, 0x0c) & 0x24;
1184 }
1185
1186 static inline bool no_signal_tmds(struct v4l2_subdev *sd)
1187 {
1188         struct adv7604_state *state = to_state(sd);
1189
1190         return !(io_read(sd, 0x6a) & (0x10 >> state->selected_input));
1191 }
1192
1193 static inline bool no_lock_tmds(struct v4l2_subdev *sd)
1194 {
1195         struct adv7604_state *state = to_state(sd);
1196         const struct adv7604_chip_info *info = state->info;
1197
1198         return (io_read(sd, 0x6a) & info->tdms_lock_mask) != info->tdms_lock_mask;
1199 }
1200
1201 static inline bool is_hdmi(struct v4l2_subdev *sd)
1202 {
1203         return hdmi_read(sd, 0x05) & 0x80;
1204 }
1205
1206 static inline bool no_lock_sspd(struct v4l2_subdev *sd)
1207 {
1208         struct adv7604_state *state = to_state(sd);
1209
1210         /*
1211          * Chips without a AFE don't expose registers for the SSPD, so just assume
1212          * that we have a lock.
1213          */
1214         if (adv7604_has_afe(state))
1215                 return false;
1216
1217         /* TODO channel 2 */
1218         return ((cp_read(sd, 0xb5) & 0xd0) != 0xd0);
1219 }
1220
1221 static inline bool no_lock_stdi(struct v4l2_subdev *sd)
1222 {
1223         /* TODO channel 2 */
1224         return !(cp_read(sd, 0xb1) & 0x80);
1225 }
1226
1227 static inline bool no_signal(struct v4l2_subdev *sd)
1228 {
1229         bool ret;
1230
1231         ret = no_power(sd);
1232
1233         ret |= no_lock_stdi(sd);
1234         ret |= no_lock_sspd(sd);
1235
1236         if (is_digital_input(sd)) {
1237                 ret |= no_lock_tmds(sd);
1238                 ret |= no_signal_tmds(sd);
1239         }
1240
1241         return ret;
1242 }
1243
1244 static inline bool no_lock_cp(struct v4l2_subdev *sd)
1245 {
1246         struct adv7604_state *state = to_state(sd);
1247
1248         if (!adv7604_has_afe(state))
1249                 return false;
1250
1251         /* CP has detected a non standard number of lines on the incoming
1252            video compared to what it is configured to receive by s_dv_timings */
1253         return io_read(sd, 0x12) & 0x01;
1254 }
1255
1256 static int adv7604_g_input_status(struct v4l2_subdev *sd, u32 *status)
1257 {
1258         *status = 0;
1259         *status |= no_power(sd) ? V4L2_IN_ST_NO_POWER : 0;
1260         *status |= no_signal(sd) ? V4L2_IN_ST_NO_SIGNAL : 0;
1261         if (no_lock_cp(sd))
1262                 *status |= is_digital_input(sd) ? V4L2_IN_ST_NO_SYNC : V4L2_IN_ST_NO_H_LOCK;
1263
1264         v4l2_dbg(1, debug, sd, "%s: status = 0x%x\n", __func__, *status);
1265
1266         return 0;
1267 }
1268
1269 /* ----------------------------------------------------------------------- */
1270
1271 struct stdi_readback {
1272         u16 bl, lcf, lcvs;
1273         u8 hs_pol, vs_pol;
1274         bool interlaced;
1275 };
1276
1277 static int stdi2dv_timings(struct v4l2_subdev *sd,
1278                 struct stdi_readback *stdi,
1279                 struct v4l2_dv_timings *timings)
1280 {
1281         struct adv7604_state *state = to_state(sd);
1282         u32 hfreq = (ADV7604_fsc * 8) / stdi->bl;
1283         u32 pix_clk;
1284         int i;
1285
1286         for (i = 0; adv7604_timings[i].bt.height; i++) {
1287                 if (vtotal(&adv7604_timings[i].bt) != stdi->lcf + 1)
1288                         continue;
1289                 if (adv7604_timings[i].bt.vsync != stdi->lcvs)
1290                         continue;
1291
1292                 pix_clk = hfreq * htotal(&adv7604_timings[i].bt);
1293
1294                 if ((pix_clk < adv7604_timings[i].bt.pixelclock + 1000000) &&
1295                     (pix_clk > adv7604_timings[i].bt.pixelclock - 1000000)) {
1296                         *timings = adv7604_timings[i];
1297                         return 0;
1298                 }
1299         }
1300
1301         if (v4l2_detect_cvt(stdi->lcf + 1, hfreq, stdi->lcvs,
1302                         (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1303                         (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
1304                         timings))
1305                 return 0;
1306         if (v4l2_detect_gtf(stdi->lcf + 1, hfreq, stdi->lcvs,
1307                         (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1308                         (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
1309                         state->aspect_ratio, timings))
1310                 return 0;
1311
1312         v4l2_dbg(2, debug, sd,
1313                 "%s: No format candidate found for lcvs = %d, lcf=%d, bl = %d, %chsync, %cvsync\n",
1314                 __func__, stdi->lcvs, stdi->lcf, stdi->bl,
1315                 stdi->hs_pol, stdi->vs_pol);
1316         return -1;
1317 }
1318
1319
1320 static int read_stdi(struct v4l2_subdev *sd, struct stdi_readback *stdi)
1321 {
1322         struct adv7604_state *state = to_state(sd);
1323         const struct adv7604_chip_info *info = state->info;
1324         u8 polarity;
1325
1326         if (no_lock_stdi(sd) || no_lock_sspd(sd)) {
1327                 v4l2_dbg(2, debug, sd, "%s: STDI and/or SSPD not locked\n", __func__);
1328                 return -1;
1329         }
1330
1331         /* read STDI */
1332         stdi->bl = cp_read16(sd, 0xb1, 0x3fff);
1333         stdi->lcf = cp_read16(sd, info->lcf_reg, 0x7ff);
1334         stdi->lcvs = cp_read(sd, 0xb3) >> 3;
1335         stdi->interlaced = io_read(sd, 0x12) & 0x10;
1336
1337         if (adv7604_has_afe(state)) {
1338                 /* read SSPD */
1339                 polarity = cp_read(sd, 0xb5);
1340                 if ((polarity & 0x03) == 0x01) {
1341                         stdi->hs_pol = polarity & 0x10
1342                                      ? (polarity & 0x08 ? '+' : '-') : 'x';
1343                         stdi->vs_pol = polarity & 0x40
1344                                      ? (polarity & 0x20 ? '+' : '-') : 'x';
1345                 } else {
1346                         stdi->hs_pol = 'x';
1347                         stdi->vs_pol = 'x';
1348                 }
1349         } else {
1350                 polarity = hdmi_read(sd, 0x05);
1351                 stdi->hs_pol = polarity & 0x20 ? '+' : '-';
1352                 stdi->vs_pol = polarity & 0x10 ? '+' : '-';
1353         }
1354
1355         if (no_lock_stdi(sd) || no_lock_sspd(sd)) {
1356                 v4l2_dbg(2, debug, sd,
1357                         "%s: signal lost during readout of STDI/SSPD\n", __func__);
1358                 return -1;
1359         }
1360
1361         if (stdi->lcf < 239 || stdi->bl < 8 || stdi->bl == 0x3fff) {
1362                 v4l2_dbg(2, debug, sd, "%s: invalid signal\n", __func__);
1363                 memset(stdi, 0, sizeof(struct stdi_readback));
1364                 return -1;
1365         }
1366
1367         v4l2_dbg(2, debug, sd,
1368                 "%s: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %chsync, %cvsync, %s\n",
1369                 __func__, stdi->lcf, stdi->bl, stdi->lcvs,
1370                 stdi->hs_pol, stdi->vs_pol,
1371                 stdi->interlaced ? "interlaced" : "progressive");
1372
1373         return 0;
1374 }
1375
1376 static int adv7604_enum_dv_timings(struct v4l2_subdev *sd,
1377                         struct v4l2_enum_dv_timings *timings)
1378 {
1379         struct adv7604_state *state = to_state(sd);
1380
1381         if (timings->index >= ARRAY_SIZE(adv7604_timings) - 1)
1382                 return -EINVAL;
1383
1384         if (timings->pad >= state->source_pad)
1385                 return -EINVAL;
1386
1387         memset(timings->reserved, 0, sizeof(timings->reserved));
1388         timings->timings = adv7604_timings[timings->index];
1389         return 0;
1390 }
1391
1392 static int adv7604_dv_timings_cap(struct v4l2_subdev *sd,
1393                         struct v4l2_dv_timings_cap *cap)
1394 {
1395         struct adv7604_state *state = to_state(sd);
1396
1397         if (cap->pad >= state->source_pad)
1398                 return -EINVAL;
1399
1400         cap->type = V4L2_DV_BT_656_1120;
1401         cap->bt.max_width = 1920;
1402         cap->bt.max_height = 1200;
1403         cap->bt.min_pixelclock = 25000000;
1404
1405         switch (cap->pad) {
1406         case ADV7604_PAD_HDMI_PORT_A:
1407         case ADV7604_PAD_HDMI_PORT_B:
1408         case ADV7604_PAD_HDMI_PORT_C:
1409         case ADV7604_PAD_HDMI_PORT_D:
1410                 cap->bt.max_pixelclock = 225000000;
1411                 break;
1412         case ADV7604_PAD_VGA_RGB:
1413         case ADV7604_PAD_VGA_COMP:
1414         default:
1415                 cap->bt.max_pixelclock = 170000000;
1416                 break;
1417         }
1418
1419         cap->bt.standards = V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
1420                          V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT;
1421         cap->bt.capabilities = V4L2_DV_BT_CAP_PROGRESSIVE |
1422                 V4L2_DV_BT_CAP_REDUCED_BLANKING | V4L2_DV_BT_CAP_CUSTOM;
1423         return 0;
1424 }
1425
1426 /* Fill the optional fields .standards and .flags in struct v4l2_dv_timings
1427    if the format is listed in adv7604_timings[] */
1428 static void adv7604_fill_optional_dv_timings_fields(struct v4l2_subdev *sd,
1429                 struct v4l2_dv_timings *timings)
1430 {
1431         int i;
1432
1433         for (i = 0; adv7604_timings[i].bt.width; i++) {
1434                 if (v4l2_match_dv_timings(timings, &adv7604_timings[i],
1435                                         is_digital_input(sd) ? 250000 : 1000000)) {
1436                         *timings = adv7604_timings[i];
1437                         break;
1438                 }
1439         }
1440 }
1441
1442 static unsigned int adv7604_read_hdmi_pixelclock(struct v4l2_subdev *sd)
1443 {
1444         unsigned int freq;
1445         int a, b;
1446
1447         a = hdmi_read(sd, 0x06);
1448         b = hdmi_read(sd, 0x3b);
1449         if (a < 0 || b < 0)
1450                 return 0;
1451         freq =  a * 1000000 + ((b & 0x30) >> 4) * 250000;
1452
1453         if (is_hdmi(sd)) {
1454                 /* adjust for deep color mode */
1455                 unsigned bits_per_channel = ((hdmi_read(sd, 0x0b) & 0x60) >> 4) + 8;
1456
1457                 freq = freq * 8 / bits_per_channel;
1458         }
1459
1460         return freq;
1461 }
1462
1463 static unsigned int adv7611_read_hdmi_pixelclock(struct v4l2_subdev *sd)
1464 {
1465         int a, b;
1466
1467         a = hdmi_read(sd, 0x51);
1468         b = hdmi_read(sd, 0x52);
1469         if (a < 0 || b < 0)
1470                 return 0;
1471         return ((a << 1) | (b >> 7)) * 1000000 + (b & 0x7f) * 1000000 / 128;
1472 }
1473
1474 static int adv7604_query_dv_timings(struct v4l2_subdev *sd,
1475                         struct v4l2_dv_timings *timings)
1476 {
1477         struct adv7604_state *state = to_state(sd);
1478         const struct adv7604_chip_info *info = state->info;
1479         struct v4l2_bt_timings *bt = &timings->bt;
1480         struct stdi_readback stdi;
1481
1482         if (!timings)
1483                 return -EINVAL;
1484
1485         memset(timings, 0, sizeof(struct v4l2_dv_timings));
1486
1487         if (no_signal(sd)) {
1488                 state->restart_stdi_once = true;
1489                 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);
1490                 return -ENOLINK;
1491         }
1492
1493         /* read STDI */
1494         if (read_stdi(sd, &stdi)) {
1495                 v4l2_dbg(1, debug, sd, "%s: STDI/SSPD not locked\n", __func__);
1496                 return -ENOLINK;
1497         }
1498         bt->interlaced = stdi.interlaced ?
1499                 V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE;
1500
1501         if (is_digital_input(sd)) {
1502                 timings->type = V4L2_DV_BT_656_1120;
1503
1504                 /* FIXME: All masks are incorrect for ADV7611 */
1505                 bt->width = hdmi_read16(sd, 0x07, 0xfff);
1506                 bt->height = hdmi_read16(sd, 0x09, 0xfff);
1507                 bt->pixelclock = info->read_hdmi_pixelclock(sd);
1508                 bt->hfrontporch = hdmi_read16(sd, 0x20, 0x3ff);
1509                 bt->hsync = hdmi_read16(sd, 0x22, 0x3ff);
1510                 bt->hbackporch = hdmi_read16(sd, 0x24, 0x3ff);
1511                 bt->vfrontporch = hdmi_read16(sd, 0x2a, 0x1fff) / 2;
1512                 bt->vsync = hdmi_read16(sd, 0x2e, 0x1fff) / 2;
1513                 bt->vbackporch = hdmi_read16(sd, 0x32, 0x1fff) / 2;
1514                 bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL : 0) |
1515                         ((hdmi_read(sd, 0x05) & 0x20) ? V4L2_DV_HSYNC_POS_POL : 0);
1516                 if (bt->interlaced == V4L2_DV_INTERLACED) {
1517                         bt->height += hdmi_read16(sd, 0x0b, 0xfff);
1518                         bt->il_vfrontporch = hdmi_read16(sd, 0x2c, 0x1fff) / 2;
1519                         bt->il_vsync = hdmi_read16(sd, 0x30, 0x1fff) / 2;
1520                         bt->il_vbackporch = hdmi_read16(sd, 0x34, 0x1fff) / 2;
1521                 }
1522                 adv7604_fill_optional_dv_timings_fields(sd, timings);
1523         } else {
1524                 /* find format
1525                  * Since LCVS values are inaccurate [REF_03, p. 275-276],
1526                  * stdi2dv_timings() is called with lcvs +-1 if the first attempt fails.
1527                  */
1528                 if (!stdi2dv_timings(sd, &stdi, timings))
1529                         goto found;
1530                 stdi.lcvs += 1;
1531                 v4l2_dbg(1, debug, sd, "%s: lcvs + 1 = %d\n", __func__, stdi.lcvs);
1532                 if (!stdi2dv_timings(sd, &stdi, timings))
1533                         goto found;
1534                 stdi.lcvs -= 2;
1535                 v4l2_dbg(1, debug, sd, "%s: lcvs - 1 = %d\n", __func__, stdi.lcvs);
1536                 if (stdi2dv_timings(sd, &stdi, timings)) {
1537                         /*
1538                          * The STDI block may measure wrong values, especially
1539                          * for lcvs and lcf. If the driver can not find any
1540                          * valid timing, the STDI block is restarted to measure
1541                          * the video timings again. The function will return an
1542                          * error, but the restart of STDI will generate a new
1543                          * STDI interrupt and the format detection process will
1544                          * restart.
1545                          */
1546                         if (state->restart_stdi_once) {
1547                                 v4l2_dbg(1, debug, sd, "%s: restart STDI\n", __func__);
1548                                 /* TODO restart STDI for Sync Channel 2 */
1549                                 /* enter one-shot mode */
1550                                 cp_write_clr_set(sd, 0x86, 0x06, 0x00);
1551                                 /* trigger STDI restart */
1552                                 cp_write_clr_set(sd, 0x86, 0x06, 0x04);
1553                                 /* reset to continuous mode */
1554                                 cp_write_clr_set(sd, 0x86, 0x06, 0x02);
1555                                 state->restart_stdi_once = false;
1556                                 return -ENOLINK;
1557                         }
1558                         v4l2_dbg(1, debug, sd, "%s: format not supported\n", __func__);
1559                         return -ERANGE;
1560                 }
1561                 state->restart_stdi_once = true;
1562         }
1563 found:
1564
1565         if (no_signal(sd)) {
1566                 v4l2_dbg(1, debug, sd, "%s: signal lost during readout\n", __func__);
1567                 memset(timings, 0, sizeof(struct v4l2_dv_timings));
1568                 return -ENOLINK;
1569         }
1570
1571         if ((is_analog_input(sd) && bt->pixelclock > 170000000) ||
1572                         (is_digital_input(sd) && bt->pixelclock > 225000000)) {
1573                 v4l2_dbg(1, debug, sd, "%s: pixelclock out of range %d\n",
1574                                 __func__, (u32)bt->pixelclock);
1575                 return -ERANGE;
1576         }
1577
1578         if (debug > 1)
1579                 v4l2_print_dv_timings(sd->name, "adv7604_query_dv_timings: ",
1580                                       timings, true);
1581
1582         return 0;
1583 }
1584
1585 static int adv7604_s_dv_timings(struct v4l2_subdev *sd,
1586                 struct v4l2_dv_timings *timings)
1587 {
1588         struct adv7604_state *state = to_state(sd);
1589         struct v4l2_bt_timings *bt;
1590         int err;
1591
1592         if (!timings)
1593                 return -EINVAL;
1594
1595         if (v4l2_match_dv_timings(&state->timings, timings, 0)) {
1596                 v4l2_dbg(1, debug, sd, "%s: no change\n", __func__);
1597                 return 0;
1598         }
1599
1600         bt = &timings->bt;
1601
1602         if ((is_analog_input(sd) && bt->pixelclock > 170000000) ||
1603                         (is_digital_input(sd) && bt->pixelclock > 225000000)) {
1604                 v4l2_dbg(1, debug, sd, "%s: pixelclock out of range %d\n",
1605                                 __func__, (u32)bt->pixelclock);
1606                 return -ERANGE;
1607         }
1608
1609         adv7604_fill_optional_dv_timings_fields(sd, timings);
1610
1611         state->timings = *timings;
1612
1613         cp_write_clr_set(sd, 0x91, 0x40, bt->interlaced ? 0x40 : 0x00);
1614
1615         /* Use prim_mode and vid_std when available */
1616         err = configure_predefined_video_timings(sd, timings);
1617         if (err) {
1618                 /* custom settings when the video format
1619                  does not have prim_mode/vid_std */
1620                 configure_custom_video_timings(sd, bt);
1621         }
1622
1623         set_rgb_quantization_range(sd);
1624
1625         if (debug > 1)
1626                 v4l2_print_dv_timings(sd->name, "adv7604_s_dv_timings: ",
1627                                       timings, true);
1628         return 0;
1629 }
1630
1631 static int adv7604_g_dv_timings(struct v4l2_subdev *sd,
1632                 struct v4l2_dv_timings *timings)
1633 {
1634         struct adv7604_state *state = to_state(sd);
1635
1636         *timings = state->timings;
1637         return 0;
1638 }
1639
1640 static void adv7604_set_termination(struct v4l2_subdev *sd, bool enable)
1641 {
1642         hdmi_write(sd, 0x01, enable ? 0x00 : 0x78);
1643 }
1644
1645 static void adv7611_set_termination(struct v4l2_subdev *sd, bool enable)
1646 {
1647         hdmi_write(sd, 0x83, enable ? 0xfe : 0xff);
1648 }
1649
1650 static void enable_input(struct v4l2_subdev *sd)
1651 {
1652         struct adv7604_state *state = to_state(sd);
1653
1654         if (is_analog_input(sd)) {
1655                 io_write(sd, 0x15, 0xb0);   /* Disable Tristate of Pins (no audio) */
1656         } else if (is_digital_input(sd)) {
1657                 hdmi_write_clr_set(sd, 0x00, 0x03, state->selected_input);
1658                 state->info->set_termination(sd, true);
1659                 io_write(sd, 0x15, 0xa0);   /* Disable Tristate of Pins */
1660                 hdmi_write_clr_set(sd, 0x1a, 0x10, 0x00); /* Unmute audio */
1661         } else {
1662                 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
1663                                 __func__, state->selected_input);
1664         }
1665 }
1666
1667 static void disable_input(struct v4l2_subdev *sd)
1668 {
1669         struct adv7604_state *state = to_state(sd);
1670
1671         hdmi_write_clr_set(sd, 0x1a, 0x10, 0x10); /* Mute audio */
1672         msleep(16); /* 512 samples with >= 32 kHz sample rate [REF_03, c. 7.16.10] */
1673         io_write(sd, 0x15, 0xbe);   /* Tristate all outputs from video core */
1674         state->info->set_termination(sd, false);
1675 }
1676
1677 static void select_input(struct v4l2_subdev *sd)
1678 {
1679         struct adv7604_state *state = to_state(sd);
1680         const struct adv7604_chip_info *info = state->info;
1681
1682         if (is_analog_input(sd)) {
1683                 adv7604_write_reg_seq(sd, info->recommended_settings[0]);
1684
1685                 afe_write(sd, 0x00, 0x08); /* power up ADC */
1686                 afe_write(sd, 0x01, 0x06); /* power up Analog Front End */
1687                 afe_write(sd, 0xc8, 0x00); /* phase control */
1688         } else if (is_digital_input(sd)) {
1689                 hdmi_write(sd, 0x00, state->selected_input & 0x03);
1690
1691                 adv7604_write_reg_seq(sd, info->recommended_settings[1]);
1692
1693                 if (adv7604_has_afe(state)) {
1694                         afe_write(sd, 0x00, 0xff); /* power down ADC */
1695                         afe_write(sd, 0x01, 0xfe); /* power down Analog Front End */
1696                         afe_write(sd, 0xc8, 0x40); /* phase control */
1697                 }
1698
1699                 cp_write(sd, 0x3e, 0x00); /* CP core pre-gain control */
1700                 cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */
1701                 cp_write(sd, 0x40, 0x80); /* CP core pre-gain control. Graphics mode */
1702         } else {
1703                 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
1704                                 __func__, state->selected_input);
1705         }
1706 }
1707
1708 static int adv7604_s_routing(struct v4l2_subdev *sd,
1709                 u32 input, u32 output, u32 config)
1710 {
1711         struct adv7604_state *state = to_state(sd);
1712
1713         v4l2_dbg(2, debug, sd, "%s: input %d, selected input %d",
1714                         __func__, input, state->selected_input);
1715
1716         if (input == state->selected_input)
1717                 return 0;
1718
1719         if (input > state->info->max_port)
1720                 return -EINVAL;
1721
1722         state->selected_input = input;
1723
1724         disable_input(sd);
1725
1726         select_input(sd);
1727
1728         enable_input(sd);
1729
1730         return 0;
1731 }
1732
1733 static int adv7604_enum_mbus_code(struct v4l2_subdev *sd,
1734                                   struct v4l2_subdev_fh *fh,
1735                                   struct v4l2_subdev_mbus_code_enum *code)
1736 {
1737         struct adv7604_state *state = to_state(sd);
1738
1739         if (code->index >= state->info->nformats)
1740                 return -EINVAL;
1741
1742         code->code = state->info->formats[code->index].code;
1743
1744         return 0;
1745 }
1746
1747 static void adv7604_fill_format(struct adv7604_state *state,
1748                                 struct v4l2_mbus_framefmt *format)
1749 {
1750         memset(format, 0, sizeof(*format));
1751
1752         format->width = state->timings.bt.width;
1753         format->height = state->timings.bt.height;
1754         format->field = V4L2_FIELD_NONE;
1755
1756         if (state->timings.bt.standards & V4L2_DV_BT_STD_CEA861)
1757                 format->colorspace = (state->timings.bt.height <= 576) ?
1758                         V4L2_COLORSPACE_SMPTE170M : V4L2_COLORSPACE_REC709;
1759 }
1760
1761 /*
1762  * Compute the op_ch_sel value required to obtain on the bus the component order
1763  * corresponding to the selected format taking into account bus reordering
1764  * applied by the board at the output of the device.
1765  *
1766  * The following table gives the op_ch_value from the format component order
1767  * (expressed as op_ch_sel value in column) and the bus reordering (expressed as
1768  * adv7604_bus_order value in row).
1769  *
1770  *           |  GBR(0)  GRB(1)  BGR(2)  RGB(3)  BRG(4)  RBG(5)
1771  * ----------+-------------------------------------------------
1772  * RGB (NOP) |  GBR     GRB     BGR     RGB     BRG     RBG
1773  * GRB (1-2) |  BGR     RGB     GBR     GRB     RBG     BRG
1774  * RBG (2-3) |  GRB     GBR     BRG     RBG     BGR     RGB
1775  * BGR (1-3) |  RBG     BRG     RGB     BGR     GRB     GBR
1776  * BRG (ROR) |  BRG     RBG     GRB     GBR     RGB     BGR
1777  * GBR (ROL) |  RGB     BGR     RBG     BRG     GBR     GRB
1778  */
1779 static unsigned int adv7604_op_ch_sel(struct adv7604_state *state)
1780 {
1781 #define _SEL(a,b,c,d,e,f)       { \
1782         ADV7604_OP_CH_SEL_##a, ADV7604_OP_CH_SEL_##b, ADV7604_OP_CH_SEL_##c, \
1783         ADV7604_OP_CH_SEL_##d, ADV7604_OP_CH_SEL_##e, ADV7604_OP_CH_SEL_##f }
1784 #define _BUS(x)                 [ADV7604_BUS_ORDER_##x]
1785
1786         static const unsigned int op_ch_sel[6][6] = {
1787                 _BUS(RGB) /* NOP */ = _SEL(GBR, GRB, BGR, RGB, BRG, RBG),
1788                 _BUS(GRB) /* 1-2 */ = _SEL(BGR, RGB, GBR, GRB, RBG, BRG),
1789                 _BUS(RBG) /* 2-3 */ = _SEL(GRB, GBR, BRG, RBG, BGR, RGB),
1790                 _BUS(BGR) /* 1-3 */ = _SEL(RBG, BRG, RGB, BGR, GRB, GBR),
1791                 _BUS(BRG) /* ROR */ = _SEL(BRG, RBG, GRB, GBR, RGB, BGR),
1792                 _BUS(GBR) /* ROL */ = _SEL(RGB, BGR, RBG, BRG, GBR, GRB),
1793         };
1794
1795         return op_ch_sel[state->pdata.bus_order][state->format->op_ch_sel >> 5];
1796 }
1797
1798 static void adv7604_setup_format(struct adv7604_state *state)
1799 {
1800         struct v4l2_subdev *sd = &state->sd;
1801
1802         io_write_clr_set(sd, 0x02, 0x02,
1803                         state->format->rgb_out ? ADV7604_RGB_OUT : 0);
1804         io_write(sd, 0x03, state->format->op_format_sel |
1805                  state->pdata.op_format_mode_sel);
1806         io_write_clr_set(sd, 0x04, 0xe0, adv7604_op_ch_sel(state));
1807         io_write_clr_set(sd, 0x05, 0x01,
1808                         state->format->swap_cb_cr ? ADV7604_OP_SWAP_CB_CR : 0);
1809 }
1810
1811 static int adv7604_get_format(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
1812                               struct v4l2_subdev_format *format)
1813 {
1814         struct adv7604_state *state = to_state(sd);
1815
1816         if (format->pad != state->source_pad)
1817                 return -EINVAL;
1818
1819         adv7604_fill_format(state, &format->format);
1820
1821         if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
1822                 struct v4l2_mbus_framefmt *fmt;
1823
1824                 fmt = v4l2_subdev_get_try_format(fh, format->pad);
1825                 format->format.code = fmt->code;
1826         } else {
1827                 format->format.code = state->format->code;
1828         }
1829
1830         return 0;
1831 }
1832
1833 static int adv7604_set_format(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
1834                               struct v4l2_subdev_format *format)
1835 {
1836         struct adv7604_state *state = to_state(sd);
1837         const struct adv7604_format_info *info;
1838
1839         if (format->pad != state->source_pad)
1840                 return -EINVAL;
1841
1842         info = adv7604_format_info(state, format->format.code);
1843         if (info == NULL)
1844                 info = adv7604_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8);
1845
1846         adv7604_fill_format(state, &format->format);
1847         format->format.code = info->code;
1848
1849         if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
1850                 struct v4l2_mbus_framefmt *fmt;
1851
1852                 fmt = v4l2_subdev_get_try_format(fh, format->pad);
1853                 fmt->code = format->format.code;
1854         } else {
1855                 state->format = info;
1856                 adv7604_setup_format(state);
1857         }
1858
1859         return 0;
1860 }
1861
1862 static int adv7604_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
1863 {
1864         struct adv7604_state *state = to_state(sd);
1865         const struct adv7604_chip_info *info = state->info;
1866         const u8 irq_reg_0x43 = io_read(sd, 0x43);
1867         const u8 irq_reg_0x6b = io_read(sd, 0x6b);
1868         const u8 irq_reg_0x70 = io_read(sd, 0x70);
1869         u8 fmt_change_digital;
1870         u8 fmt_change;
1871         u8 tx_5v;
1872
1873         if (irq_reg_0x43)
1874                 io_write(sd, 0x44, irq_reg_0x43);
1875         if (irq_reg_0x70)
1876                 io_write(sd, 0x71, irq_reg_0x70);
1877         if (irq_reg_0x6b)
1878                 io_write(sd, 0x6c, irq_reg_0x6b);
1879
1880         v4l2_dbg(2, debug, sd, "%s: ", __func__);
1881
1882         /* format change */
1883         fmt_change = irq_reg_0x43 & 0x98;
1884         fmt_change_digital = is_digital_input(sd)
1885                            ? irq_reg_0x6b & info->fmt_change_digital_mask
1886                            : 0;
1887
1888         if (fmt_change || fmt_change_digital) {
1889                 v4l2_dbg(1, debug, sd,
1890                         "%s: fmt_change = 0x%x, fmt_change_digital = 0x%x\n",
1891                         __func__, fmt_change, fmt_change_digital);
1892
1893                 v4l2_subdev_notify(sd, ADV7604_FMT_CHANGE, NULL);
1894
1895                 if (handled)
1896                         *handled = true;
1897         }
1898         /* HDMI/DVI mode */
1899         if (irq_reg_0x6b & 0x01) {
1900                 v4l2_dbg(1, debug, sd, "%s: irq %s mode\n", __func__,
1901                         (io_read(sd, 0x6a) & 0x01) ? "HDMI" : "DVI");
1902                 set_rgb_quantization_range(sd);
1903                 if (handled)
1904                         *handled = true;
1905         }
1906
1907         /* tx 5v detect */
1908         tx_5v = io_read(sd, 0x70) & info->cable_det_mask;
1909         if (tx_5v) {
1910                 v4l2_dbg(1, debug, sd, "%s: tx_5v: 0x%x\n", __func__, tx_5v);
1911                 io_write(sd, 0x71, tx_5v);
1912                 adv7604_s_detect_tx_5v_ctrl(sd);
1913                 if (handled)
1914                         *handled = true;
1915         }
1916         return 0;
1917 }
1918
1919 static int adv7604_get_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid)
1920 {
1921         struct adv7604_state *state = to_state(sd);
1922         u8 *data = NULL;
1923
1924         memset(edid->reserved, 0, sizeof(edid->reserved));
1925
1926         switch (edid->pad) {
1927         case ADV7604_PAD_HDMI_PORT_A:
1928         case ADV7604_PAD_HDMI_PORT_B:
1929         case ADV7604_PAD_HDMI_PORT_C:
1930         case ADV7604_PAD_HDMI_PORT_D:
1931                 if (state->edid.present & (1 << edid->pad))
1932                         data = state->edid.edid;
1933                 break;
1934         default:
1935                 return -EINVAL;
1936         }
1937
1938         if (edid->start_block == 0 && edid->blocks == 0) {
1939                 edid->blocks = data ? state->edid.blocks : 0;
1940                 return 0;
1941         }
1942
1943         if (data == NULL)
1944                 return -ENODATA;
1945
1946         if (edid->start_block >= state->edid.blocks)
1947                 return -EINVAL;
1948
1949         if (edid->start_block + edid->blocks > state->edid.blocks)
1950                 edid->blocks = state->edid.blocks - edid->start_block;
1951
1952         memcpy(edid->edid, data + edid->start_block * 128, edid->blocks * 128);
1953
1954         return 0;
1955 }
1956
1957 static int get_edid_spa_location(const u8 *edid)
1958 {
1959         u8 d;
1960
1961         if ((edid[0x7e] != 1) ||
1962             (edid[0x80] != 0x02) ||
1963             (edid[0x81] != 0x03)) {
1964                 return -1;
1965         }
1966
1967         /* search Vendor Specific Data Block (tag 3) */
1968         d = edid[0x82] & 0x7f;
1969         if (d > 4) {
1970                 int i = 0x84;
1971                 int end = 0x80 + d;
1972
1973                 do {
1974                         u8 tag = edid[i] >> 5;
1975                         u8 len = edid[i] & 0x1f;
1976
1977                         if ((tag == 3) && (len >= 5))
1978                                 return i + 4;
1979                         i += len + 1;
1980                 } while (i < end);
1981         }
1982         return -1;
1983 }
1984
1985 static int adv7604_set_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid)
1986 {
1987         struct adv7604_state *state = to_state(sd);
1988         const struct adv7604_chip_info *info = state->info;
1989         int spa_loc;
1990         int err;
1991         int i;
1992
1993         memset(edid->reserved, 0, sizeof(edid->reserved));
1994
1995         if (edid->pad > ADV7604_PAD_HDMI_PORT_D)
1996                 return -EINVAL;
1997         if (edid->start_block != 0)
1998                 return -EINVAL;
1999         if (edid->blocks == 0) {
2000                 /* Disable hotplug and I2C access to EDID RAM from DDC port */
2001                 state->edid.present &= ~(1 << edid->pad);
2002                 adv7604_set_hpd(state, state->edid.present);
2003                 rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, state->edid.present);
2004
2005                 /* Fall back to a 16:9 aspect ratio */
2006                 state->aspect_ratio.numerator = 16;
2007                 state->aspect_ratio.denominator = 9;
2008
2009                 if (!state->edid.present)
2010                         state->edid.blocks = 0;
2011
2012                 v4l2_dbg(2, debug, sd, "%s: clear EDID pad %d, edid.present = 0x%x\n",
2013                                 __func__, edid->pad, state->edid.present);
2014                 return 0;
2015         }
2016         if (edid->blocks > 2) {
2017                 edid->blocks = 2;
2018                 return -E2BIG;
2019         }
2020
2021         v4l2_dbg(2, debug, sd, "%s: write EDID pad %d, edid.present = 0x%x\n",
2022                         __func__, edid->pad, state->edid.present);
2023
2024         /* Disable hotplug and I2C access to EDID RAM from DDC port */
2025         cancel_delayed_work_sync(&state->delayed_work_enable_hotplug);
2026         adv7604_set_hpd(state, 0);
2027         rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, 0x00);
2028
2029         spa_loc = get_edid_spa_location(edid->edid);
2030         if (spa_loc < 0)
2031                 spa_loc = 0xc0; /* Default value [REF_02, p. 116] */
2032
2033         switch (edid->pad) {
2034         case ADV7604_PAD_HDMI_PORT_A:
2035                 state->spa_port_a[0] = edid->edid[spa_loc];
2036                 state->spa_port_a[1] = edid->edid[spa_loc + 1];
2037                 break;
2038         case ADV7604_PAD_HDMI_PORT_B:
2039                 rep_write(sd, 0x70, edid->edid[spa_loc]);
2040                 rep_write(sd, 0x71, edid->edid[spa_loc + 1]);
2041                 break;
2042         case ADV7604_PAD_HDMI_PORT_C:
2043                 rep_write(sd, 0x72, edid->edid[spa_loc]);
2044                 rep_write(sd, 0x73, edid->edid[spa_loc + 1]);
2045                 break;
2046         case ADV7604_PAD_HDMI_PORT_D:
2047                 rep_write(sd, 0x74, edid->edid[spa_loc]);
2048                 rep_write(sd, 0x75, edid->edid[spa_loc + 1]);
2049                 break;
2050         default:
2051                 return -EINVAL;
2052         }
2053
2054         if (info->type == ADV7604) {
2055                 rep_write(sd, 0x76, spa_loc & 0xff);
2056                 rep_write_clr_set(sd, 0x77, 0x40, (spa_loc & 0x100) >> 2);
2057         } else {
2058                 /* FIXME: Where is the SPA location LSB register ? */
2059                 rep_write_clr_set(sd, 0x71, 0x01, (spa_loc & 0x100) >> 8);
2060         }
2061
2062         edid->edid[spa_loc] = state->spa_port_a[0];
2063         edid->edid[spa_loc + 1] = state->spa_port_a[1];
2064
2065         memcpy(state->edid.edid, edid->edid, 128 * edid->blocks);
2066         state->edid.blocks = edid->blocks;
2067         state->aspect_ratio = v4l2_calc_aspect_ratio(edid->edid[0x15],
2068                         edid->edid[0x16]);
2069         state->edid.present |= 1 << edid->pad;
2070
2071         err = edid_write_block(sd, 128 * edid->blocks, state->edid.edid);
2072         if (err < 0) {
2073                 v4l2_err(sd, "error %d writing edid pad %d\n", err, edid->pad);
2074                 return err;
2075         }
2076
2077         /* adv7604 calculates the checksums and enables I2C access to internal
2078            EDID RAM from DDC port. */
2079         rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, state->edid.present);
2080
2081         for (i = 0; i < 1000; i++) {
2082                 if (rep_read(sd, info->edid_status_reg) & state->edid.present)
2083                         break;
2084                 mdelay(1);
2085         }
2086         if (i == 1000) {
2087                 v4l2_err(sd, "error enabling edid (0x%x)\n", state->edid.present);
2088                 return -EIO;
2089         }
2090
2091         /* enable hotplug after 100 ms */
2092         queue_delayed_work(state->work_queues,
2093                         &state->delayed_work_enable_hotplug, HZ / 10);
2094         return 0;
2095 }
2096
2097 /*********** avi info frame CEA-861-E **************/
2098
2099 static void print_avi_infoframe(struct v4l2_subdev *sd)
2100 {
2101         int i;
2102         u8 buf[14];
2103         u8 avi_len;
2104         u8 avi_ver;
2105
2106         if (!is_hdmi(sd)) {
2107                 v4l2_info(sd, "receive DVI-D signal (AVI infoframe not supported)\n");
2108                 return;
2109         }
2110         if (!(io_read(sd, 0x60) & 0x01)) {
2111                 v4l2_info(sd, "AVI infoframe not received\n");
2112                 return;
2113         }
2114
2115         if (io_read(sd, 0x83) & 0x01) {
2116                 v4l2_info(sd, "AVI infoframe checksum error has occurred earlier\n");
2117                 io_write(sd, 0x85, 0x01); /* clear AVI_INF_CKS_ERR_RAW */
2118                 if (io_read(sd, 0x83) & 0x01) {
2119                         v4l2_info(sd, "AVI infoframe checksum error still present\n");
2120                         io_write(sd, 0x85, 0x01); /* clear AVI_INF_CKS_ERR_RAW */
2121                 }
2122         }
2123
2124         avi_len = infoframe_read(sd, 0xe2);
2125         avi_ver = infoframe_read(sd, 0xe1);
2126         v4l2_info(sd, "AVI infoframe version %d (%d byte)\n",
2127                         avi_ver, avi_len);
2128
2129         if (avi_ver != 0x02)
2130                 return;
2131
2132         for (i = 0; i < 14; i++)
2133                 buf[i] = infoframe_read(sd, i);
2134
2135         v4l2_info(sd,
2136                 "\t%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
2137                 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], buf[7],
2138                 buf[8], buf[9], buf[10], buf[11], buf[12], buf[13]);
2139 }
2140
2141 static int adv7604_log_status(struct v4l2_subdev *sd)
2142 {
2143         struct adv7604_state *state = to_state(sd);
2144         const struct adv7604_chip_info *info = state->info;
2145         struct v4l2_dv_timings timings;
2146         struct stdi_readback stdi;
2147         u8 reg_io_0x02 = io_read(sd, 0x02);
2148         u8 edid_enabled;
2149         u8 cable_det;
2150
2151         static const char * const csc_coeff_sel_rb[16] = {
2152                 "bypassed", "YPbPr601 -> RGB", "reserved", "YPbPr709 -> RGB",
2153                 "reserved", "RGB -> YPbPr601", "reserved", "RGB -> YPbPr709",
2154                 "reserved", "YPbPr709 -> YPbPr601", "YPbPr601 -> YPbPr709",
2155                 "reserved", "reserved", "reserved", "reserved", "manual"
2156         };
2157         static const char * const input_color_space_txt[16] = {
2158                 "RGB limited range (16-235)", "RGB full range (0-255)",
2159                 "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)",
2160                 "xvYCC Bt.601", "xvYCC Bt.709",
2161                 "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)",
2162                 "invalid", "invalid", "invalid", "invalid", "invalid",
2163                 "invalid", "invalid", "automatic"
2164         };
2165         static const char * const rgb_quantization_range_txt[] = {
2166                 "Automatic",
2167                 "RGB limited range (16-235)",
2168                 "RGB full range (0-255)",
2169         };
2170         static const char * const deep_color_mode_txt[4] = {
2171                 "8-bits per channel",
2172                 "10-bits per channel",
2173                 "12-bits per channel",
2174                 "16-bits per channel (not supported)"
2175         };
2176
2177         v4l2_info(sd, "-----Chip status-----\n");
2178         v4l2_info(sd, "Chip power: %s\n", no_power(sd) ? "off" : "on");
2179         edid_enabled = rep_read(sd, info->edid_status_reg);
2180         v4l2_info(sd, "EDID enabled port A: %s, B: %s, C: %s, D: %s\n",
2181                         ((edid_enabled & 0x01) ? "Yes" : "No"),
2182                         ((edid_enabled & 0x02) ? "Yes" : "No"),
2183                         ((edid_enabled & 0x04) ? "Yes" : "No"),
2184                         ((edid_enabled & 0x08) ? "Yes" : "No"));
2185         v4l2_info(sd, "CEC: %s\n", !!(cec_read(sd, 0x2a) & 0x01) ?
2186                         "enabled" : "disabled");
2187
2188         v4l2_info(sd, "-----Signal status-----\n");
2189         cable_det = info->read_cable_det(sd);
2190         v4l2_info(sd, "Cable detected (+5V power) port A: %s, B: %s, C: %s, D: %s\n",
2191                         ((cable_det & 0x01) ? "Yes" : "No"),
2192                         ((cable_det & 0x02) ? "Yes" : "No"),
2193                         ((cable_det & 0x04) ? "Yes" : "No"),
2194                         ((cable_det & 0x08) ? "Yes" : "No"));
2195         v4l2_info(sd, "TMDS signal detected: %s\n",
2196                         no_signal_tmds(sd) ? "false" : "true");
2197         v4l2_info(sd, "TMDS signal locked: %s\n",
2198                         no_lock_tmds(sd) ? "false" : "true");
2199         v4l2_info(sd, "SSPD locked: %s\n", no_lock_sspd(sd) ? "false" : "true");
2200         v4l2_info(sd, "STDI locked: %s\n", no_lock_stdi(sd) ? "false" : "true");
2201         v4l2_info(sd, "CP locked: %s\n", no_lock_cp(sd) ? "false" : "true");
2202         v4l2_info(sd, "CP free run: %s\n",
2203                         (!!(cp_read(sd, 0xff) & 0x10) ? "on" : "off"));
2204         v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x, v_freq = 0x%x\n",
2205                         io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f,
2206                         (io_read(sd, 0x01) & 0x70) >> 4);
2207
2208         v4l2_info(sd, "-----Video Timings-----\n");
2209         if (read_stdi(sd, &stdi))
2210                 v4l2_info(sd, "STDI: not locked\n");
2211         else
2212                 v4l2_info(sd, "STDI: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %s, %chsync, %cvsync\n",
2213                                 stdi.lcf, stdi.bl, stdi.lcvs,
2214                                 stdi.interlaced ? "interlaced" : "progressive",
2215                                 stdi.hs_pol, stdi.vs_pol);
2216         if (adv7604_query_dv_timings(sd, &timings))
2217                 v4l2_info(sd, "No video detected\n");
2218         else
2219                 v4l2_print_dv_timings(sd->name, "Detected format: ",
2220                                       &timings, true);
2221         v4l2_print_dv_timings(sd->name, "Configured format: ",
2222                               &state->timings, true);
2223
2224         if (no_signal(sd))
2225                 return 0;
2226
2227         v4l2_info(sd, "-----Color space-----\n");
2228         v4l2_info(sd, "RGB quantization range ctrl: %s\n",
2229                         rgb_quantization_range_txt[state->rgb_quantization_range]);
2230         v4l2_info(sd, "Input color space: %s\n",
2231                         input_color_space_txt[reg_io_0x02 >> 4]);
2232         v4l2_info(sd, "Output color space: %s %s, saturator %s\n",
2233                         (reg_io_0x02 & 0x02) ? "RGB" : "YCbCr",
2234                         (reg_io_0x02 & 0x04) ? "(16-235)" : "(0-255)",
2235                         ((reg_io_0x02 & 0x04) ^ (reg_io_0x02 & 0x01)) ?
2236                                 "enabled" : "disabled");
2237         v4l2_info(sd, "Color space conversion: %s\n",
2238                         csc_coeff_sel_rb[cp_read(sd, 0xfc) >> 4]);
2239
2240         if (!is_digital_input(sd))
2241                 return 0;
2242
2243         v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D");
2244         v4l2_info(sd, "Digital video port selected: %c\n",
2245                         (hdmi_read(sd, 0x00) & 0x03) + 'A');
2246         v4l2_info(sd, "HDCP encrypted content: %s\n",
2247                         (hdmi_read(sd, 0x05) & 0x40) ? "true" : "false");
2248         v4l2_info(sd, "HDCP keys read: %s%s\n",
2249                         (hdmi_read(sd, 0x04) & 0x20) ? "yes" : "no",
2250                         (hdmi_read(sd, 0x04) & 0x10) ? "ERROR" : "");
2251         if (is_hdmi(sd)) {
2252                 bool audio_pll_locked = hdmi_read(sd, 0x04) & 0x01;
2253                 bool audio_sample_packet_detect = hdmi_read(sd, 0x18) & 0x01;
2254                 bool audio_mute = io_read(sd, 0x65) & 0x40;
2255
2256                 v4l2_info(sd, "Audio: pll %s, samples %s, %s\n",
2257                                 audio_pll_locked ? "locked" : "not locked",
2258                                 audio_sample_packet_detect ? "detected" : "not detected",
2259                                 audio_mute ? "muted" : "enabled");
2260                 if (audio_pll_locked && audio_sample_packet_detect) {
2261                         v4l2_info(sd, "Audio format: %s\n",
2262                                         (hdmi_read(sd, 0x07) & 0x20) ? "multi-channel" : "stereo");
2263                 }
2264                 v4l2_info(sd, "Audio CTS: %u\n", (hdmi_read(sd, 0x5b) << 12) +
2265                                 (hdmi_read(sd, 0x5c) << 8) +
2266                                 (hdmi_read(sd, 0x5d) & 0xf0));
2267                 v4l2_info(sd, "Audio N: %u\n", ((hdmi_read(sd, 0x5d) & 0x0f) << 16) +
2268                                 (hdmi_read(sd, 0x5e) << 8) +
2269                                 hdmi_read(sd, 0x5f));
2270                 v4l2_info(sd, "AV Mute: %s\n", (hdmi_read(sd, 0x04) & 0x40) ? "on" : "off");
2271
2272                 v4l2_info(sd, "Deep color mode: %s\n", deep_color_mode_txt[(hdmi_read(sd, 0x0b) & 0x60) >> 5]);
2273
2274                 print_avi_infoframe(sd);
2275         }
2276
2277         return 0;
2278 }
2279
2280 /* ----------------------------------------------------------------------- */
2281
2282 static const struct v4l2_ctrl_ops adv7604_ctrl_ops = {
2283         .s_ctrl = adv7604_s_ctrl,
2284 };
2285
2286 static const struct v4l2_subdev_core_ops adv7604_core_ops = {
2287         .log_status = adv7604_log_status,
2288         .interrupt_service_routine = adv7604_isr,
2289 #ifdef CONFIG_VIDEO_ADV_DEBUG
2290         .g_register = adv7604_g_register,
2291         .s_register = adv7604_s_register,
2292 #endif
2293 };
2294
2295 static const struct v4l2_subdev_video_ops adv7604_video_ops = {
2296         .s_routing = adv7604_s_routing,
2297         .g_input_status = adv7604_g_input_status,
2298         .s_dv_timings = adv7604_s_dv_timings,
2299         .g_dv_timings = adv7604_g_dv_timings,
2300         .query_dv_timings = adv7604_query_dv_timings,
2301 };
2302
2303 static const struct v4l2_subdev_pad_ops adv7604_pad_ops = {
2304         .enum_mbus_code = adv7604_enum_mbus_code,
2305         .get_fmt = adv7604_get_format,
2306         .set_fmt = adv7604_set_format,
2307         .get_edid = adv7604_get_edid,
2308         .set_edid = adv7604_set_edid,
2309         .dv_timings_cap = adv7604_dv_timings_cap,
2310         .enum_dv_timings = adv7604_enum_dv_timings,
2311 };
2312
2313 static const struct v4l2_subdev_ops adv7604_ops = {
2314         .core = &adv7604_core_ops,
2315         .video = &adv7604_video_ops,
2316         .pad = &adv7604_pad_ops,
2317 };
2318
2319 /* -------------------------- custom ctrls ---------------------------------- */
2320
2321 static const struct v4l2_ctrl_config adv7604_ctrl_analog_sampling_phase = {
2322         .ops = &adv7604_ctrl_ops,
2323         .id = V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE,
2324         .name = "Analog Sampling Phase",
2325         .type = V4L2_CTRL_TYPE_INTEGER,
2326         .min = 0,
2327         .max = 0x1f,
2328         .step = 1,
2329         .def = 0,
2330 };
2331
2332 static const struct v4l2_ctrl_config adv7604_ctrl_free_run_color_manual = {
2333         .ops = &adv7604_ctrl_ops,
2334         .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL,
2335         .name = "Free Running Color, Manual",
2336         .type = V4L2_CTRL_TYPE_BOOLEAN,
2337         .min = false,
2338         .max = true,
2339         .step = 1,
2340         .def = false,
2341 };
2342
2343 static const struct v4l2_ctrl_config adv7604_ctrl_free_run_color = {
2344         .ops = &adv7604_ctrl_ops,
2345         .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR,
2346         .name = "Free Running Color",
2347         .type = V4L2_CTRL_TYPE_INTEGER,
2348         .min = 0x0,
2349         .max = 0xffffff,
2350         .step = 0x1,
2351         .def = 0x0,
2352 };
2353
2354 /* ----------------------------------------------------------------------- */
2355
2356 static int adv7604_core_init(struct v4l2_subdev *sd)
2357 {
2358         struct adv7604_state *state = to_state(sd);
2359         const struct adv7604_chip_info *info = state->info;
2360         struct adv7604_platform_data *pdata = &state->pdata;
2361
2362         hdmi_write(sd, 0x48,
2363                 (pdata->disable_pwrdnb ? 0x80 : 0) |
2364                 (pdata->disable_cable_det_rst ? 0x40 : 0));
2365
2366         disable_input(sd);
2367
2368         if (pdata->default_input >= 0 &&
2369             pdata->default_input < state->source_pad) {
2370                 state->selected_input = pdata->default_input;
2371                 select_input(sd);
2372                 enable_input(sd);
2373         }
2374
2375         /* power */
2376         io_write(sd, 0x0c, 0x42);   /* Power up part and power down VDP */
2377         io_write(sd, 0x0b, 0x44);   /* Power down ESDP block */
2378         cp_write(sd, 0xcf, 0x01);   /* Power down macrovision */
2379
2380         /* video format */
2381         io_write_clr_set(sd, 0x02, 0x0f,
2382                         pdata->alt_gamma << 3 |
2383                         pdata->op_656_range << 2 |
2384                         pdata->alt_data_sat << 0);
2385         io_write_clr_set(sd, 0x05, 0x0e, pdata->blank_data << 3 |
2386                         pdata->insert_av_codes << 2 |
2387                         pdata->replicate_av_codes << 1);
2388         adv7604_setup_format(state);
2389
2390         cp_write(sd, 0x69, 0x30);   /* Enable CP CSC */
2391
2392         /* VS, HS polarities */
2393         io_write(sd, 0x06, 0xa0 | pdata->inv_vs_pol << 2 |
2394                  pdata->inv_hs_pol << 1 | pdata->inv_llc_pol);
2395
2396         /* Adjust drive strength */
2397         io_write(sd, 0x14, 0x40 | pdata->dr_str_data << 4 |
2398                                 pdata->dr_str_clk << 2 |
2399                                 pdata->dr_str_sync);
2400
2401         cp_write(sd, 0xba, (pdata->hdmi_free_run_mode << 1) | 0x01); /* HDMI free run */
2402         cp_write(sd, 0xf3, 0xdc); /* Low threshold to enter/exit free run mode */
2403         cp_write(sd, 0xf9, 0x23); /*  STDI ch. 1 - LCVS change threshold -
2404                                       ADI recommended setting [REF_01, c. 2.3.3] */
2405         cp_write(sd, 0x45, 0x23); /*  STDI ch. 2 - LCVS change threshold -
2406                                       ADI recommended setting [REF_01, c. 2.3.3] */
2407         cp_write(sd, 0xc9, 0x2d); /* use prim_mode and vid_std as free run resolution
2408                                      for digital formats */
2409
2410         /* HDMI audio */
2411         hdmi_write_clr_set(sd, 0x15, 0x03, 0x03); /* Mute on FIFO over-/underflow [REF_01, c. 1.2.18] */
2412         hdmi_write_clr_set(sd, 0x1a, 0x0e, 0x08); /* Wait 1 s before unmute */
2413         hdmi_write_clr_set(sd, 0x68, 0x06, 0x06); /* FIFO reset on over-/underflow [REF_01, c. 1.2.19] */
2414
2415         /* TODO from platform data */
2416         afe_write(sd, 0xb5, 0x01);  /* Setting MCLK to 256Fs */
2417
2418         if (adv7604_has_afe(state)) {
2419                 afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */
2420                 io_write_clr_set(sd, 0x30, 1 << 4, pdata->output_bus_lsb_to_msb << 4);
2421         }
2422
2423         /* interrupts */
2424         io_write(sd, 0x40, 0xc0 | pdata->int1_config); /* Configure INT1 */
2425         io_write(sd, 0x46, 0x98); /* Enable SSPD, STDI and CP unlocked interrupts */
2426         io_write(sd, 0x6e, info->fmt_change_digital_mask); /* Enable V_LOCKED and DE_REGEN_LCK interrupts */
2427         io_write(sd, 0x73, info->cable_det_mask); /* Enable cable detection (+5v) interrupts */
2428         info->setup_irqs(sd);
2429
2430         return v4l2_ctrl_handler_setup(sd->ctrl_handler);
2431 }
2432
2433 static void adv7604_setup_irqs(struct v4l2_subdev *sd)
2434 {
2435         io_write(sd, 0x41, 0xd7); /* STDI irq for any change, disable INT2 */
2436 }
2437
2438 static void adv7611_setup_irqs(struct v4l2_subdev *sd)
2439 {
2440         io_write(sd, 0x41, 0xd0); /* STDI irq for any change, disable INT2 */
2441 }
2442
2443 static void adv7604_unregister_clients(struct adv7604_state *state)
2444 {
2445         unsigned int i;
2446
2447         for (i = 1; i < ARRAY_SIZE(state->i2c_clients); ++i) {
2448                 if (state->i2c_clients[i])
2449                         i2c_unregister_device(state->i2c_clients[i]);
2450         }
2451 }
2452
2453 static struct i2c_client *adv7604_dummy_client(struct v4l2_subdev *sd,
2454                                                         u8 addr, u8 io_reg)
2455 {
2456         struct i2c_client *client = v4l2_get_subdevdata(sd);
2457
2458         if (addr)
2459                 io_write(sd, io_reg, addr << 1);
2460         return i2c_new_dummy(client->adapter, io_read(sd, io_reg) >> 1);
2461 }
2462
2463 static const struct adv7604_reg_seq adv7604_recommended_settings_afe[] = {
2464         /* reset ADI recommended settings for HDMI: */
2465         /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */
2466         { ADV7604_REG(ADV7604_PAGE_HDMI, 0x0d), 0x04 }, /* HDMI filter optimization */
2467         { ADV7604_REG(ADV7604_PAGE_HDMI, 0x0d), 0x04 }, /* HDMI filter optimization */
2468         { ADV7604_REG(ADV7604_PAGE_HDMI, 0x3d), 0x00 }, /* DDC bus active pull-up control */
2469         { ADV7604_REG(ADV7604_PAGE_HDMI, 0x3e), 0x74 }, /* TMDS PLL optimization */
2470         { ADV7604_REG(ADV7604_PAGE_HDMI, 0x4e), 0x3b }, /* TMDS PLL optimization */
2471         { ADV7604_REG(ADV7604_PAGE_HDMI, 0x57), 0x74 }, /* TMDS PLL optimization */
2472         { ADV7604_REG(ADV7604_PAGE_HDMI, 0x58), 0x63 }, /* TMDS PLL optimization */
2473         { ADV7604_REG(ADV7604_PAGE_HDMI, 0x8d), 0x18 }, /* equaliser */
2474         { ADV7604_REG(ADV7604_PAGE_HDMI, 0x8e), 0x34 }, /* equaliser */
2475         { ADV7604_REG(ADV7604_PAGE_HDMI, 0x93), 0x88 }, /* equaliser */
2476         { ADV7604_REG(ADV7604_PAGE_HDMI, 0x94), 0x2e }, /* equaliser */
2477         { ADV7604_REG(ADV7604_PAGE_HDMI, 0x96), 0x00 }, /* enable automatic EQ changing */
2478
2479         /* set ADI recommended settings for digitizer */
2480         /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */
2481         { ADV7604_REG(ADV7604_PAGE_AFE, 0x12), 0x7b }, /* ADC noise shaping filter controls */
2482         { ADV7604_REG(ADV7604_PAGE_AFE, 0x0c), 0x1f }, /* CP core gain controls */
2483         { ADV7604_REG(ADV7604_PAGE_CP, 0x3e), 0x04 }, /* CP core pre-gain control */
2484         { ADV7604_REG(ADV7604_PAGE_CP, 0xc3), 0x39 }, /* CP coast control. Graphics mode */
2485         { ADV7604_REG(ADV7604_PAGE_CP, 0x40), 0x5c }, /* CP core pre-gain control. Graphics mode */
2486
2487         { ADV7604_REG_SEQ_TERM, 0 },
2488 };
2489
2490 static const struct adv7604_reg_seq adv7604_recommended_settings_hdmi[] = {
2491         /* set ADI recommended settings for HDMI: */
2492         /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */
2493         { ADV7604_REG(ADV7604_PAGE_HDMI, 0x0d), 0x84 }, /* HDMI filter optimization */
2494         { ADV7604_REG(ADV7604_PAGE_HDMI, 0x3d), 0x10 }, /* DDC bus active pull-up control */
2495         { ADV7604_REG(ADV7604_PAGE_HDMI, 0x3e), 0x39 }, /* TMDS PLL optimization */
2496         { ADV7604_REG(ADV7604_PAGE_HDMI, 0x4e), 0x3b }, /* TMDS PLL optimization */
2497         { ADV7604_REG(ADV7604_PAGE_HDMI, 0x57), 0xb6 }, /* TMDS PLL optimization */
2498         { ADV7604_REG(ADV7604_PAGE_HDMI, 0x58), 0x03 }, /* TMDS PLL optimization */
2499         { ADV7604_REG(ADV7604_PAGE_HDMI, 0x8d), 0x18 }, /* equaliser */
2500         { ADV7604_REG(ADV7604_PAGE_HDMI, 0x8e), 0x34 }, /* equaliser */
2501         { ADV7604_REG(ADV7604_PAGE_HDMI, 0x93), 0x8b }, /* equaliser */
2502         { ADV7604_REG(ADV7604_PAGE_HDMI, 0x94), 0x2d }, /* equaliser */
2503         { ADV7604_REG(ADV7604_PAGE_HDMI, 0x96), 0x01 }, /* enable automatic EQ changing */
2504
2505         /* reset ADI recommended settings for digitizer */
2506         /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */
2507         { ADV7604_REG(ADV7604_PAGE_AFE, 0x12), 0xfb }, /* ADC noise shaping filter controls */
2508         { ADV7604_REG(ADV7604_PAGE_AFE, 0x0c), 0x0d }, /* CP core gain controls */
2509
2510         { ADV7604_REG_SEQ_TERM, 0 },
2511 };
2512
2513 static const struct adv7604_reg_seq adv7611_recommended_settings_hdmi[] = {
2514         /* ADV7611 Register Settings Recommendations Rev 1.5, May 2014 */
2515         { ADV7604_REG(ADV7604_PAGE_CP, 0x6c), 0x00 },
2516         { ADV7604_REG(ADV7604_PAGE_HDMI, 0x9b), 0x03 },
2517         { ADV7604_REG(ADV7604_PAGE_HDMI, 0x6f), 0x08 },
2518         { ADV7604_REG(ADV7604_PAGE_HDMI, 0x85), 0x1f },
2519         { ADV7604_REG(ADV7604_PAGE_HDMI, 0x87), 0x70 },
2520         { ADV7604_REG(ADV7604_PAGE_HDMI, 0x57), 0xda },
2521         { ADV7604_REG(ADV7604_PAGE_HDMI, 0x58), 0x01 },
2522         { ADV7604_REG(ADV7604_PAGE_HDMI, 0x03), 0x98 },
2523         { ADV7604_REG(ADV7604_PAGE_HDMI, 0x4c), 0x44 },
2524         { ADV7604_REG(ADV7604_PAGE_HDMI, 0x8d), 0x04 },
2525         { ADV7604_REG(ADV7604_PAGE_HDMI, 0x8e), 0x1e },
2526
2527         { ADV7604_REG_SEQ_TERM, 0 },
2528 };
2529
2530 static const struct adv7604_chip_info adv7604_chip_info[] = {
2531         [ADV7604] = {
2532                 .type = ADV7604,
2533                 .has_afe = true,
2534                 .max_port = ADV7604_PAD_VGA_COMP,
2535                 .num_dv_ports = 4,
2536                 .edid_enable_reg = 0x77,
2537                 .edid_status_reg = 0x7d,
2538                 .lcf_reg = 0xb3,
2539                 .tdms_lock_mask = 0xe0,
2540                 .cable_det_mask = 0x1e,
2541                 .fmt_change_digital_mask = 0xc1,
2542                 .formats = adv7604_formats,
2543                 .nformats = ARRAY_SIZE(adv7604_formats),
2544                 .set_termination = adv7604_set_termination,
2545                 .setup_irqs = adv7604_setup_irqs,
2546                 .read_hdmi_pixelclock = adv7604_read_hdmi_pixelclock,
2547                 .read_cable_det = adv7604_read_cable_det,
2548                 .recommended_settings = {
2549                     [0] = adv7604_recommended_settings_afe,
2550                     [1] = adv7604_recommended_settings_hdmi,
2551                 },
2552                 .num_recommended_settings = {
2553                     [0] = ARRAY_SIZE(adv7604_recommended_settings_afe),
2554                     [1] = ARRAY_SIZE(adv7604_recommended_settings_hdmi),
2555                 },
2556                 .page_mask = BIT(ADV7604_PAGE_IO) | BIT(ADV7604_PAGE_AVLINK) |
2557                         BIT(ADV7604_PAGE_CEC) | BIT(ADV7604_PAGE_INFOFRAME) |
2558                         BIT(ADV7604_PAGE_ESDP) | BIT(ADV7604_PAGE_DPP) |
2559                         BIT(ADV7604_PAGE_AFE) | BIT(ADV7604_PAGE_REP) |
2560                         BIT(ADV7604_PAGE_EDID) | BIT(ADV7604_PAGE_HDMI) |
2561                         BIT(ADV7604_PAGE_TEST) | BIT(ADV7604_PAGE_CP) |
2562                         BIT(ADV7604_PAGE_VDP),
2563         },
2564         [ADV7611] = {
2565                 .type = ADV7611,
2566                 .has_afe = false,
2567                 .max_port = ADV7604_PAD_HDMI_PORT_A,
2568                 .num_dv_ports = 1,
2569                 .edid_enable_reg = 0x74,
2570                 .edid_status_reg = 0x76,
2571                 .lcf_reg = 0xa3,
2572                 .tdms_lock_mask = 0x43,
2573                 .cable_det_mask = 0x01,
2574                 .fmt_change_digital_mask = 0x03,
2575                 .formats = adv7611_formats,
2576                 .nformats = ARRAY_SIZE(adv7611_formats),
2577                 .set_termination = adv7611_set_termination,
2578                 .setup_irqs = adv7611_setup_irqs,
2579                 .read_hdmi_pixelclock = adv7611_read_hdmi_pixelclock,
2580                 .read_cable_det = adv7611_read_cable_det,
2581                 .recommended_settings = {
2582                     [1] = adv7611_recommended_settings_hdmi,
2583                 },
2584                 .num_recommended_settings = {
2585                     [1] = ARRAY_SIZE(adv7611_recommended_settings_hdmi),
2586                 },
2587                 .page_mask = BIT(ADV7604_PAGE_IO) | BIT(ADV7604_PAGE_CEC) |
2588                         BIT(ADV7604_PAGE_INFOFRAME) | BIT(ADV7604_PAGE_AFE) |
2589                         BIT(ADV7604_PAGE_REP) |  BIT(ADV7604_PAGE_EDID) |
2590                         BIT(ADV7604_PAGE_HDMI) | BIT(ADV7604_PAGE_CP),
2591         },
2592 };
2593
2594 static struct i2c_device_id adv7604_i2c_id[] = {
2595         { "adv7604", (kernel_ulong_t)&adv7604_chip_info[ADV7604] },
2596         { "adv7611", (kernel_ulong_t)&adv7604_chip_info[ADV7611] },
2597         { }
2598 };
2599 MODULE_DEVICE_TABLE(i2c, adv7604_i2c_id);
2600
2601 static struct of_device_id adv7604_of_id[] __maybe_unused = {
2602         { .compatible = "adi,adv7611", .data = &adv7604_chip_info[ADV7611] },
2603         { }
2604 };
2605 MODULE_DEVICE_TABLE(of, adv7604_of_id);
2606
2607 static int adv7604_parse_dt(struct adv7604_state *state)
2608 {
2609         struct v4l2_of_endpoint bus_cfg;
2610         struct device_node *endpoint;
2611         struct device_node *np;
2612         unsigned int flags;
2613
2614         np = state->i2c_clients[ADV7604_PAGE_IO]->dev.of_node;
2615
2616         /* Parse the endpoint. */
2617         endpoint = of_graph_get_next_endpoint(np, NULL);
2618         if (!endpoint)
2619                 return -EINVAL;
2620
2621         v4l2_of_parse_endpoint(endpoint, &bus_cfg);
2622         of_node_put(endpoint);
2623
2624         flags = bus_cfg.bus.parallel.flags;
2625
2626         if (flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH)
2627                 state->pdata.inv_hs_pol = 1;
2628
2629         if (flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH)
2630                 state->pdata.inv_vs_pol = 1;
2631
2632         if (flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
2633                 state->pdata.inv_llc_pol = 1;
2634
2635         if (bus_cfg.bus_type == V4L2_MBUS_BT656) {
2636                 state->pdata.insert_av_codes = 1;
2637                 state->pdata.op_656_range = 1;
2638         }
2639
2640         /* Disable the interrupt for now as no DT-based board uses it. */
2641         state->pdata.int1_config = ADV7604_INT1_CONFIG_DISABLED;
2642
2643         /* Use the default I2C addresses. */
2644         state->pdata.i2c_addresses[ADV7604_PAGE_AVLINK] = 0x42;
2645         state->pdata.i2c_addresses[ADV7604_PAGE_CEC] = 0x40;
2646         state->pdata.i2c_addresses[ADV7604_PAGE_INFOFRAME] = 0x3e;
2647         state->pdata.i2c_addresses[ADV7604_PAGE_ESDP] = 0x38;
2648         state->pdata.i2c_addresses[ADV7604_PAGE_DPP] = 0x3c;
2649         state->pdata.i2c_addresses[ADV7604_PAGE_AFE] = 0x26;
2650         state->pdata.i2c_addresses[ADV7604_PAGE_REP] = 0x32;
2651         state->pdata.i2c_addresses[ADV7604_PAGE_EDID] = 0x36;
2652         state->pdata.i2c_addresses[ADV7604_PAGE_HDMI] = 0x34;
2653         state->pdata.i2c_addresses[ADV7604_PAGE_TEST] = 0x30;
2654         state->pdata.i2c_addresses[ADV7604_PAGE_CP] = 0x22;
2655         state->pdata.i2c_addresses[ADV7604_PAGE_VDP] = 0x24;
2656
2657         /* Hardcode the remaining platform data fields. */
2658         state->pdata.disable_pwrdnb = 0;
2659         state->pdata.disable_cable_det_rst = 0;
2660         state->pdata.default_input = -1;
2661         state->pdata.blank_data = 1;
2662         state->pdata.alt_data_sat = 1;
2663         state->pdata.op_format_mode_sel = ADV7604_OP_FORMAT_MODE0;
2664         state->pdata.bus_order = ADV7604_BUS_ORDER_RGB;
2665
2666         return 0;
2667 }
2668
2669 static int adv7604_probe(struct i2c_client *client,
2670                          const struct i2c_device_id *id)
2671 {
2672         static const struct v4l2_dv_timings cea640x480 =
2673                 V4L2_DV_BT_CEA_640X480P59_94;
2674         struct adv7604_state *state;
2675         struct v4l2_ctrl_handler *hdl;
2676         struct v4l2_subdev *sd;
2677         unsigned int i;
2678         u16 val;
2679         int err;
2680
2681         /* Check if the adapter supports the needed features */
2682         if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
2683                 return -EIO;
2684         v4l_dbg(1, debug, client, "detecting adv7604 client on address 0x%x\n",
2685                         client->addr << 1);
2686
2687         state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL);
2688         if (!state) {
2689                 v4l_err(client, "Could not allocate adv7604_state memory!\n");
2690                 return -ENOMEM;
2691         }
2692
2693         state->i2c_clients[ADV7604_PAGE_IO] = client;
2694
2695         /* initialize variables */
2696         state->restart_stdi_once = true;
2697         state->selected_input = ~0;
2698
2699         if (IS_ENABLED(CONFIG_OF) && client->dev.of_node) {
2700                 const struct of_device_id *oid;
2701
2702                 oid = of_match_node(adv7604_of_id, client->dev.of_node);
2703                 state->info = oid->data;
2704
2705                 err = adv7604_parse_dt(state);
2706                 if (err < 0) {
2707                         v4l_err(client, "DT parsing error\n");
2708                         return err;
2709                 }
2710         } else if (client->dev.platform_data) {
2711                 struct adv7604_platform_data *pdata = client->dev.platform_data;
2712
2713                 state->info = (const struct adv7604_chip_info *)id->driver_data;
2714                 state->pdata = *pdata;
2715         } else {
2716                 v4l_err(client, "No platform data!\n");
2717                 return -ENODEV;
2718         }
2719
2720         /* Request GPIOs. */
2721         for (i = 0; i < state->info->num_dv_ports; ++i) {
2722                 state->hpd_gpio[i] =
2723                         devm_gpiod_get_index(&client->dev, "hpd", i);
2724                 if (IS_ERR(state->hpd_gpio[i]))
2725                         continue;
2726
2727                 gpiod_direction_output(state->hpd_gpio[i], 0);
2728
2729                 v4l_info(client, "Handling HPD %u GPIO\n", i);
2730         }
2731
2732         state->timings = cea640x480;
2733         state->format = adv7604_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8);
2734
2735         sd = &state->sd;
2736         v4l2_i2c_subdev_init(sd, client, &adv7604_ops);
2737         snprintf(sd->name, sizeof(sd->name), "%s %d-%04x",
2738                 id->name, i2c_adapter_id(client->adapter),
2739                 client->addr);
2740         sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
2741
2742         /*
2743          * Verify that the chip is present. On ADV7604 the RD_INFO register only
2744          * identifies the revision, while on ADV7611 it identifies the model as
2745          * well. Use the HDMI slave address on ADV7604 and RD_INFO on ADV7611.
2746          */
2747         if (state->info->type == ADV7604) {
2748                 val = adv_smbus_read_byte_data_check(client, 0xfb, false);
2749                 if (val != 0x68) {
2750                         v4l2_info(sd, "not an adv7604 on address 0x%x\n",
2751                                         client->addr << 1);
2752                         return -ENODEV;
2753                 }
2754         } else {
2755                 val = (adv_smbus_read_byte_data_check(client, 0xea, false) << 8)
2756                     | (adv_smbus_read_byte_data_check(client, 0xeb, false) << 0);
2757                 if (val != 0x2051) {
2758                         v4l2_info(sd, "not an adv7611 on address 0x%x\n",
2759                                         client->addr << 1);
2760                         return -ENODEV;
2761                 }
2762         }
2763
2764         /* control handlers */
2765         hdl = &state->hdl;
2766         v4l2_ctrl_handler_init(hdl, adv7604_has_afe(state) ? 9 : 8);
2767
2768         v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops,
2769                         V4L2_CID_BRIGHTNESS, -128, 127, 1, 0);
2770         v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops,
2771                         V4L2_CID_CONTRAST, 0, 255, 1, 128);
2772         v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops,
2773                         V4L2_CID_SATURATION, 0, 255, 1, 128);
2774         v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops,
2775                         V4L2_CID_HUE, 0, 128, 1, 0);
2776
2777         /* private controls */
2778         state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl, NULL,
2779                         V4L2_CID_DV_RX_POWER_PRESENT, 0,
2780                         (1 << state->info->num_dv_ports) - 1, 0, 0);
2781         state->rgb_quantization_range_ctrl =
2782                 v4l2_ctrl_new_std_menu(hdl, &adv7604_ctrl_ops,
2783                         V4L2_CID_DV_RX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL,
2784                         0, V4L2_DV_RGB_RANGE_AUTO);
2785
2786         /* custom controls */
2787         if (adv7604_has_afe(state))
2788                 state->analog_sampling_phase_ctrl =
2789                         v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_analog_sampling_phase, NULL);
2790         state->free_run_color_manual_ctrl =
2791                 v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_free_run_color_manual, NULL);
2792         state->free_run_color_ctrl =
2793                 v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_free_run_color, NULL);
2794
2795         sd->ctrl_handler = hdl;
2796         if (hdl->error) {
2797                 err = hdl->error;
2798                 goto err_hdl;
2799         }
2800         state->detect_tx_5v_ctrl->is_private = true;
2801         state->rgb_quantization_range_ctrl->is_private = true;
2802         if (adv7604_has_afe(state))
2803                 state->analog_sampling_phase_ctrl->is_private = true;
2804         state->free_run_color_manual_ctrl->is_private = true;
2805         state->free_run_color_ctrl->is_private = true;
2806
2807         if (adv7604_s_detect_tx_5v_ctrl(sd)) {
2808                 err = -ENODEV;
2809                 goto err_hdl;
2810         }
2811
2812         for (i = 1; i < ADV7604_PAGE_MAX; ++i) {
2813                 if (!(BIT(i) & state->info->page_mask))
2814                         continue;
2815
2816                 state->i2c_clients[i] =
2817                         adv7604_dummy_client(sd, state->pdata.i2c_addresses[i],
2818                                              0xf2 + i);
2819                 if (state->i2c_clients[i] == NULL) {
2820                         err = -ENOMEM;
2821                         v4l2_err(sd, "failed to create i2c client %u\n", i);
2822                         goto err_i2c;
2823                 }
2824         }
2825
2826         /* work queues */
2827         state->work_queues = create_singlethread_workqueue(client->name);
2828         if (!state->work_queues) {
2829                 v4l2_err(sd, "Could not create work queue\n");
2830                 err = -ENOMEM;
2831                 goto err_i2c;
2832         }
2833
2834         INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug,
2835                         adv7604_delayed_work_enable_hotplug);
2836
2837         state->source_pad = state->info->num_dv_ports
2838                           + (state->info->has_afe ? 2 : 0);
2839         for (i = 0; i < state->source_pad; ++i)
2840                 state->pads[i].flags = MEDIA_PAD_FL_SINK;
2841         state->pads[state->source_pad].flags = MEDIA_PAD_FL_SOURCE;
2842
2843         err = media_entity_init(&sd->entity, state->source_pad + 1,
2844                                 state->pads, 0);
2845         if (err)
2846                 goto err_work_queues;
2847
2848         err = adv7604_core_init(sd);
2849         if (err)
2850                 goto err_entity;
2851         v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
2852                         client->addr << 1, client->adapter->name);
2853
2854         err = v4l2_async_register_subdev(sd);
2855         if (err)
2856                 goto err_entity;
2857
2858         return 0;
2859
2860 err_entity:
2861         media_entity_cleanup(&sd->entity);
2862 err_work_queues:
2863         cancel_delayed_work(&state->delayed_work_enable_hotplug);
2864         destroy_workqueue(state->work_queues);
2865 err_i2c:
2866         adv7604_unregister_clients(state);
2867 err_hdl:
2868         v4l2_ctrl_handler_free(hdl);
2869         return err;
2870 }
2871
2872 /* ----------------------------------------------------------------------- */
2873
2874 static int adv7604_remove(struct i2c_client *client)
2875 {
2876         struct v4l2_subdev *sd = i2c_get_clientdata(client);
2877         struct adv7604_state *state = to_state(sd);
2878
2879         cancel_delayed_work(&state->delayed_work_enable_hotplug);
2880         destroy_workqueue(state->work_queues);
2881         v4l2_async_unregister_subdev(sd);
2882         v4l2_device_unregister_subdev(sd);
2883         media_entity_cleanup(&sd->entity);
2884         adv7604_unregister_clients(to_state(sd));
2885         v4l2_ctrl_handler_free(sd->ctrl_handler);
2886         return 0;
2887 }
2888
2889 /* ----------------------------------------------------------------------- */
2890
2891 static struct i2c_driver adv7604_driver = {
2892         .driver = {
2893                 .owner = THIS_MODULE,
2894                 .name = "adv7604",
2895                 .of_match_table = of_match_ptr(adv7604_of_id),
2896         },
2897         .probe = adv7604_probe,
2898         .remove = adv7604_remove,
2899         .id_table = adv7604_i2c_id,
2900 };
2901
2902 module_i2c_driver(adv7604_driver);