2 * OKI Semiconductor ML86V7667 video decoder driver
4 * Author: Vladimir Barinov <source@cogentembedded.com>
5 * Copyright (C) 2013 Cogent Embedded, Inc.
6 * Copyright (C) 2013 Renesas Solutions Corp.
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
14 #include <linux/init.h>
15 #include <linux/module.h>
16 #include <linux/i2c.h>
17 #include <linux/slab.h>
18 #include <linux/videodev2.h>
19 #include <media/v4l2-subdev.h>
20 #include <media/v4l2-device.h>
21 #include <media/v4l2-ioctl.h>
22 #include <media/v4l2-ctrls.h>
24 #define DRV_NAME "ml86v7667"
27 #define MRA_REG 0x00 /* Mode Register A */
28 #define MRC_REG 0x02 /* Mode Register C */
29 #define LUMC_REG 0x0C /* Luminance Control */
30 #define CLC_REG 0x10 /* Contrast level control */
31 #define SSEPL_REG 0x11 /* Sync separation level */
32 #define CHRCA_REG 0x12 /* Chrominance Control A */
33 #define ACCC_REG 0x14 /* ACC Loop filter & Chrominance control */
34 #define ACCRC_REG 0x15 /* ACC Reference level control */
35 #define HUE_REG 0x16 /* Hue control */
36 #define ADC2_REG 0x1F /* ADC Register 2 */
37 #define PLLR1_REG 0x20 /* PLL Register 1 */
38 #define STATUS_REG 0x2C /* STATUS Register */
40 /* Mode Register A register bits */
41 #define MRA_OUTPUT_MODE_MASK (3 << 6)
42 #define MRA_ITUR_BT601 (1 << 6)
43 #define MRA_ITUR_BT656 (0 << 6)
44 #define MRA_INPUT_MODE_MASK (7 << 3)
45 #define MRA_PAL_BT601 (4 << 3)
46 #define MRA_NTSC_BT601 (0 << 3)
47 #define MRA_REGISTER_MODE (1 << 0)
49 /* Mode Register C register bits */
50 #define MRC_AUTOSELECT (1 << 7)
52 /* Luminance Control register bits */
53 #define LUMC_ONOFF_SHIFT 7
54 #define LUMC_ONOFF_MASK (1 << 7)
56 /* Contrast level control register bits */
57 #define CLC_CONTRAST_ONOFF (1 << 7)
58 #define CLC_CONTRAST_MASK 0x0F
60 /* Sync separation level register bits */
61 #define SSEPL_LUMINANCE_ONOFF (1 << 7)
62 #define SSEPL_LUMINANCE_MASK 0x7F
64 /* Chrominance Control A register bits */
65 #define CHRCA_MODE_SHIFT 6
66 #define CHRCA_MODE_MASK (1 << 6)
68 /* ACC Loop filter & Chrominance control register bits */
69 #define ACCC_CHROMA_CR_SHIFT 3
70 #define ACCC_CHROMA_CR_MASK (7 << 3)
71 #define ACCC_CHROMA_CB_SHIFT 0
72 #define ACCC_CHROMA_CB_MASK (7 << 0)
74 /* ACC Reference level control register bits */
75 #define ACCRC_CHROMA_MASK 0xfc
76 #define ACCRC_CHROMA_SHIFT 2
78 /* ADC Register 2 register bits */
79 #define ADC2_CLAMP_VOLTAGE_MASK (7 << 1)
80 #define ADC2_CLAMP_VOLTAGE(n) ((n & 7) << 1)
82 /* PLL Register 1 register bits */
83 #define PLLR1_FIXED_CLOCK (1 << 7)
85 /* STATUS Register register bits */
86 #define STATUS_HLOCK_DETECT (1 << 3)
87 #define STATUS_NTSCPAL (1 << 2)
89 struct ml86v7667_priv {
90 struct v4l2_subdev sd;
91 struct v4l2_ctrl_handler hdl;
95 static inline struct ml86v7667_priv *to_ml86v7667(struct v4l2_subdev *subdev)
97 return container_of(subdev, struct ml86v7667_priv, sd);
100 static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
102 return &container_of(ctrl->handler, struct ml86v7667_priv, hdl)->sd;
105 static int ml86v7667_mask_set(struct i2c_client *client, const u8 reg,
106 const u8 mask, const u8 data)
108 int val = i2c_smbus_read_byte_data(client, reg);
112 val = (val & ~mask) | (data & mask);
113 return i2c_smbus_write_byte_data(client, reg, val);
116 static int ml86v7667_s_ctrl(struct v4l2_ctrl *ctrl)
118 struct v4l2_subdev *sd = to_sd(ctrl);
119 struct i2c_client *client = v4l2_get_subdevdata(sd);
123 case V4L2_CID_BRIGHTNESS:
124 ret = ml86v7667_mask_set(client, SSEPL_REG,
125 SSEPL_LUMINANCE_MASK, ctrl->val);
127 case V4L2_CID_CONTRAST:
128 ret = ml86v7667_mask_set(client, CLC_REG,
129 CLC_CONTRAST_MASK, ctrl->val);
131 case V4L2_CID_CHROMA_GAIN:
132 ret = ml86v7667_mask_set(client, ACCRC_REG, ACCRC_CHROMA_MASK,
133 ctrl->val << ACCRC_CHROMA_SHIFT);
136 ret = ml86v7667_mask_set(client, HUE_REG, ~0, ctrl->val);
138 case V4L2_CID_RED_BALANCE:
139 ret = ml86v7667_mask_set(client, ACCC_REG,
141 ctrl->val << ACCC_CHROMA_CR_SHIFT);
143 case V4L2_CID_BLUE_BALANCE:
144 ret = ml86v7667_mask_set(client, ACCC_REG,
146 ctrl->val << ACCC_CHROMA_CB_SHIFT);
148 case V4L2_CID_SHARPNESS:
149 ret = ml86v7667_mask_set(client, LUMC_REG,
151 ctrl->val << LUMC_ONOFF_SHIFT);
153 case V4L2_CID_COLOR_KILLER:
154 ret = ml86v7667_mask_set(client, CHRCA_REG,
156 ctrl->val << CHRCA_MODE_SHIFT);
163 static int ml86v7667_querystd(struct v4l2_subdev *sd, v4l2_std_id *std)
165 struct i2c_client *client = v4l2_get_subdevdata(sd);
168 status = i2c_smbus_read_byte_data(client, STATUS_REG);
172 if (status & STATUS_HLOCK_DETECT)
173 *std &= status & STATUS_NTSCPAL ? V4L2_STD_625_50 : V4L2_STD_525_60;
175 *std = V4L2_STD_UNKNOWN;
180 static int ml86v7667_g_input_status(struct v4l2_subdev *sd, u32 *status)
182 struct i2c_client *client = v4l2_get_subdevdata(sd);
185 status_reg = i2c_smbus_read_byte_data(client, STATUS_REG);
189 *status = status_reg & STATUS_HLOCK_DETECT ? 0 : V4L2_IN_ST_NO_SIGNAL;
194 static int ml86v7667_enum_mbus_code(struct v4l2_subdev *sd,
195 struct v4l2_subdev_pad_config *cfg,
196 struct v4l2_subdev_mbus_code_enum *code)
198 if (code->pad || code->index > 0)
201 code->code = MEDIA_BUS_FMT_YUYV8_2X8;
206 static int ml86v7667_fill_fmt(struct v4l2_subdev *sd,
207 struct v4l2_subdev_pad_config *cfg,
208 struct v4l2_subdev_format *format)
210 struct ml86v7667_priv *priv = to_ml86v7667(sd);
211 struct v4l2_mbus_framefmt *fmt = &format->format;
216 fmt->code = MEDIA_BUS_FMT_YUYV8_2X8;
217 fmt->colorspace = V4L2_COLORSPACE_SMPTE170M;
218 /* The top field is always transferred first by the chip */
219 fmt->field = V4L2_FIELD_INTERLACED_TB;
221 fmt->height = priv->std & V4L2_STD_525_60 ? 480 : 576;
226 static int ml86v7667_g_mbus_config(struct v4l2_subdev *sd,
227 struct v4l2_mbus_config *cfg)
229 cfg->flags = V4L2_MBUS_MASTER | V4L2_MBUS_PCLK_SAMPLE_RISING |
230 V4L2_MBUS_DATA_ACTIVE_HIGH;
231 cfg->type = V4L2_MBUS_BT656;
236 static int ml86v7667_s_std(struct v4l2_subdev *sd, v4l2_std_id std)
238 struct ml86v7667_priv *priv = to_ml86v7667(sd);
239 struct i2c_client *client = v4l2_get_subdevdata(&priv->sd);
243 /* PAL/NTSC ITU-R BT.601 input mode */
244 mode = std & V4L2_STD_525_60 ? MRA_NTSC_BT601 : MRA_PAL_BT601;
245 ret = ml86v7667_mask_set(client, MRA_REG, MRA_INPUT_MODE_MASK, mode);
254 #ifdef CONFIG_VIDEO_ADV_DEBUG
255 static int ml86v7667_g_register(struct v4l2_subdev *sd,
256 struct v4l2_dbg_register *reg)
258 struct i2c_client *client = v4l2_get_subdevdata(sd);
261 ret = i2c_smbus_read_byte_data(client, (u8)reg->reg);
266 reg->size = sizeof(u8);
271 static int ml86v7667_s_register(struct v4l2_subdev *sd,
272 const struct v4l2_dbg_register *reg)
274 struct i2c_client *client = v4l2_get_subdevdata(sd);
276 return i2c_smbus_write_byte_data(client, (u8)reg->reg, (u8)reg->val);
280 static const struct v4l2_ctrl_ops ml86v7667_ctrl_ops = {
281 .s_ctrl = ml86v7667_s_ctrl,
284 static struct v4l2_subdev_video_ops ml86v7667_subdev_video_ops = {
285 .s_std = ml86v7667_s_std,
286 .querystd = ml86v7667_querystd,
287 .g_input_status = ml86v7667_g_input_status,
288 .g_mbus_config = ml86v7667_g_mbus_config,
291 static const struct v4l2_subdev_pad_ops ml86v7667_subdev_pad_ops = {
292 .enum_mbus_code = ml86v7667_enum_mbus_code,
293 .get_fmt = ml86v7667_fill_fmt,
294 .set_fmt = ml86v7667_fill_fmt,
297 static struct v4l2_subdev_core_ops ml86v7667_subdev_core_ops = {
298 #ifdef CONFIG_VIDEO_ADV_DEBUG
299 .g_register = ml86v7667_g_register,
300 .s_register = ml86v7667_s_register,
304 static struct v4l2_subdev_ops ml86v7667_subdev_ops = {
305 .core = &ml86v7667_subdev_core_ops,
306 .video = &ml86v7667_subdev_video_ops,
307 .pad = &ml86v7667_subdev_pad_ops,
310 static int ml86v7667_init(struct ml86v7667_priv *priv)
312 struct i2c_client *client = v4l2_get_subdevdata(&priv->sd);
316 /* BT.656-4 output mode, register mode */
317 ret = ml86v7667_mask_set(client, MRA_REG,
318 MRA_OUTPUT_MODE_MASK | MRA_REGISTER_MODE,
319 MRA_ITUR_BT656 | MRA_REGISTER_MODE);
321 /* PLL circuit fixed clock, 32MHz */
322 ret |= ml86v7667_mask_set(client, PLLR1_REG, PLLR1_FIXED_CLOCK,
325 /* ADC2 clamping voltage maximum */
326 ret |= ml86v7667_mask_set(client, ADC2_REG, ADC2_CLAMP_VOLTAGE_MASK,
327 ADC2_CLAMP_VOLTAGE(7));
329 /* enable luminance function */
330 ret |= ml86v7667_mask_set(client, SSEPL_REG, SSEPL_LUMINANCE_ONOFF,
331 SSEPL_LUMINANCE_ONOFF);
333 /* enable contrast function */
334 ret |= ml86v7667_mask_set(client, CLC_REG, CLC_CONTRAST_ONOFF, 0);
337 * PAL/NTSC autodetection is enabled after reset,
338 * set the autodetected std in manual std mode and
339 * disable autodetection
341 val = i2c_smbus_read_byte_data(client, STATUS_REG);
345 priv->std = val & STATUS_NTSCPAL ? V4L2_STD_625_50 : V4L2_STD_525_60;
346 ret |= ml86v7667_mask_set(client, MRC_REG, MRC_AUTOSELECT, 0);
348 val = priv->std & V4L2_STD_525_60 ? MRA_NTSC_BT601 : MRA_PAL_BT601;
349 ret |= ml86v7667_mask_set(client, MRA_REG, MRA_INPUT_MODE_MASK, val);
354 static int ml86v7667_probe(struct i2c_client *client,
355 const struct i2c_device_id *did)
357 struct ml86v7667_priv *priv;
360 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
363 priv = devm_kzalloc(&client->dev, sizeof(*priv), GFP_KERNEL);
367 v4l2_i2c_subdev_init(&priv->sd, client, &ml86v7667_subdev_ops);
369 v4l2_ctrl_handler_init(&priv->hdl, 8);
370 v4l2_ctrl_new_std(&priv->hdl, &ml86v7667_ctrl_ops,
371 V4L2_CID_BRIGHTNESS, -64, 63, 1, 0);
372 v4l2_ctrl_new_std(&priv->hdl, &ml86v7667_ctrl_ops,
373 V4L2_CID_CONTRAST, -8, 7, 1, 0);
374 v4l2_ctrl_new_std(&priv->hdl, &ml86v7667_ctrl_ops,
375 V4L2_CID_CHROMA_GAIN, -32, 31, 1, 0);
376 v4l2_ctrl_new_std(&priv->hdl, &ml86v7667_ctrl_ops,
377 V4L2_CID_HUE, -128, 127, 1, 0);
378 v4l2_ctrl_new_std(&priv->hdl, &ml86v7667_ctrl_ops,
379 V4L2_CID_RED_BALANCE, -4, 3, 1, 0);
380 v4l2_ctrl_new_std(&priv->hdl, &ml86v7667_ctrl_ops,
381 V4L2_CID_BLUE_BALANCE, -4, 3, 1, 0);
382 v4l2_ctrl_new_std(&priv->hdl, &ml86v7667_ctrl_ops,
383 V4L2_CID_SHARPNESS, 0, 1, 1, 0);
384 v4l2_ctrl_new_std(&priv->hdl, &ml86v7667_ctrl_ops,
385 V4L2_CID_COLOR_KILLER, 0, 1, 1, 0);
386 priv->sd.ctrl_handler = &priv->hdl;
388 ret = priv->hdl.error;
392 v4l2_ctrl_handler_setup(&priv->hdl);
394 ret = ml86v7667_init(priv);
398 v4l_info(client, "chip found @ 0x%02x (%s)\n",
399 client->addr, client->adapter->name);
403 v4l2_ctrl_handler_free(&priv->hdl);
404 v4l2_device_unregister_subdev(&priv->sd);
405 v4l_err(client, "failed to probe @ 0x%02x (%s)\n",
406 client->addr, client->adapter->name);
410 static int ml86v7667_remove(struct i2c_client *client)
412 struct v4l2_subdev *sd = i2c_get_clientdata(client);
413 struct ml86v7667_priv *priv = to_ml86v7667(sd);
415 v4l2_ctrl_handler_free(&priv->hdl);
416 v4l2_device_unregister_subdev(&priv->sd);
421 static const struct i2c_device_id ml86v7667_id[] = {
425 MODULE_DEVICE_TABLE(i2c, ml86v7667_id);
427 static struct i2c_driver ml86v7667_i2c_driver = {
430 .owner = THIS_MODULE,
432 .probe = ml86v7667_probe,
433 .remove = ml86v7667_remove,
434 .id_table = ml86v7667_id,
437 module_i2c_driver(ml86v7667_i2c_driver);
439 MODULE_DESCRIPTION("OKI Semiconductor ML86V7667 video decoder driver");
440 MODULE_AUTHOR("Vladimir Barinov");
441 MODULE_LICENSE("GPL");