drivers/media/i2c/smiapp-pll.c

   1 /*
   2  * drivers/media/i2c/smiapp-pll.c
   3  *
   4  * Generic driver for SMIA/SMIA++ compliant camera modules
   5  *
   6  * Copyright (C) 2011--2012 Nokia Corporation
   7  * Contact: Sakari Ailus <sakari.ailus@iki.fi>
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License
  11  * version 2 as published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  16  * General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  21  * 02110-1301 USA
  22  *
  23  */
  24
  25 #include <linux/gcd.h>
  26 #include <linux/lcm.h>
  27 #include <linux/module.h>
  28
  29 #include "smiapp-pll.h"
  30
  31 /* Return an even number or one. */
  32 static inline uint32_t clk_div_even(uint32_t a)
  33 {
  34         return max_t(uint32_t, 1, a & ~1);
  35 }
  36
  37 /* Return an even number or one. */
  38 static inline uint32_t clk_div_even_up(uint32_t a)
  39 {
  40         if (a == 1)
  41                 return 1;
  42         return (a + 1) & ~1;
  43 }
  44
  45 static inline uint32_t is_one_or_even(uint32_t a)
  46 {
  47         if (a == 1)
  48                 return 1;
  49         if (a & 1)
  50                 return 0;
  51
  52         return 1;
  53 }
  54
  55 static int bounds_check(struct device *dev, uint32_t val,
  56                         uint32_t min, uint32_t max, char *str)
  57 {
  58         if (val >= min && val <= max)
  59                 return 0;
  60
  61         dev_dbg(dev, "%s out of bounds: %d (%d--%d)\n", str, val, min, max);
  62
  63         return -EINVAL;
  64 }
  65
  66 static void print_pll(struct device *dev, struct smiapp_pll *pll)
  67 {
  68         dev_dbg(dev, "pre_pll_clk_div\t%u\n",  pll->pre_pll_clk_div);
  69         dev_dbg(dev, "pll_multiplier \t%u\n",  pll->pll_multiplier);
  70         if (!(pll->flags & SMIAPP_PLL_FLAG_NO_OP_CLOCKS)) {
  71                 dev_dbg(dev, "op_sys_clk_div \t%u\n", pll->op.sys_clk_div);
  72                 dev_dbg(dev, "op_pix_clk_div \t%u\n", pll->op.pix_clk_div);
  73         }
  74         dev_dbg(dev, "vt_sys_clk_div \t%u\n",  pll->vt.sys_clk_div);
  75         dev_dbg(dev, "vt_pix_clk_div \t%u\n",  pll->vt.pix_clk_div);
  76
  77         dev_dbg(dev, "ext_clk_freq_hz \t%u\n", pll->ext_clk_freq_hz);
  78         dev_dbg(dev, "pll_ip_clk_freq_hz \t%u\n", pll->pll_ip_clk_freq_hz);
  79         dev_dbg(dev, "pll_op_clk_freq_hz \t%u\n", pll->pll_op_clk_freq_hz);
  80         if (!(pll->flags & SMIAPP_PLL_FLAG_NO_OP_CLOCKS)) {
  81                 dev_dbg(dev, "op_sys_clk_freq_hz \t%u\n",
  82                         pll->op.sys_clk_freq_hz);
  83                 dev_dbg(dev, "op_pix_clk_freq_hz \t%u\n",
  84                         pll->op.pix_clk_freq_hz);
  85         }
  86         dev_dbg(dev, "vt_sys_clk_freq_hz \t%u\n", pll->vt.sys_clk_freq_hz);
  87         dev_dbg(dev, "vt_pix_clk_freq_hz \t%u\n", pll->vt.pix_clk_freq_hz);
  88 }
  89
  90 static int check_all_bounds(struct device *dev,
  91                             const struct smiapp_pll_limits *limits,
  92                             const struct smiapp_pll_branch_limits *op_limits,
  93                             struct smiapp_pll *pll,
  94                             struct smiapp_pll_branch *op_pll)
  95 {
  96         int rval;
  97
  98         rval = bounds_check(dev, pll->pll_ip_clk_freq_hz,
  99                             limits->min_pll_ip_freq_hz,
 100                             limits->max_pll_ip_freq_hz,
 101                             "pll_ip_clk_freq_hz");
 102         if (!rval)
 103                 rval = bounds_check(
 104                         dev, pll->pll_multiplier,
 105                         limits->min_pll_multiplier, limits->max_pll_multiplier,
 106                         "pll_multiplier");
 107         if (!rval)
 108                 rval = bounds_check(
 109                         dev, pll->pll_op_clk_freq_hz,
 110                         limits->min_pll_op_freq_hz, limits->max_pll_op_freq_hz,
 111                         "pll_op_clk_freq_hz");
 112         if (!rval)
 113                 rval = bounds_check(
 114                         dev, op_pll->sys_clk_div,
 115                         op_limits->min_sys_clk_div, op_limits->max_sys_clk_div,
 116                         "op_sys_clk_div");
 117         if (!rval)
 118                 rval = bounds_check(
 119                         dev, op_pll->sys_clk_freq_hz,
 120                         op_limits->min_sys_clk_freq_hz,
 121                         op_limits->max_sys_clk_freq_hz,
 122                         "op_sys_clk_freq_hz");
 123         if (!rval)
 124                 rval = bounds_check(
 125                         dev, op_pll->pix_clk_freq_hz,
 126                         op_limits->min_pix_clk_freq_hz,
 127                         op_limits->max_pix_clk_freq_hz,
 128                         "op_pix_clk_freq_hz");
 129
 130         /*
 131          * If there are no OP clocks, the VT clocks are contained in
 132          * the OP clock struct.
 133          */
 134         if (pll->flags & SMIAPP_PLL_FLAG_NO_OP_CLOCKS)
 135                 return rval;
 136
 137         if (!rval)
 138                 rval = bounds_check(
 139                         dev, pll->vt.sys_clk_freq_hz,
 140                         limits->vt.min_sys_clk_freq_hz,
 141                         limits->vt.max_sys_clk_freq_hz,
 142                         "vt_sys_clk_freq_hz");
 143         if (!rval)
 144                 rval = bounds_check(
 145                         dev, pll->vt.pix_clk_freq_hz,
 146                         limits->vt.min_pix_clk_freq_hz,
 147                         limits->vt.max_pix_clk_freq_hz,
 148                         "vt_pix_clk_freq_hz");
 149
 150         return rval;
 151 }
 152
 153 /*
 154  * Heuristically guess the PLL tree for a given common multiplier and
 155  * divisor. Begin with the operational timing and continue to video
 156  * timing once operational timing has been verified.
 157  *
 158  * @mul is the PLL multiplier and @div is the common divisor
 159  * (pre_pll_clk_div and op_sys_clk_div combined). The final PLL
 160  * multiplier will be a multiple of @mul.
 161  *
 162  * @return Zero on success, error code on error.
 163  */
 164 static int __smiapp_pll_calculate(
 165         struct device *dev, const struct smiapp_pll_limits *limits,
 166         const struct smiapp_pll_branch_limits *op_limits,
 167         struct smiapp_pll *pll, struct smiapp_pll_branch *op_pll, uint32_t mul,
 168         uint32_t div, uint32_t lane_op_clock_ratio)
 169 {
 170         uint32_t sys_div;
 171         uint32_t best_pix_div = INT_MAX >> 1;
 172         uint32_t vt_op_binning_div;
 173         /*
 174          * Higher multipliers (and divisors) are often required than
 175          * necessitated by the external clock and the output clocks.
 176          * There are limits for all values in the clock tree. These
 177          * are the minimum and maximum multiplier for mul.
 178          */
 179         uint32_t more_mul_min, more_mul_max;
 180         uint32_t more_mul_factor;
 181         uint32_t min_vt_div, max_vt_div, vt_div;
 182         uint32_t min_sys_div, max_sys_div;
 183         unsigned int i;
 184
 185         /*
 186          * Get pre_pll_clk_div so that our pll_op_clk_freq_hz won't be
 187          * too high.
 188          */
 189         dev_dbg(dev, "pre_pll_clk_div %u\n", pll->pre_pll_clk_div);
 190
 191         /* Don't go above max pll multiplier. */
 192         more_mul_max = limits->max_pll_multiplier / mul;
 193         dev_dbg(dev, "more_mul_max: max_pll_multiplier check: %u\n",
 194                 more_mul_max);
 195         /* Don't go above max pll op frequency. */
 196         more_mul_max =
 197                 min_t(uint32_t,
 198                       more_mul_max,
 199                       limits->max_pll_op_freq_hz
 200                       / (pll->ext_clk_freq_hz / pll->pre_pll_clk_div * mul));
 201         dev_dbg(dev, "more_mul_max: max_pll_op_freq_hz check: %u\n",
 202                 more_mul_max);
 203         /* Don't go above the division capability of op sys clock divider. */
 204         more_mul_max = min(more_mul_max,
 205                            op_limits->max_sys_clk_div * pll->pre_pll_clk_div
 206                            / div);
 207         dev_dbg(dev, "more_mul_max: max_op_sys_clk_div check: %u\n",
 208                 more_mul_max);
 209         /* Ensure we won't go above min_pll_multiplier. */
 210         more_mul_max = min(more_mul_max,
 211                            DIV_ROUND_UP(limits->max_pll_multiplier, mul));
 212         dev_dbg(dev, "more_mul_max: min_pll_multiplier check: %u\n",
 213                 more_mul_max);
 214
 215         /* Ensure we won't go below min_pll_op_freq_hz. */
 216         more_mul_min = DIV_ROUND_UP(limits->min_pll_op_freq_hz,
 217                                     pll->ext_clk_freq_hz / pll->pre_pll_clk_div
 218                                     * mul);
 219         dev_dbg(dev, "more_mul_min: min_pll_op_freq_hz check: %u\n",
 220                 more_mul_min);
 221         /* Ensure we won't go below min_pll_multiplier. */
 222         more_mul_min = max(more_mul_min,
 223                            DIV_ROUND_UP(limits->min_pll_multiplier, mul));
 224         dev_dbg(dev, "more_mul_min: min_pll_multiplier check: %u\n",
 225                 more_mul_min);
 226
 227         if (more_mul_min > more_mul_max) {
 228                 dev_dbg(dev,
 229                         "unable to compute more_mul_min and more_mul_max\n");
 230                 return -EINVAL;
 231         }
 232
 233         more_mul_factor = lcm(div, pll->pre_pll_clk_div) / div;
 234         dev_dbg(dev, "more_mul_factor: %u\n", more_mul_factor);
 235         more_mul_factor = lcm(more_mul_factor, op_limits->min_sys_clk_div);
 236         dev_dbg(dev, "more_mul_factor: min_op_sys_clk_div: %d\n",
 237                 more_mul_factor);
 238         i = roundup(more_mul_min, more_mul_factor);
 239         if (!is_one_or_even(i))
 240                 i <<= 1;
 241
 242         dev_dbg(dev, "final more_mul: %u\n", i);
 243         if (i > more_mul_max) {
 244                 dev_dbg(dev, "final more_mul is bad, max %u\n", more_mul_max);
 245                 return -EINVAL;
 246         }
 247
 248         pll->pll_multiplier = mul * i;
 249         op_pll->sys_clk_div = div * i / pll->pre_pll_clk_div;
 250         dev_dbg(dev, "op_sys_clk_div: %u\n", op_pll->sys_clk_div);
 251
 252         pll->pll_ip_clk_freq_hz = pll->ext_clk_freq_hz
 253                 / pll->pre_pll_clk_div;
 254
 255         pll->pll_op_clk_freq_hz = pll->pll_ip_clk_freq_hz
 256                 * pll->pll_multiplier;
 257
 258         /* Derive pll_op_clk_freq_hz. */
 259         op_pll->sys_clk_freq_hz =
 260                 pll->pll_op_clk_freq_hz / op_pll->sys_clk_div;
 261
 262         op_pll->pix_clk_div = pll->bits_per_pixel;
 263         dev_dbg(dev, "op_pix_clk_div: %u\n", op_pll->pix_clk_div);
 264
 265         op_pll->pix_clk_freq_hz =
 266                 op_pll->sys_clk_freq_hz / op_pll->pix_clk_div;
 267
 268         if (pll->flags & SMIAPP_PLL_FLAG_NO_OP_CLOCKS) {
 269                 /* No OP clocks --- VT clocks are used instead. */
 270                 goto out_skip_vt_calc;
 271         }
 272
 273         /*
 274          * Some sensors perform analogue binning and some do this
 275          * digitally. The ones doing this digitally can be roughly be
 276          * found out using this formula. The ones doing this digitally
 277          * should run at higher clock rate, so smaller divisor is used
 278          * on video timing side.
 279          */
 280         if (limits->min_line_length_pck_bin > limits->min_line_length_pck
 281             / pll->binning_horizontal)
 282                 vt_op_binning_div = pll->binning_horizontal;
 283         else
 284                 vt_op_binning_div = 1;
 285         dev_dbg(dev, "vt_op_binning_div: %u\n", vt_op_binning_div);
 286
 287         /*
 288          * Profile 2 supports vt_pix_clk_div E [4, 10]
 289          *
 290          * Horizontal binning can be used as a base for difference in
 291          * divisors. One must make sure that horizontal blanking is
 292          * enough to accommodate the CSI-2 sync codes.
 293          *
 294          * Take scaling factor into account as well.
 295          *
 296          * Find absolute limits for the factor of vt divider.
 297          */
 298         dev_dbg(dev, "scale_m: %u\n", pll->scale_m);
 299         min_vt_div = DIV_ROUND_UP(op_pll->pix_clk_div * op_pll->sys_clk_div
 300                                   * pll->scale_n,
 301                                   lane_op_clock_ratio * vt_op_binning_div
 302                                   * pll->scale_m);
 303
 304         /* Find smallest and biggest allowed vt divisor. */
 305         dev_dbg(dev, "min_vt_div: %u\n", min_vt_div);
 306         min_vt_div = max(min_vt_div,
 307                          DIV_ROUND_UP(pll->pll_op_clk_freq_hz,
 308                                       limits->vt.max_pix_clk_freq_hz));
 309         dev_dbg(dev, "min_vt_div: max_vt_pix_clk_freq_hz: %u\n",
 310                 min_vt_div);
 311         min_vt_div = max_t(uint32_t, min_vt_div,
 312                            limits->vt.min_pix_clk_div
 313                            * limits->vt.min_sys_clk_div);
 314         dev_dbg(dev, "min_vt_div: min_vt_clk_div: %u\n", min_vt_div);
 315
 316         max_vt_div = limits->vt.max_sys_clk_div * limits->vt.max_pix_clk_div;
 317         dev_dbg(dev, "max_vt_div: %u\n", max_vt_div);
 318         max_vt_div = min(max_vt_div,
 319                          DIV_ROUND_UP(pll->pll_op_clk_freq_hz,
 320                                       limits->vt.min_pix_clk_freq_hz));
 321         dev_dbg(dev, "max_vt_div: min_vt_pix_clk_freq_hz: %u\n",
 322                 max_vt_div);
 323
 324         /*
 325          * Find limitsits for sys_clk_div. Not all values are possible
 326          * with all values of pix_clk_div.
 327          */
 328         min_sys_div = limits->vt.min_sys_clk_div;
 329         dev_dbg(dev, "min_sys_div: %u\n", min_sys_div);
 330         min_sys_div = max(min_sys_div,
 331                           DIV_ROUND_UP(min_vt_div,
 332                                        limits->vt.max_pix_clk_div));
 333         dev_dbg(dev, "min_sys_div: max_vt_pix_clk_div: %u\n", min_sys_div);
 334         min_sys_div = max(min_sys_div,
 335                           pll->pll_op_clk_freq_hz
 336                           / limits->vt.max_sys_clk_freq_hz);
 337         dev_dbg(dev, "min_sys_div: max_pll_op_clk_freq_hz: %u\n", min_sys_div);
 338         min_sys_div = clk_div_even_up(min_sys_div);
 339         dev_dbg(dev, "min_sys_div: one or even: %u\n", min_sys_div);
 340
 341         max_sys_div = limits->vt.max_sys_clk_div;
 342         dev_dbg(dev, "max_sys_div: %u\n", max_sys_div);
 343         max_sys_div = min(max_sys_div,
 344                           DIV_ROUND_UP(max_vt_div,
 345                                        limits->vt.min_pix_clk_div));
 346         dev_dbg(dev, "max_sys_div: min_vt_pix_clk_div: %u\n", max_sys_div);
 347         max_sys_div = min(max_sys_div,
 348                           DIV_ROUND_UP(pll->pll_op_clk_freq_hz,
 349                                        limits->vt.min_pix_clk_freq_hz));
 350         dev_dbg(dev, "max_sys_div: min_vt_pix_clk_freq_hz: %u\n", max_sys_div);
 351
 352         /*
 353          * Find pix_div such that a legal pix_div * sys_div results
 354          * into a value which is not smaller than div, the desired
 355          * divisor.
 356          */
 357         for (vt_div = min_vt_div; vt_div <= max_vt_div;
 358              vt_div += 2 - (vt_div & 1)) {
 359                 for (sys_div = min_sys_div;
 360                      sys_div <= max_sys_div;
 361                      sys_div += 2 - (sys_div & 1)) {
 362                         uint16_t pix_div = DIV_ROUND_UP(vt_div, sys_div);
 363
 364                         if (pix_div < limits->vt.min_pix_clk_div
 365                             || pix_div > limits->vt.max_pix_clk_div) {
 366                                 dev_dbg(dev,
 367                                         "pix_div %u too small or too big (%u--%u)\n",
 368                                         pix_div,
 369                                         limits->vt.min_pix_clk_div,
 370                                         limits->vt.max_pix_clk_div);
 371                                 continue;
 372                         }
 373
 374                         /* Check if this one is better. */
 375                         if (pix_div * sys_div
 376                             <= roundup(min_vt_div, best_pix_div))
 377                                 best_pix_div = pix_div;
 378                 }
 379                 if (best_pix_div < INT_MAX >> 1)
 380                         break;
 381         }
 382
 383         pll->vt.sys_clk_div = DIV_ROUND_UP(min_vt_div, best_pix_div);
 384         pll->vt.pix_clk_div = best_pix_div;
 385
 386         pll->vt.sys_clk_freq_hz =
 387                 pll->pll_op_clk_freq_hz / pll->vt.sys_clk_div;
 388         pll->vt.pix_clk_freq_hz =
 389                 pll->vt.sys_clk_freq_hz / pll->vt.pix_clk_div;
 390
 391 out_skip_vt_calc:
 392         pll->pixel_rate_csi =
 393                 op_pll->pix_clk_freq_hz * lane_op_clock_ratio;
 394         pll->pixel_rate_pixel_array = pll->vt.pix_clk_freq_hz;
 395
 396         return check_all_bounds(dev, limits, op_limits, pll, op_pll);
 397 }
 398
 399 int smiapp_pll_calculate(struct device *dev,
 400                          const struct smiapp_pll_limits *limits,
 401                          struct smiapp_pll *pll)
 402 {
 403         const struct smiapp_pll_branch_limits *op_limits = &limits->op;
 404         struct smiapp_pll_branch *op_pll = &pll->op;
 405         uint16_t min_pre_pll_clk_div;
 406         uint16_t max_pre_pll_clk_div;
 407         uint32_t lane_op_clock_ratio;
 408         uint32_t mul, div;
 409         unsigned int i;
 410         int rval = -EINVAL;
 411
 412         if (pll->flags & SMIAPP_PLL_FLAG_NO_OP_CLOCKS) {
 413                 /*
 414                  * If there's no OP PLL at all, use the VT values
 415                  * instead. The OP values are ignored for the rest of
 416                  * the PLL calculation.
 417                  */
 418                 op_limits = &limits->vt;
 419                 op_pll = &pll->vt;
 420         }
 421
 422         if (pll->flags & SMIAPP_PLL_FLAG_OP_PIX_CLOCK_PER_LANE)
 423                 lane_op_clock_ratio = pll->csi2.lanes;
 424         else
 425                 lane_op_clock_ratio = 1;
 426         dev_dbg(dev, "lane_op_clock_ratio: %u\n", lane_op_clock_ratio);
 427
 428         dev_dbg(dev, "binning: %ux%u\n", pll->binning_horizontal,
 429                 pll->binning_vertical);
 430
 431         switch (pll->bus_type) {
 432         case SMIAPP_PLL_BUS_TYPE_CSI2:
 433                 /* CSI transfers 2 bits per clock per lane; thus times 2 */
 434                 pll->pll_op_clk_freq_hz = pll->link_freq * 2
 435                         * (pll->csi2.lanes / lane_op_clock_ratio);
 436                 break;
 437         case SMIAPP_PLL_BUS_TYPE_PARALLEL:
 438                 pll->pll_op_clk_freq_hz = pll->link_freq * pll->bits_per_pixel
 439                         / DIV_ROUND_UP(pll->bits_per_pixel,
 440                                        pll->parallel.bus_width);
 441                 break;
 442         default:
 443                 return -EINVAL;
 444         }
 445
 446         /* Figure out limits for pre-pll divider based on extclk */
 447         dev_dbg(dev, "min / max pre_pll_clk_div: %u / %u\n",
 448                 limits->min_pre_pll_clk_div, limits->max_pre_pll_clk_div);
 449         max_pre_pll_clk_div =
 450                 min_t(uint16_t, limits->max_pre_pll_clk_div,
 451                       clk_div_even(pll->ext_clk_freq_hz /
 452                                    limits->min_pll_ip_freq_hz));
 453         min_pre_pll_clk_div =
 454                 max_t(uint16_t, limits->min_pre_pll_clk_div,
 455                       clk_div_even_up(
 456                               DIV_ROUND_UP(pll->ext_clk_freq_hz,
 457                                            limits->max_pll_ip_freq_hz)));
 458         dev_dbg(dev, "pre-pll check: min / max pre_pll_clk_div: %u / %u\n",
 459                 min_pre_pll_clk_div, max_pre_pll_clk_div);
 460
 461         i = gcd(pll->pll_op_clk_freq_hz, pll->ext_clk_freq_hz);
 462         mul = div_u64(pll->pll_op_clk_freq_hz, i);
 463         div = pll->ext_clk_freq_hz / i;
 464         dev_dbg(dev, "mul %u / div %u\n", mul, div);
 465
 466         min_pre_pll_clk_div =
 467                 max_t(uint16_t, min_pre_pll_clk_div,
 468                       clk_div_even_up(
 469                               DIV_ROUND_UP(mul * pll->ext_clk_freq_hz,
 470                                            limits->max_pll_op_freq_hz)));
 471         dev_dbg(dev, "pll_op check: min / max pre_pll_clk_div: %u / %u\n",
 472                 min_pre_pll_clk_div, max_pre_pll_clk_div);
 473
 474         for (pll->pre_pll_clk_div = min_pre_pll_clk_div;
 475              pll->pre_pll_clk_div <= max_pre_pll_clk_div;
 476              pll->pre_pll_clk_div += 2 - (pll->pre_pll_clk_div & 1)) {
 477                 rval = __smiapp_pll_calculate(dev, limits, op_limits, pll,
 478                                               op_pll, mul, div,
 479                                               lane_op_clock_ratio);
 480                 if (rval)
 481                         continue;
 482
 483                 print_pll(dev, pll);
 484                 return 0;
 485         }
 486
 487         dev_info(dev, "unable to compute pre_pll divisor\n");
 488         return rval;
 489 }
 490 EXPORT_SYMBOL_GPL(smiapp_pll_calculate);
 491
 492 MODULE_AUTHOR("Sakari Ailus <sakari.ailus@iki.fi>");
 493 MODULE_DESCRIPTION("Generic SMIA/SMIA++ PLL calculator");
 494 MODULE_LICENSE("GPL");