2 * Driver for SiliconFile SR030PC30 VGA (1/10-Inch) Image Sensor with ISP
4 * Copyright (C) 2010 Samsung Electronics Co., Ltd
5 * Author: Sylwester Nawrocki, s.nawrocki@samsung.com
7 * Based on original driver authored by Dongsoo Nathaniel Kim
8 * and HeungJun Kim <riverful.kim@samsung.com>.
10 * Based on mt9v011 Micron Digital Image Sensor driver
11 * Copyright (c) 2009 Mauro Carvalho Chehab
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
19 #include <linux/i2c.h>
20 #include <linux/delay.h>
21 #include <linux/slab.h>
22 #include <linux/module.h>
23 #include <media/v4l2-device.h>
24 #include <media/v4l2-subdev.h>
25 #include <media/v4l2-mediabus.h>
26 #include <media/v4l2-ctrls.h>
27 #include <media/sr030pc30.h>
30 module_param(debug, int, 0644);
32 #define MODULE_NAME "SR030PC30"
35 * Register offsets within a page
36 * b15..b8 - page id, b7..b0 - register address
38 #define POWER_CTRL_REG 0x0001
39 #define PAGEMODE_REG 0x03
40 #define DEVICE_ID_REG 0x0004
41 #define NOON010PC30_ID 0x86
42 #define SR030PC30_ID 0x8C
43 #define VDO_CTL1_REG 0x0010
44 #define SUBSAMPL_NONE_VGA 0
45 #define SUBSAMPL_QVGA 0x10
46 #define SUBSAMPL_QQVGA 0x20
47 #define VDO_CTL2_REG 0x0011
48 #define SYNC_CTL_REG 0x0012
49 #define WIN_ROWH_REG 0x0020
50 #define WIN_ROWL_REG 0x0021
51 #define WIN_COLH_REG 0x0022
52 #define WIN_COLL_REG 0x0023
53 #define WIN_HEIGHTH_REG 0x0024
54 #define WIN_HEIGHTL_REG 0x0025
55 #define WIN_WIDTHH_REG 0x0026
56 #define WIN_WIDTHL_REG 0x0027
57 #define HBLANKH_REG 0x0040
58 #define HBLANKL_REG 0x0041
59 #define VSYNCH_REG 0x0042
60 #define VSYNCL_REG 0x0043
62 #define ISP_CTL_REG(n) (0x1010 + (n))
63 #define YOFS_REG 0x1040
64 #define DARK_YOFS_REG 0x1041
65 #define AG_ABRTH_REG 0x1050
66 #define SAT_CTL_REG 0x1060
67 #define BSAT_REG 0x1061
68 #define RSAT_REG 0x1062
69 #define AG_SAT_TH_REG 0x1063
71 #define ZLPF_CTRL_REG 0x1110
72 #define ZLPF_CTRL2_REG 0x1112
73 #define ZLPF_AGH_THR_REG 0x1121
74 #define ZLPF_THR_REG 0x1160
75 #define ZLPF_DYN_THR_REG 0x1160
77 #define YCLPF_CTL1_REG 0x1240
78 #define YCLPF_CTL2_REG 0x1241
79 #define YCLPF_THR_REG 0x1250
80 #define BLPF_CTL_REG 0x1270
81 #define BLPF_THR1_REG 0x1274
82 #define BLPF_THR2_REG 0x1275
83 /* page 14 - Lens Shading Compensation */
84 #define LENS_CTRL_REG 0x1410
85 #define LENS_XCEN_REG 0x1420
86 #define LENS_YCEN_REG 0x1421
87 #define LENS_R_COMP_REG 0x1422
88 #define LENS_G_COMP_REG 0x1423
89 #define LENS_B_COMP_REG 0x1424
90 /* page 15 - Color correction */
91 #define CMC_CTL_REG 0x1510
92 #define CMC_OFSGH_REG 0x1514
93 #define CMC_OFSGL_REG 0x1516
94 #define CMC_SIGN_REG 0x1517
95 /* Color correction coefficients */
96 #define CMC_COEF_REG(n) (0x1530 + (n))
97 /* Color correction offset coefficients */
98 #define CMC_OFS_REG(n) (0x1540 + (n))
99 /* page 16 - Gamma correction */
100 #define GMA_CTL_REG 0x1610
101 /* Gamma correction coefficients 0.14 */
102 #define GMA_COEF_REG(n) (0x1630 + (n))
103 /* page 20 - Auto Exposure */
104 #define AE_CTL1_REG 0x2010
105 #define AE_CTL2_REG 0x2011
106 #define AE_FRM_CTL_REG 0x2020
107 #define AE_FINE_CTL_REG(n) (0x2028 + (n))
108 #define EXP_TIMEH_REG 0x2083
109 #define EXP_TIMEM_REG 0x2084
110 #define EXP_TIMEL_REG 0x2085
111 #define EXP_MMINH_REG 0x2086
112 #define EXP_MMINL_REG 0x2087
113 #define EXP_MMAXH_REG 0x2088
114 #define EXP_MMAXM_REG 0x2089
115 #define EXP_MMAXL_REG 0x208A
116 /* page 22 - Auto White Balance */
117 #define AWB_CTL1_REG 0x2210
118 #define AWB_ENABLE 0x80
119 #define AWB_CTL2_REG 0x2211
120 #define MWB_ENABLE 0x01
121 /* RGB gain control (manual WB) when AWB_CTL1[7]=0 */
122 #define AWB_RGAIN_REG 0x2280
123 #define AWB_GGAIN_REG 0x2281
124 #define AWB_BGAIN_REG 0x2282
125 #define AWB_RMAX_REG 0x2283
126 #define AWB_RMIN_REG 0x2284
127 #define AWB_BMAX_REG 0x2285
128 #define AWB_BMIN_REG 0x2286
129 /* R, B gain range in bright light conditions */
130 #define AWB_RMAXB_REG 0x2287
131 #define AWB_RMINB_REG 0x2288
132 #define AWB_BMAXB_REG 0x2289
133 #define AWB_BMINB_REG 0x228A
134 /* manual white balance, when AWB_CTL2[0]=1 */
135 #define MWB_RGAIN_REG 0x22B2
136 #define MWB_BGAIN_REG 0x22B3
137 /* the token to mark an array end */
138 #define REG_TERM 0xFFFF
140 /* Minimum and maximum exposure time in ms */
141 #define EXPOS_MIN_MS 1
142 #define EXPOS_MAX_MS 125
144 struct sr030pc30_info {
145 struct v4l2_subdev sd;
146 struct v4l2_ctrl_handler hdl;
147 const struct sr030pc30_platform_data *pdata;
148 const struct sr030pc30_format *curr_fmt;
149 const struct sr030pc30_frmsize *curr_win;
150 unsigned int hflip:1;
151 unsigned int vflip:1;
152 unsigned int sleep:1;
154 /* auto whitebalance control cluster */
155 struct v4l2_ctrl *awb;
156 struct v4l2_ctrl *red;
157 struct v4l2_ctrl *blue;
160 /* auto exposure control cluster */
161 struct v4l2_ctrl *autoexp;
162 struct v4l2_ctrl *exp;
167 struct sr030pc30_format {
169 enum v4l2_colorspace colorspace;
173 struct sr030pc30_frmsize {
184 /* supported resolutions */
185 static const struct sr030pc30_frmsize sr030pc30_sizes[] = {
189 .vid_ctl1 = SUBSAMPL_NONE_VGA,
193 .vid_ctl1 = SUBSAMPL_QVGA,
197 .vid_ctl1 = SUBSAMPL_QQVGA,
201 /* supported pixel formats */
202 static const struct sr030pc30_format sr030pc30_formats[] = {
204 .code = MEDIA_BUS_FMT_YUYV8_2X8,
205 .colorspace = V4L2_COLORSPACE_JPEG,
208 .code = MEDIA_BUS_FMT_YVYU8_2X8,
209 .colorspace = V4L2_COLORSPACE_JPEG,
212 .code = MEDIA_BUS_FMT_VYUY8_2X8,
213 .colorspace = V4L2_COLORSPACE_JPEG,
216 .code = MEDIA_BUS_FMT_UYVY8_2X8,
217 .colorspace = V4L2_COLORSPACE_JPEG,
220 .code = MEDIA_BUS_FMT_RGB565_2X8_BE,
221 .colorspace = V4L2_COLORSPACE_JPEG,
226 static const struct i2c_regval sr030pc30_base_regs[] = {
227 /* Window size and position within pixel matrix */
228 { WIN_ROWH_REG, 0x00 }, { WIN_ROWL_REG, 0x06 },
229 { WIN_COLH_REG, 0x00 }, { WIN_COLL_REG, 0x06 },
230 { WIN_HEIGHTH_REG, 0x01 }, { WIN_HEIGHTL_REG, 0xE0 },
231 { WIN_WIDTHH_REG, 0x02 }, { WIN_WIDTHL_REG, 0x80 },
232 { HBLANKH_REG, 0x01 }, { HBLANKL_REG, 0x50 },
233 { VSYNCH_REG, 0x00 }, { VSYNCL_REG, 0x14 },
235 /* Color corection and saturation */
236 { ISP_CTL_REG(0), 0x30 }, { YOFS_REG, 0x80 },
237 { DARK_YOFS_REG, 0x04 }, { AG_ABRTH_REG, 0x78 },
238 { SAT_CTL_REG, 0x1F }, { BSAT_REG, 0x90 },
239 { AG_SAT_TH_REG, 0xF0 }, { 0x1064, 0x80 },
240 { CMC_CTL_REG, 0x03 }, { CMC_OFSGH_REG, 0x3C },
241 { CMC_OFSGL_REG, 0x2C }, { CMC_SIGN_REG, 0x2F },
242 { CMC_COEF_REG(0), 0xCB }, { CMC_OFS_REG(0), 0x87 },
243 { CMC_COEF_REG(1), 0x61 }, { CMC_OFS_REG(1), 0x18 },
244 { CMC_COEF_REG(2), 0x16 }, { CMC_OFS_REG(2), 0x91 },
245 { CMC_COEF_REG(3), 0x23 }, { CMC_OFS_REG(3), 0x94 },
246 { CMC_COEF_REG(4), 0xCE }, { CMC_OFS_REG(4), 0x9f },
247 { CMC_COEF_REG(5), 0x2B }, { CMC_OFS_REG(5), 0x33 },
248 { CMC_COEF_REG(6), 0x01 }, { CMC_OFS_REG(6), 0x00 },
249 { CMC_COEF_REG(7), 0x34 }, { CMC_OFS_REG(7), 0x94 },
250 { CMC_COEF_REG(8), 0x75 }, { CMC_OFS_REG(8), 0x14 },
251 /* Color corection coefficients */
252 { GMA_CTL_REG, 0x03 }, { GMA_COEF_REG(0), 0x00 },
253 { GMA_COEF_REG(1), 0x19 }, { GMA_COEF_REG(2), 0x26 },
254 { GMA_COEF_REG(3), 0x3B }, { GMA_COEF_REG(4), 0x5D },
255 { GMA_COEF_REG(5), 0x79 }, { GMA_COEF_REG(6), 0x8E },
256 { GMA_COEF_REG(7), 0x9F }, { GMA_COEF_REG(8), 0xAF },
257 { GMA_COEF_REG(9), 0xBD }, { GMA_COEF_REG(10), 0xCA },
258 { GMA_COEF_REG(11), 0xDD }, { GMA_COEF_REG(12), 0xEC },
259 { GMA_COEF_REG(13), 0xF7 }, { GMA_COEF_REG(14), 0xFF },
260 /* Noise reduction, Z-LPF, YC-LPF and BLPF filters setup */
261 { ZLPF_CTRL_REG, 0x99 }, { ZLPF_CTRL2_REG, 0x0E },
262 { ZLPF_AGH_THR_REG, 0x29 }, { ZLPF_THR_REG, 0x0F },
263 { ZLPF_DYN_THR_REG, 0x63 }, { YCLPF_CTL1_REG, 0x23 },
264 { YCLPF_CTL2_REG, 0x3B }, { YCLPF_THR_REG, 0x05 },
265 { BLPF_CTL_REG, 0x1D }, { BLPF_THR1_REG, 0x05 },
266 { BLPF_THR2_REG, 0x04 },
267 /* Automatic white balance */
268 { AWB_CTL1_REG, 0xFB }, { AWB_CTL2_REG, 0x26 },
269 { AWB_RMAX_REG, 0x54 }, { AWB_RMIN_REG, 0x2B },
270 { AWB_BMAX_REG, 0x57 }, { AWB_BMIN_REG, 0x29 },
271 { AWB_RMAXB_REG, 0x50 }, { AWB_RMINB_REG, 0x43 },
272 { AWB_BMAXB_REG, 0x30 }, { AWB_BMINB_REG, 0x22 },
274 { AE_CTL1_REG, 0x8C }, { AE_CTL2_REG, 0x04 },
275 { AE_FRM_CTL_REG, 0x01 }, { AE_FINE_CTL_REG(0), 0x3F },
276 { AE_FINE_CTL_REG(1), 0xA3 }, { AE_FINE_CTL_REG(3), 0x34 },
277 /* Lens shading compensation */
278 { LENS_CTRL_REG, 0x01 }, { LENS_XCEN_REG, 0x80 },
279 { LENS_YCEN_REG, 0x70 }, { LENS_R_COMP_REG, 0x53 },
280 { LENS_G_COMP_REG, 0x40 }, { LENS_B_COMP_REG, 0x3e },
284 static inline struct sr030pc30_info *to_sr030pc30(struct v4l2_subdev *sd)
286 return container_of(sd, struct sr030pc30_info, sd);
289 static inline int set_i2c_page(struct sr030pc30_info *info,
290 struct i2c_client *client, unsigned int reg)
293 u32 page = reg >> 8 & 0xFF;
295 if (info->i2c_reg_page != page && (reg & 0xFF) != 0x03) {
296 ret = i2c_smbus_write_byte_data(client, PAGEMODE_REG, page);
298 info->i2c_reg_page = page;
303 static int cam_i2c_read(struct v4l2_subdev *sd, u32 reg_addr)
305 struct i2c_client *client = v4l2_get_subdevdata(sd);
306 struct sr030pc30_info *info = to_sr030pc30(sd);
308 int ret = set_i2c_page(info, client, reg_addr);
310 ret = i2c_smbus_read_byte_data(client, reg_addr & 0xFF);
314 static int cam_i2c_write(struct v4l2_subdev *sd, u32 reg_addr, u32 val)
316 struct i2c_client *client = v4l2_get_subdevdata(sd);
317 struct sr030pc30_info *info = to_sr030pc30(sd);
319 int ret = set_i2c_page(info, client, reg_addr);
321 ret = i2c_smbus_write_byte_data(
322 client, reg_addr & 0xFF, val);
326 static inline int sr030pc30_bulk_write_reg(struct v4l2_subdev *sd,
327 const struct i2c_regval *msg)
329 while (msg->addr != REG_TERM) {
330 int ret = cam_i2c_write(sd, msg->addr, msg->val);
338 /* Device reset and sleep mode control */
339 static int sr030pc30_pwr_ctrl(struct v4l2_subdev *sd,
340 bool reset, bool sleep)
342 struct sr030pc30_info *info = to_sr030pc30(sd);
343 u8 reg = sleep ? 0xF1 : 0xF0;
347 ret = cam_i2c_write(sd, POWER_CTRL_REG, reg | 0x02);
349 ret = cam_i2c_write(sd, POWER_CTRL_REG, reg);
353 info->i2c_reg_page = -1;
359 static int sr030pc30_set_flip(struct v4l2_subdev *sd)
361 struct sr030pc30_info *info = to_sr030pc30(sd);
363 s32 reg = cam_i2c_read(sd, VDO_CTL2_REG);
372 return cam_i2c_write(sd, VDO_CTL2_REG, reg | 0x80);
375 /* Configure resolution, color format and image flip */
376 static int sr030pc30_set_params(struct v4l2_subdev *sd)
378 struct sr030pc30_info *info = to_sr030pc30(sd);
384 /* Configure the resolution through subsampling */
385 ret = cam_i2c_write(sd, VDO_CTL1_REG,
386 info->curr_win->vid_ctl1);
388 if (!ret && info->curr_fmt)
389 ret = cam_i2c_write(sd, ISP_CTL_REG(0),
390 info->curr_fmt->ispctl1_reg);
392 ret = sr030pc30_set_flip(sd);
397 /* Find nearest matching image pixel size. */
398 static int sr030pc30_try_frame_size(struct v4l2_mbus_framefmt *mf)
400 unsigned int min_err = ~0;
401 int i = ARRAY_SIZE(sr030pc30_sizes);
402 const struct sr030pc30_frmsize *fsize = &sr030pc30_sizes[0],
405 int err = abs(fsize->width - mf->width)
406 + abs(fsize->height - mf->height);
414 mf->width = match->width;
415 mf->height = match->height;
421 static int sr030pc30_s_ctrl(struct v4l2_ctrl *ctrl)
423 struct sr030pc30_info *info =
424 container_of(ctrl->handler, struct sr030pc30_info, hdl);
425 struct v4l2_subdev *sd = &info->sd;
428 v4l2_dbg(1, debug, sd, "%s: ctrl_id: %d, value: %d\n",
429 __func__, ctrl->id, ctrl->val);
432 case V4L2_CID_AUTO_WHITE_BALANCE:
434 ret = cam_i2c_write(sd, AWB_CTL2_REG,
435 ctrl->val ? 0x2E : 0x2F);
437 ret = cam_i2c_write(sd, AWB_CTL1_REG,
438 ctrl->val ? 0xFB : 0x7B);
440 if (!ret && info->blue->is_new)
441 ret = cam_i2c_write(sd, MWB_BGAIN_REG, info->blue->val);
442 if (!ret && info->red->is_new)
443 ret = cam_i2c_write(sd, MWB_RGAIN_REG, info->red->val);
446 case V4L2_CID_EXPOSURE_AUTO:
447 /* auto anti-flicker is also enabled here */
449 ret = cam_i2c_write(sd, AE_CTL1_REG,
450 ctrl->val == V4L2_EXPOSURE_AUTO ? 0xDC : 0x0C);
451 if (info->exp->is_new) {
452 unsigned long expos = info->exp->val;
454 expos = expos * info->pdata->clk_rate / (8 * 1000);
457 ret = cam_i2c_write(sd, EXP_TIMEH_REG,
460 ret = cam_i2c_write(sd, EXP_TIMEM_REG,
463 ret = cam_i2c_write(sd, EXP_TIMEL_REG,
474 static int sr030pc30_enum_mbus_code(struct v4l2_subdev *sd,
475 struct v4l2_subdev_pad_config *cfg,
476 struct v4l2_subdev_mbus_code_enum *code)
478 if (!code || code->pad ||
479 code->index >= ARRAY_SIZE(sr030pc30_formats))
482 code->code = sr030pc30_formats[code->index].code;
486 static int sr030pc30_get_fmt(struct v4l2_subdev *sd,
487 struct v4l2_subdev_pad_config *cfg,
488 struct v4l2_subdev_format *format)
490 struct v4l2_mbus_framefmt *mf;
491 struct sr030pc30_info *info = to_sr030pc30(sd);
494 if (!format || format->pad)
497 mf = &format->format;
499 if (!info->curr_win || !info->curr_fmt) {
500 ret = sr030pc30_set_params(sd);
505 mf->width = info->curr_win->width;
506 mf->height = info->curr_win->height;
507 mf->code = info->curr_fmt->code;
508 mf->colorspace = info->curr_fmt->colorspace;
509 mf->field = V4L2_FIELD_NONE;
514 /* Return nearest media bus frame format. */
515 static const struct sr030pc30_format *try_fmt(struct v4l2_subdev *sd,
516 struct v4l2_mbus_framefmt *mf)
518 int i = ARRAY_SIZE(sr030pc30_formats);
520 sr030pc30_try_frame_size(mf);
523 if (mf->code == sr030pc30_formats[i].code)
526 mf->code = sr030pc30_formats[i].code;
528 return &sr030pc30_formats[i];
531 /* Return nearest media bus frame format. */
532 static int sr030pc30_set_fmt(struct v4l2_subdev *sd,
533 struct v4l2_subdev_pad_config *cfg,
534 struct v4l2_subdev_format *format)
536 struct sr030pc30_info *info = sd ? to_sr030pc30(sd) : NULL;
537 const struct sr030pc30_format *fmt;
538 struct v4l2_mbus_framefmt *mf;
543 mf = &format->format;
547 fmt = try_fmt(sd, mf);
548 if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
553 info->curr_fmt = fmt;
555 return sr030pc30_set_params(sd);
558 static int sr030pc30_base_config(struct v4l2_subdev *sd)
560 struct sr030pc30_info *info = to_sr030pc30(sd);
562 unsigned long expmin, expmax;
564 ret = sr030pc30_bulk_write_reg(sd, sr030pc30_base_regs);
566 info->curr_fmt = &sr030pc30_formats[0];
567 info->curr_win = &sr030pc30_sizes[0];
568 ret = sr030pc30_set_params(sd);
571 ret = sr030pc30_pwr_ctrl(sd, false, false);
573 if (!ret && !info->pdata)
576 expmin = EXPOS_MIN_MS * info->pdata->clk_rate / (8 * 1000);
577 expmax = EXPOS_MAX_MS * info->pdata->clk_rate / (8 * 1000);
579 v4l2_dbg(1, debug, sd, "%s: expmin= %lx, expmax= %lx", __func__,
582 /* Setting up manual exposure time range */
583 ret = cam_i2c_write(sd, EXP_MMINH_REG, expmin >> 8 & 0xFF);
585 ret = cam_i2c_write(sd, EXP_MMINL_REG, expmin & 0xFF);
587 ret = cam_i2c_write(sd, EXP_MMAXH_REG, expmax >> 16 & 0xFF);
589 ret = cam_i2c_write(sd, EXP_MMAXM_REG, expmax >> 8 & 0xFF);
591 ret = cam_i2c_write(sd, EXP_MMAXL_REG, expmax & 0xFF);
596 static int sr030pc30_s_power(struct v4l2_subdev *sd, int on)
598 struct i2c_client *client = v4l2_get_subdevdata(sd);
599 struct sr030pc30_info *info = to_sr030pc30(sd);
600 const struct sr030pc30_platform_data *pdata = info->pdata;
604 WARN(1, "No platform data!\n");
609 * Put sensor into power sleep mode before switching off
610 * power and disabling MCLK.
613 sr030pc30_pwr_ctrl(sd, false, true);
615 /* set_power controls sensor's power and clock */
616 if (pdata->set_power) {
617 ret = pdata->set_power(&client->dev, on);
623 ret = sr030pc30_base_config(sd);
626 info->curr_win = NULL;
627 info->curr_fmt = NULL;
633 static const struct v4l2_ctrl_ops sr030pc30_ctrl_ops = {
634 .s_ctrl = sr030pc30_s_ctrl,
637 static const struct v4l2_subdev_core_ops sr030pc30_core_ops = {
638 .s_power = sr030pc30_s_power,
639 .g_ext_ctrls = v4l2_subdev_g_ext_ctrls,
640 .try_ext_ctrls = v4l2_subdev_try_ext_ctrls,
641 .s_ext_ctrls = v4l2_subdev_s_ext_ctrls,
642 .g_ctrl = v4l2_subdev_g_ctrl,
643 .s_ctrl = v4l2_subdev_s_ctrl,
644 .queryctrl = v4l2_subdev_queryctrl,
645 .querymenu = v4l2_subdev_querymenu,
648 static const struct v4l2_subdev_pad_ops sr030pc30_pad_ops = {
649 .enum_mbus_code = sr030pc30_enum_mbus_code,
650 .get_fmt = sr030pc30_get_fmt,
651 .set_fmt = sr030pc30_set_fmt,
654 static const struct v4l2_subdev_ops sr030pc30_ops = {
655 .core = &sr030pc30_core_ops,
656 .pad = &sr030pc30_pad_ops,
660 * Detect sensor type. Return 0 if SR030PC30 was detected
661 * or -ENODEV otherwise.
663 static int sr030pc30_detect(struct i2c_client *client)
665 const struct sr030pc30_platform_data *pdata
666 = client->dev.platform_data;
669 /* Enable sensor's power and clock */
670 if (pdata->set_power) {
671 ret = pdata->set_power(&client->dev, 1);
676 ret = i2c_smbus_read_byte_data(client, DEVICE_ID_REG);
678 if (pdata->set_power)
679 pdata->set_power(&client->dev, 0);
682 dev_err(&client->dev, "%s: I2C read failed\n", __func__);
686 return ret == SR030PC30_ID ? 0 : -ENODEV;
690 static int sr030pc30_probe(struct i2c_client *client,
691 const struct i2c_device_id *id)
693 struct sr030pc30_info *info;
694 struct v4l2_subdev *sd;
695 struct v4l2_ctrl_handler *hdl;
696 const struct sr030pc30_platform_data *pdata
697 = client->dev.platform_data;
701 dev_err(&client->dev, "No platform data!");
705 ret = sr030pc30_detect(client);
709 info = devm_kzalloc(&client->dev, sizeof(*info), GFP_KERNEL);
714 strcpy(sd->name, MODULE_NAME);
715 info->pdata = client->dev.platform_data;
717 v4l2_i2c_subdev_init(sd, client, &sr030pc30_ops);
720 v4l2_ctrl_handler_init(hdl, 6);
721 info->awb = v4l2_ctrl_new_std(hdl, &sr030pc30_ctrl_ops,
722 V4L2_CID_AUTO_WHITE_BALANCE, 0, 1, 1, 1);
723 info->red = v4l2_ctrl_new_std(hdl, &sr030pc30_ctrl_ops,
724 V4L2_CID_RED_BALANCE, 0, 127, 1, 64);
725 info->blue = v4l2_ctrl_new_std(hdl, &sr030pc30_ctrl_ops,
726 V4L2_CID_BLUE_BALANCE, 0, 127, 1, 64);
727 info->autoexp = v4l2_ctrl_new_std(hdl, &sr030pc30_ctrl_ops,
728 V4L2_CID_EXPOSURE_AUTO, 0, 1, 1, 1);
729 info->exp = v4l2_ctrl_new_std(hdl, &sr030pc30_ctrl_ops,
730 V4L2_CID_EXPOSURE, EXPOS_MIN_MS, EXPOS_MAX_MS, 1, 30);
731 sd->ctrl_handler = hdl;
733 int err = hdl->error;
735 v4l2_ctrl_handler_free(hdl);
738 v4l2_ctrl_auto_cluster(3, &info->awb, 0, false);
739 v4l2_ctrl_auto_cluster(2, &info->autoexp, V4L2_EXPOSURE_MANUAL, false);
740 v4l2_ctrl_handler_setup(hdl);
742 info->i2c_reg_page = -1;
748 static int sr030pc30_remove(struct i2c_client *client)
750 struct v4l2_subdev *sd = i2c_get_clientdata(client);
752 v4l2_device_unregister_subdev(sd);
753 v4l2_ctrl_handler_free(sd->ctrl_handler);
757 static const struct i2c_device_id sr030pc30_id[] = {
761 MODULE_DEVICE_TABLE(i2c, sr030pc30_id);
764 static struct i2c_driver sr030pc30_i2c_driver = {
768 .probe = sr030pc30_probe,
769 .remove = sr030pc30_remove,
770 .id_table = sr030pc30_id,
773 module_i2c_driver(sr030pc30_i2c_driver);
775 MODULE_DESCRIPTION("Siliconfile SR030PC30 camera driver");
776 MODULE_AUTHOR("Sylwester Nawrocki <s.nawrocki@samsung.com>");
777 MODULE_LICENSE("GPL");