2 * Driver for the Conexant CX25821 PCIe bridge
4 * Copyright (C) 2009 Conexant Systems Inc.
5 * Authors <shu.lin@conexant.com>, <hiep.huynh@conexant.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
26 #include "cx25821-medusa-video.h"
27 #include "cx25821-biffuncs.h"
30 * medusa_enable_bluefield_output()
32 * Enable the generation of blue filed output if no video
35 static void medusa_enable_bluefield_output(struct cx25821_dev *dev, int channel,
40 int out_ctrl = OUT_CTRL1;
41 int out_ctrl_ns = OUT_CTRL_NS;
48 out_ctrl = VDEC_B_OUT_CTRL1;
49 out_ctrl_ns = VDEC_B_OUT_CTRL_NS;
52 out_ctrl = VDEC_C_OUT_CTRL1;
53 out_ctrl_ns = VDEC_C_OUT_CTRL_NS;
56 out_ctrl = VDEC_D_OUT_CTRL1;
57 out_ctrl_ns = VDEC_D_OUT_CTRL_NS;
60 out_ctrl = VDEC_E_OUT_CTRL1;
61 out_ctrl_ns = VDEC_E_OUT_CTRL_NS;
64 out_ctrl = VDEC_F_OUT_CTRL1;
65 out_ctrl_ns = VDEC_F_OUT_CTRL_NS;
68 out_ctrl = VDEC_G_OUT_CTRL1;
69 out_ctrl_ns = VDEC_G_OUT_CTRL_NS;
72 out_ctrl = VDEC_H_OUT_CTRL1;
73 out_ctrl_ns = VDEC_H_OUT_CTRL_NS;
77 value = cx25821_i2c_read(&dev->i2c_bus[0], out_ctrl, &tmp);
78 value &= 0xFFFFFF7F; /* clear BLUE_FIELD_EN */
80 value |= 0x00000080; /* set BLUE_FIELD_EN */
81 cx25821_i2c_write(&dev->i2c_bus[0], out_ctrl, value);
83 value = cx25821_i2c_read(&dev->i2c_bus[0], out_ctrl_ns, &tmp);
86 value |= 0x00000080; /* set BLUE_FIELD_EN */
87 cx25821_i2c_write(&dev->i2c_bus[0], out_ctrl_ns, value);
90 static int medusa_initialize_ntsc(struct cx25821_dev *dev)
97 mutex_lock(&dev->lock);
99 for (i = 0; i < MAX_DECODERS; i++) {
100 /* set video format NTSC-M */
101 value = cx25821_i2c_read(&dev->i2c_bus[0],
102 MODE_CTRL + (0x200 * i), &tmp);
104 /* enable the fast locking mode bit[16] */
106 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
107 MODE_CTRL + (0x200 * i), value);
109 /* resolution NTSC 720x480 */
110 value = cx25821_i2c_read(&dev->i2c_bus[0],
111 HORIZ_TIM_CTRL + (0x200 * i), &tmp);
114 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
115 HORIZ_TIM_CTRL + (0x200 * i), value);
117 value = cx25821_i2c_read(&dev->i2c_bus[0],
118 VERT_TIM_CTRL + (0x200 * i), &tmp);
120 value |= 0x1C1E001A; /* vblank_cnt + 2 to get camera ID */
121 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
122 VERT_TIM_CTRL + (0x200 * i), value);
124 /* chroma subcarrier step size */
125 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
126 SC_STEP_SIZE + (0x200 * i), 0x43E00000);
128 /* enable VIP optional active */
129 value = cx25821_i2c_read(&dev->i2c_bus[0],
130 OUT_CTRL_NS + (0x200 * i), &tmp);
133 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
134 OUT_CTRL_NS + (0x200 * i), value);
136 /* enable VIP optional active (VIP_OPT_AL) for direct output. */
137 value = cx25821_i2c_read(&dev->i2c_bus[0],
138 OUT_CTRL1 + (0x200 * i), &tmp);
141 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
142 OUT_CTRL1 + (0x200 * i), value);
145 * clear VPRES_VERT_EN bit, fixes the chroma run away problem
146 * when the input switching rate < 16 fields
148 value = cx25821_i2c_read(&dev->i2c_bus[0],
149 MISC_TIM_CTRL + (0x200 * i), &tmp);
150 /* disable special play detection */
151 value = setBitAtPos(value, 14);
152 value = clearBitAtPos(value, 15);
153 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
154 MISC_TIM_CTRL + (0x200 * i), value);
156 /* set vbi_gate_en to 0 */
157 value = cx25821_i2c_read(&dev->i2c_bus[0],
158 DFE_CTRL1 + (0x200 * i), &tmp);
159 value = clearBitAtPos(value, 29);
160 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
161 DFE_CTRL1 + (0x200 * i), value);
163 /* Enable the generation of blue field output if no video */
164 medusa_enable_bluefield_output(dev, i, 1);
167 for (i = 0; i < MAX_ENCODERS; i++) {
169 value = cx25821_i2c_read(&dev->i2c_bus[0],
170 DENC_A_REG_1 + (0x100 * i), &tmp);
173 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
174 DENC_A_REG_1 + (0x100 * i), value);
176 /* burst begin and burst end */
177 value = cx25821_i2c_read(&dev->i2c_bus[0],
178 DENC_A_REG_2 + (0x100 * i), &tmp);
181 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
182 DENC_A_REG_2 + (0x100 * i), value);
184 value = cx25821_i2c_read(&dev->i2c_bus[0],
185 DENC_A_REG_3 + (0x100 * i), &tmp);
188 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
189 DENC_A_REG_3 + (0x100 * i), value);
191 /* set NTSC vblank, no phase alternation, 7.5 IRE pedestal */
192 value = cx25821_i2c_read(&dev->i2c_bus[0],
193 DENC_A_REG_4 + (0x100 * i), &tmp);
196 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
197 DENC_A_REG_4 + (0x100 * i), value);
199 value = cx25821_i2c_read(&dev->i2c_bus[0],
200 DENC_A_REG_5 + (0x100 * i), &tmp);
203 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
204 DENC_A_REG_5 + (0x100 * i), value);
206 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
207 DENC_A_REG_6 + (0x100 * i), 0x009A89C1);
209 /* Subcarrier Increment */
210 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
211 DENC_A_REG_7 + (0x100 * i), 0x21F07C1F);
214 /* set picture resolutions */
216 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], HSCALE_CTRL, 0x0);
218 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], VSCALE_CTRL, 0x0);
220 /* set Bypass input format to NTSC 525 lines */
221 value = cx25821_i2c_read(&dev->i2c_bus[0], BYP_AB_CTRL, &tmp);
223 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], BYP_AB_CTRL, value);
225 mutex_unlock(&dev->lock);
230 static int medusa_PALCombInit(struct cx25821_dev *dev, int dec)
233 u32 value = 0, tmp = 0;
235 /* Setup for 2D threshold */
236 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
237 COMB_2D_HFS_CFG + (0x200 * dec), 0x20002861);
238 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
239 COMB_2D_HFD_CFG + (0x200 * dec), 0x20002861);
240 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
241 COMB_2D_LF_CFG + (0x200 * dec), 0x200A1023);
243 /* Setup flat chroma and luma thresholds */
244 value = cx25821_i2c_read(&dev->i2c_bus[0],
245 COMB_FLAT_THRESH_CTRL + (0x200 * dec), &tmp);
247 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
248 COMB_FLAT_THRESH_CTRL + (0x200 * dec), value);
250 /* set comb 2D blend */
251 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
252 COMB_2D_BLEND + (0x200 * dec), 0x210F0F0F);
254 /* COMB MISC CONTROL */
255 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
256 COMB_MISC_CTRL + (0x200 * dec), 0x41120A7F);
261 static int medusa_initialize_pal(struct cx25821_dev *dev)
268 mutex_lock(&dev->lock);
270 for (i = 0; i < MAX_DECODERS; i++) {
271 /* set video format PAL-BDGHI */
272 value = cx25821_i2c_read(&dev->i2c_bus[0],
273 MODE_CTRL + (0x200 * i), &tmp);
275 /* enable the fast locking mode bit[16] */
277 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
278 MODE_CTRL + (0x200 * i), value);
280 /* resolution PAL 720x576 */
281 value = cx25821_i2c_read(&dev->i2c_bus[0],
282 HORIZ_TIM_CTRL + (0x200 * i), &tmp);
285 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
286 HORIZ_TIM_CTRL + (0x200 * i), value);
288 /* vblank656_cnt=x26, vactive_cnt=240h, vblank_cnt=x24 */
289 value = cx25821_i2c_read(&dev->i2c_bus[0],
290 VERT_TIM_CTRL + (0x200 * i), &tmp);
292 value |= 0x28240026; /* vblank_cnt + 2 to get camera ID */
293 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
294 VERT_TIM_CTRL + (0x200 * i), value);
296 /* chroma subcarrier step size */
297 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
298 SC_STEP_SIZE + (0x200 * i), 0x5411E2D0);
300 /* enable VIP optional active */
301 value = cx25821_i2c_read(&dev->i2c_bus[0],
302 OUT_CTRL_NS + (0x200 * i), &tmp);
305 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
306 OUT_CTRL_NS + (0x200 * i), value);
308 /* enable VIP optional active (VIP_OPT_AL) for direct output. */
309 value = cx25821_i2c_read(&dev->i2c_bus[0],
310 OUT_CTRL1 + (0x200 * i), &tmp);
313 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
314 OUT_CTRL1 + (0x200 * i), value);
317 * clear VPRES_VERT_EN bit, fixes the chroma run away problem
318 * when the input switching rate < 16 fields
320 value = cx25821_i2c_read(&dev->i2c_bus[0],
321 MISC_TIM_CTRL + (0x200 * i), &tmp);
322 /* disable special play detection */
323 value = setBitAtPos(value, 14);
324 value = clearBitAtPos(value, 15);
325 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
326 MISC_TIM_CTRL + (0x200 * i), value);
328 /* set vbi_gate_en to 0 */
329 value = cx25821_i2c_read(&dev->i2c_bus[0],
330 DFE_CTRL1 + (0x200 * i), &tmp);
331 value = clearBitAtPos(value, 29);
332 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
333 DFE_CTRL1 + (0x200 * i), value);
335 medusa_PALCombInit(dev, i);
337 /* Enable the generation of blue field output if no video */
338 medusa_enable_bluefield_output(dev, i, 1);
341 for (i = 0; i < MAX_ENCODERS; i++) {
343 value = cx25821_i2c_read(&dev->i2c_bus[0],
344 DENC_A_REG_1 + (0x100 * i), &tmp);
347 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
348 DENC_A_REG_1 + (0x100 * i), value);
350 /* burst begin and burst end */
351 value = cx25821_i2c_read(&dev->i2c_bus[0],
352 DENC_A_REG_2 + (0x100 * i), &tmp);
355 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
356 DENC_A_REG_2 + (0x100 * i), value);
358 /* hblank and vactive */
359 value = cx25821_i2c_read(&dev->i2c_bus[0],
360 DENC_A_REG_3 + (0x100 * i), &tmp);
363 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
364 DENC_A_REG_3 + (0x100 * i), value);
366 /* set PAL vblank, phase alternation, 0 IRE pedestal */
367 value = cx25821_i2c_read(&dev->i2c_bus[0],
368 DENC_A_REG_4 + (0x100 * i), &tmp);
371 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
372 DENC_A_REG_4 + (0x100 * i), value);
374 value = cx25821_i2c_read(&dev->i2c_bus[0],
375 DENC_A_REG_5 + (0x100 * i), &tmp);
378 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
379 DENC_A_REG_5 + (0x100 * i), value);
381 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
382 DENC_A_REG_6 + (0x100 * i), 0x00A493CF);
384 /* Subcarrier Increment */
385 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
386 DENC_A_REG_7 + (0x100 * i), 0x2A098ACB);
389 /* set picture resolutions */
391 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], HSCALE_CTRL, 0x0);
393 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], VSCALE_CTRL, 0x0);
395 /* set Bypass input format to PAL 625 lines */
396 value = cx25821_i2c_read(&dev->i2c_bus[0], BYP_AB_CTRL, &tmp);
398 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], BYP_AB_CTRL, value);
400 mutex_unlock(&dev->lock);
405 int medusa_set_videostandard(struct cx25821_dev *dev)
407 int status = STATUS_SUCCESS;
408 u32 value = 0, tmp = 0;
410 if (dev->tvnorm & V4L2_STD_PAL_BG || dev->tvnorm & V4L2_STD_PAL_DK)
411 status = medusa_initialize_pal(dev);
413 status = medusa_initialize_ntsc(dev);
415 /* Enable DENC_A output */
416 value = cx25821_i2c_read(&dev->i2c_bus[0], DENC_A_REG_4, &tmp);
417 value = setBitAtPos(value, 4);
418 status = cx25821_i2c_write(&dev->i2c_bus[0], DENC_A_REG_4, value);
420 /* Enable DENC_B output */
421 value = cx25821_i2c_read(&dev->i2c_bus[0], DENC_B_REG_4, &tmp);
422 value = setBitAtPos(value, 4);
423 status = cx25821_i2c_write(&dev->i2c_bus[0], DENC_B_REG_4, value);
428 void medusa_set_resolution(struct cx25821_dev *dev, int width,
432 int decoder_count = 0;
435 const int MAX_WIDTH = 720;
437 mutex_lock(&dev->lock);
439 /* validate the width */
440 if (width > MAX_WIDTH) {
441 pr_info("%s(): width %d > MAX_WIDTH %d ! resetting to MAX_WIDTH\n",
442 __func__, width, MAX_WIDTH);
446 if (decoder_select <= 7 && decoder_select >= 0) {
447 decoder = decoder_select;
448 decoder_count = decoder_select + 1;
451 decoder_count = _num_decoders;
481 for (; decoder < decoder_count; decoder++) {
482 /* write scaling values for each decoder */
483 cx25821_i2c_write(&dev->i2c_bus[0],
484 HSCALE_CTRL + (0x200 * decoder), hscale);
485 cx25821_i2c_write(&dev->i2c_bus[0],
486 VSCALE_CTRL + (0x200 * decoder), vscale);
489 mutex_unlock(&dev->lock);
492 static void medusa_set_decoderduration(struct cx25821_dev *dev, int decoder,
497 u32 disp_cnt_reg = DISP_AB_CNT;
499 mutex_lock(&dev->lock);
502 if (decoder < VDEC_A || decoder > VDEC_H) {
503 mutex_unlock(&dev->lock);
512 disp_cnt_reg = DISP_CD_CNT;
516 disp_cnt_reg = DISP_EF_CNT;
520 disp_cnt_reg = DISP_GH_CNT;
524 _display_field_cnt[decoder] = duration;
526 /* update hardware */
527 fld_cnt = cx25821_i2c_read(&dev->i2c_bus[0], disp_cnt_reg, &tmp);
529 if (!(decoder % 2)) { /* EVEN decoder */
530 fld_cnt &= 0xFFFF0000;
533 fld_cnt &= 0x0000FFFF;
534 fld_cnt |= ((u32) duration) << 16;
537 cx25821_i2c_write(&dev->i2c_bus[0], disp_cnt_reg, fld_cnt);
539 mutex_unlock(&dev->lock);
542 /* Map to Medusa register setting */
543 static int mapM(int srcMin, int srcMax, int srcVal, int dstMin, int dstMax,
550 if ((srcMin == srcMax) || (srcVal < srcMin) || (srcVal > srcMax))
553 * This is the overall expression used:
555 * (srcVal - srcMin)*(dstMax - dstMin) / (srcMax - srcMin) + dstMin;
556 * but we need to account for rounding so below we use the modulus
557 * operator to find the remainder and increment if necessary.
559 numerator = (srcVal - srcMin) * (dstMax - dstMin);
560 denominator = srcMax - srcMin;
561 quotient = numerator / denominator;
563 if (2 * (numerator % denominator) >= denominator)
566 *dstVal = quotient + dstMin;
571 static unsigned long convert_to_twos(long numeric, unsigned long bits_len)
578 temp = ~(abs(numeric) & 0xFF);
584 int medusa_set_brightness(struct cx25821_dev *dev, int brightness, int decoder)
588 u32 val = 0, tmp = 0;
590 mutex_lock(&dev->lock);
591 if ((brightness > VIDEO_PROCAMP_MAX) ||
592 (brightness < VIDEO_PROCAMP_MIN)) {
593 mutex_unlock(&dev->lock);
596 ret_val = mapM(VIDEO_PROCAMP_MIN, VIDEO_PROCAMP_MAX, brightness,
597 SIGNED_BYTE_MIN, SIGNED_BYTE_MAX, &value);
598 value = convert_to_twos(value, 8);
599 val = cx25821_i2c_read(&dev->i2c_bus[0],
600 VDEC_A_BRITE_CTRL + (0x200 * decoder), &tmp);
602 ret_val |= cx25821_i2c_write(&dev->i2c_bus[0],
603 VDEC_A_BRITE_CTRL + (0x200 * decoder), val | value);
604 mutex_unlock(&dev->lock);
608 int medusa_set_contrast(struct cx25821_dev *dev, int contrast, int decoder)
612 u32 val = 0, tmp = 0;
614 mutex_lock(&dev->lock);
616 if ((contrast > VIDEO_PROCAMP_MAX) || (contrast < VIDEO_PROCAMP_MIN)) {
617 mutex_unlock(&dev->lock);
621 ret_val = mapM(VIDEO_PROCAMP_MIN, VIDEO_PROCAMP_MAX, contrast,
622 UNSIGNED_BYTE_MIN, UNSIGNED_BYTE_MAX, &value);
623 val = cx25821_i2c_read(&dev->i2c_bus[0],
624 VDEC_A_CNTRST_CTRL + (0x200 * decoder), &tmp);
626 ret_val |= cx25821_i2c_write(&dev->i2c_bus[0],
627 VDEC_A_CNTRST_CTRL + (0x200 * decoder), val | value);
629 mutex_unlock(&dev->lock);
633 int medusa_set_hue(struct cx25821_dev *dev, int hue, int decoder)
637 u32 val = 0, tmp = 0;
639 mutex_lock(&dev->lock);
641 if ((hue > VIDEO_PROCAMP_MAX) || (hue < VIDEO_PROCAMP_MIN)) {
642 mutex_unlock(&dev->lock);
646 ret_val = mapM(VIDEO_PROCAMP_MIN, VIDEO_PROCAMP_MAX, hue,
647 SIGNED_BYTE_MIN, SIGNED_BYTE_MAX, &value);
649 value = convert_to_twos(value, 8);
650 val = cx25821_i2c_read(&dev->i2c_bus[0],
651 VDEC_A_HUE_CTRL + (0x200 * decoder), &tmp);
654 ret_val |= cx25821_i2c_write(&dev->i2c_bus[0],
655 VDEC_A_HUE_CTRL + (0x200 * decoder), val | value);
657 mutex_unlock(&dev->lock);
661 int medusa_set_saturation(struct cx25821_dev *dev, int saturation, int decoder)
665 u32 val = 0, tmp = 0;
667 mutex_lock(&dev->lock);
669 if ((saturation > VIDEO_PROCAMP_MAX) ||
670 (saturation < VIDEO_PROCAMP_MIN)) {
671 mutex_unlock(&dev->lock);
675 ret_val = mapM(VIDEO_PROCAMP_MIN, VIDEO_PROCAMP_MAX, saturation,
676 UNSIGNED_BYTE_MIN, UNSIGNED_BYTE_MAX, &value);
678 val = cx25821_i2c_read(&dev->i2c_bus[0],
679 VDEC_A_USAT_CTRL + (0x200 * decoder), &tmp);
681 ret_val |= cx25821_i2c_write(&dev->i2c_bus[0],
682 VDEC_A_USAT_CTRL + (0x200 * decoder), val | value);
684 val = cx25821_i2c_read(&dev->i2c_bus[0],
685 VDEC_A_VSAT_CTRL + (0x200 * decoder), &tmp);
687 ret_val |= cx25821_i2c_write(&dev->i2c_bus[0],
688 VDEC_A_VSAT_CTRL + (0x200 * decoder), val | value);
690 mutex_unlock(&dev->lock);
694 /* Program the display sequence and monitor output. */
696 int medusa_video_init(struct cx25821_dev *dev)
698 u32 value = 0, tmp = 0;
702 mutex_lock(&dev->lock);
704 _num_decoders = dev->_max_num_decoders;
706 /* disable Auto source selection on all video decoders */
707 value = cx25821_i2c_read(&dev->i2c_bus[0], MON_A_CTRL, &tmp);
709 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], MON_A_CTRL, value);
714 /* Turn off Master source switch enable */
715 value = cx25821_i2c_read(&dev->i2c_bus[0], MON_A_CTRL, &tmp);
717 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], MON_A_CTRL, value);
722 mutex_unlock(&dev->lock);
724 for (i = 0; i < _num_decoders; i++)
725 medusa_set_decoderduration(dev, i, _display_field_cnt[i]);
727 mutex_lock(&dev->lock);
729 /* Select monitor as DENC A input, power up the DAC */
730 value = cx25821_i2c_read(&dev->i2c_bus[0], DENC_AB_CTRL, &tmp);
732 value |= 0x00090008; /* set en_active */
733 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], DENC_AB_CTRL, value);
738 /* enable input is VIP/656 */
739 value = cx25821_i2c_read(&dev->i2c_bus[0], BYP_AB_CTRL, &tmp);
740 value |= 0x00040100; /* enable VIP */
741 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], BYP_AB_CTRL, value);
746 /* select AFE clock to output mode */
747 value = cx25821_i2c_read(&dev->i2c_bus[0], AFE_AB_DIAG_CTRL, &tmp);
749 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], AFE_AB_DIAG_CTRL,
755 /* Turn on all of the data out and control output pins. */
756 value = cx25821_i2c_read(&dev->i2c_bus[0], PIN_OE_CTRL, &tmp);
758 if (_num_decoders == MAX_DECODERS) {
760 * Note: The octal board does not support control pins(bit16-19)
761 * These bits are ignored in the octal board.
763 * disable VDEC A-C port, default to Mobilygen Interface
767 /* disable VDEC A-C port, default to Mobilygen Interface */
772 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], PIN_OE_CTRL, value);
778 mutex_unlock(&dev->lock);
780 ret_val = medusa_set_videostandard(dev);
785 mutex_unlock(&dev->lock);