drivers/media/platform/coda/coda-bit.c

   1 /*
   2  * Coda multi-standard codec IP - BIT processor functions
   3  *
   4  * Copyright (C) 2012 Vista Silicon S.L.
   5  *    Javier Martin, <javier.martin@vista-silicon.com>
   6  *    Xavier Duret
   7  * Copyright (C) 2012-2014 Philipp Zabel, Pengutronix
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License, or
  12  * (at your option) any later version.
  13  */
  14
  15 #include <linux/clk.h>
  16 #include <linux/irqreturn.h>
  17 #include <linux/kernel.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/reset.h>
  20 #include <linux/slab.h>
  21 #include <linux/videodev2.h>
  22
  23 #include <media/v4l2-common.h>
  24 #include <media/v4l2-ctrls.h>
  25 #include <media/v4l2-fh.h>
  26 #include <media/v4l2-mem2mem.h>
  27 #include <media/videobuf2-core.h>
  28 #include <media/videobuf2-dma-contig.h>
  29 #include <media/videobuf2-vmalloc.h>
  30
  31 #include "coda.h"
  32
  33 #define CODA7_PS_BUF_SIZE       0x28000
  34 #define CODA9_PS_SAVE_SIZE      (512 * 1024)
  35
  36 #define CODA_DEFAULT_GAMMA      4096
  37 #define CODA9_DEFAULT_GAMMA     24576   /* 0.75 * 32768 */
  38
  39 static inline int coda_is_initialized(struct coda_dev *dev)
  40 {
  41         return coda_read(dev, CODA_REG_BIT_CUR_PC) != 0;
  42 }
  43
  44 static inline unsigned long coda_isbusy(struct coda_dev *dev)
  45 {
  46         return coda_read(dev, CODA_REG_BIT_BUSY);
  47 }
  48
  49 static int coda_wait_timeout(struct coda_dev *dev)
  50 {
  51         unsigned long timeout = jiffies + msecs_to_jiffies(1000);
  52
  53         while (coda_isbusy(dev)) {
  54                 if (time_after(jiffies, timeout))
  55                         return -ETIMEDOUT;
  56         }
  57         return 0;
  58 }
  59
  60 static void coda_command_async(struct coda_ctx *ctx, int cmd)
  61 {
  62         struct coda_dev *dev = ctx->dev;
  63
  64         if (dev->devtype->product == CODA_960 ||
  65             dev->devtype->product == CODA_7541) {
  66                 /* Restore context related registers to CODA */
  67                 coda_write(dev, ctx->bit_stream_param,
  68                                 CODA_REG_BIT_BIT_STREAM_PARAM);
  69                 coda_write(dev, ctx->frm_dis_flg,
  70                                 CODA_REG_BIT_FRM_DIS_FLG(ctx->reg_idx));
  71                 coda_write(dev, ctx->frame_mem_ctrl,
  72                                 CODA_REG_BIT_FRAME_MEM_CTRL);
  73                 coda_write(dev, ctx->workbuf.paddr, CODA_REG_BIT_WORK_BUF_ADDR);
  74         }
  75
  76         if (dev->devtype->product == CODA_960) {
  77                 coda_write(dev, 1, CODA9_GDI_WPROT_ERR_CLR);
  78                 coda_write(dev, 0, CODA9_GDI_WPROT_RGN_EN);
  79         }
  80
  81         coda_write(dev, CODA_REG_BIT_BUSY_FLAG, CODA_REG_BIT_BUSY);
  82
  83         coda_write(dev, ctx->idx, CODA_REG_BIT_RUN_INDEX);
  84         coda_write(dev, ctx->params.codec_mode, CODA_REG_BIT_RUN_COD_STD);
  85         coda_write(dev, ctx->params.codec_mode_aux, CODA7_REG_BIT_RUN_AUX_STD);
  86
  87         coda_write(dev, cmd, CODA_REG_BIT_RUN_COMMAND);
  88 }
  89
  90 static int coda_command_sync(struct coda_ctx *ctx, int cmd)
  91 {
  92         struct coda_dev *dev = ctx->dev;
  93
  94         coda_command_async(ctx, cmd);
  95         return coda_wait_timeout(dev);
  96 }
  97
  98 int coda_hw_reset(struct coda_ctx *ctx)
  99 {
 100         struct coda_dev *dev = ctx->dev;
 101         unsigned long timeout;
 102         unsigned int idx;
 103         int ret;
 104
 105         if (!dev->rstc)
 106                 return -ENOENT;
 107
 108         idx = coda_read(dev, CODA_REG_BIT_RUN_INDEX);
 109
 110         if (dev->devtype->product == CODA_960) {
 111                 timeout = jiffies + msecs_to_jiffies(100);
 112                 coda_write(dev, 0x11, CODA9_GDI_BUS_CTRL);
 113                 while (coda_read(dev, CODA9_GDI_BUS_STATUS) != 0x77) {
 114                         if (time_after(jiffies, timeout))
 115                                 return -ETIME;
 116                         cpu_relax();
 117                 }
 118         }
 119
 120         ret = reset_control_reset(dev->rstc);
 121         if (ret < 0)
 122                 return ret;
 123
 124         if (dev->devtype->product == CODA_960)
 125                 coda_write(dev, 0x00, CODA9_GDI_BUS_CTRL);
 126         coda_write(dev, CODA_REG_BIT_BUSY_FLAG, CODA_REG_BIT_BUSY);
 127         coda_write(dev, CODA_REG_RUN_ENABLE, CODA_REG_BIT_CODE_RUN);
 128         ret = coda_wait_timeout(dev);
 129         coda_write(dev, idx, CODA_REG_BIT_RUN_INDEX);
 130
 131         return ret;
 132 }
 133
 134 static void coda_kfifo_sync_from_device(struct coda_ctx *ctx)
 135 {
 136         struct __kfifo *kfifo = &ctx->bitstream_fifo.kfifo;
 137         struct coda_dev *dev = ctx->dev;
 138         u32 rd_ptr;
 139
 140         rd_ptr = coda_read(dev, CODA_REG_BIT_RD_PTR(ctx->reg_idx));
 141         kfifo->out = (kfifo->in & ~kfifo->mask) |
 142                       (rd_ptr - ctx->bitstream.paddr);
 143         if (kfifo->out > kfifo->in)
 144                 kfifo->out -= kfifo->mask + 1;
 145 }
 146
 147 static void coda_kfifo_sync_to_device_full(struct coda_ctx *ctx)
 148 {
 149         struct __kfifo *kfifo = &ctx->bitstream_fifo.kfifo;
 150         struct coda_dev *dev = ctx->dev;
 151         u32 rd_ptr, wr_ptr;
 152
 153         rd_ptr = ctx->bitstream.paddr + (kfifo->out & kfifo->mask);
 154         coda_write(dev, rd_ptr, CODA_REG_BIT_RD_PTR(ctx->reg_idx));
 155         wr_ptr = ctx->bitstream.paddr + (kfifo->in & kfifo->mask);
 156         coda_write(dev, wr_ptr, CODA_REG_BIT_WR_PTR(ctx->reg_idx));
 157 }
 158
 159 static void coda_kfifo_sync_to_device_write(struct coda_ctx *ctx)
 160 {
 161         struct __kfifo *kfifo = &ctx->bitstream_fifo.kfifo;
 162         struct coda_dev *dev = ctx->dev;
 163         u32 wr_ptr;
 164
 165         wr_ptr = ctx->bitstream.paddr + (kfifo->in & kfifo->mask);
 166         coda_write(dev, wr_ptr, CODA_REG_BIT_WR_PTR(ctx->reg_idx));
 167 }
 168
 169 static int coda_bitstream_queue(struct coda_ctx *ctx,
 170                                 struct vb2_buffer *src_buf)
 171 {
 172         u32 src_size = vb2_get_plane_payload(src_buf, 0);
 173         u32 n;
 174
 175         n = kfifo_in(&ctx->bitstream_fifo, vb2_plane_vaddr(src_buf, 0),
 176                      src_size);
 177         if (n < src_size)
 178                 return -ENOSPC;
 179
 180         dma_sync_single_for_device(&ctx->dev->plat_dev->dev,
 181                                    ctx->bitstream.paddr, ctx->bitstream.size,
 182                                    DMA_TO_DEVICE);
 183
 184         src_buf->v4l2_buf.sequence = ctx->qsequence++;
 185
 186         return 0;
 187 }
 188
 189 static bool coda_bitstream_try_queue(struct coda_ctx *ctx,
 190                                      struct vb2_buffer *src_buf)
 191 {
 192         int ret;
 193
 194         if (coda_get_bitstream_payload(ctx) +
 195             vb2_get_plane_payload(src_buf, 0) + 512 >= ctx->bitstream.size)
 196                 return false;
 197
 198         if (vb2_plane_vaddr(src_buf, 0) == NULL) {
 199                 v4l2_err(&ctx->dev->v4l2_dev, "trying to queue empty buffer\n");
 200                 return true;
 201         }
 202
 203         ret = coda_bitstream_queue(ctx, src_buf);
 204         if (ret < 0) {
 205                 v4l2_err(&ctx->dev->v4l2_dev, "bitstream buffer overflow\n");
 206                 return false;
 207         }
 208         /* Sync read pointer to device */
 209         if (ctx == v4l2_m2m_get_curr_priv(ctx->dev->m2m_dev))
 210                 coda_kfifo_sync_to_device_write(ctx);
 211
 212         ctx->hold = false;
 213
 214         return true;
 215 }
 216
 217 void coda_fill_bitstream(struct coda_ctx *ctx)
 218 {
 219         struct vb2_buffer *src_buf;
 220         struct coda_timestamp *ts;
 221
 222         while (v4l2_m2m_num_src_bufs_ready(ctx->fh.m2m_ctx) > 0) {
 223                 src_buf = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
 224
 225                 if (coda_bitstream_try_queue(ctx, src_buf)) {
 226                         /*
 227                          * Source buffer is queued in the bitstream ringbuffer;
 228                          * queue the timestamp and mark source buffer as done
 229                          */
 230                         src_buf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
 231
 232                         ts = kmalloc(sizeof(*ts), GFP_KERNEL);
 233                         if (ts) {
 234                                 ts->sequence = src_buf->v4l2_buf.sequence;
 235                                 ts->timecode = src_buf->v4l2_buf.timecode;
 236                                 ts->timestamp = src_buf->v4l2_buf.timestamp;
 237                                 list_add_tail(&ts->list, &ctx->timestamp_list);
 238                         }
 239
 240                         v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_DONE);
 241                 } else {
 242                         break;
 243                 }
 244         }
 245 }
 246
 247 void coda_bit_stream_end_flag(struct coda_ctx *ctx)
 248 {
 249         struct coda_dev *dev = ctx->dev;
 250
 251         ctx->bit_stream_param |= CODA_BIT_STREAM_END_FLAG;
 252
 253         /* If this context is currently running, update the hardware flag */
 254         if ((dev->devtype->product == CODA_960) &&
 255             coda_isbusy(dev) &&
 256             (ctx->idx == coda_read(dev, CODA_REG_BIT_RUN_INDEX))) {
 257                 coda_write(dev, ctx->bit_stream_param,
 258                            CODA_REG_BIT_BIT_STREAM_PARAM);
 259         }
 260 }
 261
 262 static void coda_parabuf_write(struct coda_ctx *ctx, int index, u32 value)
 263 {
 264         struct coda_dev *dev = ctx->dev;
 265         u32 *p = ctx->parabuf.vaddr;
 266
 267         if (dev->devtype->product == CODA_DX6)
 268                 p[index] = value;
 269         else
 270                 p[index ^ 1] = value;
 271 }
 272
 273 static void coda_free_framebuffers(struct coda_ctx *ctx)
 274 {
 275         int i;
 276
 277         for (i = 0; i < CODA_MAX_FRAMEBUFFERS; i++)
 278                 coda_free_aux_buf(ctx->dev, &ctx->internal_frames[i]);
 279 }
 280
 281 static int coda_alloc_framebuffers(struct coda_ctx *ctx,
 282                                    struct coda_q_data *q_data, u32 fourcc)
 283 {
 284         struct coda_dev *dev = ctx->dev;
 285         int width, height;
 286         dma_addr_t paddr;
 287         int ysize;
 288         int ret;
 289         int i;
 290
 291         if (ctx->codec && (ctx->codec->src_fourcc == V4L2_PIX_FMT_H264 ||
 292              ctx->codec->dst_fourcc == V4L2_PIX_FMT_H264)) {
 293                 width = round_up(q_data->width, 16);
 294                 height = round_up(q_data->height, 16);
 295         } else {
 296                 width = round_up(q_data->width, 8);
 297                 height = q_data->height;
 298         }
 299         ysize = width * height;
 300
 301         /* Allocate frame buffers */
 302         for (i = 0; i < ctx->num_internal_frames; i++) {
 303                 size_t size;
 304                 char *name;
 305
 306                 size = ysize + ysize / 2;
 307                 if (ctx->codec->src_fourcc == V4L2_PIX_FMT_H264 &&
 308                     dev->devtype->product != CODA_DX6)
 309                         size += ysize / 4;
 310                 name = kasprintf(GFP_KERNEL, "fb%d", i);
 311                 ret = coda_alloc_context_buf(ctx, &ctx->internal_frames[i],
 312                                              size, name);
 313                 kfree(name);
 314                 if (ret < 0) {
 315                         coda_free_framebuffers(ctx);
 316                         return ret;
 317                 }
 318         }
 319
 320         /* Register frame buffers in the parameter buffer */
 321         for (i = 0; i < ctx->num_internal_frames; i++) {
 322                 paddr = ctx->internal_frames[i].paddr;
 323                 /* Start addresses of Y, Cb, Cr planes */
 324                 coda_parabuf_write(ctx, i * 3 + 0, paddr);
 325                 coda_parabuf_write(ctx, i * 3 + 1, paddr + ysize);
 326                 coda_parabuf_write(ctx, i * 3 + 2, paddr + ysize + ysize / 4);
 327
 328                 /* mvcol buffer for h.264 */
 329                 if (ctx->codec->src_fourcc == V4L2_PIX_FMT_H264 &&
 330                     dev->devtype->product != CODA_DX6)
 331                         coda_parabuf_write(ctx, 96 + i,
 332                                            ctx->internal_frames[i].paddr +
 333                                            ysize + ysize/4 + ysize/4);
 334         }
 335
 336         /* mvcol buffer for mpeg4 */
 337         if ((dev->devtype->product != CODA_DX6) &&
 338             (ctx->codec->src_fourcc == V4L2_PIX_FMT_MPEG4))
 339                 coda_parabuf_write(ctx, 97, ctx->internal_frames[i].paddr +
 340                                             ysize + ysize/4 + ysize/4);
 341
 342         return 0;
 343 }
 344
 345 static void coda_free_context_buffers(struct coda_ctx *ctx)
 346 {
 347         struct coda_dev *dev = ctx->dev;
 348
 349         coda_free_aux_buf(dev, &ctx->slicebuf);
 350         coda_free_aux_buf(dev, &ctx->psbuf);
 351         if (dev->devtype->product != CODA_DX6)
 352                 coda_free_aux_buf(dev, &ctx->workbuf);
 353 }
 354
 355 static int coda_alloc_context_buffers(struct coda_ctx *ctx,
 356                                       struct coda_q_data *q_data)
 357 {
 358         struct coda_dev *dev = ctx->dev;
 359         size_t size;
 360         int ret;
 361
 362         if (dev->devtype->product == CODA_DX6)
 363                 return 0;
 364
 365         if (ctx->psbuf.vaddr) {
 366                 v4l2_err(&dev->v4l2_dev, "psmembuf still allocated\n");
 367                 return -EBUSY;
 368         }
 369         if (ctx->slicebuf.vaddr) {
 370                 v4l2_err(&dev->v4l2_dev, "slicebuf still allocated\n");
 371                 return -EBUSY;
 372         }
 373         if (ctx->workbuf.vaddr) {
 374                 v4l2_err(&dev->v4l2_dev, "context buffer still allocated\n");
 375                 ret = -EBUSY;
 376                 return -ENOMEM;
 377         }
 378
 379         if (q_data->fourcc == V4L2_PIX_FMT_H264) {
 380                 /* worst case slice size */
 381                 size = (DIV_ROUND_UP(q_data->width, 16) *
 382                         DIV_ROUND_UP(q_data->height, 16)) * 3200 / 8 + 512;
 383                 ret = coda_alloc_context_buf(ctx, &ctx->slicebuf, size,
 384                                              "slicebuf");
 385                 if (ret < 0) {
 386                         v4l2_err(&dev->v4l2_dev,
 387                                  "failed to allocate %d byte slice buffer",
 388                                  ctx->slicebuf.size);
 389                         return ret;
 390                 }
 391         }
 392
 393         if (dev->devtype->product == CODA_7541) {
 394                 ret = coda_alloc_context_buf(ctx, &ctx->psbuf,
 395                                              CODA7_PS_BUF_SIZE, "psbuf");
 396                 if (ret < 0) {
 397                         v4l2_err(&dev->v4l2_dev,
 398                                  "failed to allocate psmem buffer");
 399                         goto err;
 400                 }
 401         }
 402
 403         size = dev->devtype->workbuf_size;
 404         if (dev->devtype->product == CODA_960 &&
 405             q_data->fourcc == V4L2_PIX_FMT_H264)
 406                 size += CODA9_PS_SAVE_SIZE;
 407         ret = coda_alloc_context_buf(ctx, &ctx->workbuf, size, "workbuf");
 408         if (ret < 0) {
 409                 v4l2_err(&dev->v4l2_dev,
 410                          "failed to allocate %d byte context buffer",
 411                          ctx->workbuf.size);
 412                 goto err;
 413         }
 414
 415         return 0;
 416
 417 err:
 418         coda_free_context_buffers(ctx);
 419         return ret;
 420 }
 421
 422 static int coda_encode_header(struct coda_ctx *ctx, struct vb2_buffer *buf,
 423                               int header_code, u8 *header, int *size)
 424 {
 425         struct coda_dev *dev = ctx->dev;
 426         size_t bufsize;
 427         int ret;
 428         int i;
 429
 430         if (dev->devtype->product == CODA_960)
 431                 memset(vb2_plane_vaddr(buf, 0), 0, 64);
 432
 433         coda_write(dev, vb2_dma_contig_plane_dma_addr(buf, 0),
 434                    CODA_CMD_ENC_HEADER_BB_START);
 435         bufsize = vb2_plane_size(buf, 0);
 436         if (dev->devtype->product == CODA_960)
 437                 bufsize /= 1024;
 438         coda_write(dev, bufsize, CODA_CMD_ENC_HEADER_BB_SIZE);
 439         coda_write(dev, header_code, CODA_CMD_ENC_HEADER_CODE);
 440         ret = coda_command_sync(ctx, CODA_COMMAND_ENCODE_HEADER);
 441         if (ret < 0) {
 442                 v4l2_err(&dev->v4l2_dev, "CODA_COMMAND_ENCODE_HEADER timeout\n");
 443                 return ret;
 444         }
 445
 446         if (dev->devtype->product == CODA_960) {
 447                 for (i = 63; i > 0; i--)
 448                         if (((char *)vb2_plane_vaddr(buf, 0))[i] != 0)
 449                                 break;
 450                 *size = i + 1;
 451         } else {
 452                 *size = coda_read(dev, CODA_REG_BIT_WR_PTR(ctx->reg_idx)) -
 453                         coda_read(dev, CODA_CMD_ENC_HEADER_BB_START);
 454         }
 455         memcpy(header, vb2_plane_vaddr(buf, 0), *size);
 456
 457         return 0;
 458 }
 459
 460 static phys_addr_t coda_iram_alloc(struct coda_iram_info *iram, size_t size)
 461 {
 462         phys_addr_t ret;
 463
 464         size = round_up(size, 1024);
 465         if (size > iram->remaining)
 466                 return 0;
 467         iram->remaining -= size;
 468
 469         ret = iram->next_paddr;
 470         iram->next_paddr += size;
 471
 472         return ret;
 473 }
 474
 475 static void coda_setup_iram(struct coda_ctx *ctx)
 476 {
 477         struct coda_iram_info *iram_info = &ctx->iram_info;
 478         struct coda_dev *dev = ctx->dev;
 479         int w64, w128;
 480         int mb_width;
 481         int dbk_bits;
 482         int bit_bits;
 483         int ip_bits;
 484
 485         memset(iram_info, 0, sizeof(*iram_info));
 486         iram_info->next_paddr = dev->iram.paddr;
 487         iram_info->remaining = dev->iram.size;
 488
 489         if (!dev->iram.vaddr)
 490                 return;
 491
 492         switch (dev->devtype->product) {
 493         case CODA_7541:
 494                 dbk_bits = CODA7_USE_HOST_DBK_ENABLE | CODA7_USE_DBK_ENABLE;
 495                 bit_bits = CODA7_USE_HOST_BIT_ENABLE | CODA7_USE_BIT_ENABLE;
 496                 ip_bits = CODA7_USE_HOST_IP_ENABLE | CODA7_USE_IP_ENABLE;
 497                 break;
 498         case CODA_960:
 499                 dbk_bits = CODA9_USE_HOST_DBK_ENABLE | CODA9_USE_DBK_ENABLE;
 500                 bit_bits = CODA9_USE_HOST_BIT_ENABLE | CODA7_USE_BIT_ENABLE;
 501                 ip_bits = CODA9_USE_HOST_IP_ENABLE | CODA7_USE_IP_ENABLE;
 502                 break;
 503         default: /* CODA_DX6 */
 504                 return;
 505         }
 506
 507         if (ctx->inst_type == CODA_INST_ENCODER) {
 508                 struct coda_q_data *q_data_src;
 509
 510                 q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
 511                 mb_width = DIV_ROUND_UP(q_data_src->width, 16);
 512                 w128 = mb_width * 128;
 513                 w64 = mb_width * 64;
 514
 515                 /* Prioritize in case IRAM is too small for everything */
 516                 if (dev->devtype->product == CODA_7541) {
 517                         iram_info->search_ram_size = round_up(mb_width * 16 *
 518                                                               36 + 2048, 1024);
 519                         iram_info->search_ram_paddr = coda_iram_alloc(iram_info,
 520                                                 iram_info->search_ram_size);
 521                         if (!iram_info->search_ram_paddr) {
 522                                 pr_err("IRAM is smaller than the search ram size\n");
 523                                 goto out;
 524                         }
 525                         iram_info->axi_sram_use |= CODA7_USE_HOST_ME_ENABLE |
 526                                                    CODA7_USE_ME_ENABLE;
 527                 }
 528
 529                 /* Only H.264BP and H.263P3 are considered */
 530                 iram_info->buf_dbk_y_use = coda_iram_alloc(iram_info, w64);
 531                 iram_info->buf_dbk_c_use = coda_iram_alloc(iram_info, w64);
 532                 if (!iram_info->buf_dbk_c_use)
 533                         goto out;
 534                 iram_info->axi_sram_use |= dbk_bits;
 535
 536                 iram_info->buf_bit_use = coda_iram_alloc(iram_info, w128);
 537                 if (!iram_info->buf_bit_use)
 538                         goto out;
 539                 iram_info->axi_sram_use |= bit_bits;
 540
 541                 iram_info->buf_ip_ac_dc_use = coda_iram_alloc(iram_info, w128);
 542                 if (!iram_info->buf_ip_ac_dc_use)
 543                         goto out;
 544                 iram_info->axi_sram_use |= ip_bits;
 545
 546                 /* OVL and BTP disabled for encoder */
 547         } else if (ctx->inst_type == CODA_INST_DECODER) {
 548                 struct coda_q_data *q_data_dst;
 549
 550                 q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
 551                 mb_width = DIV_ROUND_UP(q_data_dst->width, 16);
 552                 w128 = mb_width * 128;
 553
 554                 iram_info->buf_dbk_y_use = coda_iram_alloc(iram_info, w128);
 555                 iram_info->buf_dbk_c_use = coda_iram_alloc(iram_info, w128);
 556                 if (!iram_info->buf_dbk_c_use)
 557                         goto out;
 558                 iram_info->axi_sram_use |= dbk_bits;
 559
 560                 iram_info->buf_bit_use = coda_iram_alloc(iram_info, w128);
 561                 if (!iram_info->buf_bit_use)
 562                         goto out;
 563                 iram_info->axi_sram_use |= bit_bits;
 564
 565                 iram_info->buf_ip_ac_dc_use = coda_iram_alloc(iram_info, w128);
 566                 if (!iram_info->buf_ip_ac_dc_use)
 567                         goto out;
 568                 iram_info->axi_sram_use |= ip_bits;
 569
 570                 /* OVL and BTP unused as there is no VC1 support yet */
 571         }
 572
 573 out:
 574         if (!(iram_info->axi_sram_use & CODA7_USE_HOST_IP_ENABLE))
 575                 v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
 576                          "IRAM smaller than needed\n");
 577
 578         if (dev->devtype->product == CODA_7541) {
 579                 /* TODO - Enabling these causes picture errors on CODA7541 */
 580                 if (ctx->inst_type == CODA_INST_DECODER) {
 581                         /* fw 1.4.50 */
 582                         iram_info->axi_sram_use &= ~(CODA7_USE_HOST_IP_ENABLE |
 583                                                      CODA7_USE_IP_ENABLE);
 584                 } else {
 585                         /* fw 13.4.29 */
 586                         iram_info->axi_sram_use &= ~(CODA7_USE_HOST_IP_ENABLE |
 587                                                      CODA7_USE_HOST_DBK_ENABLE |
 588                                                      CODA7_USE_IP_ENABLE |
 589                                                      CODA7_USE_DBK_ENABLE);
 590                 }
 591         }
 592 }
 593
 594 static u32 coda_supported_firmwares[] = {
 595         CODA_FIRMWARE_VERNUM(CODA_DX6, 2, 2, 5),
 596         CODA_FIRMWARE_VERNUM(CODA_7541, 1, 4, 50),
 597         CODA_FIRMWARE_VERNUM(CODA_960, 2, 1, 5),
 598 };
 599
 600 static bool coda_firmware_supported(u32 vernum)
 601 {
 602         int i;
 603
 604         for (i = 0; i < ARRAY_SIZE(coda_supported_firmwares); i++)
 605                 if (vernum == coda_supported_firmwares[i])
 606                         return true;
 607         return false;
 608 }
 609
 610 int coda_check_firmware(struct coda_dev *dev)
 611 {
 612         u16 product, major, minor, release;
 613         u32 data;
 614         int ret;
 615
 616         ret = clk_prepare_enable(dev->clk_per);
 617         if (ret)
 618                 goto err_clk_per;
 619
 620         ret = clk_prepare_enable(dev->clk_ahb);
 621         if (ret)
 622                 goto err_clk_ahb;
 623
 624         coda_write(dev, 0, CODA_CMD_FIRMWARE_VERNUM);
 625         coda_write(dev, CODA_REG_BIT_BUSY_FLAG, CODA_REG_BIT_BUSY);
 626         coda_write(dev, 0, CODA_REG_BIT_RUN_INDEX);
 627         coda_write(dev, 0, CODA_REG_BIT_RUN_COD_STD);
 628         coda_write(dev, CODA_COMMAND_FIRMWARE_GET, CODA_REG_BIT_RUN_COMMAND);
 629         if (coda_wait_timeout(dev)) {
 630                 v4l2_err(&dev->v4l2_dev, "firmware get command error\n");
 631                 ret = -EIO;
 632                 goto err_run_cmd;
 633         }
 634
 635         if (dev->devtype->product == CODA_960) {
 636                 data = coda_read(dev, CODA9_CMD_FIRMWARE_CODE_REV);
 637                 v4l2_info(&dev->v4l2_dev, "Firmware code revision: %d\n",
 638                           data);
 639         }
 640
 641         /* Check we are compatible with the loaded firmware */
 642         data = coda_read(dev, CODA_CMD_FIRMWARE_VERNUM);
 643         product = CODA_FIRMWARE_PRODUCT(data);
 644         major = CODA_FIRMWARE_MAJOR(data);
 645         minor = CODA_FIRMWARE_MINOR(data);
 646         release = CODA_FIRMWARE_RELEASE(data);
 647
 648         clk_disable_unprepare(dev->clk_per);
 649         clk_disable_unprepare(dev->clk_ahb);
 650
 651         if (product != dev->devtype->product) {
 652                 v4l2_err(&dev->v4l2_dev,
 653                          "Wrong firmware. Hw: %s, Fw: %s, Version: %u.%u.%u\n",
 654                          coda_product_name(dev->devtype->product),
 655                          coda_product_name(product), major, minor, release);
 656                 return -EINVAL;
 657         }
 658
 659         v4l2_info(&dev->v4l2_dev, "Initialized %s.\n",
 660                   coda_product_name(product));
 661
 662         if (coda_firmware_supported(data)) {
 663                 v4l2_info(&dev->v4l2_dev, "Firmware version: %u.%u.%u\n",
 664                           major, minor, release);
 665         } else {
 666                 v4l2_warn(&dev->v4l2_dev,
 667                           "Unsupported firmware version: %u.%u.%u\n",
 668                           major, minor, release);
 669         }
 670
 671         return 0;
 672
 673 err_run_cmd:
 674         clk_disable_unprepare(dev->clk_ahb);
 675 err_clk_ahb:
 676         clk_disable_unprepare(dev->clk_per);
 677 err_clk_per:
 678         return ret;
 679 }
 680
 681 /*
 682  * Encoder context operations
 683  */
 684
 685 static int coda_start_encoding(struct coda_ctx *ctx)
 686 {
 687         struct coda_dev *dev = ctx->dev;
 688         struct v4l2_device *v4l2_dev = &dev->v4l2_dev;
 689         struct coda_q_data *q_data_src, *q_data_dst;
 690         u32 bitstream_buf, bitstream_size;
 691         struct vb2_buffer *buf;
 692         int gamma, ret, value;
 693         u32 dst_fourcc;
 694
 695         q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
 696         q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
 697         dst_fourcc = q_data_dst->fourcc;
 698
 699         /* Allocate per-instance buffers */
 700         ret = coda_alloc_context_buffers(ctx, q_data_src);
 701         if (ret < 0)
 702                 return ret;
 703
 704         buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
 705         bitstream_buf = vb2_dma_contig_plane_dma_addr(buf, 0);
 706         bitstream_size = q_data_dst->sizeimage;
 707
 708         if (!coda_is_initialized(dev)) {
 709                 v4l2_err(v4l2_dev, "coda is not initialized.\n");
 710                 return -EFAULT;
 711         }
 712
 713         mutex_lock(&dev->coda_mutex);
 714
 715         coda_write(dev, ctx->parabuf.paddr, CODA_REG_BIT_PARA_BUF_ADDR);
 716         coda_write(dev, bitstream_buf, CODA_REG_BIT_RD_PTR(ctx->reg_idx));
 717         coda_write(dev, bitstream_buf, CODA_REG_BIT_WR_PTR(ctx->reg_idx));
 718         switch (dev->devtype->product) {
 719         case CODA_DX6:
 720                 coda_write(dev, CODADX6_STREAM_BUF_DYNALLOC_EN |
 721                         CODADX6_STREAM_BUF_PIC_RESET, CODA_REG_BIT_STREAM_CTRL);
 722                 break;
 723         case CODA_960:
 724                 coda_write(dev, 0, CODA9_GDI_WPROT_RGN_EN);
 725                 /* fallthrough */
 726         case CODA_7541:
 727                 coda_write(dev, CODA7_STREAM_BUF_DYNALLOC_EN |
 728                         CODA7_STREAM_BUF_PIC_RESET, CODA_REG_BIT_STREAM_CTRL);
 729                 break;
 730         }
 731
 732         value = coda_read(dev, CODA_REG_BIT_FRAME_MEM_CTRL);
 733         value &= ~(1 << 2 | 0x7 << 9);
 734         ctx->frame_mem_ctrl = value;
 735         coda_write(dev, value, CODA_REG_BIT_FRAME_MEM_CTRL);
 736
 737         if (dev->devtype->product == CODA_DX6) {
 738                 /* Configure the coda */
 739                 coda_write(dev, dev->iram.paddr,
 740                            CODADX6_REG_BIT_SEARCH_RAM_BASE_ADDR);
 741         }
 742
 743         /* Could set rotation here if needed */
 744         switch (dev->devtype->product) {
 745         case CODA_DX6:
 746                 value = (q_data_src->width & CODADX6_PICWIDTH_MASK)
 747                         << CODADX6_PICWIDTH_OFFSET;
 748                 value |= (q_data_src->height & CODADX6_PICHEIGHT_MASK)
 749                          << CODA_PICHEIGHT_OFFSET;
 750                 break;
 751         case CODA_7541:
 752                 if (dst_fourcc == V4L2_PIX_FMT_H264) {
 753                         value = (round_up(q_data_src->width, 16) &
 754                                  CODA7_PICWIDTH_MASK) << CODA7_PICWIDTH_OFFSET;
 755                         value |= (round_up(q_data_src->height, 16) &
 756                                  CODA7_PICHEIGHT_MASK) << CODA_PICHEIGHT_OFFSET;
 757                         break;
 758                 }
 759                 /* fallthrough */
 760         case CODA_960:
 761                 value = (q_data_src->width & CODA7_PICWIDTH_MASK)
 762                         << CODA7_PICWIDTH_OFFSET;
 763                 value |= (q_data_src->height & CODA7_PICHEIGHT_MASK)
 764                          << CODA_PICHEIGHT_OFFSET;
 765         }
 766         coda_write(dev, value, CODA_CMD_ENC_SEQ_SRC_SIZE);
 767         coda_write(dev, ctx->params.framerate,
 768                    CODA_CMD_ENC_SEQ_SRC_F_RATE);
 769
 770         ctx->params.codec_mode = ctx->codec->mode;
 771         switch (dst_fourcc) {
 772         case V4L2_PIX_FMT_MPEG4:
 773                 if (dev->devtype->product == CODA_960)
 774                         coda_write(dev, CODA9_STD_MPEG4,
 775                                    CODA_CMD_ENC_SEQ_COD_STD);
 776                 else
 777                         coda_write(dev, CODA_STD_MPEG4,
 778                                    CODA_CMD_ENC_SEQ_COD_STD);
 779                 coda_write(dev, 0, CODA_CMD_ENC_SEQ_MP4_PARA);
 780                 break;
 781         case V4L2_PIX_FMT_H264:
 782                 if (dev->devtype->product == CODA_960)
 783                         coda_write(dev, CODA9_STD_H264,
 784                                    CODA_CMD_ENC_SEQ_COD_STD);
 785                 else
 786                         coda_write(dev, CODA_STD_H264,
 787                                    CODA_CMD_ENC_SEQ_COD_STD);
 788                 if (ctx->params.h264_deblk_enabled) {
 789                         value = ((ctx->params.h264_deblk_alpha &
 790                                   CODA_264PARAM_DEBLKFILTEROFFSETALPHA_MASK) <<
 791                                  CODA_264PARAM_DEBLKFILTEROFFSETALPHA_OFFSET) |
 792                                 ((ctx->params.h264_deblk_beta &
 793                                   CODA_264PARAM_DEBLKFILTEROFFSETBETA_MASK) <<
 794                                  CODA_264PARAM_DEBLKFILTEROFFSETBETA_OFFSET);
 795                 } else {
 796                         value = 1 << CODA_264PARAM_DISABLEDEBLK_OFFSET;
 797                 }
 798                 coda_write(dev, value, CODA_CMD_ENC_SEQ_264_PARA);
 799                 break;
 800         default:
 801                 v4l2_err(v4l2_dev,
 802                          "dst format (0x%08x) invalid.\n", dst_fourcc);
 803                 ret = -EINVAL;
 804                 goto out;
 805         }
 806
 807         switch (ctx->params.slice_mode) {
 808         case V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_SINGLE:
 809                 value = 0;
 810                 break;
 811         case V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_MB:
 812                 value  = (ctx->params.slice_max_mb & CODA_SLICING_SIZE_MASK)
 813                          << CODA_SLICING_SIZE_OFFSET;
 814                 value |= (1 & CODA_SLICING_UNIT_MASK)
 815                          << CODA_SLICING_UNIT_OFFSET;
 816                 value |=  1 & CODA_SLICING_MODE_MASK;
 817                 break;
 818         case V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_BYTES:
 819                 value  = (ctx->params.slice_max_bits & CODA_SLICING_SIZE_MASK)
 820                          << CODA_SLICING_SIZE_OFFSET;
 821                 value |= (0 & CODA_SLICING_UNIT_MASK)
 822                          << CODA_SLICING_UNIT_OFFSET;
 823                 value |=  1 & CODA_SLICING_MODE_MASK;
 824                 break;
 825         }
 826         coda_write(dev, value, CODA_CMD_ENC_SEQ_SLICE_MODE);
 827         value = ctx->params.gop_size & CODA_GOP_SIZE_MASK;
 828         coda_write(dev, value, CODA_CMD_ENC_SEQ_GOP_SIZE);
 829
 830         if (ctx->params.bitrate) {
 831                 /* Rate control enabled */
 832                 value = (ctx->params.bitrate & CODA_RATECONTROL_BITRATE_MASK)
 833                         << CODA_RATECONTROL_BITRATE_OFFSET;
 834                 value |=  1 & CODA_RATECONTROL_ENABLE_MASK;
 835                 if (dev->devtype->product == CODA_960)
 836                         value |= BIT(31); /* disable autoskip */
 837         } else {
 838                 value = 0;
 839         }
 840         coda_write(dev, value, CODA_CMD_ENC_SEQ_RC_PARA);
 841
 842         coda_write(dev, 0, CODA_CMD_ENC_SEQ_RC_BUF_SIZE);
 843         coda_write(dev, ctx->params.intra_refresh,
 844                    CODA_CMD_ENC_SEQ_INTRA_REFRESH);
 845
 846         coda_write(dev, bitstream_buf, CODA_CMD_ENC_SEQ_BB_START);
 847         coda_write(dev, bitstream_size / 1024, CODA_CMD_ENC_SEQ_BB_SIZE);
 848
 849
 850         value = 0;
 851         if (dev->devtype->product == CODA_960)
 852                 gamma = CODA9_DEFAULT_GAMMA;
 853         else
 854                 gamma = CODA_DEFAULT_GAMMA;
 855         if (gamma > 0) {
 856                 coda_write(dev, (gamma & CODA_GAMMA_MASK) << CODA_GAMMA_OFFSET,
 857                            CODA_CMD_ENC_SEQ_RC_GAMMA);
 858         }
 859
 860         if (ctx->params.h264_min_qp || ctx->params.h264_max_qp) {
 861                 coda_write(dev,
 862                            ctx->params.h264_min_qp << CODA_QPMIN_OFFSET |
 863                            ctx->params.h264_max_qp << CODA_QPMAX_OFFSET,
 864                            CODA_CMD_ENC_SEQ_RC_QP_MIN_MAX);
 865         }
 866         if (dev->devtype->product == CODA_960) {
 867                 if (ctx->params.h264_max_qp)
 868                         value |= 1 << CODA9_OPTION_RCQPMAX_OFFSET;
 869                 if (CODA_DEFAULT_GAMMA > 0)
 870                         value |= 1 << CODA9_OPTION_GAMMA_OFFSET;
 871         } else {
 872                 if (CODA_DEFAULT_GAMMA > 0) {
 873                         if (dev->devtype->product == CODA_DX6)
 874                                 value |= 1 << CODADX6_OPTION_GAMMA_OFFSET;
 875                         else
 876                                 value |= 1 << CODA7_OPTION_GAMMA_OFFSET;
 877                 }
 878                 if (ctx->params.h264_min_qp)
 879                         value |= 1 << CODA7_OPTION_RCQPMIN_OFFSET;
 880                 if (ctx->params.h264_max_qp)
 881                         value |= 1 << CODA7_OPTION_RCQPMAX_OFFSET;
 882         }
 883         coda_write(dev, value, CODA_CMD_ENC_SEQ_OPTION);
 884
 885         coda_write(dev, 0, CODA_CMD_ENC_SEQ_RC_INTERVAL_MODE);
 886
 887         coda_setup_iram(ctx);
 888
 889         if (dst_fourcc == V4L2_PIX_FMT_H264) {
 890                 switch (dev->devtype->product) {
 891                 case CODA_DX6:
 892                         value = FMO_SLICE_SAVE_BUF_SIZE << 7;
 893                         coda_write(dev, value, CODADX6_CMD_ENC_SEQ_FMO);
 894                         break;
 895                 case CODA_7541:
 896                         coda_write(dev, ctx->iram_info.search_ram_paddr,
 897                                         CODA7_CMD_ENC_SEQ_SEARCH_BASE);
 898                         coda_write(dev, ctx->iram_info.search_ram_size,
 899                                         CODA7_CMD_ENC_SEQ_SEARCH_SIZE);
 900                         break;
 901                 case CODA_960:
 902                         coda_write(dev, 0, CODA9_CMD_ENC_SEQ_ME_OPTION);
 903                         coda_write(dev, 0, CODA9_CMD_ENC_SEQ_INTRA_WEIGHT);
 904                 }
 905         }
 906
 907         ret = coda_command_sync(ctx, CODA_COMMAND_SEQ_INIT);
 908         if (ret < 0) {
 909                 v4l2_err(v4l2_dev, "CODA_COMMAND_SEQ_INIT timeout\n");
 910                 goto out;
 911         }
 912
 913         if (coda_read(dev, CODA_RET_ENC_SEQ_SUCCESS) == 0) {
 914                 v4l2_err(v4l2_dev, "CODA_COMMAND_SEQ_INIT failed\n");
 915                 ret = -EFAULT;
 916                 goto out;
 917         }
 918
 919         if (dev->devtype->product == CODA_960)
 920                 ctx->num_internal_frames = 4;
 921         else
 922                 ctx->num_internal_frames = 2;
 923         ret = coda_alloc_framebuffers(ctx, q_data_src, dst_fourcc);
 924         if (ret < 0) {
 925                 v4l2_err(v4l2_dev, "failed to allocate framebuffers\n");
 926                 goto out;
 927         }
 928
 929         coda_write(dev, ctx->num_internal_frames, CODA_CMD_SET_FRAME_BUF_NUM);
 930         coda_write(dev, q_data_src->bytesperline,
 931                         CODA_CMD_SET_FRAME_BUF_STRIDE);
 932         if (dev->devtype->product == CODA_7541) {
 933                 coda_write(dev, q_data_src->bytesperline,
 934                                 CODA7_CMD_SET_FRAME_SOURCE_BUF_STRIDE);
 935         }
 936         if (dev->devtype->product != CODA_DX6) {
 937                 coda_write(dev, ctx->iram_info.buf_bit_use,
 938                                 CODA7_CMD_SET_FRAME_AXI_BIT_ADDR);
 939                 coda_write(dev, ctx->iram_info.buf_ip_ac_dc_use,
 940                                 CODA7_CMD_SET_FRAME_AXI_IPACDC_ADDR);
 941                 coda_write(dev, ctx->iram_info.buf_dbk_y_use,
 942                                 CODA7_CMD_SET_FRAME_AXI_DBKY_ADDR);
 943                 coda_write(dev, ctx->iram_info.buf_dbk_c_use,
 944                                 CODA7_CMD_SET_FRAME_AXI_DBKC_ADDR);
 945                 coda_write(dev, ctx->iram_info.buf_ovl_use,
 946                                 CODA7_CMD_SET_FRAME_AXI_OVL_ADDR);
 947                 if (dev->devtype->product == CODA_960) {
 948                         coda_write(dev, ctx->iram_info.buf_btp_use,
 949                                         CODA9_CMD_SET_FRAME_AXI_BTP_ADDR);
 950
 951                         /* FIXME */
 952                         coda_write(dev, ctx->internal_frames[2].paddr,
 953                                    CODA9_CMD_SET_FRAME_SUBSAMP_A);
 954                         coda_write(dev, ctx->internal_frames[3].paddr,
 955                                    CODA9_CMD_SET_FRAME_SUBSAMP_B);
 956                 }
 957         }
 958
 959         ret = coda_command_sync(ctx, CODA_COMMAND_SET_FRAME_BUF);
 960         if (ret < 0) {
 961                 v4l2_err(v4l2_dev, "CODA_COMMAND_SET_FRAME_BUF timeout\n");
 962                 goto out;
 963         }
 964
 965         /* Save stream headers */
 966         buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
 967         switch (dst_fourcc) {
 968         case V4L2_PIX_FMT_H264:
 969                 /*
 970                  * Get SPS in the first frame and copy it to an
 971                  * intermediate buffer.
 972                  */
 973                 ret = coda_encode_header(ctx, buf, CODA_HEADER_H264_SPS,
 974                                          &ctx->vpu_header[0][0],
 975                                          &ctx->vpu_header_size[0]);
 976                 if (ret < 0)
 977                         goto out;
 978
 979                 /*
 980                  * Get PPS in the first frame and copy it to an
 981                  * intermediate buffer.
 982                  */
 983                 ret = coda_encode_header(ctx, buf, CODA_HEADER_H264_PPS,
 984                                          &ctx->vpu_header[1][0],
 985                                          &ctx->vpu_header_size[1]);
 986                 if (ret < 0)
 987                         goto out;
 988
 989                 /*
 990                  * Length of H.264 headers is variable and thus it might not be
 991                  * aligned for the coda to append the encoded frame. In that is
 992                  * the case a filler NAL must be added to header 2.
 993                  */
 994                 ctx->vpu_header_size[2] = coda_h264_padding(
 995                                         (ctx->vpu_header_size[0] +
 996                                          ctx->vpu_header_size[1]),
 997                                          ctx->vpu_header[2]);
 998                 break;
 999         case V4L2_PIX_FMT_MPEG4:
1000                 /*
1001                  * Get VOS in the first frame and copy it to an
1002                  * intermediate buffer
1003                  */
1004                 ret = coda_encode_header(ctx, buf, CODA_HEADER_MP4V_VOS,
1005                                          &ctx->vpu_header[0][0],
1006                                          &ctx->vpu_header_size[0]);
1007                 if (ret < 0)
1008                         goto out;
1009
1010                 ret = coda_encode_header(ctx, buf, CODA_HEADER_MP4V_VIS,
1011                                          &ctx->vpu_header[1][0],
1012                                          &ctx->vpu_header_size[1]);
1013                 if (ret < 0)
1014                         goto out;
1015
1016                 ret = coda_encode_header(ctx, buf, CODA_HEADER_MP4V_VOL,
1017                                          &ctx->vpu_header[2][0],
1018                                          &ctx->vpu_header_size[2]);
1019                 if (ret < 0)
1020                         goto out;
1021                 break;
1022         default:
1023                 /* No more formats need to save headers at the moment */
1024                 break;
1025         }
1026
1027 out:
1028         mutex_unlock(&dev->coda_mutex);
1029         return ret;
1030 }
1031
1032 static int coda_prepare_encode(struct coda_ctx *ctx)
1033 {
1034         struct coda_q_data *q_data_src, *q_data_dst;
1035         struct vb2_buffer *src_buf, *dst_buf;
1036         struct coda_dev *dev = ctx->dev;
1037         int force_ipicture;
1038         int quant_param = 0;
1039         u32 picture_y, picture_cb, picture_cr;
1040         u32 pic_stream_buffer_addr, pic_stream_buffer_size;
1041         u32 dst_fourcc;
1042
1043         src_buf = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
1044         dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
1045         q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
1046         q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
1047         dst_fourcc = q_data_dst->fourcc;
1048
1049         src_buf->v4l2_buf.sequence = ctx->osequence;
1050         dst_buf->v4l2_buf.sequence = ctx->osequence;
1051         ctx->osequence++;
1052
1053         /*
1054          * Workaround coda firmware BUG that only marks the first
1055          * frame as IDR. This is a problem for some decoders that can't
1056          * recover when a frame is lost.
1057          */
1058         if (src_buf->v4l2_buf.sequence % ctx->params.gop_size) {
1059                 src_buf->v4l2_buf.flags |= V4L2_BUF_FLAG_PFRAME;
1060                 src_buf->v4l2_buf.flags &= ~V4L2_BUF_FLAG_KEYFRAME;
1061         } else {
1062                 src_buf->v4l2_buf.flags |= V4L2_BUF_FLAG_KEYFRAME;
1063                 src_buf->v4l2_buf.flags &= ~V4L2_BUF_FLAG_PFRAME;
1064         }
1065
1066         if (dev->devtype->product == CODA_960)
1067                 coda_set_gdi_regs(ctx);
1068
1069         /*
1070          * Copy headers at the beginning of the first frame for H.264 only.
1071          * In MPEG4 they are already copied by the coda.
1072          */
1073         if (src_buf->v4l2_buf.sequence == 0) {
1074                 pic_stream_buffer_addr =
1075                         vb2_dma_contig_plane_dma_addr(dst_buf, 0) +
1076                         ctx->vpu_header_size[0] +
1077                         ctx->vpu_header_size[1] +
1078                         ctx->vpu_header_size[2];
1079                 pic_stream_buffer_size = CODA_MAX_FRAME_SIZE -
1080                         ctx->vpu_header_size[0] -
1081                         ctx->vpu_header_size[1] -
1082                         ctx->vpu_header_size[2];
1083                 memcpy(vb2_plane_vaddr(dst_buf, 0),
1084                        &ctx->vpu_header[0][0], ctx->vpu_header_size[0]);
1085                 memcpy(vb2_plane_vaddr(dst_buf, 0) + ctx->vpu_header_size[0],
1086                        &ctx->vpu_header[1][0], ctx->vpu_header_size[1]);
1087                 memcpy(vb2_plane_vaddr(dst_buf, 0) + ctx->vpu_header_size[0] +
1088                         ctx->vpu_header_size[1], &ctx->vpu_header[2][0],
1089                         ctx->vpu_header_size[2]);
1090         } else {
1091                 pic_stream_buffer_addr =
1092                         vb2_dma_contig_plane_dma_addr(dst_buf, 0);
1093                 pic_stream_buffer_size = CODA_MAX_FRAME_SIZE;
1094         }
1095
1096         if (src_buf->v4l2_buf.flags & V4L2_BUF_FLAG_KEYFRAME) {
1097                 force_ipicture = 1;
1098                 switch (dst_fourcc) {
1099                 case V4L2_PIX_FMT_H264:
1100                         quant_param = ctx->params.h264_intra_qp;
1101                         break;
1102                 case V4L2_PIX_FMT_MPEG4:
1103                         quant_param = ctx->params.mpeg4_intra_qp;
1104                         break;
1105                 default:
1106                         v4l2_warn(&ctx->dev->v4l2_dev,
1107                                 "cannot set intra qp, fmt not supported\n");
1108                         break;
1109                 }
1110         } else {
1111                 force_ipicture = 0;
1112                 switch (dst_fourcc) {
1113                 case V4L2_PIX_FMT_H264:
1114                         quant_param = ctx->params.h264_inter_qp;
1115                         break;
1116                 case V4L2_PIX_FMT_MPEG4:
1117                         quant_param = ctx->params.mpeg4_inter_qp;
1118                         break;
1119                 default:
1120                         v4l2_warn(&ctx->dev->v4l2_dev,
1121                                 "cannot set inter qp, fmt not supported\n");
1122                         break;
1123                 }
1124         }
1125
1126         /* submit */
1127         coda_write(dev, CODA_ROT_MIR_ENABLE | ctx->params.rot_mode,
1128                    CODA_CMD_ENC_PIC_ROT_MODE);
1129         coda_write(dev, quant_param, CODA_CMD_ENC_PIC_QS);
1130
1131
1132         picture_y = vb2_dma_contig_plane_dma_addr(src_buf, 0);
1133         switch (q_data_src->fourcc) {
1134         case V4L2_PIX_FMT_YVU420:
1135                 /* Switch Cb and Cr for YVU420 format */
1136                 picture_cr = picture_y + q_data_src->bytesperline *
1137                                 q_data_src->height;
1138                 picture_cb = picture_cr + q_data_src->bytesperline / 2 *
1139                                 q_data_src->height / 2;
1140                 break;
1141         case V4L2_PIX_FMT_YUV420:
1142         default:
1143                 picture_cb = picture_y + q_data_src->bytesperline *
1144                                 q_data_src->height;
1145                 picture_cr = picture_cb + q_data_src->bytesperline / 2 *
1146                                 q_data_src->height / 2;
1147                 break;
1148         }
1149
1150         if (dev->devtype->product == CODA_960) {
1151                 coda_write(dev, 4/*FIXME: 0*/, CODA9_CMD_ENC_PIC_SRC_INDEX);
1152                 coda_write(dev, q_data_src->width, CODA9_CMD_ENC_PIC_SRC_STRIDE);
1153                 coda_write(dev, 0, CODA9_CMD_ENC_PIC_SUB_FRAME_SYNC);
1154
1155                 coda_write(dev, picture_y, CODA9_CMD_ENC_PIC_SRC_ADDR_Y);
1156                 coda_write(dev, picture_cb, CODA9_CMD_ENC_PIC_SRC_ADDR_CB);
1157                 coda_write(dev, picture_cr, CODA9_CMD_ENC_PIC_SRC_ADDR_CR);
1158         } else {
1159                 coda_write(dev, picture_y, CODA_CMD_ENC_PIC_SRC_ADDR_Y);
1160                 coda_write(dev, picture_cb, CODA_CMD_ENC_PIC_SRC_ADDR_CB);
1161                 coda_write(dev, picture_cr, CODA_CMD_ENC_PIC_SRC_ADDR_CR);
1162         }
1163         coda_write(dev, force_ipicture << 1 & 0x2,
1164                    CODA_CMD_ENC_PIC_OPTION);
1165
1166         coda_write(dev, pic_stream_buffer_addr, CODA_CMD_ENC_PIC_BB_START);
1167         coda_write(dev, pic_stream_buffer_size / 1024,
1168                    CODA_CMD_ENC_PIC_BB_SIZE);
1169
1170         if (!ctx->streamon_out) {
1171                 /* After streamoff on the output side, set stream end flag */
1172                 ctx->bit_stream_param |= CODA_BIT_STREAM_END_FLAG;
1173                 coda_write(dev, ctx->bit_stream_param,
1174                            CODA_REG_BIT_BIT_STREAM_PARAM);
1175         }
1176
1177         if (dev->devtype->product != CODA_DX6)
1178                 coda_write(dev, ctx->iram_info.axi_sram_use,
1179                                 CODA7_REG_BIT_AXI_SRAM_USE);
1180
1181         coda_command_async(ctx, CODA_COMMAND_PIC_RUN);
1182
1183         return 0;
1184 }
1185
1186 static void coda_finish_encode(struct coda_ctx *ctx)
1187 {
1188         struct vb2_buffer *src_buf, *dst_buf;
1189         struct coda_dev *dev = ctx->dev;
1190         u32 wr_ptr, start_ptr;
1191
1192         src_buf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
1193         dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
1194
1195         /* Get results from the coda */
1196         start_ptr = coda_read(dev, CODA_CMD_ENC_PIC_BB_START);
1197         wr_ptr = coda_read(dev, CODA_REG_BIT_WR_PTR(ctx->reg_idx));
1198
1199         /* Calculate bytesused field */
1200         if (dst_buf->v4l2_buf.sequence == 0) {
1201                 vb2_set_plane_payload(dst_buf, 0, wr_ptr - start_ptr +
1202                                         ctx->vpu_header_size[0] +
1203                                         ctx->vpu_header_size[1] +
1204                                         ctx->vpu_header_size[2]);
1205         } else {
1206                 vb2_set_plane_payload(dst_buf, 0, wr_ptr - start_ptr);
1207         }
1208
1209         v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev, "frame size = %u\n",
1210                  wr_ptr - start_ptr);
1211
1212         coda_read(dev, CODA_RET_ENC_PIC_SLICE_NUM);
1213         coda_read(dev, CODA_RET_ENC_PIC_FLAG);
1214
1215         if (coda_read(dev, CODA_RET_ENC_PIC_TYPE) == 0) {
1216                 dst_buf->v4l2_buf.flags |= V4L2_BUF_FLAG_KEYFRAME;
1217                 dst_buf->v4l2_buf.flags &= ~V4L2_BUF_FLAG_PFRAME;
1218         } else {
1219                 dst_buf->v4l2_buf.flags |= V4L2_BUF_FLAG_PFRAME;
1220                 dst_buf->v4l2_buf.flags &= ~V4L2_BUF_FLAG_KEYFRAME;
1221         }
1222
1223         dst_buf->v4l2_buf.timestamp = src_buf->v4l2_buf.timestamp;
1224         dst_buf->v4l2_buf.flags &= ~V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
1225         dst_buf->v4l2_buf.flags |=
1226                 src_buf->v4l2_buf.flags & V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
1227         dst_buf->v4l2_buf.timecode = src_buf->v4l2_buf.timecode;
1228
1229         v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_DONE);
1230
1231         dst_buf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
1232         v4l2_m2m_buf_done(dst_buf, VB2_BUF_STATE_DONE);
1233
1234         ctx->gopcounter--;
1235         if (ctx->gopcounter < 0)
1236                 ctx->gopcounter = ctx->params.gop_size - 1;
1237
1238         v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
1239                 "job finished: encoding frame (%d) (%s)\n",
1240                 dst_buf->v4l2_buf.sequence,
1241                 (dst_buf->v4l2_buf.flags & V4L2_BUF_FLAG_KEYFRAME) ?
1242                 "KEYFRAME" : "PFRAME");
1243 }
1244
1245 static void coda_seq_end_work(struct work_struct *work)
1246 {
1247         struct coda_ctx *ctx = container_of(work, struct coda_ctx, seq_end_work);
1248         struct coda_dev *dev = ctx->dev;
1249
1250         mutex_lock(&ctx->buffer_mutex);
1251         mutex_lock(&dev->coda_mutex);
1252
1253         v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
1254                  "%d: %s: sent command 'SEQ_END' to coda\n", ctx->idx,
1255                  __func__);
1256         if (coda_command_sync(ctx, CODA_COMMAND_SEQ_END)) {
1257                 v4l2_err(&dev->v4l2_dev,
1258                          "CODA_COMMAND_SEQ_END failed\n");
1259         }
1260
1261         kfifo_init(&ctx->bitstream_fifo,
1262                 ctx->bitstream.vaddr, ctx->bitstream.size);
1263
1264         coda_free_framebuffers(ctx);
1265         coda_free_context_buffers(ctx);
1266
1267         mutex_unlock(&dev->coda_mutex);
1268         mutex_unlock(&ctx->buffer_mutex);
1269 }
1270
1271 static void coda_bit_release(struct coda_ctx *ctx)
1272 {
1273         coda_free_framebuffers(ctx);
1274         coda_free_context_buffers(ctx);
1275 }
1276
1277 const struct coda_context_ops coda_bit_encode_ops = {
1278         .queue_init = coda_encoder_queue_init,
1279         .start_streaming = coda_start_encoding,
1280         .prepare_run = coda_prepare_encode,
1281         .finish_run = coda_finish_encode,
1282         .seq_end_work = coda_seq_end_work,
1283         .release = coda_bit_release,
1284 };
1285
1286 /*
1287  * Decoder context operations
1288  */
1289
1290 static int __coda_start_decoding(struct coda_ctx *ctx)
1291 {
1292         struct coda_q_data *q_data_src, *q_data_dst;
1293         u32 bitstream_buf, bitstream_size;
1294         struct coda_dev *dev = ctx->dev;
1295         int width, height;
1296         u32 src_fourcc;
1297         u32 val;
1298         int ret;
1299
1300         /* Start decoding */
1301         q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
1302         q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
1303         bitstream_buf = ctx->bitstream.paddr;
1304         bitstream_size = ctx->bitstream.size;
1305         src_fourcc = q_data_src->fourcc;
1306
1307         /* Allocate per-instance buffers */
1308         ret = coda_alloc_context_buffers(ctx, q_data_src);
1309         if (ret < 0)
1310                 return ret;
1311
1312         coda_write(dev, ctx->parabuf.paddr, CODA_REG_BIT_PARA_BUF_ADDR);
1313
1314         /* Update coda bitstream read and write pointers from kfifo */
1315         coda_kfifo_sync_to_device_full(ctx);
1316
1317         ctx->display_idx = -1;
1318         ctx->frm_dis_flg = 0;
1319         coda_write(dev, 0, CODA_REG_BIT_FRM_DIS_FLG(ctx->reg_idx));
1320
1321         coda_write(dev, CODA_BIT_DEC_SEQ_INIT_ESCAPE,
1322                         CODA_REG_BIT_BIT_STREAM_PARAM);
1323
1324         coda_write(dev, bitstream_buf, CODA_CMD_DEC_SEQ_BB_START);
1325         coda_write(dev, bitstream_size / 1024, CODA_CMD_DEC_SEQ_BB_SIZE);
1326         val = 0;
1327         if ((dev->devtype->product == CODA_7541) ||
1328             (dev->devtype->product == CODA_960))
1329                 val |= CODA_REORDER_ENABLE;
1330         coda_write(dev, val, CODA_CMD_DEC_SEQ_OPTION);
1331
1332         ctx->params.codec_mode = ctx->codec->mode;
1333         if (dev->devtype->product == CODA_960 &&
1334             src_fourcc == V4L2_PIX_FMT_MPEG4)
1335                 ctx->params.codec_mode_aux = CODA_MP4_AUX_MPEG4;
1336         else
1337                 ctx->params.codec_mode_aux = 0;
1338         if (src_fourcc == V4L2_PIX_FMT_H264) {
1339                 if (dev->devtype->product == CODA_7541) {
1340                         coda_write(dev, ctx->psbuf.paddr,
1341                                         CODA_CMD_DEC_SEQ_PS_BB_START);
1342                         coda_write(dev, (CODA7_PS_BUF_SIZE / 1024),
1343                                         CODA_CMD_DEC_SEQ_PS_BB_SIZE);
1344                 }
1345                 if (dev->devtype->product == CODA_960) {
1346                         coda_write(dev, 0, CODA_CMD_DEC_SEQ_X264_MV_EN);
1347                         coda_write(dev, 512, CODA_CMD_DEC_SEQ_SPP_CHUNK_SIZE);
1348                 }
1349         }
1350         if (dev->devtype->product != CODA_960)
1351                 coda_write(dev, 0, CODA_CMD_DEC_SEQ_SRC_SIZE);
1352
1353         if (coda_command_sync(ctx, CODA_COMMAND_SEQ_INIT)) {
1354                 v4l2_err(&dev->v4l2_dev, "CODA_COMMAND_SEQ_INIT timeout\n");
1355                 coda_write(dev, 0, CODA_REG_BIT_BIT_STREAM_PARAM);
1356                 return -ETIMEDOUT;
1357         }
1358
1359         /* Update kfifo out pointer from coda bitstream read pointer */
1360         coda_kfifo_sync_from_device(ctx);
1361
1362         coda_write(dev, 0, CODA_REG_BIT_BIT_STREAM_PARAM);
1363
1364         if (coda_read(dev, CODA_RET_DEC_SEQ_SUCCESS) == 0) {
1365                 v4l2_err(&dev->v4l2_dev,
1366                         "CODA_COMMAND_SEQ_INIT failed, error code = %d\n",
1367                         coda_read(dev, CODA_RET_DEC_SEQ_ERR_REASON));
1368                 return -EAGAIN;
1369         }
1370
1371         val = coda_read(dev, CODA_RET_DEC_SEQ_SRC_SIZE);
1372         if (dev->devtype->product == CODA_DX6) {
1373                 width = (val >> CODADX6_PICWIDTH_OFFSET) & CODADX6_PICWIDTH_MASK;
1374                 height = val & CODADX6_PICHEIGHT_MASK;
1375         } else {
1376                 width = (val >> CODA7_PICWIDTH_OFFSET) & CODA7_PICWIDTH_MASK;
1377                 height = val & CODA7_PICHEIGHT_MASK;
1378         }
1379
1380         if (width > q_data_dst->width || height > q_data_dst->height) {
1381                 v4l2_err(&dev->v4l2_dev, "stream is %dx%d, not %dx%d\n",
1382                          width, height, q_data_dst->width, q_data_dst->height);
1383                 return -EINVAL;
1384         }
1385
1386         width = round_up(width, 16);
1387         height = round_up(height, 16);
1388
1389         v4l2_dbg(1, coda_debug, &dev->v4l2_dev, "%s instance %d now: %dx%d\n",
1390                  __func__, ctx->idx, width, height);
1391
1392         ctx->num_internal_frames = coda_read(dev, CODA_RET_DEC_SEQ_FRAME_NEED);
1393         if (ctx->num_internal_frames > CODA_MAX_FRAMEBUFFERS) {
1394                 v4l2_err(&dev->v4l2_dev,
1395                          "not enough framebuffers to decode (%d < %d)\n",
1396                          CODA_MAX_FRAMEBUFFERS, ctx->num_internal_frames);
1397                 return -EINVAL;
1398         }
1399
1400         if (src_fourcc == V4L2_PIX_FMT_H264) {
1401                 u32 left_right;
1402                 u32 top_bottom;
1403
1404                 left_right = coda_read(dev, CODA_RET_DEC_SEQ_CROP_LEFT_RIGHT);
1405                 top_bottom = coda_read(dev, CODA_RET_DEC_SEQ_CROP_TOP_BOTTOM);
1406
1407                 q_data_dst->rect.left = (left_right >> 10) & 0x3ff;
1408                 q_data_dst->rect.top = (top_bottom >> 10) & 0x3ff;
1409                 q_data_dst->rect.width = width - q_data_dst->rect.left -
1410                                          (left_right & 0x3ff);
1411                 q_data_dst->rect.height = height - q_data_dst->rect.top -
1412                                           (top_bottom & 0x3ff);
1413         }
1414
1415         ret = coda_alloc_framebuffers(ctx, q_data_dst, src_fourcc);
1416         if (ret < 0) {
1417                 v4l2_err(&dev->v4l2_dev, "failed to allocate framebuffers\n");
1418                 return ret;
1419         }
1420
1421         /* Tell the decoder how many frame buffers we allocated. */
1422         coda_write(dev, ctx->num_internal_frames, CODA_CMD_SET_FRAME_BUF_NUM);
1423         coda_write(dev, width, CODA_CMD_SET_FRAME_BUF_STRIDE);
1424
1425         if (dev->devtype->product != CODA_DX6) {
1426                 /* Set secondary AXI IRAM */
1427                 coda_setup_iram(ctx);
1428
1429                 coda_write(dev, ctx->iram_info.buf_bit_use,
1430                                 CODA7_CMD_SET_FRAME_AXI_BIT_ADDR);
1431                 coda_write(dev, ctx->iram_info.buf_ip_ac_dc_use,
1432                                 CODA7_CMD_SET_FRAME_AXI_IPACDC_ADDR);
1433                 coda_write(dev, ctx->iram_info.buf_dbk_y_use,
1434                                 CODA7_CMD_SET_FRAME_AXI_DBKY_ADDR);
1435                 coda_write(dev, ctx->iram_info.buf_dbk_c_use,
1436                                 CODA7_CMD_SET_FRAME_AXI_DBKC_ADDR);
1437                 coda_write(dev, ctx->iram_info.buf_ovl_use,
1438                                 CODA7_CMD_SET_FRAME_AXI_OVL_ADDR);
1439                 if (dev->devtype->product == CODA_960)
1440                         coda_write(dev, ctx->iram_info.buf_btp_use,
1441                                         CODA9_CMD_SET_FRAME_AXI_BTP_ADDR);
1442         }
1443
1444         if (dev->devtype->product == CODA_960) {
1445                 coda_write(dev, -1, CODA9_CMD_SET_FRAME_DELAY);
1446
1447                 coda_write(dev, 0x20262024, CODA9_CMD_SET_FRAME_CACHE_SIZE);
1448                 coda_write(dev, 2 << CODA9_CACHE_PAGEMERGE_OFFSET |
1449                                 32 << CODA9_CACHE_LUMA_BUFFER_SIZE_OFFSET |
1450                                 8 << CODA9_CACHE_CB_BUFFER_SIZE_OFFSET |
1451                                 8 << CODA9_CACHE_CR_BUFFER_SIZE_OFFSET,
1452                                 CODA9_CMD_SET_FRAME_CACHE_CONFIG);
1453         }
1454
1455         if (src_fourcc == V4L2_PIX_FMT_H264) {
1456                 coda_write(dev, ctx->slicebuf.paddr,
1457                                 CODA_CMD_SET_FRAME_SLICE_BB_START);
1458                 coda_write(dev, ctx->slicebuf.size / 1024,
1459                                 CODA_CMD_SET_FRAME_SLICE_BB_SIZE);
1460         }
1461
1462         if (dev->devtype->product == CODA_7541) {
1463                 int max_mb_x = 1920 / 16;
1464                 int max_mb_y = 1088 / 16;
1465                 int max_mb_num = max_mb_x * max_mb_y;
1466
1467                 coda_write(dev, max_mb_num << 16 | max_mb_x << 8 | max_mb_y,
1468                                 CODA7_CMD_SET_FRAME_MAX_DEC_SIZE);
1469         } else if (dev->devtype->product == CODA_960) {
1470                 int max_mb_x = 1920 / 16;
1471                 int max_mb_y = 1088 / 16;
1472                 int max_mb_num = max_mb_x * max_mb_y;
1473
1474                 coda_write(dev, max_mb_num << 16 | max_mb_x << 8 | max_mb_y,
1475                                 CODA9_CMD_SET_FRAME_MAX_DEC_SIZE);
1476         }
1477
1478         if (coda_command_sync(ctx, CODA_COMMAND_SET_FRAME_BUF)) {
1479                 v4l2_err(&ctx->dev->v4l2_dev,
1480                          "CODA_COMMAND_SET_FRAME_BUF timeout\n");
1481                 return -ETIMEDOUT;
1482         }
1483
1484         return 0;
1485 }
1486
1487 static int coda_start_decoding(struct coda_ctx *ctx)
1488 {
1489         struct coda_dev *dev = ctx->dev;
1490         int ret;
1491
1492         mutex_lock(&dev->coda_mutex);
1493         ret = __coda_start_decoding(ctx);
1494         mutex_unlock(&dev->coda_mutex);
1495
1496         return ret;
1497 }
1498
1499 static int coda_prepare_decode(struct coda_ctx *ctx)
1500 {
1501         struct vb2_buffer *dst_buf;
1502         struct coda_dev *dev = ctx->dev;
1503         struct coda_q_data *q_data_dst;
1504         u32 stridey, height;
1505         u32 picture_y, picture_cb, picture_cr;
1506
1507         dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
1508         q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
1509
1510         if (ctx->params.rot_mode & CODA_ROT_90) {
1511                 stridey = q_data_dst->height;
1512                 height = q_data_dst->width;
1513         } else {
1514                 stridey = q_data_dst->width;
1515                 height = q_data_dst->height;
1516         }
1517
1518         /* Try to copy source buffer contents into the bitstream ringbuffer */
1519         mutex_lock(&ctx->bitstream_mutex);
1520         coda_fill_bitstream(ctx);
1521         mutex_unlock(&ctx->bitstream_mutex);
1522
1523         if (coda_get_bitstream_payload(ctx) < 512 &&
1524             (!(ctx->bit_stream_param & CODA_BIT_STREAM_END_FLAG))) {
1525                 v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
1526                          "bitstream payload: %d, skipping\n",
1527                          coda_get_bitstream_payload(ctx));
1528                 v4l2_m2m_job_finish(ctx->dev->m2m_dev, ctx->fh.m2m_ctx);
1529                 return -EAGAIN;
1530         }
1531
1532         /* Run coda_start_decoding (again) if not yet initialized */
1533         if (!ctx->initialized) {
1534                 int ret = __coda_start_decoding(ctx);
1535
1536                 if (ret < 0) {
1537                         v4l2_err(&dev->v4l2_dev, "failed to start decoding\n");
1538                         v4l2_m2m_job_finish(ctx->dev->m2m_dev, ctx->fh.m2m_ctx);
1539                         return -EAGAIN;
1540                 } else {
1541                         ctx->initialized = 1;
1542                 }
1543         }
1544
1545         if (dev->devtype->product == CODA_960)
1546                 coda_set_gdi_regs(ctx);
1547
1548         /* Set rotator output */
1549         picture_y = vb2_dma_contig_plane_dma_addr(dst_buf, 0);
1550         if (q_data_dst->fourcc == V4L2_PIX_FMT_YVU420) {
1551                 /* Switch Cr and Cb for YVU420 format */
1552                 picture_cr = picture_y + stridey * height;
1553                 picture_cb = picture_cr + stridey / 2 * height / 2;
1554         } else {
1555                 picture_cb = picture_y + stridey * height;
1556                 picture_cr = picture_cb + stridey / 2 * height / 2;
1557         }
1558
1559         if (dev->devtype->product == CODA_960) {
1560                 /*
1561                  * The CODA960 seems to have an internal list of buffers with
1562                  * 64 entries that includes the registered frame buffers as
1563                  * well as the rotator buffer output.
1564                  * ROT_INDEX needs to be < 0x40, but > ctx->num_internal_frames.
1565                  */
1566                 coda_write(dev, CODA_MAX_FRAMEBUFFERS + dst_buf->v4l2_buf.index,
1567                                 CODA9_CMD_DEC_PIC_ROT_INDEX);
1568                 coda_write(dev, picture_y, CODA9_CMD_DEC_PIC_ROT_ADDR_Y);
1569                 coda_write(dev, picture_cb, CODA9_CMD_DEC_PIC_ROT_ADDR_CB);
1570                 coda_write(dev, picture_cr, CODA9_CMD_DEC_PIC_ROT_ADDR_CR);
1571                 coda_write(dev, stridey, CODA9_CMD_DEC_PIC_ROT_STRIDE);
1572         } else {
1573                 coda_write(dev, picture_y, CODA_CMD_DEC_PIC_ROT_ADDR_Y);
1574                 coda_write(dev, picture_cb, CODA_CMD_DEC_PIC_ROT_ADDR_CB);
1575                 coda_write(dev, picture_cr, CODA_CMD_DEC_PIC_ROT_ADDR_CR);
1576                 coda_write(dev, stridey, CODA_CMD_DEC_PIC_ROT_STRIDE);
1577         }
1578         coda_write(dev, CODA_ROT_MIR_ENABLE | ctx->params.rot_mode,
1579                         CODA_CMD_DEC_PIC_ROT_MODE);
1580
1581         switch (dev->devtype->product) {
1582         case CODA_DX6:
1583                 /* TBD */
1584         case CODA_7541:
1585                 coda_write(dev, CODA_PRE_SCAN_EN, CODA_CMD_DEC_PIC_OPTION);
1586                 break;
1587         case CODA_960:
1588                 /* 'hardcode to use interrupt disable mode'? */
1589                 coda_write(dev, (1 << 10), CODA_CMD_DEC_PIC_OPTION);
1590                 break;
1591         }
1592
1593         coda_write(dev, 0, CODA_CMD_DEC_PIC_SKIP_NUM);
1594
1595         coda_write(dev, 0, CODA_CMD_DEC_PIC_BB_START);
1596         coda_write(dev, 0, CODA_CMD_DEC_PIC_START_BYTE);
1597
1598         if (dev->devtype->product != CODA_DX6)
1599                 coda_write(dev, ctx->iram_info.axi_sram_use,
1600                                 CODA7_REG_BIT_AXI_SRAM_USE);
1601
1602         coda_kfifo_sync_to_device_full(ctx);
1603
1604         coda_command_async(ctx, CODA_COMMAND_PIC_RUN);
1605
1606         return 0;
1607 }
1608
1609 static void coda_finish_decode(struct coda_ctx *ctx)
1610 {
1611         struct coda_dev *dev = ctx->dev;
1612         struct coda_q_data *q_data_src;
1613         struct coda_q_data *q_data_dst;
1614         struct vb2_buffer *dst_buf;
1615         struct coda_timestamp *ts;
1616         int width, height;
1617         int decoded_idx;
1618         int display_idx;
1619         u32 src_fourcc;
1620         int success;
1621         u32 err_mb;
1622         u32 val;
1623
1624         /* Update kfifo out pointer from coda bitstream read pointer */
1625         coda_kfifo_sync_from_device(ctx);
1626
1627         /*
1628          * in stream-end mode, the read pointer can overshoot the write pointer
1629          * by up to 512 bytes
1630          */
1631         if (ctx->bit_stream_param & CODA_BIT_STREAM_END_FLAG) {
1632                 if (coda_get_bitstream_payload(ctx) >= CODA_MAX_FRAME_SIZE - 512)
1633                         kfifo_init(&ctx->bitstream_fifo,
1634                                 ctx->bitstream.vaddr, ctx->bitstream.size);
1635         }
1636
1637         q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
1638         src_fourcc = q_data_src->fourcc;
1639
1640         val = coda_read(dev, CODA_RET_DEC_PIC_SUCCESS);
1641         if (val != 1)
1642                 pr_err("DEC_PIC_SUCCESS = %d\n", val);
1643
1644         success = val & 0x1;
1645         if (!success)
1646                 v4l2_err(&dev->v4l2_dev, "decode failed\n");
1647
1648         if (src_fourcc == V4L2_PIX_FMT_H264) {
1649                 if (val & (1 << 3))
1650                         v4l2_err(&dev->v4l2_dev,
1651                                  "insufficient PS buffer space (%d bytes)\n",
1652                                  ctx->psbuf.size);
1653                 if (val & (1 << 2))
1654                         v4l2_err(&dev->v4l2_dev,
1655                                  "insufficient slice buffer space (%d bytes)\n",
1656                                  ctx->slicebuf.size);
1657         }
1658
1659         val = coda_read(dev, CODA_RET_DEC_PIC_SIZE);
1660         width = (val >> 16) & 0xffff;
1661         height = val & 0xffff;
1662
1663         q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
1664
1665         /* frame crop information */
1666         if (src_fourcc == V4L2_PIX_FMT_H264) {
1667                 u32 left_right;
1668                 u32 top_bottom;
1669
1670                 left_right = coda_read(dev, CODA_RET_DEC_PIC_CROP_LEFT_RIGHT);
1671                 top_bottom = coda_read(dev, CODA_RET_DEC_PIC_CROP_TOP_BOTTOM);
1672
1673                 if (left_right == 0xffffffff && top_bottom == 0xffffffff) {
1674                         /* Keep current crop information */
1675                 } else {
1676                         struct v4l2_rect *rect = &q_data_dst->rect;
1677
1678                         rect->left = left_right >> 16 & 0xffff;
1679                         rect->top = top_bottom >> 16 & 0xffff;
1680                         rect->width = width - rect->left -
1681                                       (left_right & 0xffff);
1682                         rect->height = height - rect->top -
1683                                        (top_bottom & 0xffff);
1684                 }
1685         } else {
1686                 /* no cropping */
1687         }
1688
1689         err_mb = coda_read(dev, CODA_RET_DEC_PIC_ERR_MB);
1690         if (err_mb > 0)
1691                 v4l2_err(&dev->v4l2_dev,
1692                          "errors in %d macroblocks\n", err_mb);
1693
1694         if (dev->devtype->product == CODA_7541) {
1695                 val = coda_read(dev, CODA_RET_DEC_PIC_OPTION);
1696                 if (val == 0) {
1697                         /* not enough bitstream data */
1698                         v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
1699                                  "prescan failed: %d\n", val);
1700                         ctx->hold = true;
1701                         return;
1702                 }
1703         }
1704
1705         ctx->frm_dis_flg = coda_read(dev,
1706                                      CODA_REG_BIT_FRM_DIS_FLG(ctx->reg_idx));
1707
1708         /*
1709          * The previous display frame was copied out by the rotator,
1710          * now it can be overwritten again
1711          */
1712         if (ctx->display_idx >= 0 &&
1713             ctx->display_idx < ctx->num_internal_frames) {
1714                 ctx->frm_dis_flg &= ~(1 << ctx->display_idx);
1715                 coda_write(dev, ctx->frm_dis_flg,
1716                                 CODA_REG_BIT_FRM_DIS_FLG(ctx->reg_idx));
1717         }
1718
1719         /*
1720          * The index of the last decoded frame, not necessarily in
1721          * display order, and the index of the next display frame.
1722          * The latter could have been decoded in a previous run.
1723          */
1724         decoded_idx = coda_read(dev, CODA_RET_DEC_PIC_CUR_IDX);
1725         display_idx = coda_read(dev, CODA_RET_DEC_PIC_FRAME_IDX);
1726
1727         if (decoded_idx == -1) {
1728                 /* no frame was decoded, but we might have a display frame */
1729                 if (display_idx >= 0 && display_idx < ctx->num_internal_frames)
1730                         ctx->sequence_offset++;
1731                 else if (ctx->display_idx < 0)
1732                         ctx->hold = true;
1733         } else if (decoded_idx == -2) {
1734                 /* no frame was decoded, we still return remaining buffers */
1735         } else if (decoded_idx < 0 || decoded_idx >= ctx->num_internal_frames) {
1736                 v4l2_err(&dev->v4l2_dev,
1737                          "decoded frame index out of range: %d\n", decoded_idx);
1738         } else {
1739                 val = coda_read(dev, CODA_RET_DEC_PIC_FRAME_NUM) - 1;
1740                 val -= ctx->sequence_offset;
1741                 mutex_lock(&ctx->bitstream_mutex);
1742                 if (!list_empty(&ctx->timestamp_list)) {
1743                         ts = list_first_entry(&ctx->timestamp_list,
1744                                               struct coda_timestamp, list);
1745                         list_del(&ts->list);
1746                         if (val != (ts->sequence & 0xffff)) {
1747                                 v4l2_err(&dev->v4l2_dev,
1748                                          "sequence number mismatch (%d(%d) != %d)\n",
1749                                          val, ctx->sequence_offset,
1750                                          ts->sequence);
1751                         }
1752                         ctx->frame_timestamps[decoded_idx] = *ts;
1753                         kfree(ts);
1754                 } else {
1755                         v4l2_err(&dev->v4l2_dev, "empty timestamp list!\n");
1756                         memset(&ctx->frame_timestamps[decoded_idx], 0,
1757                                sizeof(struct coda_timestamp));
1758                         ctx->frame_timestamps[decoded_idx].sequence = val;
1759                 }
1760                 mutex_unlock(&ctx->bitstream_mutex);
1761
1762                 val = coda_read(dev, CODA_RET_DEC_PIC_TYPE) & 0x7;
1763                 if (val == 0)
1764                         ctx->frame_types[decoded_idx] = V4L2_BUF_FLAG_KEYFRAME;
1765                 else if (val == 1)
1766                         ctx->frame_types[decoded_idx] = V4L2_BUF_FLAG_PFRAME;
1767                 else
1768                         ctx->frame_types[decoded_idx] = V4L2_BUF_FLAG_BFRAME;
1769
1770                 ctx->frame_errors[decoded_idx] = err_mb;
1771         }
1772
1773         if (display_idx == -1) {
1774                 /*
1775                  * no more frames to be decoded, but there could still
1776                  * be rotator output to dequeue
1777                  */
1778                 ctx->hold = true;
1779         } else if (display_idx == -3) {
1780                 /* possibly prescan failure */
1781         } else if (display_idx < 0 || display_idx >= ctx->num_internal_frames) {
1782                 v4l2_err(&dev->v4l2_dev,
1783                          "presentation frame index out of range: %d\n",
1784                          display_idx);
1785         }
1786
1787         /* If a frame was copied out, return it */
1788         if (ctx->display_idx >= 0 &&
1789             ctx->display_idx < ctx->num_internal_frames) {
1790                 dst_buf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
1791                 dst_buf->v4l2_buf.sequence = ctx->osequence++;
1792
1793                 dst_buf->v4l2_buf.flags &= ~(V4L2_BUF_FLAG_KEYFRAME |
1794                                              V4L2_BUF_FLAG_PFRAME |
1795                                              V4L2_BUF_FLAG_BFRAME);
1796                 dst_buf->v4l2_buf.flags |= ctx->frame_types[ctx->display_idx];
1797                 ts = &ctx->frame_timestamps[ctx->display_idx];
1798                 dst_buf->v4l2_buf.timecode = ts->timecode;
1799                 dst_buf->v4l2_buf.timestamp = ts->timestamp;
1800
1801                 vb2_set_plane_payload(dst_buf, 0, width * height * 3 / 2);
1802
1803                 v4l2_m2m_buf_done(dst_buf, ctx->frame_errors[display_idx] ?
1804                                   VB2_BUF_STATE_ERROR : VB2_BUF_STATE_DONE);
1805
1806                 v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
1807                         "job finished: decoding frame (%d) (%s)\n",
1808                         dst_buf->v4l2_buf.sequence,
1809                         (dst_buf->v4l2_buf.flags & V4L2_BUF_FLAG_KEYFRAME) ?
1810                         "KEYFRAME" : "PFRAME");
1811         } else {
1812                 v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
1813                         "job finished: no frame decoded\n");
1814         }
1815
1816         /* The rotator will copy the current display frame next time */
1817         ctx->display_idx = display_idx;
1818 }
1819
1820 const struct coda_context_ops coda_bit_decode_ops = {
1821         .queue_init = coda_decoder_queue_init,
1822         .start_streaming = coda_start_decoding,
1823         .prepare_run = coda_prepare_decode,
1824         .finish_run = coda_finish_decode,
1825         .seq_end_work = coda_seq_end_work,
1826         .release = coda_bit_release,
1827 };
1828
1829 irqreturn_t coda_irq_handler(int irq, void *data)
1830 {
1831         struct coda_dev *dev = data;
1832         struct coda_ctx *ctx;
1833
1834         /* read status register to attend the IRQ */
1835         coda_read(dev, CODA_REG_BIT_INT_STATUS);
1836         coda_write(dev, CODA_REG_BIT_INT_CLEAR_SET,
1837                       CODA_REG_BIT_INT_CLEAR);
1838
1839         ctx = v4l2_m2m_get_curr_priv(dev->m2m_dev);
1840         if (ctx == NULL) {
1841                 v4l2_err(&dev->v4l2_dev,
1842                          "Instance released before the end of transaction\n");
1843                 mutex_unlock(&dev->coda_mutex);
1844                 return IRQ_HANDLED;
1845         }
1846
1847         if (ctx->aborting) {
1848                 v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
1849                          "task has been aborted\n");
1850         }
1851
1852         if (coda_isbusy(ctx->dev)) {
1853                 v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
1854                          "coda is still busy!!!!\n");
1855                 return IRQ_NONE;
1856         }
1857
1858         complete(&ctx->completion);
1859
1860         return IRQ_HANDLED;
1861 }