2 * Author: Mikhail Ulyanov
3 * Copyright (C) 2014-2015 Cogent Embedded, Inc. <source@cogentembedded.com>
4 * Copyright (C) 2014-2015 Renesas Electronics Corporation
6 * This is based on the drivers/media/platform/s5p-jpeg driver by
7 * Andrzej Pietrasiewicz and Jacek Anaszewski.
8 * Some portions of code inspired by VSP1 driver by Laurent Pinchart.
10 * TODO in order of priority:
13 * 3) V4L2_CID_JPEG_ACTIVE_MARKER
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
20 #include <asm/unaligned.h>
21 #include <linux/clk.h>
22 #include <linux/err.h>
23 #include <linux/interrupt.h>
25 #include <linux/kernel.h>
26 #include <linux/module.h>
28 #include <linux/of_device.h>
29 #include <linux/platform_device.h>
30 #include <linux/slab.h>
31 #include <linux/spinlock.h>
32 #include <linux/string.h>
33 #include <linux/videodev2.h>
34 #include <media/v4l2-ctrls.h>
35 #include <media/v4l2-device.h>
36 #include <media/v4l2-event.h>
37 #include <media/v4l2-fh.h>
38 #include <media/v4l2-mem2mem.h>
39 #include <media/v4l2-ioctl.h>
40 #include <media/videobuf2-v4l2.h>
41 #include <media/videobuf2-dma-contig.h>
44 #define DRV_NAME "rcar_jpu"
47 * Align JPEG header end to cache line to make sure we will not have any issues
48 * with cache; additionally to requerment (33.3.27 R01UH0501EJ0100 Rev.1.00)
50 #define JPU_JPEG_HDR_SIZE (ALIGN(0x258, L1_CACHE_BYTES))
51 #define JPU_JPEG_MAX_BYTES_PER_PIXEL 2 /* 16 bit precision format */
52 #define JPU_JPEG_MIN_SIZE 25 /* SOI + SOF + EOI */
53 #define JPU_JPEG_QTBL_SIZE 0x40
54 #define JPU_JPEG_HDCTBL_SIZE 0x1c
55 #define JPU_JPEG_HACTBL_SIZE 0xb2
56 #define JPU_JPEG_HEIGHT_OFFSET 0x91
57 #define JPU_JPEG_WIDTH_OFFSET 0x93
58 #define JPU_JPEG_SUBS_OFFSET 0x97
59 #define JPU_JPEG_QTBL_LUM_OFFSET 0x07
60 #define JPU_JPEG_QTBL_CHR_OFFSET 0x4c
61 #define JPU_JPEG_HDCTBL_LUM_OFFSET 0xa4
62 #define JPU_JPEG_HACTBL_LUM_OFFSET 0xc5
63 #define JPU_JPEG_HDCTBL_CHR_OFFSET 0x17c
64 #define JPU_JPEG_HACTBL_CHR_OFFSET 0x19d
65 #define JPU_JPEG_PADDING_OFFSET 0x24f
66 #define JPU_JPEG_LUM 0x00
67 #define JPU_JPEG_CHR 0x01
68 #define JPU_JPEG_DC 0x00
69 #define JPU_JPEG_AC 0x10
71 #define JPU_JPEG_422 0x21
72 #define JPU_JPEG_420 0x22
74 #define JPU_JPEG_DEFAULT_422_PIX_FMT V4L2_PIX_FMT_NV16M
75 #define JPU_JPEG_DEFAULT_420_PIX_FMT V4L2_PIX_FMT_NV12M
90 #define JPU_RESET_TIMEOUT 100 /* ms */
91 #define JPU_JOB_TIMEOUT 300 /* ms */
92 #define JPU_MAX_QUALITY 4
93 #define JPU_WIDTH_MIN 16
94 #define JPU_HEIGHT_MIN 16
95 #define JPU_WIDTH_MAX 4096
96 #define JPU_HEIGHT_MAX 4096
97 #define JPU_MEMALIGN 8
99 /* Flags that indicate a format can be used for capture/output */
100 #define JPU_FMT_TYPE_OUTPUT 0
101 #define JPU_FMT_TYPE_CAPTURE 1
102 #define JPU_ENC_CAPTURE (1 << 0)
103 #define JPU_ENC_OUTPUT (1 << 1)
104 #define JPU_DEC_CAPTURE (1 << 2)
105 #define JPU_DEC_OUTPUT (1 << 3)
108 * JPEG registers and bits
111 /* JPEG code mode register */
113 #define JCMOD_PCTR (1 << 7)
114 #define JCMOD_MSKIP_ENABLE (1 << 5)
115 #define JCMOD_DSP_ENC (0 << 3)
116 #define JCMOD_DSP_DEC (1 << 3)
117 #define JCMOD_REDU (7 << 0)
118 #define JCMOD_REDU_422 (1 << 0)
119 #define JCMOD_REDU_420 (2 << 0)
121 /* JPEG code command register */
123 #define JCCMD_SRST (1 << 12)
124 #define JCCMD_JEND (1 << 2)
125 #define JCCMD_JSRT (1 << 0)
127 /* JPEG code quantanization table number register */
129 #define JCQTN_SHIFT(t) (((t) - 1) << 1)
131 /* JPEG code Huffman table number register */
133 #define JCHTN_AC_SHIFT(t) (((t) << 1) - 1)
134 #define JCHTN_DC_SHIFT(t) (((t) - 1) << 1)
136 #define JCVSZU 0x1c /* JPEG code vertical size upper register */
137 #define JCVSZD 0x20 /* JPEG code vertical size lower register */
138 #define JCHSZU 0x24 /* JPEG code horizontal size upper register */
139 #define JCHSZD 0x28 /* JPEG code horizontal size lower register */
140 #define JCSZ_MASK 0xff /* JPEG code h/v size register contains only 1 byte*/
142 #define JCDTCU 0x2c /* JPEG code data count upper register */
143 #define JCDTCM 0x30 /* JPEG code data count middle register */
144 #define JCDTCD 0x34 /* JPEG code data count lower register */
146 /* JPEG interrupt enable register */
148 #define JINTE_ERR (7 << 5) /* INT5 + INT6 + INT7 */
149 #define JINTE_TRANSF_COMPL (1 << 10)
151 /* JPEG interrupt status register */
153 #define JINTS_MASK 0x7c68
154 #define JINTS_ERR (1 << 5)
155 #define JINTS_PROCESS_COMPL (1 << 6)
156 #define JINTS_TRANSF_COMPL (1 << 10)
158 #define JCDERR 0x40 /* JPEG code decode error register */
159 #define JCDERR_MASK 0xf /* JPEG code decode error register mask*/
161 /* JPEG interface encoding */
163 #define JIFECNT_INFT_422 0
164 #define JIFECNT_INFT_420 1
165 #define JIFECNT_SWAP_WB (3 << 4) /* to JPU */
167 #define JIFESYA1 0x74 /* encode source Y address register 1 */
168 #define JIFESCA1 0x78 /* encode source C address register 1 */
169 #define JIFESYA2 0x7c /* encode source Y address register 2 */
170 #define JIFESCA2 0x80 /* encode source C address register 2 */
171 #define JIFESMW 0x84 /* encode source memory width register */
172 #define JIFESVSZ 0x88 /* encode source vertical size register */
173 #define JIFESHSZ 0x8c /* encode source horizontal size register */
174 #define JIFEDA1 0x90 /* encode destination address register 1 */
175 #define JIFEDA2 0x94 /* encode destination address register 2 */
177 /* JPEG decoding control register */
179 #define JIFDCNT_SWAP_WB (3 << 1) /* from JPU */
181 #define JIFDSA1 0xa4 /* decode source address register 1 */
182 #define JIFDDMW 0xb0 /* decode destination memory width register */
183 #define JIFDDVSZ 0xb4 /* decode destination vert. size register */
184 #define JIFDDHSZ 0xb8 /* decode destination horiz. size register */
185 #define JIFDDYA1 0xbc /* decode destination Y address register 1 */
186 #define JIFDDCA1 0xc0 /* decode destination C address register 1 */
188 #define JCQTBL(n) (0x10000 + (n) * 0x40) /* quantization tables regs */
189 #define JCHTBD(n) (0x10100 + (n) * 0x100) /* Huffman table DC regs */
190 #define JCHTBA(n) (0x10120 + (n) * 0x100) /* Huffman table AC regs */
193 * struct jpu - JPEG IP abstraction
194 * @mutex: the mutex protecting this structure
195 * @lock: spinlock protecting the device contexts
196 * @v4l2_dev: v4l2 device for mem2mem mode
197 * @vfd_encoder: video device node for encoder mem2mem mode
198 * @vfd_decoder: video device node for decoder mem2mem mode
199 * @m2m_dev: v4l2 mem2mem device data
200 * @curr: pointer to current context
201 * @irq_queue: interrupt handler waitqueue
202 * @regs: JPEG IP registers mapping
204 * @clk: JPEG IP clock
205 * @dev: JPEG IP struct device
206 * @alloc_ctx: videobuf2 memory allocator's context
207 * @ref_count: reference counter
212 struct v4l2_device v4l2_dev;
213 struct video_device vfd_encoder;
214 struct video_device vfd_decoder;
215 struct v4l2_m2m_dev *m2m_dev;
216 struct jpu_ctx *curr;
217 wait_queue_head_t irq_queue;
228 * struct jpu_buffer - driver's specific video buffer
230 * @compr_quality: destination image quality in compression mode
231 * @subsampling: source image subsampling in decompression mode
234 struct v4l2_m2m_buffer buf;
235 unsigned short compr_quality;
236 unsigned char subsampling;
240 * struct jpu_fmt - driver's internal format data
241 * @fourcc: the fourcc code, 0 if not applicable
242 * @colorspace: the colorspace specifier
243 * @bpp: number of bits per pixel per plane
244 * @h_align: horizontal alignment order (align to 2^h_align)
245 * @v_align: vertical alignment order (align to 2^v_align)
246 * @subsampling: (horizontal:4 | vertical:4) subsampling factor
247 * @num_planes: number of planes
248 * @types: types of queue this format is applicable to
262 * jpu_q_data - parameters of one queue
263 * @fmtinfo: driver-specific format of this queue
264 * @format: multiplanar format of this queue
265 * @sequence: sequence number
268 struct jpu_fmt *fmtinfo;
269 struct v4l2_pix_format_mplane format;
270 unsigned int sequence;
274 * jpu_ctx - the device context data
275 * @jpu: JPEG IP device for this context
276 * @encoder: compression (encode) operation or decompression (decode)
277 * @compr_quality: destination image quality in compression (encode) mode
278 * @out_q: source (output) queue information
279 * @cap_q: destination (capture) queue information
281 * @ctrl_handler: controls handler
286 unsigned short compr_quality;
287 struct jpu_q_data out_q;
288 struct jpu_q_data cap_q;
290 struct v4l2_ctrl_handler ctrl_handler;
294 * jpeg_buffer - description of memory containing input JPEG data
295 * @end: end position in the buffer
296 * @curr: current position in the buffer
303 static struct jpu_fmt jpu_formats[] = {
304 { V4L2_PIX_FMT_JPEG, V4L2_COLORSPACE_JPEG,
305 {0, 0}, 0, 0, 0, 1, JPU_ENC_CAPTURE | JPU_DEC_OUTPUT },
306 { V4L2_PIX_FMT_NV16M, V4L2_COLORSPACE_SRGB,
307 {8, 8}, 2, 2, JPU_JPEG_422, 2, JPU_ENC_OUTPUT | JPU_DEC_CAPTURE },
308 { V4L2_PIX_FMT_NV12M, V4L2_COLORSPACE_SRGB,
309 {8, 4}, 2, 2, JPU_JPEG_420, 2, JPU_ENC_OUTPUT | JPU_DEC_CAPTURE },
310 { V4L2_PIX_FMT_NV16, V4L2_COLORSPACE_SRGB,
311 {16, 0}, 2, 2, JPU_JPEG_422, 1, JPU_ENC_OUTPUT | JPU_DEC_CAPTURE },
312 { V4L2_PIX_FMT_NV12, V4L2_COLORSPACE_SRGB,
313 {12, 0}, 2, 2, JPU_JPEG_420, 1, JPU_ENC_OUTPUT | JPU_DEC_CAPTURE },
316 static const u8 zigzag[] = {
317 0x03, 0x02, 0x0b, 0x13, 0x0a, 0x01, 0x00, 0x09,
318 0x12, 0x1b, 0x23, 0x1a, 0x11, 0x08, 0x07, 0x06,
319 0x0f, 0x10, 0x19, 0x22, 0x2b, 0x33, 0x2a, 0x21,
320 0x18, 0x17, 0x0e, 0x05, 0x04, 0x0d, 0x16, 0x1f,
321 0x20, 0x29, 0x32, 0x3b, 0x3a, 0x31, 0x28, 0x27,
322 0x1e, 0x15, 0x0e, 0x14, 0x10, 0x26, 0x2f, 0x30,
323 0x39, 0x38, 0x37, 0x2e, 0x25, 0x1c, 0x24, 0x2b,
324 0x36, 0x3f, 0x3e, 0x35, 0x2c, 0x34, 0x3d, 0x3c
327 #define QTBL_SIZE (ALIGN(JPU_JPEG_QTBL_SIZE, \
328 sizeof(unsigned int)) / sizeof(unsigned int))
329 #define HDCTBL_SIZE (ALIGN(JPU_JPEG_HDCTBL_SIZE, \
330 sizeof(unsigned int)) / sizeof(unsigned int))
331 #define HACTBL_SIZE (ALIGN(JPU_JPEG_HACTBL_SIZE, \
332 sizeof(unsigned int)) / sizeof(unsigned int))
334 * Start of image; Quantization tables
335 * SOF0 (17 bytes payload) is Baseline DCT - Sample precision, height, width,
336 * Number of image components, (Ci:8 - Hi:4 - Vi:4 - Tq:8) * 3 - Y,Cb,Cr;
337 * Huffman tables; Padding with 0xff (33.3.27 R01UH0501EJ0100 Rev.1.00)
339 #define JPU_JPEG_HDR_BLOB { \
340 0xff, SOI, 0xff, DQT, 0x00, JPU_JPEG_QTBL_SIZE + 0x3, JPU_JPEG_LUM, \
341 [JPU_JPEG_QTBL_LUM_OFFSET ... \
342 JPU_JPEG_QTBL_LUM_OFFSET + JPU_JPEG_QTBL_SIZE - 1] = 0x00, \
343 0xff, DQT, 0x00, JPU_JPEG_QTBL_SIZE + 0x3, JPU_JPEG_CHR, \
344 [JPU_JPEG_QTBL_CHR_OFFSET ... JPU_JPEG_QTBL_CHR_OFFSET + \
345 JPU_JPEG_QTBL_SIZE - 1] = 0x00, 0xff, SOF0, 0x00, 0x11, 0x08, \
346 [JPU_JPEG_HEIGHT_OFFSET ... JPU_JPEG_HEIGHT_OFFSET + 1] = 0x00, \
347 [JPU_JPEG_WIDTH_OFFSET ... JPU_JPEG_WIDTH_OFFSET + 1] = 0x00, \
348 0x03, 0x01, [JPU_JPEG_SUBS_OFFSET] = 0x00, JPU_JPEG_LUM, \
349 0x02, 0x11, JPU_JPEG_CHR, 0x03, 0x11, JPU_JPEG_CHR, \
350 0xff, DHT, 0x00, JPU_JPEG_HDCTBL_SIZE + 0x3, JPU_JPEG_LUM|JPU_JPEG_DC, \
351 [JPU_JPEG_HDCTBL_LUM_OFFSET ... \
352 JPU_JPEG_HDCTBL_LUM_OFFSET + JPU_JPEG_HDCTBL_SIZE - 1] = 0x00, \
353 0xff, DHT, 0x00, JPU_JPEG_HACTBL_SIZE + 0x3, JPU_JPEG_LUM|JPU_JPEG_AC, \
354 [JPU_JPEG_HACTBL_LUM_OFFSET ... \
355 JPU_JPEG_HACTBL_LUM_OFFSET + JPU_JPEG_HACTBL_SIZE - 1] = 0x00, \
356 0xff, DHT, 0x00, JPU_JPEG_HDCTBL_SIZE + 0x3, JPU_JPEG_CHR|JPU_JPEG_DC, \
357 [JPU_JPEG_HDCTBL_CHR_OFFSET ... \
358 JPU_JPEG_HDCTBL_CHR_OFFSET + JPU_JPEG_HDCTBL_SIZE - 1] = 0x00, \
359 0xff, DHT, 0x00, JPU_JPEG_HACTBL_SIZE + 0x3, JPU_JPEG_CHR|JPU_JPEG_AC, \
360 [JPU_JPEG_HACTBL_CHR_OFFSET ... \
361 JPU_JPEG_HACTBL_CHR_OFFSET + JPU_JPEG_HACTBL_SIZE - 1] = 0x00, \
362 [JPU_JPEG_PADDING_OFFSET ... JPU_JPEG_HDR_SIZE - 1] = 0xff \
365 static unsigned char jpeg_hdrs[JPU_MAX_QUALITY][JPU_JPEG_HDR_SIZE] = {
366 [0 ... JPU_MAX_QUALITY - 1] = JPU_JPEG_HDR_BLOB
369 static const unsigned int qtbl_lum[JPU_MAX_QUALITY][QTBL_SIZE] = {
371 0x14101927, 0x322e3e44, 0x10121726, 0x26354144,
372 0x19171f26, 0x35414444, 0x27262635, 0x41444444,
373 0x32263541, 0x44444444, 0x2e354144, 0x44444444,
374 0x3e414444, 0x44444444, 0x44444444, 0x44444444
377 0x100b0b10, 0x171b1f1e, 0x0b0c0c0f, 0x1417171e,
378 0x0b0c0d10, 0x171a232f, 0x100f1017, 0x1a252f40,
379 0x1714171a, 0x27334040, 0x1b171a25, 0x33404040,
380 0x1f17232f, 0x40404040, 0x1e1e2f40, 0x40404040
383 0x0c08080c, 0x11151817, 0x0809090b, 0x0f131217,
384 0x08090a0c, 0x13141b24, 0x0c0b0c15, 0x141c2435,
385 0x110f1314, 0x1e27333b, 0x1513141c, 0x27333b3b,
386 0x18121b24, 0x333b3b3b, 0x17172435, 0x3b3b3b3b
389 0x08060608, 0x0c0e1011, 0x06060608, 0x0a0d0c0f,
390 0x06060708, 0x0d0e1218, 0x0808080e, 0x0d131823,
391 0x0c0a0d0d, 0x141a2227, 0x0e0d0e13, 0x1a222727,
392 0x100c1318, 0x22272727, 0x110f1823, 0x27272727
396 static const unsigned int qtbl_chr[JPU_MAX_QUALITY][QTBL_SIZE] = {
398 0x15192026, 0x36444444, 0x191c1826, 0x36444444,
399 0x2018202b, 0x42444444, 0x26262b35, 0x44444444,
400 0x36424444, 0x44444444, 0x44444444, 0x44444444,
401 0x44444444, 0x44444444, 0x44444444, 0x44444444
404 0x110f1115, 0x141a2630, 0x0f131211, 0x141a232b,
405 0x11121416, 0x1a1e2e35, 0x1511161c, 0x1e273540,
406 0x14141a1e, 0x27304040, 0x1a1a1e27, 0x303f4040,
407 0x26232e35, 0x40404040, 0x302b3540, 0x40404040
410 0x0d0b0d10, 0x14141d25, 0x0b0e0e0e, 0x10141a20,
411 0x0d0e0f11, 0x14172328, 0x100e1115, 0x171e2832,
412 0x14101417, 0x1e25323b, 0x1414171e, 0x25303b3b,
413 0x1d1a2328, 0x323b3b3b, 0x25202832, 0x3b3b3b3b
416 0x0908090b, 0x0e111318, 0x080a090b, 0x0e0d1116,
417 0x09090d0e, 0x0d0f171a, 0x0b0b0e0e, 0x0f141a21,
418 0x0e0e0d0f, 0x14182127, 0x110d0f14, 0x18202727,
419 0x1311171a, 0x21272727, 0x18161a21, 0x27272727
423 static const unsigned int hdctbl_lum[HDCTBL_SIZE] = {
424 0x00010501, 0x01010101, 0x01000000, 0x00000000,
425 0x00010203, 0x04050607, 0x08090a0b
428 static const unsigned int hdctbl_chr[HDCTBL_SIZE] = {
429 0x00010501, 0x01010101, 0x01000000, 0x00000000,
430 0x00010203, 0x04050607, 0x08090a0b
433 static const unsigned int hactbl_lum[HACTBL_SIZE] = {
434 0x00020103, 0x03020403, 0x05050404, 0x0000017d, 0x01020300, 0x04110512,
435 0x21314106, 0x13516107, 0x22711432, 0x8191a108, 0x2342b1c1, 0x1552d1f0,
436 0x24336272, 0x82090a16, 0x1718191a, 0x25262728, 0x292a3435, 0x36373839,
437 0x3a434445, 0x46474849, 0x4a535455, 0x56575859, 0x5a636465, 0x66676869,
438 0x6a737475, 0x76777879, 0x7a838485, 0x86878889, 0x8a929394, 0x95969798,
439 0x999aa2a3, 0xa4a5a6a7, 0xa8a9aab2, 0xb3b4b5b6, 0xb7b8b9ba, 0xc2c3c4c5,
440 0xc6c7c8c9, 0xcad2d3d4, 0xd5d6d7d8, 0xd9dae1e2, 0xe3e4e5e6, 0xe7e8e9ea,
441 0xf1f2f3f4, 0xf5f6f7f8, 0xf9fa0000
444 static const unsigned int hactbl_chr[HACTBL_SIZE] = {
445 0x00020103, 0x03020403, 0x05050404, 0x0000017d, 0x01020300, 0x04110512,
446 0x21314106, 0x13516107, 0x22711432, 0x8191a108, 0x2342b1c1, 0x1552d1f0,
447 0x24336272, 0x82090a16, 0x1718191a, 0x25262728, 0x292a3435, 0x36373839,
448 0x3a434445, 0x46474849, 0x4a535455, 0x56575859, 0x5a636465, 0x66676869,
449 0x6a737475, 0x76777879, 0x7a838485, 0x86878889, 0x8a929394, 0x95969798,
450 0x999aa2a3, 0xa4a5a6a7, 0xa8a9aab2, 0xb3b4b5b6, 0xb7b8b9ba, 0xc2c3c4c5,
451 0xc6c7c8c9, 0xcad2d3d4, 0xd5d6d7d8, 0xd9dae1e2, 0xe3e4e5e6, 0xe7e8e9ea,
452 0xf1f2f3f4, 0xf5f6f7f8, 0xf9fa0000
455 static const char *error_to_text[16] = {
458 "SOF1 to SOFF detected",
459 "Subsampling not detected",
460 "SOF accuracy error",
461 "DQT accuracy error",
464 "SOF0, DQT, and DHT not detected when SOS detected",
467 "Restart interval data number error detected",
469 "Last MCU data number error",
470 "Block data number error",
474 static struct jpu_buffer *vb2_to_jpu_buffer(struct vb2_v4l2_buffer *vb)
476 struct v4l2_m2m_buffer *b =
477 container_of(vb, struct v4l2_m2m_buffer, vb);
479 return container_of(b, struct jpu_buffer, buf);
482 static u32 jpu_read(struct jpu *jpu, unsigned int reg)
484 return ioread32(jpu->regs + reg);
487 static void jpu_write(struct jpu *jpu, u32 val, unsigned int reg)
489 iowrite32(val, jpu->regs + reg);
492 static struct jpu_ctx *ctrl_to_ctx(struct v4l2_ctrl *c)
494 return container_of(c->handler, struct jpu_ctx, ctrl_handler);
497 static struct jpu_ctx *fh_to_ctx(struct v4l2_fh *fh)
499 return container_of(fh, struct jpu_ctx, fh);
502 static void jpu_set_tbl(struct jpu *jpu, u32 reg, const unsigned int *tbl,
506 for (i = 0; i < len; i++)
507 jpu_write(jpu, tbl[i], reg + (i << 2));
510 static void jpu_set_qtbl(struct jpu *jpu, unsigned short quality)
512 jpu_set_tbl(jpu, JCQTBL(0), qtbl_lum[quality], QTBL_SIZE);
513 jpu_set_tbl(jpu, JCQTBL(1), qtbl_chr[quality], QTBL_SIZE);
516 static void jpu_set_htbl(struct jpu *jpu)
518 jpu_set_tbl(jpu, JCHTBD(0), hdctbl_lum, HDCTBL_SIZE);
519 jpu_set_tbl(jpu, JCHTBA(0), hactbl_lum, HACTBL_SIZE);
520 jpu_set_tbl(jpu, JCHTBD(1), hdctbl_chr, HDCTBL_SIZE);
521 jpu_set_tbl(jpu, JCHTBA(1), hactbl_chr, HACTBL_SIZE);
524 static int jpu_wait_reset(struct jpu *jpu)
526 unsigned long timeout;
528 timeout = jiffies + msecs_to_jiffies(JPU_RESET_TIMEOUT);
530 while (jpu_read(jpu, JCCMD) & JCCMD_SRST) {
531 if (time_after(jiffies, timeout)) {
532 dev_err(jpu->dev, "timed out in reset\n");
541 static int jpu_reset(struct jpu *jpu)
543 jpu_write(jpu, JCCMD_SRST, JCCMD);
544 return jpu_wait_reset(jpu);
548 * ============================================================================
549 * video ioctl operations
550 * ============================================================================
552 static void put_qtbl(u8 *p, const u8 *qtbl)
556 for (i = 0; i < ARRAY_SIZE(zigzag); i++)
557 p[i] = *(qtbl + zigzag[i]);
560 static void put_htbl(u8 *p, const u8 *htbl, unsigned int len)
564 for (i = 0; i < len; i += 4)
565 for (j = 0; j < 4 && (i + j) < len; ++j)
566 p[i + j] = htbl[i + 3 - j];
569 static void jpu_generate_hdr(unsigned short quality, unsigned char *p)
571 put_qtbl(p + JPU_JPEG_QTBL_LUM_OFFSET, (const u8 *)qtbl_lum[quality]);
572 put_qtbl(p + JPU_JPEG_QTBL_CHR_OFFSET, (const u8 *)qtbl_chr[quality]);
574 put_htbl(p + JPU_JPEG_HDCTBL_LUM_OFFSET, (const u8 *)hdctbl_lum,
575 JPU_JPEG_HDCTBL_SIZE);
576 put_htbl(p + JPU_JPEG_HACTBL_LUM_OFFSET, (const u8 *)hactbl_lum,
577 JPU_JPEG_HACTBL_SIZE);
579 put_htbl(p + JPU_JPEG_HDCTBL_CHR_OFFSET, (const u8 *)hdctbl_chr,
580 JPU_JPEG_HDCTBL_SIZE);
581 put_htbl(p + JPU_JPEG_HACTBL_CHR_OFFSET, (const u8 *)hactbl_chr,
582 JPU_JPEG_HACTBL_SIZE);
585 static int get_byte(struct jpeg_buffer *buf)
587 if (buf->curr >= buf->end)
590 return *(u8 *)buf->curr++;
593 static int get_word_be(struct jpeg_buffer *buf, unsigned int *word)
595 if (buf->end - buf->curr < 2)
598 *word = get_unaligned_be16(buf->curr);
604 static void skip(struct jpeg_buffer *buf, unsigned long len)
606 buf->curr += min((unsigned long)(buf->end - buf->curr), len);
609 static u8 jpu_parse_hdr(void *buffer, unsigned long size, unsigned int *width,
610 unsigned int *height)
612 struct jpeg_buffer jpeg_buffer;
616 jpeg_buffer.end = buffer + size;
617 jpeg_buffer.curr = buffer;
620 * basic size check and EOI - we don't want to let JPU cross
621 * buffer bounds in any case. Hope it's stopping by EOI.
623 if (size < JPU_JPEG_MIN_SIZE || *(u8 *)(buffer + size - 1) != EOI)
629 /* skip preceding filler bytes */
631 c = get_byte(&jpeg_buffer);
632 while (c == 0xff || c == 0);
634 if (!soi && c == SOI) {
637 } else if (soi != (c != SOI))
641 case SOF0: /* SOF0: baseline JPEG */
642 skip(&jpeg_buffer, 3); /* segment length and bpp */
643 if (get_word_be(&jpeg_buffer, height) ||
644 get_word_be(&jpeg_buffer, width) ||
645 get_byte(&jpeg_buffer) != 3) /* YCbCr only */
648 skip(&jpeg_buffer, 1);
649 return get_byte(&jpeg_buffer);
654 case APP0 ... APP0 + 0x0f:
655 if (get_word_be(&jpeg_buffer, &word))
657 skip(&jpeg_buffer, (long)word - 2);
668 static int jpu_querycap(struct file *file, void *priv,
669 struct v4l2_capability *cap)
671 struct jpu_ctx *ctx = fh_to_ctx(priv);
674 strlcpy(cap->card, DRV_NAME " encoder", sizeof(cap->card));
676 strlcpy(cap->card, DRV_NAME " decoder", sizeof(cap->card));
678 strlcpy(cap->driver, DRV_NAME, sizeof(cap->driver));
679 snprintf(cap->bus_info, sizeof(cap->bus_info), "platform:%s",
680 dev_name(ctx->jpu->dev));
681 cap->device_caps |= V4L2_CAP_STREAMING | V4L2_CAP_VIDEO_M2M_MPLANE;
682 cap->capabilities = V4L2_CAP_DEVICE_CAPS | cap->device_caps;
683 memset(cap->reserved, 0, sizeof(cap->reserved));
688 static struct jpu_fmt *jpu_find_format(bool encoder, u32 pixelformat,
689 unsigned int fmt_type)
691 unsigned int i, fmt_flag;
694 fmt_flag = fmt_type == JPU_FMT_TYPE_OUTPUT ? JPU_ENC_OUTPUT :
697 fmt_flag = fmt_type == JPU_FMT_TYPE_OUTPUT ? JPU_DEC_OUTPUT :
700 for (i = 0; i < ARRAY_SIZE(jpu_formats); i++) {
701 struct jpu_fmt *fmt = &jpu_formats[i];
703 if (fmt->fourcc == pixelformat && fmt->types & fmt_flag)
710 static int jpu_enum_fmt(struct v4l2_fmtdesc *f, u32 type)
712 unsigned int i, num = 0;
714 for (i = 0; i < ARRAY_SIZE(jpu_formats); ++i) {
715 if (jpu_formats[i].types & type) {
722 if (i >= ARRAY_SIZE(jpu_formats))
725 f->pixelformat = jpu_formats[i].fourcc;
730 static int jpu_enum_fmt_cap(struct file *file, void *priv,
731 struct v4l2_fmtdesc *f)
733 struct jpu_ctx *ctx = fh_to_ctx(priv);
735 return jpu_enum_fmt(f, ctx->encoder ? JPU_ENC_CAPTURE :
739 static int jpu_enum_fmt_out(struct file *file, void *priv,
740 struct v4l2_fmtdesc *f)
742 struct jpu_ctx *ctx = fh_to_ctx(priv);
744 return jpu_enum_fmt(f, ctx->encoder ? JPU_ENC_OUTPUT : JPU_DEC_OUTPUT);
747 static struct jpu_q_data *jpu_get_q_data(struct jpu_ctx *ctx,
748 enum v4l2_buf_type type)
750 if (V4L2_TYPE_IS_OUTPUT(type))
756 static void jpu_bound_align_image(u32 *w, unsigned int w_min,
757 unsigned int w_max, unsigned int w_align,
758 u32 *h, unsigned int h_min,
759 unsigned int h_max, unsigned int h_align)
761 unsigned int width, height, w_step, h_step;
766 w_step = 1U << w_align;
767 h_step = 1U << h_align;
768 v4l_bound_align_image(w, w_min, w_max, w_align, h, h_min, h_max,
771 if (*w < width && *w + w_step < w_max)
773 if (*h < height && *h + h_step < h_max)
777 static int __jpu_try_fmt(struct jpu_ctx *ctx, struct jpu_fmt **fmtinfo,
778 struct v4l2_pix_format_mplane *pix,
779 enum v4l2_buf_type type)
782 unsigned int f_type, w, h;
784 f_type = V4L2_TYPE_IS_OUTPUT(type) ? JPU_FMT_TYPE_OUTPUT :
785 JPU_FMT_TYPE_CAPTURE;
787 fmt = jpu_find_format(ctx->encoder, pix->pixelformat, f_type);
789 unsigned int pixelformat;
791 dev_dbg(ctx->jpu->dev, "unknown format; set default format\n");
793 pixelformat = f_type == JPU_FMT_TYPE_OUTPUT ?
794 V4L2_PIX_FMT_NV16M : V4L2_PIX_FMT_JPEG;
796 pixelformat = f_type == JPU_FMT_TYPE_CAPTURE ?
797 V4L2_PIX_FMT_NV16M : V4L2_PIX_FMT_JPEG;
798 fmt = jpu_find_format(ctx->encoder, pixelformat, f_type);
801 pix->pixelformat = fmt->fourcc;
802 pix->colorspace = fmt->colorspace;
803 pix->field = V4L2_FIELD_NONE;
804 pix->num_planes = fmt->num_planes;
805 memset(pix->reserved, 0, sizeof(pix->reserved));
807 jpu_bound_align_image(&pix->width, JPU_WIDTH_MIN, JPU_WIDTH_MAX,
808 fmt->h_align, &pix->height, JPU_HEIGHT_MIN,
809 JPU_HEIGHT_MAX, fmt->v_align);
814 if (fmt->fourcc == V4L2_PIX_FMT_JPEG) {
815 /* ignore userspaces's sizeimage for encoding */
816 if (pix->plane_fmt[0].sizeimage <= 0 || ctx->encoder)
817 pix->plane_fmt[0].sizeimage = JPU_JPEG_HDR_SIZE +
818 (JPU_JPEG_MAX_BYTES_PER_PIXEL * w * h);
819 pix->plane_fmt[0].bytesperline = 0;
820 memset(pix->plane_fmt[0].reserved, 0,
821 sizeof(pix->plane_fmt[0].reserved));
823 unsigned int i, bpl = 0;
825 for (i = 0; i < pix->num_planes; ++i)
826 bpl = max(bpl, pix->plane_fmt[i].bytesperline);
828 bpl = clamp_t(unsigned int, bpl, w, JPU_WIDTH_MAX);
829 bpl = round_up(bpl, JPU_MEMALIGN);
831 for (i = 0; i < pix->num_planes; ++i) {
832 pix->plane_fmt[i].bytesperline = bpl;
833 pix->plane_fmt[i].sizeimage = bpl * h * fmt->bpp[i] / 8;
834 memset(pix->plane_fmt[i].reserved, 0,
835 sizeof(pix->plane_fmt[i].reserved));
845 static int jpu_try_fmt(struct file *file, void *priv, struct v4l2_format *f)
847 struct jpu_ctx *ctx = fh_to_ctx(priv);
849 if (!v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type))
852 return __jpu_try_fmt(ctx, NULL, &f->fmt.pix_mp, f->type);
855 static int jpu_s_fmt(struct file *file, void *priv, struct v4l2_format *f)
857 struct vb2_queue *vq;
858 struct jpu_ctx *ctx = fh_to_ctx(priv);
859 struct v4l2_m2m_ctx *m2m_ctx = ctx->fh.m2m_ctx;
860 struct jpu_fmt *fmtinfo;
861 struct jpu_q_data *q_data;
864 vq = v4l2_m2m_get_vq(m2m_ctx, f->type);
868 if (vb2_is_busy(vq)) {
869 v4l2_err(&ctx->jpu->v4l2_dev, "%s queue busy\n", __func__);
873 ret = __jpu_try_fmt(ctx, &fmtinfo, &f->fmt.pix_mp, f->type);
877 q_data = jpu_get_q_data(ctx, f->type);
879 q_data->format = f->fmt.pix_mp;
880 q_data->fmtinfo = fmtinfo;
885 static int jpu_g_fmt(struct file *file, void *priv, struct v4l2_format *f)
887 struct jpu_q_data *q_data;
888 struct jpu_ctx *ctx = fh_to_ctx(priv);
890 if (!v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type))
893 q_data = jpu_get_q_data(ctx, f->type);
894 f->fmt.pix_mp = q_data->format;
902 static int jpu_s_ctrl(struct v4l2_ctrl *ctrl)
904 struct jpu_ctx *ctx = ctrl_to_ctx(ctrl);
907 spin_lock_irqsave(&ctx->jpu->lock, flags);
908 if (ctrl->id == V4L2_CID_JPEG_COMPRESSION_QUALITY)
909 ctx->compr_quality = ctrl->val;
910 spin_unlock_irqrestore(&ctx->jpu->lock, flags);
915 static const struct v4l2_ctrl_ops jpu_ctrl_ops = {
916 .s_ctrl = jpu_s_ctrl,
919 static int jpu_streamon(struct file *file, void *priv, enum v4l2_buf_type type)
921 struct jpu_ctx *ctx = fh_to_ctx(priv);
922 struct jpu_q_data *src_q_data, *dst_q_data, *orig, adj, *ref;
923 enum v4l2_buf_type adj_type;
925 src_q_data = jpu_get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE);
926 dst_q_data = jpu_get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE);
932 adj_type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
937 adj_type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
940 adj.format.width = ref->format.width;
941 adj.format.height = ref->format.height;
943 __jpu_try_fmt(ctx, NULL, &adj.format, adj_type);
945 if (adj.format.width != orig->format.width ||
946 adj.format.height != orig->format.height) {
947 dev_err(ctx->jpu->dev, "src and dst formats do not match.\n");
948 /* maybe we can return -EPIPE here? */
952 return v4l2_m2m_streamon(file, ctx->fh.m2m_ctx, type);
955 static const struct v4l2_ioctl_ops jpu_ioctl_ops = {
956 .vidioc_querycap = jpu_querycap,
958 .vidioc_enum_fmt_vid_cap_mplane = jpu_enum_fmt_cap,
959 .vidioc_enum_fmt_vid_out_mplane = jpu_enum_fmt_out,
960 .vidioc_g_fmt_vid_cap_mplane = jpu_g_fmt,
961 .vidioc_g_fmt_vid_out_mplane = jpu_g_fmt,
962 .vidioc_try_fmt_vid_cap_mplane = jpu_try_fmt,
963 .vidioc_try_fmt_vid_out_mplane = jpu_try_fmt,
964 .vidioc_s_fmt_vid_cap_mplane = jpu_s_fmt,
965 .vidioc_s_fmt_vid_out_mplane = jpu_s_fmt,
967 .vidioc_reqbufs = v4l2_m2m_ioctl_reqbufs,
968 .vidioc_create_bufs = v4l2_m2m_ioctl_create_bufs,
969 .vidioc_querybuf = v4l2_m2m_ioctl_querybuf,
970 .vidioc_qbuf = v4l2_m2m_ioctl_qbuf,
971 .vidioc_dqbuf = v4l2_m2m_ioctl_dqbuf,
972 .vidioc_expbuf = v4l2_m2m_ioctl_expbuf,
974 .vidioc_streamon = jpu_streamon,
975 .vidioc_streamoff = v4l2_m2m_ioctl_streamoff,
977 .vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
978 .vidioc_unsubscribe_event = v4l2_event_unsubscribe
981 static int jpu_controls_create(struct jpu_ctx *ctx)
983 struct v4l2_ctrl *ctrl;
986 v4l2_ctrl_handler_init(&ctx->ctrl_handler, 1);
988 ctrl = v4l2_ctrl_new_std(&ctx->ctrl_handler, &jpu_ctrl_ops,
989 V4L2_CID_JPEG_COMPRESSION_QUALITY,
990 0, JPU_MAX_QUALITY - 1, 1, 0);
992 if (ctx->ctrl_handler.error) {
993 ret = ctx->ctrl_handler.error;
998 ctrl->flags |= V4L2_CTRL_FLAG_VOLATILE |
999 V4L2_CTRL_FLAG_READ_ONLY;
1001 ret = v4l2_ctrl_handler_setup(&ctx->ctrl_handler);
1008 v4l2_ctrl_handler_free(&ctx->ctrl_handler);
1013 * ============================================================================
1015 * ============================================================================
1017 static int jpu_queue_setup(struct vb2_queue *vq,
1019 unsigned int *nbuffers, unsigned int *nplanes,
1020 unsigned int sizes[], void *alloc_ctxs[])
1022 const struct v4l2_format *fmt = parg;
1023 struct jpu_ctx *ctx = vb2_get_drv_priv(vq);
1024 struct jpu_q_data *q_data;
1027 q_data = jpu_get_q_data(ctx, vq->type);
1029 *nplanes = q_data->format.num_planes;
1031 for (i = 0; i < *nplanes; i++) {
1032 unsigned int q_size = q_data->format.plane_fmt[i].sizeimage;
1033 unsigned int f_size = fmt ?
1034 fmt->fmt.pix_mp.plane_fmt[i].sizeimage : 0;
1036 if (fmt && f_size < q_size)
1039 sizes[i] = fmt ? f_size : q_size;
1040 alloc_ctxs[i] = ctx->jpu->alloc_ctx;
1046 static int jpu_buf_prepare(struct vb2_buffer *vb)
1048 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
1049 struct jpu_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
1050 struct jpu_q_data *q_data;
1053 q_data = jpu_get_q_data(ctx, vb->vb2_queue->type);
1055 if (V4L2_TYPE_IS_OUTPUT(vb->vb2_queue->type)) {
1056 if (vbuf->field == V4L2_FIELD_ANY)
1057 vbuf->field = V4L2_FIELD_NONE;
1058 if (vbuf->field != V4L2_FIELD_NONE) {
1059 dev_err(ctx->jpu->dev, "%s field isn't supported\n",
1065 for (i = 0; i < q_data->format.num_planes; i++) {
1066 unsigned long size = q_data->format.plane_fmt[i].sizeimage;
1068 if (vb2_plane_size(vb, i) < size) {
1069 dev_err(ctx->jpu->dev,
1070 "%s: data will not fit into plane (%lu < %lu)\n",
1071 __func__, vb2_plane_size(vb, i), size);
1075 /* decoder capture queue */
1076 if (!ctx->encoder && !V4L2_TYPE_IS_OUTPUT(vb->vb2_queue->type))
1077 vb2_set_plane_payload(vb, i, size);
1083 static void jpu_buf_queue(struct vb2_buffer *vb)
1085 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
1086 struct jpu_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
1088 if (!ctx->encoder && V4L2_TYPE_IS_OUTPUT(vb->vb2_queue->type)) {
1089 struct jpu_buffer *jpu_buf = vb2_to_jpu_buffer(vbuf);
1090 struct jpu_q_data *q_data, adjust;
1091 void *buffer = vb2_plane_vaddr(vb, 0);
1092 unsigned long buf_size = vb2_get_plane_payload(vb, 0);
1093 unsigned int width, height;
1095 u8 subsampling = jpu_parse_hdr(buffer, buf_size, &width,
1098 /* check if JPEG data basic parsing was successful */
1099 if (subsampling != JPU_JPEG_422 && subsampling != JPU_JPEG_420)
1102 q_data = &ctx->out_q;
1105 adjust.format.width = width;
1106 adjust.format.height = height;
1108 __jpu_try_fmt(ctx, &adjust.fmtinfo, &adjust.format,
1109 V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE);
1111 if (adjust.format.width != q_data->format.width ||
1112 adjust.format.height != q_data->format.height)
1116 * keep subsampling in buffer to check it
1117 * for compatibility in device_run
1119 jpu_buf->subsampling = subsampling;
1122 if (ctx->fh.m2m_ctx)
1123 v4l2_m2m_buf_queue(ctx->fh.m2m_ctx, vbuf);
1128 dev_err(ctx->jpu->dev, "incompatible or corrupted JPEG data\n");
1129 vb2_buffer_done(vb, VB2_BUF_STATE_ERROR);
1132 static void jpu_buf_finish(struct vb2_buffer *vb)
1134 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
1135 struct jpu_buffer *jpu_buf = vb2_to_jpu_buffer(vbuf);
1136 struct jpu_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
1137 struct jpu_q_data *q_data = &ctx->out_q;
1138 enum v4l2_buf_type type = vb->vb2_queue->type;
1141 if (vb->state == VB2_BUF_STATE_DONE)
1142 vbuf->sequence = jpu_get_q_data(ctx, type)->sequence++;
1144 if (!ctx->encoder || vb->state != VB2_BUF_STATE_DONE ||
1145 V4L2_TYPE_IS_OUTPUT(type))
1148 buffer = vb2_plane_vaddr(vb, 0);
1150 memcpy(buffer, jpeg_hdrs[jpu_buf->compr_quality], JPU_JPEG_HDR_SIZE);
1151 *(__be16 *)(buffer + JPU_JPEG_HEIGHT_OFFSET) =
1152 cpu_to_be16(q_data->format.height);
1153 *(__be16 *)(buffer + JPU_JPEG_WIDTH_OFFSET) =
1154 cpu_to_be16(q_data->format.width);
1155 *(buffer + JPU_JPEG_SUBS_OFFSET) = q_data->fmtinfo->subsampling;
1158 static int jpu_start_streaming(struct vb2_queue *vq, unsigned count)
1160 struct jpu_ctx *ctx = vb2_get_drv_priv(vq);
1161 struct jpu_q_data *q_data = jpu_get_q_data(ctx, vq->type);
1163 q_data->sequence = 0;
1167 static void jpu_stop_streaming(struct vb2_queue *vq)
1169 struct jpu_ctx *ctx = vb2_get_drv_priv(vq);
1170 struct vb2_v4l2_buffer *vb;
1171 unsigned long flags;
1174 if (V4L2_TYPE_IS_OUTPUT(vq->type))
1175 vb = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
1177 vb = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
1180 spin_lock_irqsave(&ctx->jpu->lock, flags);
1181 v4l2_m2m_buf_done(vb, VB2_BUF_STATE_ERROR);
1182 spin_unlock_irqrestore(&ctx->jpu->lock, flags);
1186 static struct vb2_ops jpu_qops = {
1187 .queue_setup = jpu_queue_setup,
1188 .buf_prepare = jpu_buf_prepare,
1189 .buf_queue = jpu_buf_queue,
1190 .buf_finish = jpu_buf_finish,
1191 .start_streaming = jpu_start_streaming,
1192 .stop_streaming = jpu_stop_streaming,
1193 .wait_prepare = vb2_ops_wait_prepare,
1194 .wait_finish = vb2_ops_wait_finish,
1197 static int jpu_queue_init(void *priv, struct vb2_queue *src_vq,
1198 struct vb2_queue *dst_vq)
1200 struct jpu_ctx *ctx = priv;
1203 memset(src_vq, 0, sizeof(*src_vq));
1204 src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
1205 src_vq->io_modes = VB2_MMAP | VB2_DMABUF;
1206 src_vq->drv_priv = ctx;
1207 src_vq->buf_struct_size = sizeof(struct jpu_buffer);
1208 src_vq->ops = &jpu_qops;
1209 src_vq->mem_ops = &vb2_dma_contig_memops;
1210 src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
1211 src_vq->lock = &ctx->jpu->mutex;
1213 ret = vb2_queue_init(src_vq);
1217 memset(dst_vq, 0, sizeof(*dst_vq));
1218 dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
1219 dst_vq->io_modes = VB2_MMAP | VB2_DMABUF;
1220 dst_vq->drv_priv = ctx;
1221 dst_vq->buf_struct_size = sizeof(struct jpu_buffer);
1222 dst_vq->ops = &jpu_qops;
1223 dst_vq->mem_ops = &vb2_dma_contig_memops;
1224 dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
1225 dst_vq->lock = &ctx->jpu->mutex;
1227 return vb2_queue_init(dst_vq);
1231 * ============================================================================
1232 * Device file operations
1233 * ============================================================================
1235 static int jpu_open(struct file *file)
1237 struct jpu *jpu = video_drvdata(file);
1238 struct video_device *vfd = video_devdata(file);
1239 struct jpu_ctx *ctx;
1242 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
1246 v4l2_fh_init(&ctx->fh, vfd);
1247 ctx->fh.ctrl_handler = &ctx->ctrl_handler;
1248 file->private_data = &ctx->fh;
1249 v4l2_fh_add(&ctx->fh);
1252 ctx->encoder = vfd == &jpu->vfd_encoder;
1254 __jpu_try_fmt(ctx, &ctx->out_q.fmtinfo, &ctx->out_q.format,
1255 V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE);
1256 __jpu_try_fmt(ctx, &ctx->cap_q.fmtinfo, &ctx->cap_q.format,
1257 V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE);
1259 ctx->fh.m2m_ctx = v4l2_m2m_ctx_init(jpu->m2m_dev, ctx, jpu_queue_init);
1260 if (IS_ERR(ctx->fh.m2m_ctx)) {
1261 ret = PTR_ERR(ctx->fh.m2m_ctx);
1262 goto v4l_prepare_rollback;
1265 ret = jpu_controls_create(ctx);
1267 goto v4l_prepare_rollback;
1269 if (mutex_lock_interruptible(&jpu->mutex)) {
1271 goto v4l_prepare_rollback;
1274 if (jpu->ref_count == 0) {
1275 ret = clk_prepare_enable(jpu->clk);
1277 goto device_prepare_rollback;
1278 /* ...issue software reset */
1279 ret = jpu_reset(jpu);
1281 goto device_prepare_rollback;
1286 mutex_unlock(&jpu->mutex);
1289 device_prepare_rollback:
1290 mutex_unlock(&jpu->mutex);
1291 v4l_prepare_rollback:
1292 v4l2_fh_del(&ctx->fh);
1293 v4l2_fh_exit(&ctx->fh);
1298 static int jpu_release(struct file *file)
1300 struct jpu *jpu = video_drvdata(file);
1301 struct jpu_ctx *ctx = fh_to_ctx(file->private_data);
1303 mutex_lock(&jpu->mutex);
1304 if (--jpu->ref_count == 0)
1305 clk_disable_unprepare(jpu->clk);
1306 mutex_unlock(&jpu->mutex);
1308 v4l2_m2m_ctx_release(ctx->fh.m2m_ctx);
1309 v4l2_ctrl_handler_free(&ctx->ctrl_handler);
1310 v4l2_fh_del(&ctx->fh);
1311 v4l2_fh_exit(&ctx->fh);
1317 static const struct v4l2_file_operations jpu_fops = {
1318 .owner = THIS_MODULE,
1320 .release = jpu_release,
1321 .unlocked_ioctl = video_ioctl2,
1322 .poll = v4l2_m2m_fop_poll,
1323 .mmap = v4l2_m2m_fop_mmap,
1327 * ============================================================================
1329 * ============================================================================
1331 static void jpu_cleanup(struct jpu_ctx *ctx, bool reset)
1333 /* remove current buffers and finish job */
1334 struct vb2_v4l2_buffer *src_buf, *dst_buf;
1335 unsigned long flags;
1337 spin_lock_irqsave(&ctx->jpu->lock, flags);
1339 src_buf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
1340 dst_buf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
1342 v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_ERROR);
1343 v4l2_m2m_buf_done(dst_buf, VB2_BUF_STATE_ERROR);
1345 /* ...and give it a chance on next run */
1347 jpu_write(ctx->jpu, JCCMD_SRST, JCCMD);
1349 spin_unlock_irqrestore(&ctx->jpu->lock, flags);
1351 v4l2_m2m_job_finish(ctx->jpu->m2m_dev, ctx->fh.m2m_ctx);
1354 static void jpu_device_run(void *priv)
1356 struct jpu_ctx *ctx = priv;
1357 struct jpu *jpu = ctx->jpu;
1358 struct jpu_buffer *jpu_buf;
1359 struct jpu_q_data *q_data;
1360 struct vb2_v4l2_buffer *src_buf, *dst_buf;
1361 unsigned int w, h, bpl;
1362 unsigned char num_planes, subsampling;
1363 unsigned long flags;
1365 /* ...wait until module reset completes; we have mutex locked here */
1366 if (jpu_wait_reset(jpu)) {
1367 jpu_cleanup(ctx, true);
1371 spin_lock_irqsave(&ctx->jpu->lock, flags);
1375 src_buf = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
1376 dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
1379 jpu_buf = vb2_to_jpu_buffer(dst_buf);
1380 q_data = &ctx->out_q;
1382 jpu_buf = vb2_to_jpu_buffer(src_buf);
1383 q_data = &ctx->cap_q;
1386 w = q_data->format.width;
1387 h = q_data->format.height;
1388 bpl = q_data->format.plane_fmt[0].bytesperline;
1389 num_planes = q_data->fmtinfo->num_planes;
1390 subsampling = q_data->fmtinfo->subsampling;
1393 unsigned long src_1_addr, src_2_addr, dst_addr;
1394 unsigned int redu, inft;
1396 dst_addr = vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0);
1398 vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 0);
1400 src_2_addr = vb2_dma_contig_plane_dma_addr(
1401 &src_buf->vb2_buf, 1);
1403 src_2_addr = src_1_addr + w * h;
1405 jpu_buf->compr_quality = ctx->compr_quality;
1407 if (subsampling == JPU_JPEG_420) {
1408 redu = JCMOD_REDU_420;
1409 inft = JIFECNT_INFT_420;
1411 redu = JCMOD_REDU_422;
1412 inft = JIFECNT_INFT_422;
1415 /* only no marker mode works for encoding */
1416 jpu_write(jpu, JCMOD_DSP_ENC | JCMOD_PCTR | redu |
1417 JCMOD_MSKIP_ENABLE, JCMOD);
1419 jpu_write(jpu, JIFECNT_SWAP_WB | inft, JIFECNT);
1420 jpu_write(jpu, JIFDCNT_SWAP_WB, JIFDCNT);
1421 jpu_write(jpu, JINTE_TRANSF_COMPL, JINTE);
1423 /* Y and C components source addresses */
1424 jpu_write(jpu, src_1_addr, JIFESYA1);
1425 jpu_write(jpu, src_2_addr, JIFESCA1);
1428 jpu_write(jpu, bpl, JIFESMW);
1430 jpu_write(jpu, (w >> 8) & JCSZ_MASK, JCHSZU);
1431 jpu_write(jpu, w & JCSZ_MASK, JCHSZD);
1433 jpu_write(jpu, (h >> 8) & JCSZ_MASK, JCVSZU);
1434 jpu_write(jpu, h & JCSZ_MASK, JCVSZD);
1436 jpu_write(jpu, w, JIFESHSZ);
1437 jpu_write(jpu, h, JIFESVSZ);
1439 jpu_write(jpu, dst_addr + JPU_JPEG_HDR_SIZE, JIFEDA1);
1441 jpu_write(jpu, 0 << JCQTN_SHIFT(1) | 1 << JCQTN_SHIFT(2) |
1442 1 << JCQTN_SHIFT(3), JCQTN);
1444 jpu_write(jpu, 0 << JCHTN_AC_SHIFT(1) | 0 << JCHTN_DC_SHIFT(1) |
1445 1 << JCHTN_AC_SHIFT(2) | 1 << JCHTN_DC_SHIFT(2) |
1446 1 << JCHTN_AC_SHIFT(3) | 1 << JCHTN_DC_SHIFT(3),
1449 jpu_set_qtbl(jpu, ctx->compr_quality);
1452 unsigned long src_addr, dst_1_addr, dst_2_addr;
1454 if (jpu_buf->subsampling != subsampling) {
1455 dev_err(ctx->jpu->dev,
1456 "src and dst formats do not match.\n");
1457 spin_unlock_irqrestore(&ctx->jpu->lock, flags);
1458 jpu_cleanup(ctx, false);
1462 src_addr = vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 0);
1464 vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0);
1465 if (q_data->fmtinfo->num_planes > 1)
1466 dst_2_addr = vb2_dma_contig_plane_dma_addr(
1467 &dst_buf->vb2_buf, 1);
1469 dst_2_addr = dst_1_addr + w * h;
1471 /* ...set up decoder operation */
1472 jpu_write(jpu, JCMOD_DSP_DEC | JCMOD_PCTR, JCMOD);
1473 jpu_write(jpu, JIFECNT_SWAP_WB, JIFECNT);
1474 jpu_write(jpu, JIFDCNT_SWAP_WB, JIFDCNT);
1476 /* ...enable interrupts on transfer completion and d-g error */
1477 jpu_write(jpu, JINTE_TRANSF_COMPL | JINTE_ERR, JINTE);
1479 /* ...set source/destination addresses of encoded data */
1480 jpu_write(jpu, src_addr, JIFDSA1);
1481 jpu_write(jpu, dst_1_addr, JIFDDYA1);
1482 jpu_write(jpu, dst_2_addr, JIFDDCA1);
1484 jpu_write(jpu, bpl, JIFDDMW);
1487 /* ...start encoder/decoder operation */
1488 jpu_write(jpu, JCCMD_JSRT, JCCMD);
1490 spin_unlock_irqrestore(&ctx->jpu->lock, flags);
1493 static int jpu_job_ready(void *priv)
1498 static void jpu_job_abort(void *priv)
1500 struct jpu_ctx *ctx = priv;
1502 if (!wait_event_timeout(ctx->jpu->irq_queue, !ctx->jpu->curr,
1503 msecs_to_jiffies(JPU_JOB_TIMEOUT)))
1504 jpu_cleanup(ctx, true);
1507 static struct v4l2_m2m_ops jpu_m2m_ops = {
1508 .device_run = jpu_device_run,
1509 .job_ready = jpu_job_ready,
1510 .job_abort = jpu_job_abort,
1514 * ============================================================================
1516 * ============================================================================
1518 static irqreturn_t jpu_irq_handler(int irq, void *dev_id)
1520 struct jpu *jpu = dev_id;
1521 struct jpu_ctx *curr_ctx;
1522 struct vb2_v4l2_buffer *src_buf, *dst_buf;
1523 unsigned int int_status;
1525 int_status = jpu_read(jpu, JINTS);
1527 /* ...spurious interrupt */
1528 if (!((JINTS_TRANSF_COMPL | JINTS_PROCESS_COMPL | JINTS_ERR) &
1532 /* ...clear interrupts */
1533 jpu_write(jpu, ~(int_status & JINTS_MASK), JINTS);
1534 if (int_status & (JINTS_ERR | JINTS_PROCESS_COMPL))
1535 jpu_write(jpu, JCCMD_JEND, JCCMD);
1537 spin_lock(&jpu->lock);
1539 if ((int_status & JINTS_PROCESS_COMPL) &&
1540 !(int_status & JINTS_TRANSF_COMPL))
1543 curr_ctx = v4l2_m2m_get_curr_priv(jpu->m2m_dev);
1545 /* ...instance is not running */
1546 dev_err(jpu->dev, "no active context for m2m\n");
1550 src_buf = v4l2_m2m_src_buf_remove(curr_ctx->fh.m2m_ctx);
1551 dst_buf = v4l2_m2m_dst_buf_remove(curr_ctx->fh.m2m_ctx);
1553 if (int_status & JINTS_TRANSF_COMPL) {
1554 if (curr_ctx->encoder) {
1555 unsigned long payload_size = jpu_read(jpu, JCDTCU) << 16
1556 | jpu_read(jpu, JCDTCM) << 8
1557 | jpu_read(jpu, JCDTCD);
1558 vb2_set_plane_payload(&dst_buf->vb2_buf, 0,
1559 payload_size + JPU_JPEG_HDR_SIZE);
1562 dst_buf->field = src_buf->field;
1563 dst_buf->timestamp = src_buf->timestamp;
1564 if (src_buf->flags & V4L2_BUF_FLAG_TIMECODE)
1565 dst_buf->timecode = src_buf->timecode;
1566 dst_buf->flags &= ~V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
1567 dst_buf->flags |= src_buf->flags &
1568 V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
1569 dst_buf->flags = src_buf->flags &
1570 (V4L2_BUF_FLAG_TIMECODE | V4L2_BUF_FLAG_KEYFRAME |
1571 V4L2_BUF_FLAG_PFRAME | V4L2_BUF_FLAG_BFRAME |
1572 V4L2_BUF_FLAG_TSTAMP_SRC_MASK);
1574 v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_DONE);
1575 v4l2_m2m_buf_done(dst_buf, VB2_BUF_STATE_DONE);
1576 } else if (int_status & JINTS_ERR) {
1577 unsigned char error = jpu_read(jpu, JCDERR) & JCDERR_MASK;
1579 dev_dbg(jpu->dev, "processing error: %#X: %s\n", error,
1580 error_to_text[error]);
1582 v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_ERROR);
1583 v4l2_m2m_buf_done(dst_buf, VB2_BUF_STATE_ERROR);
1588 /* ...reset JPU after completion */
1589 jpu_write(jpu, JCCMD_SRST, JCCMD);
1590 spin_unlock(&jpu->lock);
1592 v4l2_m2m_job_finish(jpu->m2m_dev, curr_ctx->fh.m2m_ctx);
1594 /* ...wakeup abort routine if needed */
1595 wake_up(&jpu->irq_queue);
1600 spin_unlock(&jpu->lock);
1605 * ============================================================================
1606 * Driver basic infrastructure
1607 * ============================================================================
1609 static const struct of_device_id jpu_dt_ids[] = {
1610 { .compatible = "renesas,jpu-r8a7790" }, /* H2 */
1611 { .compatible = "renesas,jpu-r8a7791" }, /* M2-W */
1612 { .compatible = "renesas,jpu-r8a7792" }, /* V2H */
1613 { .compatible = "renesas,jpu-r8a7793" }, /* M2-N */
1616 MODULE_DEVICE_TABLE(of, jpu_dt_ids);
1618 static int jpu_probe(struct platform_device *pdev)
1621 struct resource *res;
1625 jpu = devm_kzalloc(&pdev->dev, sizeof(*jpu), GFP_KERNEL);
1629 init_waitqueue_head(&jpu->irq_queue);
1630 mutex_init(&jpu->mutex);
1631 spin_lock_init(&jpu->lock);
1632 jpu->dev = &pdev->dev;
1634 /* memory-mapped registers */
1635 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1636 jpu->regs = devm_ioremap_resource(&pdev->dev, res);
1637 if (IS_ERR(jpu->regs))
1638 return PTR_ERR(jpu->regs);
1640 /* interrupt service routine registration */
1641 jpu->irq = ret = platform_get_irq(pdev, 0);
1643 dev_err(&pdev->dev, "cannot find IRQ\n");
1647 ret = devm_request_irq(&pdev->dev, jpu->irq, jpu_irq_handler, 0,
1648 dev_name(&pdev->dev), jpu);
1650 dev_err(&pdev->dev, "cannot claim IRQ %d\n", jpu->irq);
1655 jpu->clk = devm_clk_get(&pdev->dev, NULL);
1656 if (IS_ERR(jpu->clk)) {
1657 dev_err(&pdev->dev, "cannot get clock\n");
1658 return PTR_ERR(jpu->clk);
1662 ret = v4l2_device_register(&pdev->dev, &jpu->v4l2_dev);
1664 dev_err(&pdev->dev, "Failed to register v4l2 device\n");
1668 /* mem2mem device */
1669 jpu->m2m_dev = v4l2_m2m_init(&jpu_m2m_ops);
1670 if (IS_ERR(jpu->m2m_dev)) {
1671 v4l2_err(&jpu->v4l2_dev, "Failed to init mem2mem device\n");
1672 ret = PTR_ERR(jpu->m2m_dev);
1673 goto device_register_rollback;
1676 jpu->alloc_ctx = vb2_dma_contig_init_ctx(&pdev->dev);
1677 if (IS_ERR(jpu->alloc_ctx)) {
1678 v4l2_err(&jpu->v4l2_dev, "Failed to init memory allocator\n");
1679 ret = PTR_ERR(jpu->alloc_ctx);
1680 goto m2m_init_rollback;
1683 /* fill in qantization and Huffman tables for encoder */
1684 for (i = 0; i < JPU_MAX_QUALITY; i++)
1685 jpu_generate_hdr(i, (unsigned char *)jpeg_hdrs[i]);
1687 strlcpy(jpu->vfd_encoder.name, DRV_NAME, sizeof(jpu->vfd_encoder.name));
1688 jpu->vfd_encoder.fops = &jpu_fops;
1689 jpu->vfd_encoder.ioctl_ops = &jpu_ioctl_ops;
1690 jpu->vfd_encoder.minor = -1;
1691 jpu->vfd_encoder.release = video_device_release_empty;
1692 jpu->vfd_encoder.lock = &jpu->mutex;
1693 jpu->vfd_encoder.v4l2_dev = &jpu->v4l2_dev;
1694 jpu->vfd_encoder.vfl_dir = VFL_DIR_M2M;
1696 ret = video_register_device(&jpu->vfd_encoder, VFL_TYPE_GRABBER, -1);
1698 v4l2_err(&jpu->v4l2_dev, "Failed to register video device\n");
1699 goto vb2_allocator_rollback;
1702 video_set_drvdata(&jpu->vfd_encoder, jpu);
1704 strlcpy(jpu->vfd_decoder.name, DRV_NAME, sizeof(jpu->vfd_decoder.name));
1705 jpu->vfd_decoder.fops = &jpu_fops;
1706 jpu->vfd_decoder.ioctl_ops = &jpu_ioctl_ops;
1707 jpu->vfd_decoder.minor = -1;
1708 jpu->vfd_decoder.release = video_device_release_empty;
1709 jpu->vfd_decoder.lock = &jpu->mutex;
1710 jpu->vfd_decoder.v4l2_dev = &jpu->v4l2_dev;
1711 jpu->vfd_decoder.vfl_dir = VFL_DIR_M2M;
1713 ret = video_register_device(&jpu->vfd_decoder, VFL_TYPE_GRABBER, -1);
1715 v4l2_err(&jpu->v4l2_dev, "Failed to register video device\n");
1716 goto enc_vdev_register_rollback;
1719 video_set_drvdata(&jpu->vfd_decoder, jpu);
1720 platform_set_drvdata(pdev, jpu);
1722 v4l2_info(&jpu->v4l2_dev, "encoder device registered as /dev/video%d\n",
1723 jpu->vfd_encoder.num);
1724 v4l2_info(&jpu->v4l2_dev, "decoder device registered as /dev/video%d\n",
1725 jpu->vfd_decoder.num);
1729 enc_vdev_register_rollback:
1730 video_unregister_device(&jpu->vfd_encoder);
1732 vb2_allocator_rollback:
1733 vb2_dma_contig_cleanup_ctx(jpu->alloc_ctx);
1736 v4l2_m2m_release(jpu->m2m_dev);
1738 device_register_rollback:
1739 v4l2_device_unregister(&jpu->v4l2_dev);
1744 static int jpu_remove(struct platform_device *pdev)
1746 struct jpu *jpu = platform_get_drvdata(pdev);
1748 video_unregister_device(&jpu->vfd_decoder);
1749 video_unregister_device(&jpu->vfd_encoder);
1750 vb2_dma_contig_cleanup_ctx(jpu->alloc_ctx);
1751 v4l2_m2m_release(jpu->m2m_dev);
1752 v4l2_device_unregister(&jpu->v4l2_dev);
1757 #ifdef CONFIG_PM_SLEEP
1758 static int jpu_suspend(struct device *dev)
1760 struct jpu *jpu = dev_get_drvdata(dev);
1762 if (jpu->ref_count == 0)
1765 clk_disable_unprepare(jpu->clk);
1770 static int jpu_resume(struct device *dev)
1772 struct jpu *jpu = dev_get_drvdata(dev);
1774 if (jpu->ref_count == 0)
1777 clk_prepare_enable(jpu->clk);
1783 static const struct dev_pm_ops jpu_pm_ops = {
1784 SET_SYSTEM_SLEEP_PM_OPS(jpu_suspend, jpu_resume)
1787 static struct platform_driver jpu_driver = {
1789 .remove = jpu_remove,
1791 .of_match_table = jpu_dt_ids,
1797 module_platform_driver(jpu_driver);
1799 MODULE_ALIAS("platform:" DRV_NAME);
1800 MODULE_AUTHOR("Mikhail Ulianov <mikhail.ulyanov@cogentembedded.com>");
1801 MODULE_DESCRIPTION("Renesas R-Car JPEG processing unit driver");
1802 MODULE_LICENSE("GPL v2");